1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) Huawei Technologies Co., Ltd. 2025. All rights reserved. */ 3 4 #ifndef _HINIC3_CSR_H_ 5 #define _HINIC3_CSR_H_ 6 7 #define HINIC3_CFG_REGS_FLAG 0x40000000 8 #define HINIC3_REGS_FLAG_MASK 0x3FFFFFFF 9 10 #define HINIC3_VF_CFG_REG_OFFSET 0x2000 11 12 /* HW interface registers */ 13 #define HINIC3_CSR_FUNC_ATTR0_ADDR (HINIC3_CFG_REGS_FLAG + 0x0) 14 #define HINIC3_CSR_FUNC_ATTR1_ADDR (HINIC3_CFG_REGS_FLAG + 0x4) 15 #define HINIC3_CSR_FUNC_ATTR2_ADDR (HINIC3_CFG_REGS_FLAG + 0x8) 16 #define HINIC3_CSR_FUNC_ATTR3_ADDR (HINIC3_CFG_REGS_FLAG + 0xC) 17 #define HINIC3_CSR_FUNC_ATTR4_ADDR (HINIC3_CFG_REGS_FLAG + 0x10) 18 #define HINIC3_CSR_FUNC_ATTR5_ADDR (HINIC3_CFG_REGS_FLAG + 0x14) 19 #define HINIC3_CSR_FUNC_ATTR6_ADDR (HINIC3_CFG_REGS_FLAG + 0x18) 20 21 #define HINIC3_FUNC_CSR_MAILBOX_DATA_OFF 0x80 22 #define HINIC3_FUNC_CSR_MAILBOX_CONTROL_OFF (HINIC3_CFG_REGS_FLAG + 0x0100) 23 #define HINIC3_FUNC_CSR_MAILBOX_INT_OFF (HINIC3_CFG_REGS_FLAG + 0x0104) 24 #define HINIC3_FUNC_CSR_MAILBOX_RESULT_H_OFF (HINIC3_CFG_REGS_FLAG + 0x0108) 25 #define HINIC3_FUNC_CSR_MAILBOX_RESULT_L_OFF (HINIC3_CFG_REGS_FLAG + 0x010C) 26 27 #define HINIC3_CSR_DMA_ATTR_TBL_ADDR (HINIC3_CFG_REGS_FLAG + 0x380) 28 #define HINIC3_CSR_DMA_ATTR_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x390) 29 30 /* MSI-X registers */ 31 #define HINIC3_CSR_FUNC_MSI_CLR_WR_ADDR (HINIC3_CFG_REGS_FLAG + 0x58) 32 33 #define HINIC3_MSI_CLR_INDIR_RESEND_TIMER_CLR_MASK BIT(0) 34 #define HINIC3_MSI_CLR_INDIR_INT_MSK_SET_MASK BIT(1) 35 #define HINIC3_MSI_CLR_INDIR_INT_MSK_CLR_MASK BIT(2) 36 #define HINIC3_MSI_CLR_INDIR_AUTO_MSK_SET_MASK BIT(3) 37 #define HINIC3_MSI_CLR_INDIR_AUTO_MSK_CLR_MASK BIT(4) 38 #define HINIC3_MSI_CLR_INDIR_SIMPLE_INDIR_IDX_MASK GENMASK(31, 22) 39 #define HINIC3_MSI_CLR_INDIR_SET(val, member) \ 40 FIELD_PREP(HINIC3_MSI_CLR_INDIR_##member##_MASK, val) 41 42 /* EQ registers */ 43 #define HINIC3_AEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x210) 44 #define HINIC3_CEQ_INDIR_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x290) 45 46 #define HINIC3_EQ_INDIR_IDX_ADDR(type) \ 47 ((type == HINIC3_AEQ) ? HINIC3_AEQ_INDIR_IDX_ADDR : \ 48 HINIC3_CEQ_INDIR_IDX_ADDR) 49 50 #define HINIC3_AEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x240) 51 #define HINIC3_CEQ_MTT_OFF_BASE_ADDR (HINIC3_CFG_REGS_FLAG + 0x2C0) 52 53 #define HINIC3_CSR_EQ_PAGE_OFF_STRIDE 8 54 55 #define HINIC3_AEQ_HI_PHYS_ADDR_REG(pg_num) \ 56 (HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 57 HINIC3_CSR_EQ_PAGE_OFF_STRIDE) 58 59 #define HINIC3_AEQ_LO_PHYS_ADDR_REG(pg_num) \ 60 (HINIC3_AEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 61 HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4) 62 63 #define HINIC3_CEQ_HI_PHYS_ADDR_REG(pg_num) \ 64 (HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 65 HINIC3_CSR_EQ_PAGE_OFF_STRIDE) 66 67 #define HINIC3_CEQ_LO_PHYS_ADDR_REG(pg_num) \ 68 (HINIC3_CEQ_MTT_OFF_BASE_ADDR + (pg_num) * \ 69 HINIC3_CSR_EQ_PAGE_OFF_STRIDE + 4) 70 71 #define HINIC3_CSR_AEQ_CTRL_0_ADDR (HINIC3_CFG_REGS_FLAG + 0x200) 72 #define HINIC3_CSR_AEQ_CTRL_1_ADDR (HINIC3_CFG_REGS_FLAG + 0x204) 73 #define HINIC3_CSR_AEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x20C) 74 #define HINIC3_CSR_AEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x50) 75 76 #define HINIC3_CSR_CEQ_PROD_IDX_ADDR (HINIC3_CFG_REGS_FLAG + 0x28c) 77 #define HINIC3_CSR_CEQ_CI_SIMPLE_INDIR_ADDR (HINIC3_CFG_REGS_FLAG + 0x54) 78 79 #endif 80