1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/device.h> 5 6 #include "hclge_debugfs.h" 7 #include "hclge_cmd.h" 8 #include "hclge_main.h" 9 #include "hclge_tm.h" 10 #include "hnae3.h" 11 12 static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index, 13 char *title_buf, char *true_buf, 14 char *false_buf) 15 { 16 if (flag) 17 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 18 true_buf); 19 else 20 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 21 false_buf); 22 } 23 24 static void hclge_dbg_dump_tc(struct hclge_dev *hdev) 25 { 26 struct hclge_ets_tc_weight_cmd *ets_weight; 27 struct hclge_desc desc; 28 int i, ret; 29 30 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true); 31 32 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 33 if (ret) { 34 dev_err(&hdev->pdev->dev, "dump tc fail, status is %d.\n", ret); 35 return; 36 } 37 38 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 39 40 dev_info(&hdev->pdev->dev, "dump tc\n"); 41 dev_info(&hdev->pdev->dev, "weight_offset: %u\n", 42 ets_weight->weight_offset); 43 44 for (i = 0; i < HNAE3_MAX_TC; i++) 45 hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i, 46 "tc", "no sp mode", "sp mode"); 47 } 48 49 static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev) 50 { 51 struct hclge_port_shapping_cmd *port_shap_cfg_cmd; 52 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 53 struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd; 54 enum hclge_opcode_type cmd; 55 struct hclge_desc desc; 56 int ret; 57 58 cmd = HCLGE_OPC_TM_PG_C_SHAPPING; 59 hclge_cmd_setup_basic_desc(&desc, cmd, true); 60 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 61 if (ret) 62 goto err_tm_pg_cmd_send; 63 64 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 65 dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 66 dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n", 67 pg_shap_cfg_cmd->pg_shapping_para); 68 69 cmd = HCLGE_OPC_TM_PG_P_SHAPPING; 70 hclge_cmd_setup_basic_desc(&desc, cmd, true); 71 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 72 if (ret) 73 goto err_tm_pg_cmd_send; 74 75 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 76 dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 77 dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n", 78 pg_shap_cfg_cmd->pg_shapping_para); 79 80 cmd = HCLGE_OPC_TM_PORT_SHAPPING; 81 hclge_cmd_setup_basic_desc(&desc, cmd, true); 82 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 83 if (ret) 84 goto err_tm_pg_cmd_send; 85 86 port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 87 dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n", 88 port_shap_cfg_cmd->port_shapping_para); 89 90 cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG; 91 hclge_cmd_setup_basic_desc(&desc, cmd, true); 92 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 93 if (ret) 94 goto err_tm_pg_cmd_send; 95 96 dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n", desc.data[0]); 97 98 cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG; 99 hclge_cmd_setup_basic_desc(&desc, cmd, true); 100 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 101 if (ret) 102 goto err_tm_pg_cmd_send; 103 104 dev_info(&hdev->pdev->dev, "PRI_SCH pg_id: %u\n", desc.data[0]); 105 106 cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG; 107 hclge_cmd_setup_basic_desc(&desc, cmd, true); 108 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 109 if (ret) 110 goto err_tm_pg_cmd_send; 111 112 dev_info(&hdev->pdev->dev, "QS_SCH pg_id: %u\n", desc.data[0]); 113 114 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING; 115 hclge_cmd_setup_basic_desc(&desc, cmd, true); 116 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 117 if (ret) 118 goto err_tm_pg_cmd_send; 119 120 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 121 dev_info(&hdev->pdev->dev, "BP_TO_QSET pg_id: %u\n", 122 bp_to_qs_map_cmd->tc_id); 123 dev_info(&hdev->pdev->dev, "BP_TO_QSET pg_shapping: 0x%x\n", 124 bp_to_qs_map_cmd->qs_group_id); 125 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n", 126 bp_to_qs_map_cmd->qs_bit_map); 127 return; 128 129 err_tm_pg_cmd_send: 130 dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), status is %d\n", 131 cmd, ret); 132 } 133 134 static void hclge_dbg_dump_tm(struct hclge_dev *hdev) 135 { 136 struct hclge_priority_weight_cmd *priority_weight; 137 struct hclge_pg_to_pri_link_cmd *pg_to_pri_map; 138 struct hclge_qs_to_pri_link_cmd *qs_to_pri_map; 139 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map; 140 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 141 struct hclge_pg_weight_cmd *pg_weight; 142 struct hclge_qs_weight_cmd *qs_weight; 143 enum hclge_opcode_type cmd; 144 struct hclge_desc desc; 145 int ret; 146 147 cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK; 148 hclge_cmd_setup_basic_desc(&desc, cmd, true); 149 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 150 if (ret) 151 goto err_tm_cmd_send; 152 153 pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 154 dev_info(&hdev->pdev->dev, "dump tm\n"); 155 dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n", 156 pg_to_pri_map->pg_id); 157 dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n", 158 pg_to_pri_map->pri_bit_map); 159 160 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; 161 hclge_cmd_setup_basic_desc(&desc, cmd, true); 162 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 163 if (ret) 164 goto err_tm_cmd_send; 165 166 qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 167 dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n", 168 qs_to_pri_map->qs_id); 169 dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n", 170 qs_to_pri_map->priority); 171 dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n", 172 qs_to_pri_map->link_vld); 173 174 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK; 175 hclge_cmd_setup_basic_desc(&desc, cmd, true); 176 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 177 if (ret) 178 goto err_tm_cmd_send; 179 180 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 181 dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n", nq_to_qs_map->nq_id); 182 dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: %u\n", 183 nq_to_qs_map->qset_id); 184 185 cmd = HCLGE_OPC_TM_PG_WEIGHT; 186 hclge_cmd_setup_basic_desc(&desc, cmd, true); 187 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 188 if (ret) 189 goto err_tm_cmd_send; 190 191 pg_weight = (struct hclge_pg_weight_cmd *)desc.data; 192 dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id); 193 dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr); 194 195 cmd = HCLGE_OPC_TM_QS_WEIGHT; 196 hclge_cmd_setup_basic_desc(&desc, cmd, true); 197 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 198 if (ret) 199 goto err_tm_cmd_send; 200 201 qs_weight = (struct hclge_qs_weight_cmd *)desc.data; 202 dev_info(&hdev->pdev->dev, "QS qs_id: %u\n", qs_weight->qs_id); 203 dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr); 204 205 cmd = HCLGE_OPC_TM_PRI_WEIGHT; 206 hclge_cmd_setup_basic_desc(&desc, cmd, true); 207 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 208 if (ret) 209 goto err_tm_cmd_send; 210 211 priority_weight = (struct hclge_priority_weight_cmd *)desc.data; 212 dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id); 213 dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr); 214 215 cmd = HCLGE_OPC_TM_PRI_C_SHAPPING; 216 hclge_cmd_setup_basic_desc(&desc, cmd, true); 217 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 218 if (ret) 219 goto err_tm_cmd_send; 220 221 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 222 dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id); 223 dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n", 224 shap_cfg_cmd->pri_shapping_para); 225 226 cmd = HCLGE_OPC_TM_PRI_P_SHAPPING; 227 hclge_cmd_setup_basic_desc(&desc, cmd, true); 228 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 229 if (ret) 230 goto err_tm_cmd_send; 231 232 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 233 dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id); 234 dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n", 235 shap_cfg_cmd->pri_shapping_para); 236 237 hclge_dbg_dump_tm_pg(hdev); 238 239 return; 240 241 err_tm_cmd_send: 242 dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), status is %d\n", 243 cmd, ret); 244 } 245 246 static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev) 247 { 248 struct hclge_cfg_pause_param_cmd *pause_param; 249 struct hclge_desc desc; 250 int ret; 251 252 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 253 254 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 255 if (ret) { 256 dev_err(&hdev->pdev->dev, "dump checksum fail, status is %d.\n", 257 ret); 258 return; 259 } 260 261 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 262 dev_info(&hdev->pdev->dev, "dump qos pause cfg\n"); 263 dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n", 264 pause_param->pause_trans_gap); 265 dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n", 266 pause_param->pause_trans_time); 267 } 268 269 static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev) 270 { 271 struct hclge_qos_pri_map_cmd *pri_map; 272 struct hclge_desc desc; 273 int ret; 274 275 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true); 276 277 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 278 if (ret) { 279 dev_err(&hdev->pdev->dev, 280 "dump qos pri map fail, status is %d.\n", ret); 281 return; 282 } 283 284 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; 285 dev_info(&hdev->pdev->dev, "dump qos pri map\n"); 286 dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri); 287 dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc); 288 dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc); 289 dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc); 290 dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc); 291 dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc); 292 dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc); 293 dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc); 294 dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc); 295 } 296 297 static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev) 298 { 299 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; 300 struct hclge_rx_priv_buff_cmd *rx_buf_cmd; 301 struct hclge_rx_priv_wl_buf *rx_priv_wl; 302 struct hclge_rx_com_wl *rx_packet_cnt; 303 struct hclge_rx_com_thrd *rx_com_thrd; 304 struct hclge_rx_com_wl *rx_com_wl; 305 enum hclge_opcode_type cmd; 306 struct hclge_desc desc[2]; 307 int i, ret; 308 309 cmd = HCLGE_OPC_TX_BUFF_ALLOC; 310 hclge_cmd_setup_basic_desc(desc, cmd, true); 311 ret = hclge_cmd_send(&hdev->hw, desc, 1); 312 if (ret) 313 goto err_qos_cmd_send; 314 315 dev_info(&hdev->pdev->dev, "dump qos buf cfg\n"); 316 317 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc[0].data; 318 for (i = 0; i < HCLGE_TC_NUM; i++) 319 dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i, 320 tx_buf_cmd->tx_pkt_buff[i]); 321 322 cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC; 323 hclge_cmd_setup_basic_desc(desc, cmd, true); 324 ret = hclge_cmd_send(&hdev->hw, desc, 1); 325 if (ret) 326 goto err_qos_cmd_send; 327 328 dev_info(&hdev->pdev->dev, "\n"); 329 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc[0].data; 330 for (i = 0; i < HCLGE_TC_NUM; i++) 331 dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i, 332 rx_buf_cmd->buf_num[i]); 333 334 dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n", 335 rx_buf_cmd->shared_buf); 336 337 cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC; 338 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 339 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 340 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 341 ret = hclge_cmd_send(&hdev->hw, desc, 2); 342 if (ret) 343 goto err_qos_cmd_send; 344 345 dev_info(&hdev->pdev->dev, "\n"); 346 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; 347 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 348 dev_info(&hdev->pdev->dev, 349 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, 350 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 351 352 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; 353 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 354 dev_info(&hdev->pdev->dev, 355 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 356 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 357 358 cmd = HCLGE_OPC_RX_COM_THRD_ALLOC; 359 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 360 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 361 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 362 ret = hclge_cmd_send(&hdev->hw, desc, 2); 363 if (ret) 364 goto err_qos_cmd_send; 365 366 dev_info(&hdev->pdev->dev, "\n"); 367 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; 368 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 369 dev_info(&hdev->pdev->dev, 370 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, 371 rx_com_thrd->com_thrd[i].high, 372 rx_com_thrd->com_thrd[i].low); 373 374 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; 375 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 376 dev_info(&hdev->pdev->dev, 377 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 378 rx_com_thrd->com_thrd[i].high, 379 rx_com_thrd->com_thrd[i].low); 380 381 cmd = HCLGE_OPC_RX_COM_WL_ALLOC; 382 hclge_cmd_setup_basic_desc(desc, cmd, true); 383 ret = hclge_cmd_send(&hdev->hw, desc, 1); 384 if (ret) 385 goto err_qos_cmd_send; 386 387 rx_com_wl = (struct hclge_rx_com_wl *)desc[0].data; 388 dev_info(&hdev->pdev->dev, "\n"); 389 dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n", 390 rx_com_wl->com_wl.high, rx_com_wl->com_wl.low); 391 392 cmd = HCLGE_OPC_RX_GBL_PKT_CNT; 393 hclge_cmd_setup_basic_desc(desc, cmd, true); 394 ret = hclge_cmd_send(&hdev->hw, desc, 1); 395 if (ret) 396 goto err_qos_cmd_send; 397 398 rx_packet_cnt = (struct hclge_rx_com_wl *)desc[0].data; 399 dev_info(&hdev->pdev->dev, 400 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", 401 rx_packet_cnt->com_wl.high, rx_packet_cnt->com_wl.low); 402 403 return; 404 405 err_qos_cmd_send: 406 dev_err(&hdev->pdev->dev, 407 "dump qos buf cfg fail(0x%x), status is %d\n", cmd, ret); 408 } 409 410 static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage, 411 bool sel_x, u32 loc) 412 { 413 struct hclge_fd_tcam_config_1_cmd *req1; 414 struct hclge_fd_tcam_config_2_cmd *req2; 415 struct hclge_fd_tcam_config_3_cmd *req3; 416 struct hclge_desc desc[3]; 417 int ret, i; 418 u32 *req; 419 420 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true); 421 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 422 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true); 423 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 424 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true); 425 426 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 427 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 428 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 429 430 req1->stage = stage; 431 req1->xy_sel = sel_x ? 1 : 0; 432 req1->index = cpu_to_le32(loc); 433 434 ret = hclge_cmd_send(&hdev->hw, desc, 3); 435 if (ret) 436 return; 437 438 dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n", 439 sel_x ? "x" : "y", loc); 440 441 req = (u32 *)req1->tcam_data; 442 for (i = 0; i < 2; i++) 443 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 444 445 req = (u32 *)req2->tcam_data; 446 for (i = 0; i < 6; i++) 447 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 448 449 req = (u32 *)req3->tcam_data; 450 for (i = 0; i < 5; i++) 451 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 452 } 453 454 static void hclge_dbg_fd_tcam(struct hclge_dev *hdev) 455 { 456 u32 i; 457 458 for (i = 0; i < hdev->fd_cfg.rule_num[0]; i++) { 459 hclge_dbg_fd_tcam_read(hdev, 0, true, i); 460 hclge_dbg_fd_tcam_read(hdev, 0, false, i); 461 } 462 } 463 464 int hclge_dbg_run_cmd(struct hnae3_handle *handle, char *cmd_buf) 465 { 466 struct hclge_vport *vport = hclge_get_vport(handle); 467 struct hclge_dev *hdev = vport->back; 468 469 if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) { 470 hclge_dbg_fd_tcam(hdev); 471 } else if (strncmp(cmd_buf, "dump tc", 7) == 0) { 472 hclge_dbg_dump_tc(hdev); 473 } else if (strncmp(cmd_buf, "dump tm", 7) == 0) { 474 hclge_dbg_dump_tm(hdev); 475 } else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) { 476 hclge_dbg_dump_qos_pause_cfg(hdev); 477 } else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) { 478 hclge_dbg_dump_qos_pri_map(hdev); 479 } else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) { 480 hclge_dbg_dump_qos_buf_cfg(hdev); 481 } else { 482 dev_info(&hdev->pdev->dev, "unknown command\n"); 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488