1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
3
4 #include <linux/device.h>
5 #include <linux/sched/clock.h>
6
7 #include "hclge_debugfs.h"
8 #include "hclge_err.h"
9 #include "hclge_main.h"
10 #include "hclge_regs.h"
11 #include "hclge_tm.h"
12 #include "hnae3.h"
13
14 static const char * const state_str[] = { "off", "on" };
15 static const char * const hclge_mac_state_str[] = {
16 "TO_ADD", "TO_DEL", "ACTIVE"
17 };
18
19 static const char * const tc_map_mode_str[] = { "PRIO", "DSCP" };
20
21 static const struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = {
22 {false, "Reserved"},
23 {true, "BP_CPU_STATE"},
24 {true, "DFX_MSIX_INFO_NIC_0"},
25 {true, "DFX_MSIX_INFO_NIC_1"},
26 {true, "DFX_MSIX_INFO_NIC_2"},
27 {true, "DFX_MSIX_INFO_NIC_3"},
28
29 {true, "DFX_MSIX_INFO_ROC_0"},
30 {true, "DFX_MSIX_INFO_ROC_1"},
31 {true, "DFX_MSIX_INFO_ROC_2"},
32 {true, "DFX_MSIX_INFO_ROC_3"},
33 {false, "Reserved"},
34 {false, "Reserved"},
35 };
36
37 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = {
38 {false, "Reserved"},
39 {true, "SSU_ETS_PORT_STATUS"},
40 {true, "SSU_ETS_TCG_STATUS"},
41 {false, "Reserved"},
42 {false, "Reserved"},
43 {true, "SSU_BP_STATUS_0"},
44
45 {true, "SSU_BP_STATUS_1"},
46 {true, "SSU_BP_STATUS_2"},
47 {true, "SSU_BP_STATUS_3"},
48 {true, "SSU_BP_STATUS_4"},
49 {true, "SSU_BP_STATUS_5"},
50 {true, "SSU_MAC_TX_PFC_IND"},
51
52 {true, "MAC_SSU_RX_PFC_IND"},
53 {true, "BTMP_AGEING_ST_B0"},
54 {true, "BTMP_AGEING_ST_B1"},
55 {true, "BTMP_AGEING_ST_B2"},
56 {false, "Reserved"},
57 {false, "Reserved"},
58
59 {true, "FULL_DROP_NUM"},
60 {true, "PART_DROP_NUM"},
61 {true, "PPP_KEY_DROP_NUM"},
62 {true, "PPP_RLT_DROP_NUM"},
63 {true, "LO_PRI_UNICAST_RLT_DROP_NUM"},
64 {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"},
65
66 {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"},
67 {true, "NCSI_PACKET_CURR_BUFFER_CNT"},
68 {true, "BTMP_AGEING_RLS_CNT_BANK0"},
69 {true, "BTMP_AGEING_RLS_CNT_BANK1"},
70 {true, "BTMP_AGEING_RLS_CNT_BANK2"},
71 {true, "SSU_MB_RD_RLT_DROP_CNT"},
72
73 {true, "SSU_PPP_MAC_KEY_NUM_L"},
74 {true, "SSU_PPP_MAC_KEY_NUM_H"},
75 {true, "SSU_PPP_HOST_KEY_NUM_L"},
76 {true, "SSU_PPP_HOST_KEY_NUM_H"},
77 {true, "PPP_SSU_MAC_RLT_NUM_L"},
78 {true, "PPP_SSU_MAC_RLT_NUM_H"},
79
80 {true, "PPP_SSU_HOST_RLT_NUM_L"},
81 {true, "PPP_SSU_HOST_RLT_NUM_H"},
82 {true, "NCSI_RX_PACKET_IN_CNT_L"},
83 {true, "NCSI_RX_PACKET_IN_CNT_H"},
84 {true, "NCSI_TX_PACKET_OUT_CNT_L"},
85 {true, "NCSI_TX_PACKET_OUT_CNT_H"},
86
87 {true, "SSU_KEY_DROP_NUM"},
88 {true, "MB_UNCOPY_NUM"},
89 {true, "RX_OQ_DROP_PKT_CNT"},
90 {true, "TX_OQ_DROP_PKT_CNT"},
91 {true, "BANK_UNBALANCE_DROP_CNT"},
92 {true, "BANK_UNBALANCE_RX_DROP_CNT"},
93
94 {true, "NIC_L2_ERR_DROP_PKT_CNT"},
95 {true, "ROC_L2_ERR_DROP_PKT_CNT"},
96 {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"},
97 {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"},
98 {true, "RX_OQ_GLB_DROP_PKT_CNT"},
99 {false, "Reserved"},
100
101 {true, "LO_PRI_UNICAST_CUR_CNT"},
102 {true, "HI_PRI_MULTICAST_CUR_CNT"},
103 {true, "LO_PRI_MULTICAST_CUR_CNT"},
104 {false, "Reserved"},
105 {false, "Reserved"},
106 {false, "Reserved"},
107 };
108
109 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = {
110 {true, "prt_id"},
111 {true, "PACKET_TC_CURR_BUFFER_CNT_0"},
112 {true, "PACKET_TC_CURR_BUFFER_CNT_1"},
113 {true, "PACKET_TC_CURR_BUFFER_CNT_2"},
114 {true, "PACKET_TC_CURR_BUFFER_CNT_3"},
115 {true, "PACKET_TC_CURR_BUFFER_CNT_4"},
116
117 {true, "PACKET_TC_CURR_BUFFER_CNT_5"},
118 {true, "PACKET_TC_CURR_BUFFER_CNT_6"},
119 {true, "PACKET_TC_CURR_BUFFER_CNT_7"},
120 {true, "PACKET_CURR_BUFFER_CNT"},
121 {false, "Reserved"},
122 {false, "Reserved"},
123
124 {true, "RX_PACKET_IN_CNT_L"},
125 {true, "RX_PACKET_IN_CNT_H"},
126 {true, "RX_PACKET_OUT_CNT_L"},
127 {true, "RX_PACKET_OUT_CNT_H"},
128 {true, "TX_PACKET_IN_CNT_L"},
129 {true, "TX_PACKET_IN_CNT_H"},
130
131 {true, "TX_PACKET_OUT_CNT_L"},
132 {true, "TX_PACKET_OUT_CNT_H"},
133 {true, "ROC_RX_PACKET_IN_CNT_L"},
134 {true, "ROC_RX_PACKET_IN_CNT_H"},
135 {true, "ROC_TX_PACKET_OUT_CNT_L"},
136 {true, "ROC_TX_PACKET_OUT_CNT_H"},
137
138 {true, "RX_PACKET_TC_IN_CNT_0_L"},
139 {true, "RX_PACKET_TC_IN_CNT_0_H"},
140 {true, "RX_PACKET_TC_IN_CNT_1_L"},
141 {true, "RX_PACKET_TC_IN_CNT_1_H"},
142 {true, "RX_PACKET_TC_IN_CNT_2_L"},
143 {true, "RX_PACKET_TC_IN_CNT_2_H"},
144
145 {true, "RX_PACKET_TC_IN_CNT_3_L"},
146 {true, "RX_PACKET_TC_IN_CNT_3_H"},
147 {true, "RX_PACKET_TC_IN_CNT_4_L"},
148 {true, "RX_PACKET_TC_IN_CNT_4_H"},
149 {true, "RX_PACKET_TC_IN_CNT_5_L"},
150 {true, "RX_PACKET_TC_IN_CNT_5_H"},
151
152 {true, "RX_PACKET_TC_IN_CNT_6_L"},
153 {true, "RX_PACKET_TC_IN_CNT_6_H"},
154 {true, "RX_PACKET_TC_IN_CNT_7_L"},
155 {true, "RX_PACKET_TC_IN_CNT_7_H"},
156 {true, "RX_PACKET_TC_OUT_CNT_0_L"},
157 {true, "RX_PACKET_TC_OUT_CNT_0_H"},
158
159 {true, "RX_PACKET_TC_OUT_CNT_1_L"},
160 {true, "RX_PACKET_TC_OUT_CNT_1_H"},
161 {true, "RX_PACKET_TC_OUT_CNT_2_L"},
162 {true, "RX_PACKET_TC_OUT_CNT_2_H"},
163 {true, "RX_PACKET_TC_OUT_CNT_3_L"},
164 {true, "RX_PACKET_TC_OUT_CNT_3_H"},
165
166 {true, "RX_PACKET_TC_OUT_CNT_4_L"},
167 {true, "RX_PACKET_TC_OUT_CNT_4_H"},
168 {true, "RX_PACKET_TC_OUT_CNT_5_L"},
169 {true, "RX_PACKET_TC_OUT_CNT_5_H"},
170 {true, "RX_PACKET_TC_OUT_CNT_6_L"},
171 {true, "RX_PACKET_TC_OUT_CNT_6_H"},
172
173 {true, "RX_PACKET_TC_OUT_CNT_7_L"},
174 {true, "RX_PACKET_TC_OUT_CNT_7_H"},
175 {true, "TX_PACKET_TC_IN_CNT_0_L"},
176 {true, "TX_PACKET_TC_IN_CNT_0_H"},
177 {true, "TX_PACKET_TC_IN_CNT_1_L"},
178 {true, "TX_PACKET_TC_IN_CNT_1_H"},
179
180 {true, "TX_PACKET_TC_IN_CNT_2_L"},
181 {true, "TX_PACKET_TC_IN_CNT_2_H"},
182 {true, "TX_PACKET_TC_IN_CNT_3_L"},
183 {true, "TX_PACKET_TC_IN_CNT_3_H"},
184 {true, "TX_PACKET_TC_IN_CNT_4_L"},
185 {true, "TX_PACKET_TC_IN_CNT_4_H"},
186
187 {true, "TX_PACKET_TC_IN_CNT_5_L"},
188 {true, "TX_PACKET_TC_IN_CNT_5_H"},
189 {true, "TX_PACKET_TC_IN_CNT_6_L"},
190 {true, "TX_PACKET_TC_IN_CNT_6_H"},
191 {true, "TX_PACKET_TC_IN_CNT_7_L"},
192 {true, "TX_PACKET_TC_IN_CNT_7_H"},
193
194 {true, "TX_PACKET_TC_OUT_CNT_0_L"},
195 {true, "TX_PACKET_TC_OUT_CNT_0_H"},
196 {true, "TX_PACKET_TC_OUT_CNT_1_L"},
197 {true, "TX_PACKET_TC_OUT_CNT_1_H"},
198 {true, "TX_PACKET_TC_OUT_CNT_2_L"},
199 {true, "TX_PACKET_TC_OUT_CNT_2_H"},
200
201 {true, "TX_PACKET_TC_OUT_CNT_3_L"},
202 {true, "TX_PACKET_TC_OUT_CNT_3_H"},
203 {true, "TX_PACKET_TC_OUT_CNT_4_L"},
204 {true, "TX_PACKET_TC_OUT_CNT_4_H"},
205 {true, "TX_PACKET_TC_OUT_CNT_5_L"},
206 {true, "TX_PACKET_TC_OUT_CNT_5_H"},
207
208 {true, "TX_PACKET_TC_OUT_CNT_6_L"},
209 {true, "TX_PACKET_TC_OUT_CNT_6_H"},
210 {true, "TX_PACKET_TC_OUT_CNT_7_L"},
211 {true, "TX_PACKET_TC_OUT_CNT_7_H"},
212 {false, "Reserved"},
213 {false, "Reserved"},
214 };
215
216 static const struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = {
217 {true, "OQ_INDEX"},
218 {true, "QUEUE_CNT"},
219 {false, "Reserved"},
220 {false, "Reserved"},
221 {false, "Reserved"},
222 {false, "Reserved"},
223 };
224
225 static const struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = {
226 {true, "prt_id"},
227 {true, "IGU_RX_ERR_PKT"},
228 {true, "IGU_RX_NO_SOF_PKT"},
229 {true, "EGU_TX_1588_SHORT_PKT"},
230 {true, "EGU_TX_1588_PKT"},
231 {true, "EGU_TX_ERR_PKT"},
232
233 {true, "IGU_RX_OUT_L2_PKT"},
234 {true, "IGU_RX_OUT_L3_PKT"},
235 {true, "IGU_RX_OUT_L4_PKT"},
236 {true, "IGU_RX_IN_L2_PKT"},
237 {true, "IGU_RX_IN_L3_PKT"},
238 {true, "IGU_RX_IN_L4_PKT"},
239
240 {true, "IGU_RX_EL3E_PKT"},
241 {true, "IGU_RX_EL4E_PKT"},
242 {true, "IGU_RX_L3E_PKT"},
243 {true, "IGU_RX_L4E_PKT"},
244 {true, "IGU_RX_ROCEE_PKT"},
245 {true, "IGU_RX_OUT_UDP0_PKT"},
246
247 {true, "IGU_RX_IN_UDP0_PKT"},
248 {true, "IGU_MC_CAR_DROP_PKT_L"},
249 {true, "IGU_MC_CAR_DROP_PKT_H"},
250 {true, "IGU_BC_CAR_DROP_PKT_L"},
251 {true, "IGU_BC_CAR_DROP_PKT_H"},
252 {false, "Reserved"},
253
254 {true, "IGU_RX_OVERSIZE_PKT_L"},
255 {true, "IGU_RX_OVERSIZE_PKT_H"},
256 {true, "IGU_RX_UNDERSIZE_PKT_L"},
257 {true, "IGU_RX_UNDERSIZE_PKT_H"},
258 {true, "IGU_RX_OUT_ALL_PKT_L"},
259 {true, "IGU_RX_OUT_ALL_PKT_H"},
260
261 {true, "IGU_TX_OUT_ALL_PKT_L"},
262 {true, "IGU_TX_OUT_ALL_PKT_H"},
263 {true, "IGU_RX_UNI_PKT_L"},
264 {true, "IGU_RX_UNI_PKT_H"},
265 {true, "IGU_RX_MULTI_PKT_L"},
266 {true, "IGU_RX_MULTI_PKT_H"},
267
268 {true, "IGU_RX_BROAD_PKT_L"},
269 {true, "IGU_RX_BROAD_PKT_H"},
270 {true, "EGU_TX_OUT_ALL_PKT_L"},
271 {true, "EGU_TX_OUT_ALL_PKT_H"},
272 {true, "EGU_TX_UNI_PKT_L"},
273 {true, "EGU_TX_UNI_PKT_H"},
274
275 {true, "EGU_TX_MULTI_PKT_L"},
276 {true, "EGU_TX_MULTI_PKT_H"},
277 {true, "EGU_TX_BROAD_PKT_L"},
278 {true, "EGU_TX_BROAD_PKT_H"},
279 {true, "IGU_TX_KEY_NUM_L"},
280 {true, "IGU_TX_KEY_NUM_H"},
281
282 {true, "IGU_RX_NON_TUN_PKT_L"},
283 {true, "IGU_RX_NON_TUN_PKT_H"},
284 {true, "IGU_RX_TUN_PKT_L"},
285 {true, "IGU_RX_TUN_PKT_H"},
286 {false, "Reserved"},
287 {false, "Reserved"},
288 };
289
290 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = {
291 {true, "tc_queue_num"},
292 {true, "FSM_DFX_ST0"},
293 {true, "FSM_DFX_ST1"},
294 {true, "RPU_RX_PKT_DROP_CNT"},
295 {true, "BUF_WAIT_TIMEOUT"},
296 {true, "BUF_WAIT_TIMEOUT_QID"},
297 };
298
299 static const struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = {
300 {false, "Reserved"},
301 {true, "FIFO_DFX_ST0"},
302 {true, "FIFO_DFX_ST1"},
303 {true, "FIFO_DFX_ST2"},
304 {true, "FIFO_DFX_ST3"},
305 {true, "FIFO_DFX_ST4"},
306
307 {true, "FIFO_DFX_ST5"},
308 {false, "Reserved"},
309 {false, "Reserved"},
310 {false, "Reserved"},
311 {false, "Reserved"},
312 {false, "Reserved"},
313 };
314
315 static const struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = {
316 {false, "Reserved"},
317 {true, "NCSI_EGU_TX_FIFO_STS"},
318 {true, "NCSI_PAUSE_STATUS"},
319 {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"},
320 {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"},
321 {true, "NCSI_RX_CTRL_CKS_ERR_CNT"},
322
323 {true, "NCSI_RX_CTRL_PKT_CNT"},
324 {true, "NCSI_RX_PT_DMAC_ERR_CNT"},
325 {true, "NCSI_RX_PT_SMAC_ERR_CNT"},
326 {true, "NCSI_RX_PT_PKT_CNT"},
327 {true, "NCSI_RX_FCS_ERR_CNT"},
328 {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"},
329
330 {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"},
331 {true, "NCSI_TX_CTRL_PKT_CNT"},
332 {true, "NCSI_TX_PT_DMAC_ERR_CNT"},
333 {true, "NCSI_TX_PT_SMAC_ERR_CNT"},
334 {true, "NCSI_TX_PT_PKT_CNT"},
335 {true, "NCSI_TX_PT_PKT_TRUNC_CNT"},
336
337 {true, "NCSI_TX_PT_PKT_ERR_CNT"},
338 {true, "NCSI_TX_CTRL_PKT_ERR_CNT"},
339 {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"},
340 {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"},
341 {false, "Reserved"},
342 {false, "Reserved"},
343
344 {true, "NCSI_MAC_RX_OCTETS_OK"},
345 {true, "NCSI_MAC_RX_OCTETS_BAD"},
346 {true, "NCSI_MAC_RX_UC_PKTS"},
347 {true, "NCSI_MAC_RX_MC_PKTS"},
348 {true, "NCSI_MAC_RX_BC_PKTS"},
349 {true, "NCSI_MAC_RX_PKTS_64OCTETS"},
350
351 {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"},
352 {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"},
353 {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"},
354 {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"},
355 {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"},
356 {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"},
357
358 {true, "NCSI_MAC_RX_FCS_ERRORS"},
359 {true, "NCSI_MAC_RX_LONG_ERRORS"},
360 {true, "NCSI_MAC_RX_JABBER_ERRORS"},
361 {true, "NCSI_MAC_RX_RUNT_ERR_CNT"},
362 {true, "NCSI_MAC_RX_SHORT_ERR_CNT"},
363 {true, "NCSI_MAC_RX_FILT_PKT_CNT"},
364
365 {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"},
366 {true, "NCSI_MAC_TX_OCTETS_OK"},
367 {true, "NCSI_MAC_TX_OCTETS_BAD"},
368 {true, "NCSI_MAC_TX_UC_PKTS"},
369 {true, "NCSI_MAC_TX_MC_PKTS"},
370 {true, "NCSI_MAC_TX_BC_PKTS"},
371
372 {true, "NCSI_MAC_TX_PKTS_64OCTETS"},
373 {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"},
374 {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"},
375 {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"},
376 {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"},
377 {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"},
378
379 {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"},
380 {true, "NCSI_MAC_TX_UNDERRUN"},
381 {true, "NCSI_MAC_TX_CRC_ERROR"},
382 {true, "NCSI_MAC_TX_PAUSE_FRAMES"},
383 {true, "NCSI_MAC_RX_PAD_PKTS"},
384 {true, "NCSI_MAC_RX_PAUSE_FRAMES"},
385 };
386
387 static const struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = {
388 {false, "Reserved"},
389 {true, "LGE_IGU_AFIFO_DFX_0"},
390 {true, "LGE_IGU_AFIFO_DFX_1"},
391 {true, "LGE_IGU_AFIFO_DFX_2"},
392 {true, "LGE_IGU_AFIFO_DFX_3"},
393 {true, "LGE_IGU_AFIFO_DFX_4"},
394
395 {true, "LGE_IGU_AFIFO_DFX_5"},
396 {true, "LGE_IGU_AFIFO_DFX_6"},
397 {true, "LGE_IGU_AFIFO_DFX_7"},
398 {true, "LGE_EGU_AFIFO_DFX_0"},
399 {true, "LGE_EGU_AFIFO_DFX_1"},
400 {true, "LGE_EGU_AFIFO_DFX_2"},
401
402 {true, "LGE_EGU_AFIFO_DFX_3"},
403 {true, "LGE_EGU_AFIFO_DFX_4"},
404 {true, "LGE_EGU_AFIFO_DFX_5"},
405 {true, "LGE_EGU_AFIFO_DFX_6"},
406 {true, "LGE_EGU_AFIFO_DFX_7"},
407 {true, "CGE_IGU_AFIFO_DFX_0"},
408
409 {true, "CGE_IGU_AFIFO_DFX_1"},
410 {true, "CGE_EGU_AFIFO_DFX_0"},
411 {true, "CGE_EGU_AFIFO_DFX_1"},
412 {false, "Reserved"},
413 {false, "Reserved"},
414 {false, "Reserved"},
415 };
416
417 static const struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = {
418 {false, "Reserved"},
419 {true, "DROP_FROM_PRT_PKT_CNT"},
420 {true, "DROP_FROM_HOST_PKT_CNT"},
421 {true, "DROP_TX_VLAN_PROC_CNT"},
422 {true, "DROP_MNG_CNT"},
423 {true, "DROP_FD_CNT"},
424
425 {true, "DROP_NO_DST_CNT"},
426 {true, "DROP_MC_MBID_FULL_CNT"},
427 {true, "DROP_SC_FILTERED"},
428 {true, "PPP_MC_DROP_PKT_CNT"},
429 {true, "DROP_PT_CNT"},
430 {true, "DROP_MAC_ANTI_SPOOF_CNT"},
431
432 {true, "DROP_IG_VFV_CNT"},
433 {true, "DROP_IG_PRTV_CNT"},
434 {true, "DROP_CNM_PFC_PAUSE_CNT"},
435 {true, "DROP_TORUS_TC_CNT"},
436 {true, "DROP_TORUS_LPBK_CNT"},
437 {true, "PPP_HFS_STS"},
438
439 {true, "PPP_MC_RSLT_STS"},
440 {true, "PPP_P3U_STS"},
441 {true, "PPP_RSLT_DESCR_STS"},
442 {true, "PPP_UMV_STS_0"},
443 {true, "PPP_UMV_STS_1"},
444 {true, "PPP_VFV_STS"},
445
446 {true, "PPP_GRO_KEY_CNT"},
447 {true, "PPP_GRO_INFO_CNT"},
448 {true, "PPP_GRO_DROP_CNT"},
449 {true, "PPP_GRO_OUT_CNT"},
450 {true, "PPP_GRO_KEY_MATCH_DATA_CNT"},
451 {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"},
452
453 {true, "PPP_GRO_INFO_MATCH_CNT"},
454 {true, "PPP_GRO_FREE_ENTRY_CNT"},
455 {true, "PPP_GRO_INNER_DFX_SIGNAL"},
456 {false, "Reserved"},
457 {false, "Reserved"},
458 {false, "Reserved"},
459
460 {true, "GET_RX_PKT_CNT_L"},
461 {true, "GET_RX_PKT_CNT_H"},
462 {true, "GET_TX_PKT_CNT_L"},
463 {true, "GET_TX_PKT_CNT_H"},
464 {true, "SEND_UC_PRT2HOST_PKT_CNT_L"},
465 {true, "SEND_UC_PRT2HOST_PKT_CNT_H"},
466
467 {true, "SEND_UC_PRT2PRT_PKT_CNT_L"},
468 {true, "SEND_UC_PRT2PRT_PKT_CNT_H"},
469 {true, "SEND_UC_HOST2HOST_PKT_CNT_L"},
470 {true, "SEND_UC_HOST2HOST_PKT_CNT_H"},
471 {true, "SEND_UC_HOST2PRT_PKT_CNT_L"},
472 {true, "SEND_UC_HOST2PRT_PKT_CNT_H"},
473
474 {true, "SEND_MC_FROM_PRT_CNT_L"},
475 {true, "SEND_MC_FROM_PRT_CNT_H"},
476 {true, "SEND_MC_FROM_HOST_CNT_L"},
477 {true, "SEND_MC_FROM_HOST_CNT_H"},
478 {true, "SSU_MC_RD_CNT_L"},
479 {true, "SSU_MC_RD_CNT_H"},
480
481 {true, "SSU_MC_DROP_CNT_L"},
482 {true, "SSU_MC_DROP_CNT_H"},
483 {true, "SSU_MC_RD_PKT_CNT_L"},
484 {true, "SSU_MC_RD_PKT_CNT_H"},
485 {true, "PPP_MC_2HOST_PKT_CNT_L"},
486 {true, "PPP_MC_2HOST_PKT_CNT_H"},
487
488 {true, "PPP_MC_2PRT_PKT_CNT_L"},
489 {true, "PPP_MC_2PRT_PKT_CNT_H"},
490 {true, "NTSNOS_PKT_CNT_L"},
491 {true, "NTSNOS_PKT_CNT_H"},
492 {true, "NTUP_PKT_CNT_L"},
493 {true, "NTUP_PKT_CNT_H"},
494
495 {true, "NTLCL_PKT_CNT_L"},
496 {true, "NTLCL_PKT_CNT_H"},
497 {true, "NTTGT_PKT_CNT_L"},
498 {true, "NTTGT_PKT_CNT_H"},
499 {true, "RTNS_PKT_CNT_L"},
500 {true, "RTNS_PKT_CNT_H"},
501
502 {true, "RTLPBK_PKT_CNT_L"},
503 {true, "RTLPBK_PKT_CNT_H"},
504 {true, "NR_PKT_CNT_L"},
505 {true, "NR_PKT_CNT_H"},
506 {true, "RR_PKT_CNT_L"},
507 {true, "RR_PKT_CNT_H"},
508
509 {true, "MNG_TBL_HIT_CNT_L"},
510 {true, "MNG_TBL_HIT_CNT_H"},
511 {true, "FD_TBL_HIT_CNT_L"},
512 {true, "FD_TBL_HIT_CNT_H"},
513 {true, "FD_LKUP_CNT_L"},
514 {true, "FD_LKUP_CNT_H"},
515
516 {true, "BC_HIT_CNT_L"},
517 {true, "BC_HIT_CNT_H"},
518 {true, "UM_TBL_UC_HIT_CNT_L"},
519 {true, "UM_TBL_UC_HIT_CNT_H"},
520 {true, "UM_TBL_MC_HIT_CNT_L"},
521 {true, "UM_TBL_MC_HIT_CNT_H"},
522
523 {true, "UM_TBL_VMDQ1_HIT_CNT_L"},
524 {true, "UM_TBL_VMDQ1_HIT_CNT_H"},
525 {true, "MTA_TBL_HIT_CNT_L"},
526 {true, "MTA_TBL_HIT_CNT_H"},
527 {true, "FWD_BONDING_HIT_CNT_L"},
528 {true, "FWD_BONDING_HIT_CNT_H"},
529
530 {true, "PROMIS_TBL_HIT_CNT_L"},
531 {true, "PROMIS_TBL_HIT_CNT_H"},
532 {true, "GET_TUNL_PKT_CNT_L"},
533 {true, "GET_TUNL_PKT_CNT_H"},
534 {true, "GET_BMC_PKT_CNT_L"},
535 {true, "GET_BMC_PKT_CNT_H"},
536
537 {true, "SEND_UC_PRT2BMC_PKT_CNT_L"},
538 {true, "SEND_UC_PRT2BMC_PKT_CNT_H"},
539 {true, "SEND_UC_HOST2BMC_PKT_CNT_L"},
540 {true, "SEND_UC_HOST2BMC_PKT_CNT_H"},
541 {true, "SEND_UC_BMC2HOST_PKT_CNT_L"},
542 {true, "SEND_UC_BMC2HOST_PKT_CNT_H"},
543
544 {true, "SEND_UC_BMC2PRT_PKT_CNT_L"},
545 {true, "SEND_UC_BMC2PRT_PKT_CNT_H"},
546 {true, "PPP_MC_2BMC_PKT_CNT_L"},
547 {true, "PPP_MC_2BMC_PKT_CNT_H"},
548 {true, "VLAN_MIRR_CNT_L"},
549 {true, "VLAN_MIRR_CNT_H"},
550
551 {true, "IG_MIRR_CNT_L"},
552 {true, "IG_MIRR_CNT_H"},
553 {true, "EG_MIRR_CNT_L"},
554 {true, "EG_MIRR_CNT_H"},
555 {true, "RX_DEFAULT_HOST_HIT_CNT_L"},
556 {true, "RX_DEFAULT_HOST_HIT_CNT_H"},
557
558 {true, "LAN_PAIR_CNT_L"},
559 {true, "LAN_PAIR_CNT_H"},
560 {true, "UM_TBL_MC_HIT_PKT_CNT_L"},
561 {true, "UM_TBL_MC_HIT_PKT_CNT_H"},
562 {true, "MTA_TBL_HIT_PKT_CNT_L"},
563 {true, "MTA_TBL_HIT_PKT_CNT_H"},
564
565 {true, "PROMIS_TBL_HIT_PKT_CNT_L"},
566 {true, "PROMIS_TBL_HIT_PKT_CNT_H"},
567 {false, "Reserved"},
568 {false, "Reserved"},
569 {false, "Reserved"},
570 {false, "Reserved"},
571 };
572
573 static const struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = {
574 {false, "Reserved"},
575 {true, "FSM_DFX_ST0"},
576 {true, "FSM_DFX_ST1"},
577 {true, "FSM_DFX_ST2"},
578 {true, "FIFO_DFX_ST0"},
579 {true, "FIFO_DFX_ST1"},
580
581 {true, "FIFO_DFX_ST2"},
582 {true, "FIFO_DFX_ST3"},
583 {true, "FIFO_DFX_ST4"},
584 {true, "FIFO_DFX_ST5"},
585 {true, "FIFO_DFX_ST6"},
586 {true, "FIFO_DFX_ST7"},
587
588 {true, "FIFO_DFX_ST8"},
589 {true, "FIFO_DFX_ST9"},
590 {true, "FIFO_DFX_ST10"},
591 {true, "FIFO_DFX_ST11"},
592 {true, "Q_CREDIT_VLD_0"},
593 {true, "Q_CREDIT_VLD_1"},
594
595 {true, "Q_CREDIT_VLD_2"},
596 {true, "Q_CREDIT_VLD_3"},
597 {true, "Q_CREDIT_VLD_4"},
598 {true, "Q_CREDIT_VLD_5"},
599 {true, "Q_CREDIT_VLD_6"},
600 {true, "Q_CREDIT_VLD_7"},
601
602 {true, "Q_CREDIT_VLD_8"},
603 {true, "Q_CREDIT_VLD_9"},
604 {true, "Q_CREDIT_VLD_10"},
605 {true, "Q_CREDIT_VLD_11"},
606 {true, "Q_CREDIT_VLD_12"},
607 {true, "Q_CREDIT_VLD_13"},
608
609 {true, "Q_CREDIT_VLD_14"},
610 {true, "Q_CREDIT_VLD_15"},
611 {true, "Q_CREDIT_VLD_16"},
612 {true, "Q_CREDIT_VLD_17"},
613 {true, "Q_CREDIT_VLD_18"},
614 {true, "Q_CREDIT_VLD_19"},
615
616 {true, "Q_CREDIT_VLD_20"},
617 {true, "Q_CREDIT_VLD_21"},
618 {true, "Q_CREDIT_VLD_22"},
619 {true, "Q_CREDIT_VLD_23"},
620 {true, "Q_CREDIT_VLD_24"},
621 {true, "Q_CREDIT_VLD_25"},
622
623 {true, "Q_CREDIT_VLD_26"},
624 {true, "Q_CREDIT_VLD_27"},
625 {true, "Q_CREDIT_VLD_28"},
626 {true, "Q_CREDIT_VLD_29"},
627 {true, "Q_CREDIT_VLD_30"},
628 {true, "Q_CREDIT_VLD_31"},
629
630 {true, "GRO_BD_SERR_CNT"},
631 {true, "GRO_CONTEXT_SERR_CNT"},
632 {true, "RX_STASH_CFG_SERR_CNT"},
633 {true, "AXI_RD_FBD_SERR_CNT"},
634 {true, "GRO_BD_MERR_CNT"},
635 {true, "GRO_CONTEXT_MERR_CNT"},
636
637 {true, "RX_STASH_CFG_MERR_CNT"},
638 {true, "AXI_RD_FBD_MERR_CNT"},
639 {false, "Reserved"},
640 {false, "Reserved"},
641 {false, "Reserved"},
642 {false, "Reserved"},
643 };
644
645 static const struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = {
646 {true, "q_num"},
647 {true, "RCB_CFG_RX_RING_TAIL"},
648 {true, "RCB_CFG_RX_RING_HEAD"},
649 {true, "RCB_CFG_RX_RING_FBDNUM"},
650 {true, "RCB_CFG_RX_RING_OFFSET"},
651 {true, "RCB_CFG_RX_RING_FBDOFFSET"},
652
653 {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"},
654 {true, "RCB_CFG_TX_RING_TAIL"},
655 {true, "RCB_CFG_TX_RING_HEAD"},
656 {true, "RCB_CFG_TX_RING_FBDNUM"},
657 {true, "RCB_CFG_TX_RING_OFFSET"},
658 {true, "RCB_CFG_TX_RING_EBDNUM"},
659 };
660
661 static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = {
662 { .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
663 .dfx_msg = &hclge_dbg_bios_common_reg[0],
664 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_bios_common_reg),
665 .offset = HCLGE_DBG_DFX_BIOS_OFFSET,
666 .cmd = HCLGE_OPC_DFX_BIOS_COMMON_REG } },
667 { .cmd = HNAE3_DBG_CMD_REG_SSU,
668 .dfx_msg = &hclge_dbg_ssu_reg_0[0],
669 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_0),
670 .offset = HCLGE_DBG_DFX_SSU_0_OFFSET,
671 .cmd = HCLGE_OPC_DFX_SSU_REG_0 } },
672 { .cmd = HNAE3_DBG_CMD_REG_SSU,
673 .dfx_msg = &hclge_dbg_ssu_reg_1[0],
674 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_1),
675 .offset = HCLGE_DBG_DFX_SSU_1_OFFSET,
676 .cmd = HCLGE_OPC_DFX_SSU_REG_1 } },
677 { .cmd = HNAE3_DBG_CMD_REG_SSU,
678 .dfx_msg = &hclge_dbg_ssu_reg_2[0],
679 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_2),
680 .offset = HCLGE_DBG_DFX_SSU_2_OFFSET,
681 .cmd = HCLGE_OPC_DFX_SSU_REG_2 } },
682 { .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
683 .dfx_msg = &hclge_dbg_igu_egu_reg[0],
684 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_igu_egu_reg),
685 .offset = HCLGE_DBG_DFX_IGU_OFFSET,
686 .cmd = HCLGE_OPC_DFX_IGU_EGU_REG } },
687 { .cmd = HNAE3_DBG_CMD_REG_RPU,
688 .dfx_msg = &hclge_dbg_rpu_reg_0[0],
689 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_0),
690 .offset = HCLGE_DBG_DFX_RPU_0_OFFSET,
691 .cmd = HCLGE_OPC_DFX_RPU_REG_0 } },
692 { .cmd = HNAE3_DBG_CMD_REG_RPU,
693 .dfx_msg = &hclge_dbg_rpu_reg_1[0],
694 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_1),
695 .offset = HCLGE_DBG_DFX_RPU_1_OFFSET,
696 .cmd = HCLGE_OPC_DFX_RPU_REG_1 } },
697 { .cmd = HNAE3_DBG_CMD_REG_NCSI,
698 .dfx_msg = &hclge_dbg_ncsi_reg[0],
699 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ncsi_reg),
700 .offset = HCLGE_DBG_DFX_NCSI_OFFSET,
701 .cmd = HCLGE_OPC_DFX_NCSI_REG } },
702 { .cmd = HNAE3_DBG_CMD_REG_RTC,
703 .dfx_msg = &hclge_dbg_rtc_reg[0],
704 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rtc_reg),
705 .offset = HCLGE_DBG_DFX_RTC_OFFSET,
706 .cmd = HCLGE_OPC_DFX_RTC_REG } },
707 { .cmd = HNAE3_DBG_CMD_REG_PPP,
708 .dfx_msg = &hclge_dbg_ppp_reg[0],
709 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ppp_reg),
710 .offset = HCLGE_DBG_DFX_PPP_OFFSET,
711 .cmd = HCLGE_OPC_DFX_PPP_REG } },
712 { .cmd = HNAE3_DBG_CMD_REG_RCB,
713 .dfx_msg = &hclge_dbg_rcb_reg[0],
714 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rcb_reg),
715 .offset = HCLGE_DBG_DFX_RCB_OFFSET,
716 .cmd = HCLGE_OPC_DFX_RCB_REG } },
717 { .cmd = HNAE3_DBG_CMD_REG_TQP,
718 .dfx_msg = &hclge_dbg_tqp_reg[0],
719 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_tqp_reg),
720 .offset = HCLGE_DBG_DFX_TQP_OFFSET,
721 .cmd = HCLGE_OPC_DFX_TQP_REG } },
722 };
723
724 /* make sure: len(name) + interval >= maxlen(item data) + 2,
725 * for example, name = "pkt_num"(len: 7), the prototype of item data is u32,
726 * and print as "%u"(maxlen: 10), so the interval should be at least 5.
727 */
hclge_dbg_fill_content(char * content,u16 len,const struct hclge_dbg_item * items,const char ** result,u16 size)728 static void hclge_dbg_fill_content(char *content, u16 len,
729 const struct hclge_dbg_item *items,
730 const char **result, u16 size)
731 {
732 #define HCLGE_DBG_LINE_END_LEN 2
733 char *pos = content;
734 u16 item_len;
735 u16 i;
736
737 if (!len) {
738 return;
739 } else if (len <= HCLGE_DBG_LINE_END_LEN) {
740 *pos++ = '\0';
741 return;
742 }
743
744 memset(content, ' ', len);
745 len -= HCLGE_DBG_LINE_END_LEN;
746
747 for (i = 0; i < size; i++) {
748 item_len = strlen(items[i].name) + items[i].interval;
749 if (len < item_len)
750 break;
751
752 if (result) {
753 if (item_len < strlen(result[i]))
754 break;
755 memcpy(pos, result[i], strlen(result[i]));
756 } else {
757 memcpy(pos, items[i].name, strlen(items[i].name));
758 }
759 pos += item_len;
760 len -= item_len;
761 }
762 *pos++ = '\n';
763 *pos++ = '\0';
764 }
765
hclge_dbg_get_func_id_str(char * buf,u8 id)766 static char *hclge_dbg_get_func_id_str(char *buf, u8 id)
767 {
768 if (id)
769 sprintf(buf, "vf%u", id - 1U);
770 else
771 sprintf(buf, "pf");
772
773 return buf;
774 }
775
hclge_dbg_get_dfx_bd_num(struct hclge_dev * hdev,int offset,u32 * bd_num)776 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset,
777 u32 *bd_num)
778 {
779 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT];
780 int entries_per_desc;
781 int index;
782 int ret;
783
784 ret = hclge_query_bd_num_cmd_send(hdev, desc);
785 if (ret) {
786 dev_err(&hdev->pdev->dev,
787 "failed to get dfx bd_num, offset = %d, ret = %d\n",
788 offset, ret);
789 return ret;
790 }
791
792 entries_per_desc = ARRAY_SIZE(desc[0].data);
793 index = offset % entries_per_desc;
794
795 *bd_num = le32_to_cpu(desc[offset / entries_per_desc].data[index]);
796 if (!(*bd_num)) {
797 dev_err(&hdev->pdev->dev, "The value of dfx bd_num is 0!\n");
798 return -EINVAL;
799 }
800
801 return 0;
802 }
803
hclge_dbg_cmd_send(struct hclge_dev * hdev,struct hclge_desc * desc_src,int index,int bd_num,enum hclge_opcode_type cmd)804 int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,
805 int index, int bd_num, enum hclge_opcode_type cmd)
806 {
807 struct hclge_desc *desc = desc_src;
808 int ret, i;
809
810 hclge_cmd_setup_basic_desc(desc, cmd, true);
811 desc->data[0] = cpu_to_le32(index);
812
813 for (i = 1; i < bd_num; i++) {
814 desc->flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
815 desc++;
816 hclge_cmd_setup_basic_desc(desc, cmd, true);
817 }
818
819 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num);
820 if (ret)
821 dev_err(&hdev->pdev->dev,
822 "cmd(0x%x) send fail, ret = %d\n", cmd, ret);
823 return ret;
824 }
825
826 static int
hclge_dbg_dump_reg_tqp(struct hclge_dev * hdev,const struct hclge_dbg_reg_type_info * reg_info,char * buf,int len,int * pos)827 hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev,
828 const struct hclge_dbg_reg_type_info *reg_info,
829 char *buf, int len, int *pos)
830 {
831 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
832 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg;
833 struct hclge_desc *desc_src;
834 u32 index, entry, i, cnt;
835 int bd_num, min_num, ret;
836 struct hclge_desc *desc;
837
838 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
839 if (ret)
840 return ret;
841
842 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
843 if (!desc_src)
844 return -ENOMEM;
845
846 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num);
847
848 for (i = 0, cnt = 0; i < min_num; i++, dfx_message++)
849 *pos += scnprintf(buf + *pos, len - *pos, "item%u = %s\n",
850 cnt++, dfx_message->message);
851
852 for (i = 0; i < cnt; i++)
853 *pos += scnprintf(buf + *pos, len - *pos, "item%u\t", i);
854
855 *pos += scnprintf(buf + *pos, len - *pos, "\n");
856
857 for (index = 0; index < hdev->vport[0].alloc_tqps; index++) {
858 dfx_message = reg_info->dfx_msg;
859 desc = desc_src;
860 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num,
861 reg_msg->cmd);
862 if (ret)
863 break;
864
865 for (i = 0; i < min_num; i++, dfx_message++) {
866 entry = i % HCLGE_DESC_DATA_LEN;
867 if (i > 0 && !entry)
868 desc++;
869
870 *pos += scnprintf(buf + *pos, len - *pos, "%#x\t",
871 le32_to_cpu(desc->data[entry]));
872 }
873 *pos += scnprintf(buf + *pos, len - *pos, "\n");
874 }
875
876 kfree(desc_src);
877 return ret;
878 }
879
880 static int
hclge_dbg_dump_reg_common(struct hclge_dev * hdev,const struct hclge_dbg_reg_type_info * reg_info,char * buf,int len,int * pos)881 hclge_dbg_dump_reg_common(struct hclge_dev *hdev,
882 const struct hclge_dbg_reg_type_info *reg_info,
883 char *buf, int len, int *pos)
884 {
885 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg;
886 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg;
887 struct hclge_desc *desc_src;
888 int bd_num, min_num, ret;
889 struct hclge_desc *desc;
890 u32 entry, i;
891
892 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num);
893 if (ret)
894 return ret;
895
896 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
897 if (!desc_src)
898 return -ENOMEM;
899
900 desc = desc_src;
901
902 ret = hclge_dbg_cmd_send(hdev, desc, 0, bd_num, reg_msg->cmd);
903 if (ret) {
904 kfree(desc);
905 return ret;
906 }
907
908 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num);
909
910 for (i = 0; i < min_num; i++, dfx_message++) {
911 entry = i % HCLGE_DESC_DATA_LEN;
912 if (i > 0 && !entry)
913 desc++;
914 if (!dfx_message->flag)
915 continue;
916
917 *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n",
918 dfx_message->message,
919 le32_to_cpu(desc->data[entry]));
920 }
921
922 kfree(desc_src);
923 return 0;
924 }
925
926 static const struct hclge_dbg_status_dfx_info hclge_dbg_mac_en_status[] = {
927 {HCLGE_MAC_TX_EN_B, "mac_trans_en"},
928 {HCLGE_MAC_RX_EN_B, "mac_rcv_en"},
929 {HCLGE_MAC_PAD_TX_B, "pad_trans_en"},
930 {HCLGE_MAC_PAD_RX_B, "pad_rcv_en"},
931 {HCLGE_MAC_1588_TX_B, "1588_trans_en"},
932 {HCLGE_MAC_1588_RX_B, "1588_rcv_en"},
933 {HCLGE_MAC_APP_LP_B, "mac_app_loop_en"},
934 {HCLGE_MAC_LINE_LP_B, "mac_line_loop_en"},
935 {HCLGE_MAC_FCS_TX_B, "mac_fcs_tx_en"},
936 {HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, "mac_rx_oversize_truncate_en"},
937 {HCLGE_MAC_RX_FCS_STRIP_B, "mac_rx_fcs_strip_en"},
938 {HCLGE_MAC_RX_FCS_B, "mac_rx_fcs_en"},
939 {HCLGE_MAC_TX_UNDER_MIN_ERR_B, "mac_tx_under_min_err_en"},
940 {HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, "mac_tx_oversize_truncate_en"}
941 };
942
hclge_dbg_dump_mac_enable_status(struct hclge_dev * hdev,char * buf,int len,int * pos)943 static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf,
944 int len, int *pos)
945 {
946 struct hclge_config_mac_mode_cmd *req;
947 struct hclge_desc desc;
948 u32 loop_en, i, offset;
949 int ret;
950
951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
952
953 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
954 if (ret) {
955 dev_err(&hdev->pdev->dev,
956 "failed to dump mac enable status, ret = %d\n", ret);
957 return ret;
958 }
959
960 req = (struct hclge_config_mac_mode_cmd *)desc.data;
961 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
962
963 for (i = 0; i < ARRAY_SIZE(hclge_dbg_mac_en_status); i++) {
964 offset = hclge_dbg_mac_en_status[i].offset;
965 *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n",
966 hclge_dbg_mac_en_status[i].message,
967 hnae3_get_bit(loop_en, offset));
968 }
969
970 return 0;
971 }
972
hclge_dbg_dump_mac_frame_size(struct hclge_dev * hdev,char * buf,int len,int * pos)973 static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf,
974 int len, int *pos)
975 {
976 struct hclge_config_max_frm_size_cmd *req;
977 struct hclge_desc desc;
978 int ret;
979
980 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, true);
981
982 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
983 if (ret) {
984 dev_err(&hdev->pdev->dev,
985 "failed to dump mac frame size, ret = %d\n", ret);
986 return ret;
987 }
988
989 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
990
991 *pos += scnprintf(buf + *pos, len - *pos, "max_frame_size: %u\n",
992 le16_to_cpu(req->max_frm_size));
993 *pos += scnprintf(buf + *pos, len - *pos, "min_frame_size: %u\n",
994 req->min_frm_size);
995
996 return 0;
997 }
998
hclge_dbg_dump_mac_speed_duplex(struct hclge_dev * hdev,char * buf,int len,int * pos)999 static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf,
1000 int len, int *pos)
1001 {
1002 #define HCLGE_MAC_SPEED_SHIFT 0
1003 #define HCLGE_MAC_SPEED_MASK GENMASK(5, 0)
1004 #define HCLGE_MAC_DUPLEX_SHIFT 7
1005
1006 struct hclge_config_mac_speed_dup_cmd *req;
1007 struct hclge_desc desc;
1008 int ret;
1009
1010 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, true);
1011
1012 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1013 if (ret) {
1014 dev_err(&hdev->pdev->dev,
1015 "failed to dump mac speed duplex, ret = %d\n", ret);
1016 return ret;
1017 }
1018
1019 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
1020
1021 *pos += scnprintf(buf + *pos, len - *pos, "speed: %#lx\n",
1022 hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK,
1023 HCLGE_MAC_SPEED_SHIFT));
1024 *pos += scnprintf(buf + *pos, len - *pos, "duplex: %#x\n",
1025 hnae3_get_bit(req->speed_dup,
1026 HCLGE_MAC_DUPLEX_SHIFT));
1027 return 0;
1028 }
1029
hclge_dbg_dump_mac(struct hclge_dev * hdev,char * buf,int len)1030 static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len)
1031 {
1032 int pos = 0;
1033 int ret;
1034
1035 ret = hclge_dbg_dump_mac_enable_status(hdev, buf, len, &pos);
1036 if (ret)
1037 return ret;
1038
1039 ret = hclge_dbg_dump_mac_frame_size(hdev, buf, len, &pos);
1040 if (ret)
1041 return ret;
1042
1043 return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos);
1044 }
1045
hclge_dbg_dump_dcb_qset(struct hclge_dev * hdev,char * buf,int len,int * pos)1046 static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len,
1047 int *pos)
1048 {
1049 struct hclge_dbg_bitmap_cmd req;
1050 struct hclge_desc desc;
1051 u16 qset_id, qset_num;
1052 int ret;
1053
1054 ret = hclge_tm_get_qset_num(hdev, &qset_num);
1055 if (ret)
1056 return ret;
1057
1058 *pos += scnprintf(buf + *pos, len - *pos,
1059 "qset_id roce_qset_mask nic_qset_mask qset_shaping_pass qset_bp_status\n");
1060 for (qset_id = 0; qset_id < qset_num; qset_id++) {
1061 ret = hclge_dbg_cmd_send(hdev, &desc, qset_id, 1,
1062 HCLGE_OPC_QSET_DFX_STS);
1063 if (ret)
1064 return ret;
1065
1066 req.bitmap = (u8)le32_to_cpu(desc.data[1]);
1067
1068 *pos += scnprintf(buf + *pos, len - *pos,
1069 "%04u %#x %#x %#x %#x\n",
1070 qset_id, req.bit0, req.bit1, req.bit2,
1071 req.bit3);
1072 }
1073
1074 return 0;
1075 }
1076
hclge_dbg_dump_dcb_pri(struct hclge_dev * hdev,char * buf,int len,int * pos)1077 static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len,
1078 int *pos)
1079 {
1080 struct hclge_dbg_bitmap_cmd req;
1081 struct hclge_desc desc;
1082 u8 pri_id, pri_num;
1083 int ret;
1084
1085 ret = hclge_tm_get_pri_num(hdev, &pri_num);
1086 if (ret)
1087 return ret;
1088
1089 *pos += scnprintf(buf + *pos, len - *pos,
1090 "pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n");
1091 for (pri_id = 0; pri_id < pri_num; pri_id++) {
1092 ret = hclge_dbg_cmd_send(hdev, &desc, pri_id, 1,
1093 HCLGE_OPC_PRI_DFX_STS);
1094 if (ret)
1095 return ret;
1096
1097 req.bitmap = (u8)le32_to_cpu(desc.data[1]);
1098
1099 *pos += scnprintf(buf + *pos, len - *pos,
1100 "%03u %#x %#x %#x\n",
1101 pri_id, req.bit0, req.bit1, req.bit2);
1102 }
1103
1104 return 0;
1105 }
1106
hclge_dbg_dump_dcb_pg(struct hclge_dev * hdev,char * buf,int len,int * pos)1107 static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len,
1108 int *pos)
1109 {
1110 struct hclge_dbg_bitmap_cmd req;
1111 struct hclge_desc desc;
1112 u8 pg_id;
1113 int ret;
1114
1115 *pos += scnprintf(buf + *pos, len - *pos,
1116 "pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n");
1117 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) {
1118 ret = hclge_dbg_cmd_send(hdev, &desc, pg_id, 1,
1119 HCLGE_OPC_PG_DFX_STS);
1120 if (ret)
1121 return ret;
1122
1123 req.bitmap = (u8)le32_to_cpu(desc.data[1]);
1124
1125 *pos += scnprintf(buf + *pos, len - *pos,
1126 "%03u %#x %#x %#x\n",
1127 pg_id, req.bit0, req.bit1, req.bit2);
1128 }
1129
1130 return 0;
1131 }
1132
hclge_dbg_dump_dcb_queue(struct hclge_dev * hdev,char * buf,int len,int * pos)1133 static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, char *buf, int len,
1134 int *pos)
1135 {
1136 struct hclge_desc desc;
1137 u16 nq_id;
1138 int ret;
1139
1140 *pos += scnprintf(buf + *pos, len - *pos,
1141 "nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n");
1142 for (nq_id = 0; nq_id < hdev->num_tqps; nq_id++) {
1143 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1,
1144 HCLGE_OPC_SCH_NQ_CNT);
1145 if (ret)
1146 return ret;
1147
1148 *pos += scnprintf(buf + *pos, len - *pos, "%04u %#x",
1149 nq_id, le32_to_cpu(desc.data[1]));
1150
1151 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1,
1152 HCLGE_OPC_SCH_RQ_CNT);
1153 if (ret)
1154 return ret;
1155
1156 *pos += scnprintf(buf + *pos, len - *pos,
1157 " %#x\n",
1158 le32_to_cpu(desc.data[1]));
1159 }
1160
1161 return 0;
1162 }
1163
hclge_dbg_dump_dcb_port(struct hclge_dev * hdev,char * buf,int len,int * pos)1164 static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len,
1165 int *pos)
1166 {
1167 struct hclge_dbg_bitmap_cmd req;
1168 struct hclge_desc desc;
1169 u8 port_id = 0;
1170 int ret;
1171
1172 ret = hclge_dbg_cmd_send(hdev, &desc, port_id, 1,
1173 HCLGE_OPC_PORT_DFX_STS);
1174 if (ret)
1175 return ret;
1176
1177 req.bitmap = (u8)le32_to_cpu(desc.data[1]);
1178
1179 *pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n",
1180 req.bit0);
1181 *pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n",
1182 req.bit1);
1183
1184 return 0;
1185 }
1186
hclge_dbg_dump_dcb_tm(struct hclge_dev * hdev,char * buf,int len,int * pos)1187 static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len,
1188 int *pos)
1189 {
1190 struct hclge_desc desc[2];
1191 u8 port_id = 0;
1192 int ret;
1193
1194 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
1195 HCLGE_OPC_TM_INTERNAL_CNT);
1196 if (ret)
1197 return ret;
1198
1199 *pos += scnprintf(buf + *pos, len - *pos, "SCH_NIC_NUM: %#x\n",
1200 le32_to_cpu(desc[0].data[1]));
1201 *pos += scnprintf(buf + *pos, len - *pos, "SCH_ROCE_NUM: %#x\n",
1202 le32_to_cpu(desc[0].data[2]));
1203
1204 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 2,
1205 HCLGE_OPC_TM_INTERNAL_STS);
1206 if (ret)
1207 return ret;
1208
1209 *pos += scnprintf(buf + *pos, len - *pos, "pri_bp: %#x\n",
1210 le32_to_cpu(desc[0].data[1]));
1211 *pos += scnprintf(buf + *pos, len - *pos, "fifo_dfx_info: %#x\n",
1212 le32_to_cpu(desc[0].data[2]));
1213 *pos += scnprintf(buf + *pos, len - *pos,
1214 "sch_roce_fifo_afull_gap: %#x\n",
1215 le32_to_cpu(desc[0].data[3]));
1216 *pos += scnprintf(buf + *pos, len - *pos,
1217 "tx_private_waterline: %#x\n",
1218 le32_to_cpu(desc[0].data[4]));
1219 *pos += scnprintf(buf + *pos, len - *pos, "tm_bypass_en: %#x\n",
1220 le32_to_cpu(desc[0].data[5]));
1221 *pos += scnprintf(buf + *pos, len - *pos, "SSU_TM_BYPASS_EN: %#x\n",
1222 le32_to_cpu(desc[1].data[0]));
1223 *pos += scnprintf(buf + *pos, len - *pos, "SSU_RESERVE_CFG: %#x\n",
1224 le32_to_cpu(desc[1].data[1]));
1225
1226 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER)
1227 return 0;
1228
1229 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1,
1230 HCLGE_OPC_TM_INTERNAL_STS_1);
1231 if (ret)
1232 return ret;
1233
1234 *pos += scnprintf(buf + *pos, len - *pos, "TC_MAP_SEL: %#x\n",
1235 le32_to_cpu(desc[0].data[1]));
1236 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PFC_PRI_EN: %#x\n",
1237 le32_to_cpu(desc[0].data[2]));
1238 *pos += scnprintf(buf + *pos, len - *pos, "MAC_PFC_PRI_EN: %#x\n",
1239 le32_to_cpu(desc[0].data[3]));
1240 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PRI_MAP_TC_CFG: %#x\n",
1241 le32_to_cpu(desc[0].data[4]));
1242 *pos += scnprintf(buf + *pos, len - *pos,
1243 "IGU_TX_PRI_MAP_TC_CFG: %#x\n",
1244 le32_to_cpu(desc[0].data[5]));
1245
1246 return 0;
1247 }
1248
hclge_dbg_dump_dcb(struct hclge_dev * hdev,char * buf,int len)1249 static int hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *buf, int len)
1250 {
1251 int pos = 0;
1252 int ret;
1253
1254 ret = hclge_dbg_dump_dcb_qset(hdev, buf, len, &pos);
1255 if (ret)
1256 return ret;
1257
1258 ret = hclge_dbg_dump_dcb_pri(hdev, buf, len, &pos);
1259 if (ret)
1260 return ret;
1261
1262 ret = hclge_dbg_dump_dcb_pg(hdev, buf, len, &pos);
1263 if (ret)
1264 return ret;
1265
1266 ret = hclge_dbg_dump_dcb_queue(hdev, buf, len, &pos);
1267 if (ret)
1268 return ret;
1269
1270 ret = hclge_dbg_dump_dcb_port(hdev, buf, len, &pos);
1271 if (ret)
1272 return ret;
1273
1274 return hclge_dbg_dump_dcb_tm(hdev, buf, len, &pos);
1275 }
1276
hclge_dbg_dump_reg_cmd(struct hclge_dev * hdev,enum hnae3_dbg_cmd cmd,char * buf,int len)1277 static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev,
1278 enum hnae3_dbg_cmd cmd, char *buf, int len)
1279 {
1280 const struct hclge_dbg_reg_type_info *reg_info;
1281 int pos = 0, ret = 0;
1282 int i;
1283
1284 for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) {
1285 reg_info = &hclge_dbg_reg_info[i];
1286 if (cmd == reg_info->cmd) {
1287 if (cmd == HNAE3_DBG_CMD_REG_TQP)
1288 return hclge_dbg_dump_reg_tqp(hdev, reg_info,
1289 buf, len, &pos);
1290
1291 ret = hclge_dbg_dump_reg_common(hdev, reg_info, buf,
1292 len, &pos);
1293 if (ret)
1294 break;
1295 }
1296 }
1297
1298 return ret;
1299 }
1300
hclge_dbg_dump_tc(struct hclge_dev * hdev,char * buf,int len)1301 static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len)
1302 {
1303 struct hclge_ets_tc_weight_cmd *ets_weight;
1304 struct hclge_desc desc;
1305 char *sch_mode_str;
1306 int pos = 0;
1307 int ret;
1308 u8 i;
1309
1310 if (!hnae3_dev_dcb_supported(hdev)) {
1311 dev_err(&hdev->pdev->dev,
1312 "Only DCB-supported dev supports tc\n");
1313 return -EOPNOTSUPP;
1314 }
1315
1316 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true);
1317 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1318 if (ret) {
1319 dev_err(&hdev->pdev->dev, "failed to get tc weight, ret = %d\n",
1320 ret);
1321 return ret;
1322 }
1323
1324 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
1325
1326 pos += scnprintf(buf + pos, len - pos, "enabled tc number: %u\n",
1327 hdev->tm_info.num_tc);
1328 pos += scnprintf(buf + pos, len - pos, "weight_offset: %u\n",
1329 ets_weight->weight_offset);
1330
1331 pos += scnprintf(buf + pos, len - pos, "TC MODE WEIGHT\n");
1332 for (i = 0; i < HNAE3_MAX_TC; i++) {
1333 sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp";
1334 pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n",
1335 i, sch_mode_str, ets_weight->tc_weight[i]);
1336 }
1337
1338 return 0;
1339 }
1340
1341 static const struct hclge_dbg_item tm_pg_items[] = {
1342 { "ID", 2 },
1343 { "PRI_MAP", 2 },
1344 { "MODE", 2 },
1345 { "DWRR", 2 },
1346 { "C_IR_B", 2 },
1347 { "C_IR_U", 2 },
1348 { "C_IR_S", 2 },
1349 { "C_BS_B", 2 },
1350 { "C_BS_S", 2 },
1351 { "C_FLAG", 2 },
1352 { "C_RATE(Mbps)", 2 },
1353 { "P_IR_B", 2 },
1354 { "P_IR_U", 2 },
1355 { "P_IR_S", 2 },
1356 { "P_BS_B", 2 },
1357 { "P_BS_S", 2 },
1358 { "P_FLAG", 2 },
1359 { "P_RATE(Mbps)", 0 }
1360 };
1361
hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para * para,char ** result,u8 * index)1362 static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para,
1363 char **result, u8 *index)
1364 {
1365 sprintf(result[(*index)++], "%3u", para->ir_b);
1366 sprintf(result[(*index)++], "%3u", para->ir_u);
1367 sprintf(result[(*index)++], "%3u", para->ir_s);
1368 sprintf(result[(*index)++], "%3u", para->bs_b);
1369 sprintf(result[(*index)++], "%3u", para->bs_s);
1370 sprintf(result[(*index)++], "%3u", para->flag);
1371 sprintf(result[(*index)++], "%6u", para->rate);
1372 }
1373
__hclge_dbg_dump_tm_pg(struct hclge_dev * hdev,char * data_str,char * buf,int len)1374 static int __hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *data_str,
1375 char *buf, int len)
1376 {
1377 struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
1378 char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str;
1379 u8 pg_id, sch_mode, weight, pri_bit_map, i, j;
1380 char content[HCLGE_DBG_TM_INFO_LEN];
1381 int pos = 0;
1382 int ret;
1383
1384 for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++) {
1385 result[i] = data_str;
1386 data_str += HCLGE_DBG_DATA_STR_LEN;
1387 }
1388
1389 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items,
1390 NULL, ARRAY_SIZE(tm_pg_items));
1391 pos += scnprintf(buf + pos, len - pos, "%s", content);
1392
1393 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) {
1394 ret = hclge_tm_get_pg_to_pri_map(hdev, pg_id, &pri_bit_map);
1395 if (ret)
1396 return ret;
1397
1398 ret = hclge_tm_get_pg_sch_mode(hdev, pg_id, &sch_mode);
1399 if (ret)
1400 return ret;
1401
1402 ret = hclge_tm_get_pg_weight(hdev, pg_id, &weight);
1403 if (ret)
1404 return ret;
1405
1406 ret = hclge_tm_get_pg_shaper(hdev, pg_id,
1407 HCLGE_OPC_TM_PG_C_SHAPPING,
1408 &c_shaper_para);
1409 if (ret)
1410 return ret;
1411
1412 ret = hclge_tm_get_pg_shaper(hdev, pg_id,
1413 HCLGE_OPC_TM_PG_P_SHAPPING,
1414 &p_shaper_para);
1415 if (ret)
1416 return ret;
1417
1418 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
1419 "sp";
1420
1421 j = 0;
1422 sprintf(result[j++], "%02u", pg_id);
1423 sprintf(result[j++], "0x%02x", pri_bit_map);
1424 sprintf(result[j++], "%4s", sch_mode_str);
1425 sprintf(result[j++], "%3u", weight);
1426 hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j);
1427 hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j);
1428
1429 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items,
1430 (const char **)result,
1431 ARRAY_SIZE(tm_pg_items));
1432 pos += scnprintf(buf + pos, len - pos, "%s", content);
1433 }
1434
1435 return 0;
1436 }
1437
hclge_dbg_dump_tm_pg(struct hclge_dev * hdev,char * buf,int len)1438 static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len)
1439 {
1440 char *data_str;
1441 int ret;
1442
1443 data_str = kcalloc(ARRAY_SIZE(tm_pg_items),
1444 HCLGE_DBG_DATA_STR_LEN, GFP_KERNEL);
1445 if (!data_str)
1446 return -ENOMEM;
1447
1448 ret = __hclge_dbg_dump_tm_pg(hdev, data_str, buf, len);
1449
1450 kfree(data_str);
1451
1452 return ret;
1453 }
1454
hclge_dbg_dump_tm_port(struct hclge_dev * hdev,char * buf,int len)1455 static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev, char *buf, int len)
1456 {
1457 struct hclge_tm_shaper_para shaper_para;
1458 int pos = 0;
1459 int ret;
1460
1461 ret = hclge_tm_get_port_shaper(hdev, &shaper_para);
1462 if (ret)
1463 return ret;
1464
1465 pos += scnprintf(buf + pos, len - pos,
1466 "IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n");
1467 pos += scnprintf(buf + pos, len - pos,
1468 "%3u %3u %3u %3u %3u %1u %6u\n",
1469 shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s,
1470 shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag,
1471 shaper_para.rate);
1472
1473 return 0;
1474 }
1475
hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev * hdev,u8 tc_id,char * buf,int len)1476 static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id,
1477 char *buf, int len)
1478 {
1479 u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM];
1480 struct hclge_bp_to_qs_map_cmd *map;
1481 struct hclge_desc desc;
1482 int pos = 0;
1483 u8 group_id;
1484 u8 grp_num;
1485 u16 i = 0;
1486 int ret;
1487
1488 grp_num = hdev->num_tqps <= HCLGE_TQP_MAX_SIZE_DEV_V2 ?
1489 HCLGE_BP_GRP_NUM : HCLGE_BP_EXT_GRP_NUM;
1490 map = (struct hclge_bp_to_qs_map_cmd *)desc.data;
1491 for (group_id = 0; group_id < grp_num; group_id++) {
1492 hclge_cmd_setup_basic_desc(&desc,
1493 HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
1494 true);
1495 map->tc_id = tc_id;
1496 map->qs_group_id = group_id;
1497 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1498 if (ret) {
1499 dev_err(&hdev->pdev->dev,
1500 "failed to get bp to qset map, ret = %d\n",
1501 ret);
1502 return ret;
1503 }
1504
1505 qset_mapping[group_id] = le32_to_cpu(map->qs_bit_map);
1506 }
1507
1508 pos += scnprintf(buf + pos, len - pos, "INDEX | TM BP QSET MAPPING:\n");
1509 for (group_id = 0; group_id < grp_num / 8; group_id++) {
1510 pos += scnprintf(buf + pos, len - pos,
1511 "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n",
1512 group_id * 256, qset_mapping[i + 7],
1513 qset_mapping[i + 6], qset_mapping[i + 5],
1514 qset_mapping[i + 4], qset_mapping[i + 3],
1515 qset_mapping[i + 2], qset_mapping[i + 1],
1516 qset_mapping[i]);
1517 i += 8;
1518 }
1519
1520 return pos;
1521 }
1522
hclge_dbg_dump_tm_map(struct hclge_dev * hdev,char * buf,int len)1523 static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len)
1524 {
1525 u16 queue_id;
1526 u16 qset_id;
1527 u8 link_vld;
1528 int pos = 0;
1529 u8 pri_id;
1530 u8 tc_id;
1531 int ret;
1532
1533 for (queue_id = 0; queue_id < hdev->num_tqps; queue_id++) {
1534 ret = hclge_tm_get_q_to_qs_map(hdev, queue_id, &qset_id);
1535 if (ret)
1536 return ret;
1537
1538 ret = hclge_tm_get_qset_map_pri(hdev, qset_id, &pri_id,
1539 &link_vld);
1540 if (ret)
1541 return ret;
1542
1543 ret = hclge_tm_get_q_to_tc(hdev, queue_id, &tc_id);
1544 if (ret)
1545 return ret;
1546
1547 pos += scnprintf(buf + pos, len - pos,
1548 "QUEUE_ID QSET_ID PRI_ID TC_ID\n");
1549 pos += scnprintf(buf + pos, len - pos,
1550 "%04u %4u %3u %2u\n",
1551 queue_id, qset_id, pri_id, tc_id);
1552
1553 if (!hnae3_dev_dcb_supported(hdev))
1554 continue;
1555
1556 ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, buf + pos,
1557 len - pos);
1558 if (ret < 0)
1559 return ret;
1560 pos += ret;
1561
1562 pos += scnprintf(buf + pos, len - pos, "\n");
1563 }
1564
1565 return 0;
1566 }
1567
hclge_dbg_dump_tm_nodes(struct hclge_dev * hdev,char * buf,int len)1568 static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len)
1569 {
1570 struct hclge_tm_nodes_cmd *nodes;
1571 struct hclge_desc desc;
1572 int pos = 0;
1573 int ret;
1574
1575 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true);
1576 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1577 if (ret) {
1578 dev_err(&hdev->pdev->dev,
1579 "failed to dump tm nodes, ret = %d\n", ret);
1580 return ret;
1581 }
1582
1583 nodes = (struct hclge_tm_nodes_cmd *)desc.data;
1584
1585 pos += scnprintf(buf + pos, len - pos, " BASE_ID MAX_NUM\n");
1586 pos += scnprintf(buf + pos, len - pos, "PG %4u %4u\n",
1587 nodes->pg_base_id, nodes->pg_num);
1588 pos += scnprintf(buf + pos, len - pos, "PRI %4u %4u\n",
1589 nodes->pri_base_id, nodes->pri_num);
1590 pos += scnprintf(buf + pos, len - pos, "QSET %4u %4u\n",
1591 le16_to_cpu(nodes->qset_base_id),
1592 le16_to_cpu(nodes->qset_num));
1593 pos += scnprintf(buf + pos, len - pos, "QUEUE %4u %4u\n",
1594 le16_to_cpu(nodes->queue_base_id),
1595 le16_to_cpu(nodes->queue_num));
1596
1597 return 0;
1598 }
1599
1600 static const struct hclge_dbg_item tm_pri_items[] = {
1601 { "ID", 4 },
1602 { "MODE", 2 },
1603 { "DWRR", 2 },
1604 { "C_IR_B", 2 },
1605 { "C_IR_U", 2 },
1606 { "C_IR_S", 2 },
1607 { "C_BS_B", 2 },
1608 { "C_BS_S", 2 },
1609 { "C_FLAG", 2 },
1610 { "C_RATE(Mbps)", 2 },
1611 { "P_IR_B", 2 },
1612 { "P_IR_U", 2 },
1613 { "P_IR_S", 2 },
1614 { "P_BS_B", 2 },
1615 { "P_BS_S", 2 },
1616 { "P_FLAG", 2 },
1617 { "P_RATE(Mbps)", 0 }
1618 };
1619
hclge_dbg_dump_tm_pri(struct hclge_dev * hdev,char * buf,int len)1620 static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
1621 {
1622 struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
1623 char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str;
1624 char content[HCLGE_DBG_TM_INFO_LEN];
1625 u8 pri_num, sch_mode, weight, i, j;
1626 char *data_str;
1627 int pos, ret;
1628
1629 ret = hclge_tm_get_pri_num(hdev, &pri_num);
1630 if (ret)
1631 return ret;
1632
1633 data_str = kcalloc(ARRAY_SIZE(tm_pri_items), HCLGE_DBG_DATA_STR_LEN,
1634 GFP_KERNEL);
1635 if (!data_str)
1636 return -ENOMEM;
1637
1638 for (i = 0; i < ARRAY_SIZE(tm_pri_items); i++)
1639 result[i] = &data_str[i * HCLGE_DBG_DATA_STR_LEN];
1640
1641 hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
1642 NULL, ARRAY_SIZE(tm_pri_items));
1643 pos = scnprintf(buf, len, "%s", content);
1644
1645 for (i = 0; i < pri_num; i++) {
1646 ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode);
1647 if (ret)
1648 goto out;
1649
1650 ret = hclge_tm_get_pri_weight(hdev, i, &weight);
1651 if (ret)
1652 goto out;
1653
1654 ret = hclge_tm_get_pri_shaper(hdev, i,
1655 HCLGE_OPC_TM_PRI_C_SHAPPING,
1656 &c_shaper_para);
1657 if (ret)
1658 goto out;
1659
1660 ret = hclge_tm_get_pri_shaper(hdev, i,
1661 HCLGE_OPC_TM_PRI_P_SHAPPING,
1662 &p_shaper_para);
1663 if (ret)
1664 goto out;
1665
1666 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
1667 "sp";
1668
1669 j = 0;
1670 sprintf(result[j++], "%04u", i);
1671 sprintf(result[j++], "%4s", sch_mode_str);
1672 sprintf(result[j++], "%3u", weight);
1673 hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j);
1674 hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j);
1675 hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
1676 (const char **)result,
1677 ARRAY_SIZE(tm_pri_items));
1678 pos += scnprintf(buf + pos, len - pos, "%s", content);
1679 }
1680
1681 out:
1682 kfree(data_str);
1683 return ret;
1684 }
1685
1686 static const struct hclge_dbg_item tm_qset_items[] = {
1687 { "ID", 4 },
1688 { "MAP_PRI", 2 },
1689 { "LINK_VLD", 2 },
1690 { "MODE", 2 },
1691 { "DWRR", 2 },
1692 { "IR_B", 2 },
1693 { "IR_U", 2 },
1694 { "IR_S", 2 },
1695 { "BS_B", 2 },
1696 { "BS_S", 2 },
1697 { "FLAG", 2 },
1698 { "RATE(Mbps)", 0 }
1699 };
1700
hclge_dbg_dump_tm_qset(struct hclge_dev * hdev,char * buf,int len)1701 static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len)
1702 {
1703 char data_str[ARRAY_SIZE(tm_qset_items)][HCLGE_DBG_DATA_STR_LEN];
1704 char *result[ARRAY_SIZE(tm_qset_items)], *sch_mode_str;
1705 u8 priority, link_vld, sch_mode, weight;
1706 struct hclge_tm_shaper_para shaper_para;
1707 char content[HCLGE_DBG_TM_INFO_LEN];
1708 u16 qset_num, i;
1709 int ret, pos;
1710 u8 j;
1711
1712 ret = hclge_tm_get_qset_num(hdev, &qset_num);
1713 if (ret)
1714 return ret;
1715
1716 for (i = 0; i < ARRAY_SIZE(tm_qset_items); i++)
1717 result[i] = &data_str[i][0];
1718
1719 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items,
1720 NULL, ARRAY_SIZE(tm_qset_items));
1721 pos = scnprintf(buf, len, "%s", content);
1722
1723 for (i = 0; i < qset_num; i++) {
1724 ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld);
1725 if (ret)
1726 return ret;
1727
1728 ret = hclge_tm_get_qset_sch_mode(hdev, i, &sch_mode);
1729 if (ret)
1730 return ret;
1731
1732 ret = hclge_tm_get_qset_weight(hdev, i, &weight);
1733 if (ret)
1734 return ret;
1735
1736 ret = hclge_tm_get_qset_shaper(hdev, i, &shaper_para);
1737 if (ret)
1738 return ret;
1739
1740 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
1741 "sp";
1742
1743 j = 0;
1744 sprintf(result[j++], "%04u", i);
1745 sprintf(result[j++], "%4u", priority);
1746 sprintf(result[j++], "%4u", link_vld);
1747 sprintf(result[j++], "%4s", sch_mode_str);
1748 sprintf(result[j++], "%3u", weight);
1749 hclge_dbg_fill_shaper_content(&shaper_para, result, &j);
1750
1751 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items,
1752 (const char **)result,
1753 ARRAY_SIZE(tm_qset_items));
1754 pos += scnprintf(buf + pos, len - pos, "%s", content);
1755 }
1756
1757 return 0;
1758 }
1759
hclge_dbg_dump_qos_pause_cfg(struct hclge_dev * hdev,char * buf,int len)1760 static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf,
1761 int len)
1762 {
1763 struct hclge_cfg_pause_param_cmd *pause_param;
1764 struct hclge_desc desc;
1765 int pos = 0;
1766 int ret;
1767
1768 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
1769 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1770 if (ret) {
1771 dev_err(&hdev->pdev->dev,
1772 "failed to dump qos pause, ret = %d\n", ret);
1773 return ret;
1774 }
1775
1776 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
1777
1778 pos += scnprintf(buf + pos, len - pos, "pause_trans_gap: 0x%x\n",
1779 pause_param->pause_trans_gap);
1780 pos += scnprintf(buf + pos, len - pos, "pause_trans_time: 0x%x\n",
1781 le16_to_cpu(pause_param->pause_trans_time));
1782 return 0;
1783 }
1784
1785 #define HCLGE_DBG_TC_MASK 0x0F
1786
hclge_dbg_dump_qos_pri_map(struct hclge_dev * hdev,char * buf,int len)1787 static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf,
1788 int len)
1789 {
1790 #define HCLGE_DBG_TC_BIT_WIDTH 4
1791
1792 struct hclge_qos_pri_map_cmd *pri_map;
1793 struct hclge_desc desc;
1794 int pos = 0;
1795 u8 *pri_tc;
1796 u8 tc, i;
1797 int ret;
1798
1799 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true);
1800 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1801 if (ret) {
1802 dev_err(&hdev->pdev->dev,
1803 "failed to dump qos pri map, ret = %d\n", ret);
1804 return ret;
1805 }
1806
1807 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data;
1808
1809 pos += scnprintf(buf + pos, len - pos, "vlan_to_pri: 0x%x\n",
1810 pri_map->vlan_pri);
1811 pos += scnprintf(buf + pos, len - pos, "PRI TC\n");
1812
1813 pri_tc = (u8 *)pri_map;
1814 for (i = 0; i < HNAE3_MAX_TC; i++) {
1815 tc = pri_tc[i >> 1] >> ((i & 1) * HCLGE_DBG_TC_BIT_WIDTH);
1816 tc &= HCLGE_DBG_TC_MASK;
1817 pos += scnprintf(buf + pos, len - pos, "%u %u\n", i, tc);
1818 }
1819
1820 return 0;
1821 }
1822
hclge_dbg_dump_qos_dscp_map(struct hclge_dev * hdev,char * buf,int len)1823 static int hclge_dbg_dump_qos_dscp_map(struct hclge_dev *hdev, char *buf,
1824 int len)
1825 {
1826 struct hnae3_knic_private_info *kinfo = &hdev->vport[0].nic.kinfo;
1827 struct hclge_desc desc[HCLGE_DSCP_MAP_TC_BD_NUM];
1828 u8 *req0 = (u8 *)desc[0].data;
1829 u8 *req1 = (u8 *)desc[1].data;
1830 u8 dscp_tc[HNAE3_MAX_DSCP];
1831 int pos, ret;
1832 u8 i, j;
1833
1834 pos = scnprintf(buf, len, "tc map mode: %s\n",
1835 tc_map_mode_str[kinfo->tc_map_mode]);
1836
1837 if (kinfo->tc_map_mode != HNAE3_TC_MAP_MODE_DSCP)
1838 return 0;
1839
1840 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QOS_MAP, true);
1841 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1842 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_QOS_MAP, true);
1843 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_DSCP_MAP_TC_BD_NUM);
1844 if (ret) {
1845 dev_err(&hdev->pdev->dev,
1846 "failed to dump qos dscp map, ret = %d\n", ret);
1847 return ret;
1848 }
1849
1850 pos += scnprintf(buf + pos, len - pos, "\nDSCP PRIO TC\n");
1851
1852 /* The low 32 dscp setting use bd0, high 32 dscp setting use bd1 */
1853 for (i = 0; i < HNAE3_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM; i++) {
1854 j = i + HNAE3_MAX_DSCP / HCLGE_DSCP_MAP_TC_BD_NUM;
1855 /* Each dscp setting has 4 bits, so each byte saves two dscp
1856 * setting
1857 */
1858 dscp_tc[i] = req0[i >> 1] >> HCLGE_DSCP_TC_SHIFT(i);
1859 dscp_tc[j] = req1[i >> 1] >> HCLGE_DSCP_TC_SHIFT(i);
1860 dscp_tc[i] &= HCLGE_DBG_TC_MASK;
1861 dscp_tc[j] &= HCLGE_DBG_TC_MASK;
1862 }
1863
1864 for (i = 0; i < HNAE3_MAX_DSCP; i++) {
1865 if (kinfo->dscp_prio[i] == HNAE3_PRIO_ID_INVALID)
1866 continue;
1867
1868 pos += scnprintf(buf + pos, len - pos, " %2u %u %u\n",
1869 i, kinfo->dscp_prio[i], dscp_tc[i]);
1870 }
1871
1872 return 0;
1873 }
1874
hclge_dbg_dump_tx_buf_cfg(struct hclge_dev * hdev,char * buf,int len)1875 static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len)
1876 {
1877 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd;
1878 struct hclge_desc desc;
1879 int pos = 0;
1880 int i, ret;
1881
1882 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, true);
1883 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1884 if (ret) {
1885 dev_err(&hdev->pdev->dev,
1886 "failed to dump tx buf, ret = %d\n", ret);
1887 return ret;
1888 }
1889
1890 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc.data;
1891 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1892 pos += scnprintf(buf + pos, len - pos,
1893 "tx_packet_buf_tc_%d: 0x%x\n", i,
1894 le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i]));
1895
1896 return pos;
1897 }
1898
hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev * hdev,char * buf,int len)1899 static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf,
1900 int len)
1901 {
1902 struct hclge_rx_priv_buff_cmd *rx_buf_cmd;
1903 struct hclge_desc desc;
1904 int pos = 0;
1905 int i, ret;
1906
1907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, true);
1908 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1909 if (ret) {
1910 dev_err(&hdev->pdev->dev,
1911 "failed to dump rx priv buf, ret = %d\n", ret);
1912 return ret;
1913 }
1914
1915 pos += scnprintf(buf + pos, len - pos, "\n");
1916
1917 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc.data;
1918 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1919 pos += scnprintf(buf + pos, len - pos,
1920 "rx_packet_buf_tc_%d: 0x%x\n", i,
1921 le16_to_cpu(rx_buf_cmd->buf_num[i]));
1922
1923 pos += scnprintf(buf + pos, len - pos, "rx_share_buf: 0x%x\n",
1924 le16_to_cpu(rx_buf_cmd->shared_buf));
1925
1926 return pos;
1927 }
1928
hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev * hdev,char * buf,int len)1929 static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf,
1930 int len)
1931 {
1932 struct hclge_rx_com_wl *rx_com_wl;
1933 struct hclge_desc desc;
1934 int pos = 0;
1935 int ret;
1936
1937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, true);
1938 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1939 if (ret) {
1940 dev_err(&hdev->pdev->dev,
1941 "failed to dump rx common wl, ret = %d\n", ret);
1942 return ret;
1943 }
1944
1945 rx_com_wl = (struct hclge_rx_com_wl *)desc.data;
1946 pos += scnprintf(buf + pos, len - pos, "\n");
1947 pos += scnprintf(buf + pos, len - pos,
1948 "rx_com_wl: high: 0x%x, low: 0x%x\n",
1949 le16_to_cpu(rx_com_wl->com_wl.high),
1950 le16_to_cpu(rx_com_wl->com_wl.low));
1951
1952 return pos;
1953 }
1954
hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev * hdev,char * buf,int len)1955 static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf,
1956 int len)
1957 {
1958 struct hclge_rx_com_wl *rx_packet_cnt;
1959 struct hclge_desc desc;
1960 int pos = 0;
1961 int ret;
1962
1963 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_GBL_PKT_CNT, true);
1964 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1965 if (ret) {
1966 dev_err(&hdev->pdev->dev,
1967 "failed to dump rx global pkt cnt, ret = %d\n", ret);
1968 return ret;
1969 }
1970
1971 rx_packet_cnt = (struct hclge_rx_com_wl *)desc.data;
1972 pos += scnprintf(buf + pos, len - pos,
1973 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n",
1974 le16_to_cpu(rx_packet_cnt->com_wl.high),
1975 le16_to_cpu(rx_packet_cnt->com_wl.low));
1976
1977 return pos;
1978 }
1979
hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev * hdev,char * buf,int len)1980 static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf,
1981 int len)
1982 {
1983 struct hclge_rx_priv_wl_buf *rx_priv_wl;
1984 struct hclge_desc desc[2];
1985 int pos = 0;
1986 int i, ret;
1987
1988 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
1989 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
1990 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_PRIV_WL_ALLOC, true);
1991 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1992 if (ret) {
1993 dev_err(&hdev->pdev->dev,
1994 "failed to dump rx priv wl buf, ret = %d\n", ret);
1995 return ret;
1996 }
1997
1998 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data;
1999 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
2000 pos += scnprintf(buf + pos, len - pos,
2001 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i,
2002 le16_to_cpu(rx_priv_wl->tc_wl[i].high),
2003 le16_to_cpu(rx_priv_wl->tc_wl[i].low));
2004
2005 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data;
2006 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
2007 pos += scnprintf(buf + pos, len - pos,
2008 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n",
2009 i + HCLGE_TC_NUM_ONE_DESC,
2010 le16_to_cpu(rx_priv_wl->tc_wl[i].high),
2011 le16_to_cpu(rx_priv_wl->tc_wl[i].low));
2012
2013 return pos;
2014 }
2015
hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev * hdev,char * buf,int len)2016 static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev,
2017 char *buf, int len)
2018 {
2019 struct hclge_rx_com_thrd *rx_com_thrd;
2020 struct hclge_desc desc[2];
2021 int pos = 0;
2022 int i, ret;
2023
2024 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
2025 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2026 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_COM_THRD_ALLOC, true);
2027 ret = hclge_cmd_send(&hdev->hw, desc, 2);
2028 if (ret) {
2029 dev_err(&hdev->pdev->dev,
2030 "failed to dump rx common threshold, ret = %d\n", ret);
2031 return ret;
2032 }
2033
2034 pos += scnprintf(buf + pos, len - pos, "\n");
2035 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data;
2036 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
2037 pos += scnprintf(buf + pos, len - pos,
2038 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i,
2039 le16_to_cpu(rx_com_thrd->com_thrd[i].high),
2040 le16_to_cpu(rx_com_thrd->com_thrd[i].low));
2041
2042 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data;
2043 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++)
2044 pos += scnprintf(buf + pos, len - pos,
2045 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n",
2046 i + HCLGE_TC_NUM_ONE_DESC,
2047 le16_to_cpu(rx_com_thrd->com_thrd[i].high),
2048 le16_to_cpu(rx_com_thrd->com_thrd[i].low));
2049
2050 return pos;
2051 }
2052
hclge_dbg_dump_qos_buf_cfg(struct hclge_dev * hdev,char * buf,int len)2053 static int hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev, char *buf,
2054 int len)
2055 {
2056 int pos = 0;
2057 int ret;
2058
2059 ret = hclge_dbg_dump_tx_buf_cfg(hdev, buf + pos, len - pos);
2060 if (ret < 0)
2061 return ret;
2062 pos += ret;
2063
2064 ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, buf + pos, len - pos);
2065 if (ret < 0)
2066 return ret;
2067 pos += ret;
2068
2069 ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, buf + pos, len - pos);
2070 if (ret < 0)
2071 return ret;
2072 pos += ret;
2073
2074 ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, buf + pos, len - pos);
2075 if (ret < 0)
2076 return ret;
2077 pos += ret;
2078
2079 pos += scnprintf(buf + pos, len - pos, "\n");
2080 if (!hnae3_dev_dcb_supported(hdev))
2081 return 0;
2082
2083 ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, buf + pos, len - pos);
2084 if (ret < 0)
2085 return ret;
2086 pos += ret;
2087
2088 ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, buf + pos,
2089 len - pos);
2090 if (ret < 0)
2091 return ret;
2092
2093 return 0;
2094 }
2095
hclge_dbg_dump_mng_table(struct hclge_dev * hdev,char * buf,int len)2096 static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len)
2097 {
2098 struct hclge_mac_ethertype_idx_rd_cmd *req0;
2099 struct hclge_desc desc;
2100 u32 msg_egress_port;
2101 int pos = 0;
2102 int ret, i;
2103
2104 pos += scnprintf(buf + pos, len - pos,
2105 "entry mac_addr mask ether ");
2106 pos += scnprintf(buf + pos, len - pos,
2107 "mask vlan mask i_map i_dir e_type ");
2108 pos += scnprintf(buf + pos, len - pos, "pf_id vf_id q_id drop\n");
2109
2110 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) {
2111 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD,
2112 true);
2113 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data;
2114 req0->index = cpu_to_le16(i);
2115
2116 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2117 if (ret) {
2118 dev_err(&hdev->pdev->dev,
2119 "failed to dump manage table, ret = %d\n", ret);
2120 return ret;
2121 }
2122
2123 if (!req0->resp_code)
2124 continue;
2125
2126 pos += scnprintf(buf + pos, len - pos, "%02u %pM ",
2127 le16_to_cpu(req0->index), req0->mac_addr);
2128
2129 pos += scnprintf(buf + pos, len - pos,
2130 "%x %04x %x %04x ",
2131 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B),
2132 le16_to_cpu(req0->ethter_type),
2133 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B),
2134 le16_to_cpu(req0->vlan_tag) &
2135 HCLGE_DBG_MNG_VLAN_TAG);
2136
2137 pos += scnprintf(buf + pos, len - pos,
2138 "%x %02x %02x ",
2139 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B),
2140 req0->i_port_bitmap, req0->i_port_direction);
2141
2142 msg_egress_port = le16_to_cpu(req0->egress_port);
2143 pos += scnprintf(buf + pos, len - pos,
2144 "%x %x %02x %04x %x\n",
2145 !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B),
2146 msg_egress_port & HCLGE_DBG_MNG_PF_ID,
2147 (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID,
2148 le16_to_cpu(req0->egress_queue),
2149 !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B));
2150 }
2151
2152 return 0;
2153 }
2154
2155 #define HCLGE_DBG_TCAM_BUF_SIZE 256
2156
hclge_dbg_fd_tcam_read(struct hclge_dev * hdev,bool sel_x,char * tcam_buf,struct hclge_dbg_tcam_msg tcam_msg)2157 static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x,
2158 char *tcam_buf,
2159 struct hclge_dbg_tcam_msg tcam_msg)
2160 {
2161 struct hclge_fd_tcam_config_1_cmd *req1;
2162 struct hclge_fd_tcam_config_2_cmd *req2;
2163 struct hclge_fd_tcam_config_3_cmd *req3;
2164 struct hclge_desc desc[3];
2165 int pos = 0;
2166 int ret, i;
2167 __le32 *req;
2168
2169 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true);
2170 desc[0].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2171 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true);
2172 desc[1].flag |= cpu_to_le16(HCLGE_COMM_CMD_FLAG_NEXT);
2173 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true);
2174
2175 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
2176 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
2177 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
2178
2179 req1->stage = tcam_msg.stage;
2180 req1->xy_sel = sel_x ? 1 : 0;
2181 req1->index = cpu_to_le32(tcam_msg.loc);
2182
2183 ret = hclge_cmd_send(&hdev->hw, desc, 3);
2184 if (ret)
2185 return ret;
2186
2187 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
2188 "read result tcam key %s(%u):\n", sel_x ? "x" : "y",
2189 tcam_msg.loc);
2190
2191 /* tcam_data0 ~ tcam_data1 */
2192 req = (__le32 *)req1->tcam_data;
2193 for (i = 0; i < 2; i++)
2194 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
2195 "%08x\n", le32_to_cpu(*req++));
2196
2197 /* tcam_data2 ~ tcam_data7 */
2198 req = (__le32 *)req2->tcam_data;
2199 for (i = 0; i < 6; i++)
2200 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
2201 "%08x\n", le32_to_cpu(*req++));
2202
2203 /* tcam_data8 ~ tcam_data12 */
2204 req = (__le32 *)req3->tcam_data;
2205 for (i = 0; i < 5; i++)
2206 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos,
2207 "%08x\n", le32_to_cpu(*req++));
2208
2209 return ret;
2210 }
2211
hclge_dbg_get_rules_location(struct hclge_dev * hdev,u16 * rule_locs)2212 static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs)
2213 {
2214 struct hclge_fd_rule *rule;
2215 struct hlist_node *node;
2216 int cnt = 0;
2217
2218 spin_lock_bh(&hdev->fd_rule_lock);
2219 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
2220 rule_locs[cnt] = rule->location;
2221 cnt++;
2222 }
2223 spin_unlock_bh(&hdev->fd_rule_lock);
2224
2225 if (cnt != hdev->hclge_fd_rule_num || cnt == 0)
2226 return -EINVAL;
2227
2228 return cnt;
2229 }
2230
hclge_dbg_dump_fd_tcam(struct hclge_dev * hdev,char * buf,int len)2231 static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len)
2232 {
2233 u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
2234 struct hclge_dbg_tcam_msg tcam_msg;
2235 int i, ret, rule_cnt;
2236 u16 *rule_locs;
2237 char *tcam_buf;
2238 int pos = 0;
2239
2240 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev)) {
2241 dev_err(&hdev->pdev->dev,
2242 "Only FD-supported dev supports dump fd tcam\n");
2243 return -EOPNOTSUPP;
2244 }
2245
2246 if (!hdev->hclge_fd_rule_num || !rule_num)
2247 return 0;
2248
2249 rule_locs = kcalloc(rule_num, sizeof(u16), GFP_KERNEL);
2250 if (!rule_locs)
2251 return -ENOMEM;
2252
2253 tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL);
2254 if (!tcam_buf) {
2255 kfree(rule_locs);
2256 return -ENOMEM;
2257 }
2258
2259 rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs);
2260 if (rule_cnt < 0) {
2261 ret = rule_cnt;
2262 dev_err(&hdev->pdev->dev,
2263 "failed to get rule number, ret = %d\n", ret);
2264 goto out;
2265 }
2266
2267 ret = 0;
2268 for (i = 0; i < rule_cnt; i++) {
2269 tcam_msg.stage = HCLGE_FD_STAGE_1;
2270 tcam_msg.loc = rule_locs[i];
2271
2272 ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg);
2273 if (ret) {
2274 dev_err(&hdev->pdev->dev,
2275 "failed to get fd tcam key x, ret = %d\n", ret);
2276 goto out;
2277 }
2278
2279 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
2280
2281 ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg);
2282 if (ret) {
2283 dev_err(&hdev->pdev->dev,
2284 "failed to get fd tcam key y, ret = %d\n", ret);
2285 goto out;
2286 }
2287
2288 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf);
2289 }
2290
2291 out:
2292 kfree(tcam_buf);
2293 kfree(rule_locs);
2294 return ret;
2295 }
2296
hclge_dbg_dump_fd_counter(struct hclge_dev * hdev,char * buf,int len)2297 static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len)
2298 {
2299 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */
2300 struct hclge_fd_ad_cnt_read_cmd *req;
2301 char str_id[HCLGE_DBG_ID_LEN];
2302 struct hclge_desc desc;
2303 int pos = 0;
2304 int ret;
2305 u64 cnt;
2306 u8 i;
2307
2308 if (!hnae3_ae_dev_fd_supported(hdev->ae_dev))
2309 return -EOPNOTSUPP;
2310
2311 pos += scnprintf(buf + pos, len - pos,
2312 "func_id\thit_times\n");
2313
2314 for (i = 0; i < func_num; i++) {
2315 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_CNT_OP, true);
2316 req = (struct hclge_fd_ad_cnt_read_cmd *)desc.data;
2317 req->index = cpu_to_le16(i);
2318 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2319 if (ret) {
2320 dev_err(&hdev->pdev->dev, "failed to get fd counter, ret = %d\n",
2321 ret);
2322 return ret;
2323 }
2324 cnt = le64_to_cpu(req->cnt);
2325 hclge_dbg_get_func_id_str(str_id, i);
2326 pos += scnprintf(buf + pos, len - pos,
2327 "%s\t%llu\n", str_id, cnt);
2328 }
2329
2330 return 0;
2331 }
2332
2333 static const struct hclge_dbg_status_dfx_info hclge_dbg_rst_info[] = {
2334 {HCLGE_MISC_VECTOR_REG_BASE, "vector0 interrupt enable status"},
2335 {HCLGE_MISC_RESET_STS_REG, "reset interrupt source"},
2336 {HCLGE_MISC_VECTOR_INT_STS, "reset interrupt status"},
2337 {HCLGE_RAS_PF_OTHER_INT_STS_REG, "RAS interrupt status"},
2338 {HCLGE_GLOBAL_RESET_REG, "hardware reset status"},
2339 {HCLGE_NIC_CSQ_DEPTH_REG, "handshake status"},
2340 {HCLGE_FUN_RST_ING, "function reset status"}
2341 };
2342
hclge_dbg_dump_rst_info(struct hclge_dev * hdev,char * buf,int len)2343 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len)
2344 {
2345 u32 i, offset;
2346 int pos = 0;
2347
2348 pos += scnprintf(buf + pos, len - pos, "PF reset count: %u\n",
2349 hdev->rst_stats.pf_rst_cnt);
2350 pos += scnprintf(buf + pos, len - pos, "FLR reset count: %u\n",
2351 hdev->rst_stats.flr_rst_cnt);
2352 pos += scnprintf(buf + pos, len - pos, "GLOBAL reset count: %u\n",
2353 hdev->rst_stats.global_rst_cnt);
2354 pos += scnprintf(buf + pos, len - pos, "IMP reset count: %u\n",
2355 hdev->rst_stats.imp_rst_cnt);
2356 pos += scnprintf(buf + pos, len - pos, "reset done count: %u\n",
2357 hdev->rst_stats.reset_done_cnt);
2358 pos += scnprintf(buf + pos, len - pos, "HW reset done count: %u\n",
2359 hdev->rst_stats.hw_reset_done_cnt);
2360 pos += scnprintf(buf + pos, len - pos, "reset count: %u\n",
2361 hdev->rst_stats.reset_cnt);
2362 pos += scnprintf(buf + pos, len - pos, "reset fail count: %u\n",
2363 hdev->rst_stats.reset_fail_cnt);
2364
2365 for (i = 0; i < ARRAY_SIZE(hclge_dbg_rst_info); i++) {
2366 offset = hclge_dbg_rst_info[i].offset;
2367 pos += scnprintf(buf + pos, len - pos, "%s: 0x%x\n",
2368 hclge_dbg_rst_info[i].message,
2369 hclge_read_dev(&hdev->hw, offset));
2370 }
2371
2372 pos += scnprintf(buf + pos, len - pos, "hdev state: 0x%lx\n",
2373 hdev->state);
2374
2375 return 0;
2376 }
2377
hclge_dbg_dump_serv_info(struct hclge_dev * hdev,char * buf,int len)2378 static int hclge_dbg_dump_serv_info(struct hclge_dev *hdev, char *buf, int len)
2379 {
2380 unsigned long rem_nsec;
2381 int pos = 0;
2382 u64 lc;
2383
2384 lc = local_clock();
2385 rem_nsec = do_div(lc, HCLGE_BILLION_NANO_SECONDS);
2386
2387 pos += scnprintf(buf + pos, len - pos, "local_clock: [%5lu.%06lu]\n",
2388 (unsigned long)lc, rem_nsec / 1000);
2389 pos += scnprintf(buf + pos, len - pos, "delta: %u(ms)\n",
2390 jiffies_to_msecs(jiffies - hdev->last_serv_processed));
2391 pos += scnprintf(buf + pos, len - pos,
2392 "last_service_task_processed: %lu(jiffies)\n",
2393 hdev->last_serv_processed);
2394 pos += scnprintf(buf + pos, len - pos, "last_service_task_cnt: %lu\n",
2395 hdev->serv_processed_cnt);
2396
2397 return 0;
2398 }
2399
hclge_dbg_dump_interrupt(struct hclge_dev * hdev,char * buf,int len)2400 static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len)
2401 {
2402 int pos = 0;
2403
2404 pos += scnprintf(buf + pos, len - pos, "num_nic_msi: %u\n",
2405 hdev->num_nic_msi);
2406 pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n",
2407 hdev->num_roce_msi);
2408 pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n",
2409 hdev->num_msi_used);
2410 pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n",
2411 hdev->num_msi_left);
2412
2413 return 0;
2414 }
2415
hclge_dbg_imp_info_data_print(struct hclge_desc * desc_src,char * buf,int len,u32 bd_num)2416 static void hclge_dbg_imp_info_data_print(struct hclge_desc *desc_src,
2417 char *buf, int len, u32 bd_num)
2418 {
2419 #define HCLGE_DBG_IMP_INFO_PRINT_OFFSET 0x2
2420
2421 struct hclge_desc *desc_index = desc_src;
2422 u32 offset = 0;
2423 int pos = 0;
2424 u32 i, j;
2425
2426 pos += scnprintf(buf + pos, len - pos, "offset | data\n");
2427
2428 for (i = 0; i < bd_num; i++) {
2429 j = 0;
2430 while (j < HCLGE_DESC_DATA_LEN - 1) {
2431 pos += scnprintf(buf + pos, len - pos, "0x%04x | ",
2432 offset);
2433 pos += scnprintf(buf + pos, len - pos, "0x%08x ",
2434 le32_to_cpu(desc_index->data[j++]));
2435 pos += scnprintf(buf + pos, len - pos, "0x%08x\n",
2436 le32_to_cpu(desc_index->data[j++]));
2437 offset += sizeof(u32) * HCLGE_DBG_IMP_INFO_PRINT_OFFSET;
2438 }
2439 desc_index++;
2440 }
2441 }
2442
2443 static int
hclge_dbg_get_imp_stats_info(struct hclge_dev * hdev,char * buf,int len)2444 hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len)
2445 {
2446 struct hclge_get_imp_bd_cmd *req;
2447 struct hclge_desc *desc_src;
2448 struct hclge_desc desc;
2449 u32 bd_num;
2450 int ret;
2451
2452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_STATS_BD, true);
2453
2454 req = (struct hclge_get_imp_bd_cmd *)desc.data;
2455 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2456 if (ret) {
2457 dev_err(&hdev->pdev->dev,
2458 "failed to get imp statistics bd number, ret = %d\n",
2459 ret);
2460 return ret;
2461 }
2462
2463 bd_num = le32_to_cpu(req->bd_num);
2464 if (!bd_num) {
2465 dev_err(&hdev->pdev->dev, "imp statistics bd number is 0!\n");
2466 return -EINVAL;
2467 }
2468
2469 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
2470 if (!desc_src)
2471 return -ENOMEM;
2472
2473 ret = hclge_dbg_cmd_send(hdev, desc_src, 0, bd_num,
2474 HCLGE_OPC_IMP_STATS_INFO);
2475 if (ret) {
2476 kfree(desc_src);
2477 dev_err(&hdev->pdev->dev,
2478 "failed to get imp statistics, ret = %d\n", ret);
2479 return ret;
2480 }
2481
2482 hclge_dbg_imp_info_data_print(desc_src, buf, len, bd_num);
2483
2484 kfree(desc_src);
2485
2486 return 0;
2487 }
2488
2489 #define HCLGE_CMD_NCL_CONFIG_BD_NUM 5
2490 #define HCLGE_MAX_NCL_CONFIG_LENGTH 16384
2491
hclge_ncl_config_data_print(struct hclge_desc * desc,int * index,char * buf,int len,int * pos)2492 static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index,
2493 char *buf, int len, int *pos)
2494 {
2495 #define HCLGE_CMD_DATA_NUM 6
2496
2497 int offset = HCLGE_MAX_NCL_CONFIG_LENGTH - *index;
2498 int i, j;
2499
2500 for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) {
2501 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) {
2502 if (i == 0 && j == 0)
2503 continue;
2504
2505 *pos += scnprintf(buf + *pos, len - *pos,
2506 "0x%04x | 0x%08x\n", offset,
2507 le32_to_cpu(desc[i].data[j]));
2508
2509 offset += sizeof(u32);
2510 *index -= sizeof(u32);
2511
2512 if (*index <= 0)
2513 return;
2514 }
2515 }
2516 }
2517
2518 static int
hclge_dbg_dump_ncl_config(struct hclge_dev * hdev,char * buf,int len)2519 hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, char *buf, int len)
2520 {
2521 #define HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD (20 + 24 * 4)
2522
2523 struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM];
2524 int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM;
2525 int index = HCLGE_MAX_NCL_CONFIG_LENGTH;
2526 int pos = 0;
2527 u32 data0;
2528 int ret;
2529
2530 pos += scnprintf(buf + pos, len - pos, "offset | data\n");
2531
2532 while (index > 0) {
2533 data0 = HCLGE_MAX_NCL_CONFIG_LENGTH - index;
2534 if (index >= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD)
2535 data0 |= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD << 16;
2536 else
2537 data0 |= (u32)index << 16;
2538 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num,
2539 HCLGE_OPC_QUERY_NCL_CONFIG);
2540 if (ret)
2541 return ret;
2542
2543 hclge_ncl_config_data_print(desc, &index, buf, len, &pos);
2544 }
2545
2546 return 0;
2547 }
2548
hclge_dbg_dump_loopback(struct hclge_dev * hdev,char * buf,int len)2549 static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len)
2550 {
2551 struct phy_device *phydev = hdev->hw.mac.phydev;
2552 struct hclge_config_mac_mode_cmd *req_app;
2553 struct hclge_common_lb_cmd *req_common;
2554 struct hclge_desc desc;
2555 u8 loopback_en;
2556 int pos = 0;
2557 int ret;
2558
2559 req_app = (struct hclge_config_mac_mode_cmd *)desc.data;
2560 req_common = (struct hclge_common_lb_cmd *)desc.data;
2561
2562 pos += scnprintf(buf + pos, len - pos, "mac id: %u\n",
2563 hdev->hw.mac.mac_id);
2564
2565 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
2566 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2567 if (ret) {
2568 dev_err(&hdev->pdev->dev,
2569 "failed to dump app loopback status, ret = %d\n", ret);
2570 return ret;
2571 }
2572
2573 loopback_en = hnae3_get_bit(le32_to_cpu(req_app->txrx_pad_fcs_loop_en),
2574 HCLGE_MAC_APP_LP_B);
2575 pos += scnprintf(buf + pos, len - pos, "app loopback: %s\n",
2576 state_str[loopback_en]);
2577
2578 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, true);
2579 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2580 if (ret) {
2581 dev_err(&hdev->pdev->dev,
2582 "failed to dump common loopback status, ret = %d\n",
2583 ret);
2584 return ret;
2585 }
2586
2587 loopback_en = req_common->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
2588 pos += scnprintf(buf + pos, len - pos, "serdes serial loopback: %s\n",
2589 state_str[loopback_en]);
2590
2591 loopback_en = req_common->enable &
2592 HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0;
2593 pos += scnprintf(buf + pos, len - pos, "serdes parallel loopback: %s\n",
2594 state_str[loopback_en]);
2595
2596 if (phydev) {
2597 loopback_en = phydev->loopback_enabled;
2598 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n",
2599 state_str[loopback_en]);
2600 } else if (hnae3_dev_phy_imp_supported(hdev)) {
2601 loopback_en = req_common->enable &
2602 HCLGE_CMD_GE_PHY_INNER_LOOP_B;
2603 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n",
2604 state_str[loopback_en]);
2605 }
2606
2607 return 0;
2608 }
2609
2610 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt
2611 * @hdev: pointer to struct hclge_dev
2612 */
2613 static int
hclge_dbg_dump_mac_tnl_status(struct hclge_dev * hdev,char * buf,int len)2614 hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev, char *buf, int len)
2615 {
2616 struct hclge_mac_tnl_stats stats;
2617 unsigned long rem_nsec;
2618 int pos = 0;
2619
2620 pos += scnprintf(buf + pos, len - pos,
2621 "Recently generated mac tnl interruption:\n");
2622
2623 while (kfifo_get(&hdev->mac_tnl_log, &stats)) {
2624 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS);
2625
2626 pos += scnprintf(buf + pos, len - pos,
2627 "[%07lu.%03lu] status = 0x%x\n",
2628 (unsigned long)stats.time, rem_nsec / 1000,
2629 stats.status);
2630 }
2631
2632 return 0;
2633 }
2634
2635
2636 static const struct hclge_dbg_item mac_list_items[] = {
2637 { "FUNC_ID", 2 },
2638 { "MAC_ADDR", 12 },
2639 { "STATE", 2 },
2640 };
2641
hclge_dbg_dump_mac_list(struct hclge_dev * hdev,char * buf,int len,bool is_unicast)2642 static void hclge_dbg_dump_mac_list(struct hclge_dev *hdev, char *buf, int len,
2643 bool is_unicast)
2644 {
2645 char data_str[ARRAY_SIZE(mac_list_items)][HCLGE_DBG_DATA_STR_LEN];
2646 char content[HCLGE_DBG_INFO_LEN], str_id[HCLGE_DBG_ID_LEN];
2647 char *result[ARRAY_SIZE(mac_list_items)];
2648 struct hclge_mac_node *mac_node, *tmp;
2649 struct hclge_vport *vport;
2650 struct list_head *list;
2651 u32 func_id;
2652 int pos = 0;
2653 int i;
2654
2655 for (i = 0; i < ARRAY_SIZE(mac_list_items); i++)
2656 result[i] = &data_str[i][0];
2657
2658 pos += scnprintf(buf + pos, len - pos, "%s MAC_LIST:\n",
2659 is_unicast ? "UC" : "MC");
2660 hclge_dbg_fill_content(content, sizeof(content), mac_list_items,
2661 NULL, ARRAY_SIZE(mac_list_items));
2662 pos += scnprintf(buf + pos, len - pos, "%s", content);
2663
2664 for (func_id = 0; func_id < hdev->num_alloc_vport; func_id++) {
2665 vport = &hdev->vport[func_id];
2666 list = is_unicast ? &vport->uc_mac_list : &vport->mc_mac_list;
2667 spin_lock_bh(&vport->mac_list_lock);
2668 list_for_each_entry_safe(mac_node, tmp, list, node) {
2669 i = 0;
2670 result[i++] = hclge_dbg_get_func_id_str(str_id,
2671 func_id);
2672 sprintf(result[i++], "%pM", mac_node->mac_addr);
2673 sprintf(result[i++], "%5s",
2674 hclge_mac_state_str[mac_node->state]);
2675 hclge_dbg_fill_content(content, sizeof(content),
2676 mac_list_items,
2677 (const char **)result,
2678 ARRAY_SIZE(mac_list_items));
2679 pos += scnprintf(buf + pos, len - pos, "%s", content);
2680 }
2681 spin_unlock_bh(&vport->mac_list_lock);
2682 }
2683 }
2684
hclge_dbg_dump_umv_info(struct hclge_dev * hdev,char * buf,int len)2685 static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len)
2686 {
2687 u8 func_num = pci_num_vf(hdev->pdev) + 1;
2688 struct hclge_vport *vport;
2689 int pos = 0;
2690 u8 i;
2691
2692 pos += scnprintf(buf, len, "num_alloc_vport : %u\n",
2693 hdev->num_alloc_vport);
2694 pos += scnprintf(buf + pos, len - pos, "max_umv_size : %u\n",
2695 hdev->max_umv_size);
2696 pos += scnprintf(buf + pos, len - pos, "wanted_umv_size : %u\n",
2697 hdev->wanted_umv_size);
2698 pos += scnprintf(buf + pos, len - pos, "priv_umv_size : %u\n",
2699 hdev->priv_umv_size);
2700
2701 mutex_lock(&hdev->vport_lock);
2702 pos += scnprintf(buf + pos, len - pos, "share_umv_size : %u\n",
2703 hdev->share_umv_size);
2704 for (i = 0; i < func_num; i++) {
2705 vport = &hdev->vport[i];
2706 pos += scnprintf(buf + pos, len - pos,
2707 "vport(%u) used_umv_num : %u\n",
2708 i, vport->used_umv_num);
2709 }
2710 mutex_unlock(&hdev->vport_lock);
2711
2712 pos += scnprintf(buf + pos, len - pos, "used_mc_mac_num : %u\n",
2713 hdev->used_mc_mac_num);
2714
2715 return 0;
2716 }
2717
hclge_get_vlan_rx_offload_cfg(struct hclge_dev * hdev,u8 vf_id,struct hclge_dbg_vlan_cfg * vlan_cfg)2718 static int hclge_get_vlan_rx_offload_cfg(struct hclge_dev *hdev, u8 vf_id,
2719 struct hclge_dbg_vlan_cfg *vlan_cfg)
2720 {
2721 struct hclge_vport_vtag_rx_cfg_cmd *req;
2722 struct hclge_desc desc;
2723 u16 bmap_index;
2724 u8 rx_cfg;
2725 int ret;
2726
2727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, true);
2728
2729 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
2730 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD;
2731 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE;
2732 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE);
2733
2734 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2735 if (ret) {
2736 dev_err(&hdev->pdev->dev,
2737 "failed to get vport%u rxvlan cfg, ret = %d\n",
2738 vf_id, ret);
2739 return ret;
2740 }
2741
2742 rx_cfg = req->vport_vlan_cfg;
2743 vlan_cfg->strip_tag1 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG1_EN_B);
2744 vlan_cfg->strip_tag2 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG2_EN_B);
2745 vlan_cfg->drop_tag1 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG1_EN_B);
2746 vlan_cfg->drop_tag2 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG2_EN_B);
2747 vlan_cfg->pri_only1 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG1_EN_B);
2748 vlan_cfg->pri_only2 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG2_EN_B);
2749
2750 return 0;
2751 }
2752
hclge_get_vlan_tx_offload_cfg(struct hclge_dev * hdev,u8 vf_id,struct hclge_dbg_vlan_cfg * vlan_cfg)2753 static int hclge_get_vlan_tx_offload_cfg(struct hclge_dev *hdev, u8 vf_id,
2754 struct hclge_dbg_vlan_cfg *vlan_cfg)
2755 {
2756 struct hclge_vport_vtag_tx_cfg_cmd *req;
2757 struct hclge_desc desc;
2758 u16 bmap_index;
2759 u8 tx_cfg;
2760 int ret;
2761
2762 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, true);
2763 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
2764 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD;
2765 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE;
2766 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE);
2767
2768 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2769 if (ret) {
2770 dev_err(&hdev->pdev->dev,
2771 "failed to get vport%u txvlan cfg, ret = %d\n",
2772 vf_id, ret);
2773 return ret;
2774 }
2775
2776 tx_cfg = req->vport_vlan_cfg;
2777 vlan_cfg->pvid = le16_to_cpu(req->def_vlan_tag1);
2778
2779 vlan_cfg->accept_tag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG1_B);
2780 vlan_cfg->accept_tag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG2_B);
2781 vlan_cfg->accept_untag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG1_B);
2782 vlan_cfg->accept_untag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG2_B);
2783 vlan_cfg->insert_tag1 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG1_EN_B);
2784 vlan_cfg->insert_tag2 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG2_EN_B);
2785 vlan_cfg->shift_tag = hnae3_get_bit(tx_cfg, HCLGE_TAG_SHIFT_MODE_EN_B);
2786
2787 return 0;
2788 }
2789
hclge_get_vlan_filter_config_cmd(struct hclge_dev * hdev,u8 vlan_type,u8 vf_id,struct hclge_desc * desc)2790 static int hclge_get_vlan_filter_config_cmd(struct hclge_dev *hdev,
2791 u8 vlan_type, u8 vf_id,
2792 struct hclge_desc *desc)
2793 {
2794 struct hclge_vlan_filter_ctrl_cmd *req;
2795 int ret;
2796
2797 hclge_cmd_setup_basic_desc(desc, HCLGE_OPC_VLAN_FILTER_CTRL, true);
2798 req = (struct hclge_vlan_filter_ctrl_cmd *)desc->data;
2799 req->vlan_type = vlan_type;
2800 req->vf_id = vf_id;
2801
2802 ret = hclge_cmd_send(&hdev->hw, desc, 1);
2803 if (ret)
2804 dev_err(&hdev->pdev->dev,
2805 "failed to get vport%u vlan filter config, ret = %d.\n",
2806 vf_id, ret);
2807
2808 return ret;
2809 }
2810
hclge_get_vlan_filter_state(struct hclge_dev * hdev,u8 vlan_type,u8 vf_id,u8 * vlan_fe)2811 static int hclge_get_vlan_filter_state(struct hclge_dev *hdev, u8 vlan_type,
2812 u8 vf_id, u8 *vlan_fe)
2813 {
2814 struct hclge_vlan_filter_ctrl_cmd *req;
2815 struct hclge_desc desc;
2816 int ret;
2817
2818 ret = hclge_get_vlan_filter_config_cmd(hdev, vlan_type, vf_id, &desc);
2819 if (ret)
2820 return ret;
2821
2822 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
2823 *vlan_fe = req->vlan_fe;
2824
2825 return 0;
2826 }
2827
hclge_get_port_vlan_filter_bypass_state(struct hclge_dev * hdev,u8 vf_id,u8 * bypass_en)2828 static int hclge_get_port_vlan_filter_bypass_state(struct hclge_dev *hdev,
2829 u8 vf_id, u8 *bypass_en)
2830 {
2831 struct hclge_port_vlan_filter_bypass_cmd *req;
2832 struct hclge_desc desc;
2833 int ret;
2834
2835 if (!test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps))
2836 return 0;
2837
2838 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, true);
2839 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data;
2840 req->vf_id = vf_id;
2841
2842 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2843 if (ret) {
2844 dev_err(&hdev->pdev->dev,
2845 "failed to get vport%u port vlan filter bypass state, ret = %d.\n",
2846 vf_id, ret);
2847 return ret;
2848 }
2849
2850 *bypass_en = hnae3_get_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B);
2851
2852 return 0;
2853 }
2854
2855 static const struct hclge_dbg_item vlan_filter_items[] = {
2856 { "FUNC_ID", 2 },
2857 { "I_VF_VLAN_FILTER", 2 },
2858 { "E_VF_VLAN_FILTER", 2 },
2859 { "PORT_VLAN_FILTER_BYPASS", 0 }
2860 };
2861
2862 static const struct hclge_dbg_item vlan_offload_items[] = {
2863 { "FUNC_ID", 2 },
2864 { "PVID", 4 },
2865 { "ACCEPT_TAG1", 2 },
2866 { "ACCEPT_TAG2", 2 },
2867 { "ACCEPT_UNTAG1", 2 },
2868 { "ACCEPT_UNTAG2", 2 },
2869 { "INSERT_TAG1", 2 },
2870 { "INSERT_TAG2", 2 },
2871 { "SHIFT_TAG", 2 },
2872 { "STRIP_TAG1", 2 },
2873 { "STRIP_TAG2", 2 },
2874 { "DROP_TAG1", 2 },
2875 { "DROP_TAG2", 2 },
2876 { "PRI_ONLY_TAG1", 2 },
2877 { "PRI_ONLY_TAG2", 0 }
2878 };
2879
hclge_dbg_dump_vlan_filter_config(struct hclge_dev * hdev,char * buf,int len,int * pos)2880 static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf,
2881 int len, int *pos)
2882 {
2883 char content[HCLGE_DBG_VLAN_FLTR_INFO_LEN], str_id[HCLGE_DBG_ID_LEN];
2884 const char *result[ARRAY_SIZE(vlan_filter_items)];
2885 u8 i, j, vlan_fe, bypass, ingress, egress;
2886 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */
2887 int ret;
2888
2889 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_PORT, 0,
2890 &vlan_fe);
2891 if (ret)
2892 return ret;
2893 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B;
2894 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0;
2895
2896 *pos += scnprintf(buf, len, "I_PORT_VLAN_FILTER: %s\n",
2897 state_str[ingress]);
2898 *pos += scnprintf(buf + *pos, len - *pos, "E_PORT_VLAN_FILTER: %s\n",
2899 state_str[egress]);
2900
2901 hclge_dbg_fill_content(content, sizeof(content), vlan_filter_items,
2902 NULL, ARRAY_SIZE(vlan_filter_items));
2903 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
2904
2905 for (i = 0; i < func_num; i++) {
2906 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_VF, i,
2907 &vlan_fe);
2908 if (ret)
2909 return ret;
2910
2911 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B;
2912 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0;
2913 ret = hclge_get_port_vlan_filter_bypass_state(hdev, i, &bypass);
2914 if (ret)
2915 return ret;
2916 j = 0;
2917 result[j++] = hclge_dbg_get_func_id_str(str_id, i);
2918 result[j++] = state_str[ingress];
2919 result[j++] = state_str[egress];
2920 result[j++] =
2921 test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B,
2922 hdev->ae_dev->caps) ? state_str[bypass] : "NA";
2923 hclge_dbg_fill_content(content, sizeof(content),
2924 vlan_filter_items, result,
2925 ARRAY_SIZE(vlan_filter_items));
2926 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
2927 }
2928 *pos += scnprintf(buf + *pos, len - *pos, "\n");
2929
2930 return 0;
2931 }
2932
hclge_dbg_dump_vlan_offload_config(struct hclge_dev * hdev,char * buf,int len,int * pos)2933 static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, char *buf,
2934 int len, int *pos)
2935 {
2936 char str_id[HCLGE_DBG_ID_LEN], str_pvid[HCLGE_DBG_ID_LEN];
2937 const char *result[ARRAY_SIZE(vlan_offload_items)];
2938 char content[HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN];
2939 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */
2940 struct hclge_dbg_vlan_cfg vlan_cfg;
2941 int ret;
2942 u8 i, j;
2943
2944 hclge_dbg_fill_content(content, sizeof(content), vlan_offload_items,
2945 NULL, ARRAY_SIZE(vlan_offload_items));
2946 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
2947
2948 for (i = 0; i < func_num; i++) {
2949 ret = hclge_get_vlan_tx_offload_cfg(hdev, i, &vlan_cfg);
2950 if (ret)
2951 return ret;
2952
2953 ret = hclge_get_vlan_rx_offload_cfg(hdev, i, &vlan_cfg);
2954 if (ret)
2955 return ret;
2956
2957 sprintf(str_pvid, "%u", vlan_cfg.pvid);
2958 j = 0;
2959 result[j++] = hclge_dbg_get_func_id_str(str_id, i);
2960 result[j++] = str_pvid;
2961 result[j++] = state_str[vlan_cfg.accept_tag1];
2962 result[j++] = state_str[vlan_cfg.accept_tag2];
2963 result[j++] = state_str[vlan_cfg.accept_untag1];
2964 result[j++] = state_str[vlan_cfg.accept_untag2];
2965 result[j++] = state_str[vlan_cfg.insert_tag1];
2966 result[j++] = state_str[vlan_cfg.insert_tag2];
2967 result[j++] = state_str[vlan_cfg.shift_tag];
2968 result[j++] = state_str[vlan_cfg.strip_tag1];
2969 result[j++] = state_str[vlan_cfg.strip_tag2];
2970 result[j++] = state_str[vlan_cfg.drop_tag1];
2971 result[j++] = state_str[vlan_cfg.drop_tag2];
2972 result[j++] = state_str[vlan_cfg.pri_only1];
2973 result[j++] = state_str[vlan_cfg.pri_only2];
2974
2975 hclge_dbg_fill_content(content, sizeof(content),
2976 vlan_offload_items, result,
2977 ARRAY_SIZE(vlan_offload_items));
2978 *pos += scnprintf(buf + *pos, len - *pos, "%s", content);
2979 }
2980
2981 return 0;
2982 }
2983
hclge_dbg_dump_vlan_config(struct hclge_dev * hdev,char * buf,int len)2984 static int hclge_dbg_dump_vlan_config(struct hclge_dev *hdev, char *buf,
2985 int len)
2986 {
2987 int pos = 0;
2988 int ret;
2989
2990 ret = hclge_dbg_dump_vlan_filter_config(hdev, buf, len, &pos);
2991 if (ret)
2992 return ret;
2993
2994 return hclge_dbg_dump_vlan_offload_config(hdev, buf, len, &pos);
2995 }
2996
hclge_dbg_dump_ptp_info(struct hclge_dev * hdev,char * buf,int len)2997 static int hclge_dbg_dump_ptp_info(struct hclge_dev *hdev, char *buf, int len)
2998 {
2999 struct hclge_ptp *ptp = hdev->ptp;
3000 u32 sw_cfg = ptp->ptp_cfg;
3001 unsigned int tx_start;
3002 unsigned int last_rx;
3003 int pos = 0;
3004 u32 hw_cfg;
3005 int ret;
3006
3007 pos += scnprintf(buf + pos, len - pos, "phc %s's debug info:\n",
3008 ptp->info.name);
3009 pos += scnprintf(buf + pos, len - pos, "ptp enable: %s\n",
3010 test_bit(HCLGE_PTP_FLAG_EN, &ptp->flags) ?
3011 "yes" : "no");
3012 pos += scnprintf(buf + pos, len - pos, "ptp tx enable: %s\n",
3013 test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ?
3014 "yes" : "no");
3015 pos += scnprintf(buf + pos, len - pos, "ptp rx enable: %s\n",
3016 test_bit(HCLGE_PTP_FLAG_RX_EN, &ptp->flags) ?
3017 "yes" : "no");
3018
3019 last_rx = jiffies_to_msecs(ptp->last_rx);
3020 pos += scnprintf(buf + pos, len - pos, "last rx time: %lu.%lu\n",
3021 last_rx / MSEC_PER_SEC, last_rx % MSEC_PER_SEC);
3022 pos += scnprintf(buf + pos, len - pos, "rx count: %lu\n", ptp->rx_cnt);
3023
3024 tx_start = jiffies_to_msecs(ptp->tx_start);
3025 pos += scnprintf(buf + pos, len - pos, "last tx start time: %lu.%lu\n",
3026 tx_start / MSEC_PER_SEC, tx_start % MSEC_PER_SEC);
3027 pos += scnprintf(buf + pos, len - pos, "tx count: %lu\n", ptp->tx_cnt);
3028 pos += scnprintf(buf + pos, len - pos, "tx skipped count: %lu\n",
3029 ptp->tx_skipped);
3030 pos += scnprintf(buf + pos, len - pos, "tx timeout count: %lu\n",
3031 ptp->tx_timeout);
3032 pos += scnprintf(buf + pos, len - pos, "last tx seqid: %u\n",
3033 ptp->last_tx_seqid);
3034
3035 ret = hclge_ptp_cfg_qry(hdev, &hw_cfg);
3036 if (ret)
3037 return ret;
3038
3039 pos += scnprintf(buf + pos, len - pos, "sw_cfg: %#x, hw_cfg: %#x\n",
3040 sw_cfg, hw_cfg);
3041
3042 pos += scnprintf(buf + pos, len - pos, "tx type: %d, rx filter: %d\n",
3043 ptp->ts_cfg.tx_type, ptp->ts_cfg.rx_filter);
3044
3045 return 0;
3046 }
3047
hclge_dbg_dump_mac_uc(struct hclge_dev * hdev,char * buf,int len)3048 static int hclge_dbg_dump_mac_uc(struct hclge_dev *hdev, char *buf, int len)
3049 {
3050 hclge_dbg_dump_mac_list(hdev, buf, len, true);
3051
3052 return 0;
3053 }
3054
hclge_dbg_dump_mac_mc(struct hclge_dev * hdev,char * buf,int len)3055 static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len)
3056 {
3057 hclge_dbg_dump_mac_list(hdev, buf, len, false);
3058
3059 return 0;
3060 }
3061
3062 static const struct hclge_dbg_func hclge_dbg_cmd_func[] = {
3063 {
3064 .cmd = HNAE3_DBG_CMD_TM_NODES,
3065 .dbg_dump = hclge_dbg_dump_tm_nodes,
3066 },
3067 {
3068 .cmd = HNAE3_DBG_CMD_TM_PRI,
3069 .dbg_dump = hclge_dbg_dump_tm_pri,
3070 },
3071 {
3072 .cmd = HNAE3_DBG_CMD_TM_QSET,
3073 .dbg_dump = hclge_dbg_dump_tm_qset,
3074 },
3075 {
3076 .cmd = HNAE3_DBG_CMD_TM_MAP,
3077 .dbg_dump = hclge_dbg_dump_tm_map,
3078 },
3079 {
3080 .cmd = HNAE3_DBG_CMD_TM_PG,
3081 .dbg_dump = hclge_dbg_dump_tm_pg,
3082 },
3083 {
3084 .cmd = HNAE3_DBG_CMD_TM_PORT,
3085 .dbg_dump = hclge_dbg_dump_tm_port,
3086 },
3087 {
3088 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO,
3089 .dbg_dump = hclge_dbg_dump_tc,
3090 },
3091 {
3092 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG,
3093 .dbg_dump = hclge_dbg_dump_qos_pause_cfg,
3094 },
3095 {
3096 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP,
3097 .dbg_dump = hclge_dbg_dump_qos_pri_map,
3098 },
3099 {
3100 .cmd = HNAE3_DBG_CMD_QOS_DSCP_MAP,
3101 .dbg_dump = hclge_dbg_dump_qos_dscp_map,
3102 },
3103 {
3104 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG,
3105 .dbg_dump = hclge_dbg_dump_qos_buf_cfg,
3106 },
3107 {
3108 .cmd = HNAE3_DBG_CMD_MAC_UC,
3109 .dbg_dump = hclge_dbg_dump_mac_uc,
3110 },
3111 {
3112 .cmd = HNAE3_DBG_CMD_MAC_MC,
3113 .dbg_dump = hclge_dbg_dump_mac_mc,
3114 },
3115 {
3116 .cmd = HNAE3_DBG_CMD_MNG_TBL,
3117 .dbg_dump = hclge_dbg_dump_mng_table,
3118 },
3119 {
3120 .cmd = HNAE3_DBG_CMD_LOOPBACK,
3121 .dbg_dump = hclge_dbg_dump_loopback,
3122 },
3123 {
3124 .cmd = HNAE3_DBG_CMD_PTP_INFO,
3125 .dbg_dump = hclge_dbg_dump_ptp_info,
3126 },
3127 {
3128 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO,
3129 .dbg_dump = hclge_dbg_dump_interrupt,
3130 },
3131 {
3132 .cmd = HNAE3_DBG_CMD_RESET_INFO,
3133 .dbg_dump = hclge_dbg_dump_rst_info,
3134 },
3135 {
3136 .cmd = HNAE3_DBG_CMD_IMP_INFO,
3137 .dbg_dump = hclge_dbg_get_imp_stats_info,
3138 },
3139 {
3140 .cmd = HNAE3_DBG_CMD_NCL_CONFIG,
3141 .dbg_dump = hclge_dbg_dump_ncl_config,
3142 },
3143 {
3144 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON,
3145 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3146 },
3147 {
3148 .cmd = HNAE3_DBG_CMD_REG_SSU,
3149 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3150 },
3151 {
3152 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU,
3153 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3154 },
3155 {
3156 .cmd = HNAE3_DBG_CMD_REG_RPU,
3157 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3158 },
3159 {
3160 .cmd = HNAE3_DBG_CMD_REG_NCSI,
3161 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3162 },
3163 {
3164 .cmd = HNAE3_DBG_CMD_REG_RTC,
3165 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3166 },
3167 {
3168 .cmd = HNAE3_DBG_CMD_REG_PPP,
3169 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3170 },
3171 {
3172 .cmd = HNAE3_DBG_CMD_REG_RCB,
3173 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3174 },
3175 {
3176 .cmd = HNAE3_DBG_CMD_REG_TQP,
3177 .dbg_dump_reg = hclge_dbg_dump_reg_cmd,
3178 },
3179 {
3180 .cmd = HNAE3_DBG_CMD_REG_MAC,
3181 .dbg_dump = hclge_dbg_dump_mac,
3182 },
3183 {
3184 .cmd = HNAE3_DBG_CMD_REG_DCB,
3185 .dbg_dump = hclge_dbg_dump_dcb,
3186 },
3187 {
3188 .cmd = HNAE3_DBG_CMD_FD_TCAM,
3189 .dbg_dump = hclge_dbg_dump_fd_tcam,
3190 },
3191 {
3192 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS,
3193 .dbg_dump = hclge_dbg_dump_mac_tnl_status,
3194 },
3195 {
3196 .cmd = HNAE3_DBG_CMD_SERV_INFO,
3197 .dbg_dump = hclge_dbg_dump_serv_info,
3198 },
3199 {
3200 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG,
3201 .dbg_dump = hclge_dbg_dump_vlan_config,
3202 },
3203 {
3204 .cmd = HNAE3_DBG_CMD_FD_COUNTER,
3205 .dbg_dump = hclge_dbg_dump_fd_counter,
3206 },
3207 {
3208 .cmd = HNAE3_DBG_CMD_UMV_INFO,
3209 .dbg_dump = hclge_dbg_dump_umv_info,
3210 },
3211 };
3212
hclge_dbg_read_cmd(struct hnae3_handle * handle,enum hnae3_dbg_cmd cmd,char * buf,int len)3213 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd,
3214 char *buf, int len)
3215 {
3216 struct hclge_vport *vport = hclge_get_vport(handle);
3217 const struct hclge_dbg_func *cmd_func;
3218 struct hclge_dev *hdev = vport->back;
3219 u32 i;
3220
3221 for (i = 0; i < ARRAY_SIZE(hclge_dbg_cmd_func); i++) {
3222 if (cmd == hclge_dbg_cmd_func[i].cmd) {
3223 cmd_func = &hclge_dbg_cmd_func[i];
3224 if (cmd_func->dbg_dump)
3225 return cmd_func->dbg_dump(hdev, buf, len);
3226 else
3227 return cmd_func->dbg_dump_reg(hdev, cmd, buf,
3228 len);
3229 }
3230 }
3231
3232 dev_err(&hdev->pdev->dev, "invalid command(%d)\n", cmd);
3233 return -EINVAL;
3234 }
3235