1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/device.h> 5 6 #include "hclge_debugfs.h" 7 #include "hclge_err.h" 8 #include "hclge_main.h" 9 #include "hclge_tm.h" 10 #include "hnae3.h" 11 12 static const char * const state_str[] = { "off", "on" }; 13 static const char * const hclge_mac_state_str[] = { 14 "TO_ADD", "TO_DEL", "ACTIVE" 15 }; 16 17 static const struct hclge_dbg_reg_type_info hclge_dbg_reg_info[] = { 18 { .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 19 .dfx_msg = &hclge_dbg_bios_common_reg[0], 20 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_bios_common_reg), 21 .offset = HCLGE_DBG_DFX_BIOS_OFFSET, 22 .cmd = HCLGE_OPC_DFX_BIOS_COMMON_REG } }, 23 { .cmd = HNAE3_DBG_CMD_REG_SSU, 24 .dfx_msg = &hclge_dbg_ssu_reg_0[0], 25 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_0), 26 .offset = HCLGE_DBG_DFX_SSU_0_OFFSET, 27 .cmd = HCLGE_OPC_DFX_SSU_REG_0 } }, 28 { .cmd = HNAE3_DBG_CMD_REG_SSU, 29 .dfx_msg = &hclge_dbg_ssu_reg_1[0], 30 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_1), 31 .offset = HCLGE_DBG_DFX_SSU_1_OFFSET, 32 .cmd = HCLGE_OPC_DFX_SSU_REG_1 } }, 33 { .cmd = HNAE3_DBG_CMD_REG_SSU, 34 .dfx_msg = &hclge_dbg_ssu_reg_2[0], 35 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ssu_reg_2), 36 .offset = HCLGE_DBG_DFX_SSU_2_OFFSET, 37 .cmd = HCLGE_OPC_DFX_SSU_REG_2 } }, 38 { .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 39 .dfx_msg = &hclge_dbg_igu_egu_reg[0], 40 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_igu_egu_reg), 41 .offset = HCLGE_DBG_DFX_IGU_OFFSET, 42 .cmd = HCLGE_OPC_DFX_IGU_EGU_REG } }, 43 { .cmd = HNAE3_DBG_CMD_REG_RPU, 44 .dfx_msg = &hclge_dbg_rpu_reg_0[0], 45 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_0), 46 .offset = HCLGE_DBG_DFX_RPU_0_OFFSET, 47 .cmd = HCLGE_OPC_DFX_RPU_REG_0 } }, 48 { .cmd = HNAE3_DBG_CMD_REG_RPU, 49 .dfx_msg = &hclge_dbg_rpu_reg_1[0], 50 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rpu_reg_1), 51 .offset = HCLGE_DBG_DFX_RPU_1_OFFSET, 52 .cmd = HCLGE_OPC_DFX_RPU_REG_1 } }, 53 { .cmd = HNAE3_DBG_CMD_REG_NCSI, 54 .dfx_msg = &hclge_dbg_ncsi_reg[0], 55 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ncsi_reg), 56 .offset = HCLGE_DBG_DFX_NCSI_OFFSET, 57 .cmd = HCLGE_OPC_DFX_NCSI_REG } }, 58 { .cmd = HNAE3_DBG_CMD_REG_RTC, 59 .dfx_msg = &hclge_dbg_rtc_reg[0], 60 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rtc_reg), 61 .offset = HCLGE_DBG_DFX_RTC_OFFSET, 62 .cmd = HCLGE_OPC_DFX_RTC_REG } }, 63 { .cmd = HNAE3_DBG_CMD_REG_PPP, 64 .dfx_msg = &hclge_dbg_ppp_reg[0], 65 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_ppp_reg), 66 .offset = HCLGE_DBG_DFX_PPP_OFFSET, 67 .cmd = HCLGE_OPC_DFX_PPP_REG } }, 68 { .cmd = HNAE3_DBG_CMD_REG_RCB, 69 .dfx_msg = &hclge_dbg_rcb_reg[0], 70 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_rcb_reg), 71 .offset = HCLGE_DBG_DFX_RCB_OFFSET, 72 .cmd = HCLGE_OPC_DFX_RCB_REG } }, 73 { .cmd = HNAE3_DBG_CMD_REG_TQP, 74 .dfx_msg = &hclge_dbg_tqp_reg[0], 75 .reg_msg = { .msg_num = ARRAY_SIZE(hclge_dbg_tqp_reg), 76 .offset = HCLGE_DBG_DFX_TQP_OFFSET, 77 .cmd = HCLGE_OPC_DFX_TQP_REG } }, 78 }; 79 80 static void hclge_dbg_fill_content(char *content, u16 len, 81 const struct hclge_dbg_item *items, 82 const char **result, u16 size) 83 { 84 char *pos = content; 85 u16 i; 86 87 memset(content, ' ', len); 88 for (i = 0; i < size; i++) { 89 if (result) 90 strncpy(pos, result[i], strlen(result[i])); 91 else 92 strncpy(pos, items[i].name, strlen(items[i].name)); 93 pos += strlen(items[i].name) + items[i].interval; 94 } 95 *pos++ = '\n'; 96 *pos++ = '\0'; 97 } 98 99 static char *hclge_dbg_get_func_id_str(char *buf, u8 id) 100 { 101 if (id) 102 sprintf(buf, "vf%u", id - 1); 103 else 104 sprintf(buf, "pf"); 105 106 return buf; 107 } 108 109 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset, 110 u32 *bd_num) 111 { 112 struct hclge_desc desc[HCLGE_GET_DFX_REG_TYPE_CNT]; 113 int entries_per_desc; 114 int index; 115 int ret; 116 117 ret = hclge_query_bd_num_cmd_send(hdev, desc); 118 if (ret) { 119 dev_err(&hdev->pdev->dev, 120 "failed to get dfx bd_num, offset = %d, ret = %d\n", 121 offset, ret); 122 return ret; 123 } 124 125 entries_per_desc = ARRAY_SIZE(desc[0].data); 126 index = offset % entries_per_desc; 127 128 *bd_num = le32_to_cpu(desc[offset / entries_per_desc].data[index]); 129 if (!(*bd_num)) { 130 dev_err(&hdev->pdev->dev, "The value of dfx bd_num is 0!\n"); 131 return -EINVAL; 132 } 133 134 return 0; 135 } 136 137 static int hclge_dbg_cmd_send(struct hclge_dev *hdev, 138 struct hclge_desc *desc_src, 139 int index, int bd_num, 140 enum hclge_opcode_type cmd) 141 { 142 struct hclge_desc *desc = desc_src; 143 int ret, i; 144 145 hclge_cmd_setup_basic_desc(desc, cmd, true); 146 desc->data[0] = cpu_to_le32(index); 147 148 for (i = 1; i < bd_num; i++) { 149 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 150 desc++; 151 hclge_cmd_setup_basic_desc(desc, cmd, true); 152 } 153 154 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num); 155 if (ret) 156 dev_err(&hdev->pdev->dev, 157 "cmd(0x%x) send fail, ret = %d\n", cmd, ret); 158 return ret; 159 } 160 161 static int 162 hclge_dbg_dump_reg_tqp(struct hclge_dev *hdev, 163 const struct hclge_dbg_reg_type_info *reg_info, 164 char *buf, int len, int *pos) 165 { 166 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; 167 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; 168 struct hclge_desc *desc_src; 169 u32 index, entry, i, cnt; 170 int bd_num, min_num, ret; 171 struct hclge_desc *desc; 172 173 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); 174 if (ret) 175 return ret; 176 177 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 178 if (!desc_src) 179 return -ENOMEM; 180 181 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num); 182 183 for (i = 0, cnt = 0; i < min_num; i++, dfx_message++) 184 *pos += scnprintf(buf + *pos, len - *pos, "item%u = %s\n", 185 cnt++, dfx_message->message); 186 187 for (i = 0; i < cnt; i++) 188 *pos += scnprintf(buf + *pos, len - *pos, "item%u\t", i); 189 190 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 191 192 for (index = 0; index < hdev->vport[0].alloc_tqps; index++) { 193 dfx_message = reg_info->dfx_msg; 194 desc = desc_src; 195 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, 196 reg_msg->cmd); 197 if (ret) 198 break; 199 200 for (i = 0; i < min_num; i++, dfx_message++) { 201 entry = i % HCLGE_DESC_DATA_LEN; 202 if (i > 0 && !entry) 203 desc++; 204 205 *pos += scnprintf(buf + *pos, len - *pos, "%#x\t", 206 le32_to_cpu(desc->data[entry])); 207 } 208 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 209 } 210 211 kfree(desc_src); 212 return ret; 213 } 214 215 static int 216 hclge_dbg_dump_reg_common(struct hclge_dev *hdev, 217 const struct hclge_dbg_reg_type_info *reg_info, 218 char *buf, int len, int *pos) 219 { 220 const struct hclge_dbg_reg_common_msg *reg_msg = ®_info->reg_msg; 221 const struct hclge_dbg_dfx_message *dfx_message = reg_info->dfx_msg; 222 struct hclge_desc *desc_src; 223 int bd_num, min_num, ret; 224 struct hclge_desc *desc; 225 u32 entry, i; 226 227 ret = hclge_dbg_get_dfx_bd_num(hdev, reg_msg->offset, &bd_num); 228 if (ret) 229 return ret; 230 231 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 232 if (!desc_src) 233 return -ENOMEM; 234 235 desc = desc_src; 236 237 ret = hclge_dbg_cmd_send(hdev, desc, 0, bd_num, reg_msg->cmd); 238 if (ret) { 239 kfree(desc); 240 return ret; 241 } 242 243 min_num = min_t(int, bd_num * HCLGE_DESC_DATA_LEN, reg_msg->msg_num); 244 245 for (i = 0; i < min_num; i++, dfx_message++) { 246 entry = i % HCLGE_DESC_DATA_LEN; 247 if (i > 0 && !entry) 248 desc++; 249 if (!dfx_message->flag) 250 continue; 251 252 *pos += scnprintf(buf + *pos, len - *pos, "%s: %#x\n", 253 dfx_message->message, 254 le32_to_cpu(desc->data[entry])); 255 } 256 257 kfree(desc_src); 258 return 0; 259 } 260 261 static int hclge_dbg_dump_mac_enable_status(struct hclge_dev *hdev, char *buf, 262 int len, int *pos) 263 { 264 struct hclge_config_mac_mode_cmd *req; 265 struct hclge_desc desc; 266 u32 loop_en; 267 int ret; 268 269 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 270 271 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 272 if (ret) { 273 dev_err(&hdev->pdev->dev, 274 "failed to dump mac enable status, ret = %d\n", ret); 275 return ret; 276 } 277 278 req = (struct hclge_config_mac_mode_cmd *)desc.data; 279 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); 280 281 *pos += scnprintf(buf + *pos, len - *pos, "mac_trans_en: %#x\n", 282 hnae3_get_bit(loop_en, HCLGE_MAC_TX_EN_B)); 283 *pos += scnprintf(buf + *pos, len - *pos, "mac_rcv_en: %#x\n", 284 hnae3_get_bit(loop_en, HCLGE_MAC_RX_EN_B)); 285 *pos += scnprintf(buf + *pos, len - *pos, "pad_trans_en: %#x\n", 286 hnae3_get_bit(loop_en, HCLGE_MAC_PAD_TX_B)); 287 *pos += scnprintf(buf + *pos, len - *pos, "pad_rcv_en: %#x\n", 288 hnae3_get_bit(loop_en, HCLGE_MAC_PAD_RX_B)); 289 *pos += scnprintf(buf + *pos, len - *pos, "1588_trans_en: %#x\n", 290 hnae3_get_bit(loop_en, HCLGE_MAC_1588_TX_B)); 291 *pos += scnprintf(buf + *pos, len - *pos, "1588_rcv_en: %#x\n", 292 hnae3_get_bit(loop_en, HCLGE_MAC_1588_RX_B)); 293 *pos += scnprintf(buf + *pos, len - *pos, "mac_app_loop_en: %#x\n", 294 hnae3_get_bit(loop_en, HCLGE_MAC_APP_LP_B)); 295 *pos += scnprintf(buf + *pos, len - *pos, "mac_line_loop_en: %#x\n", 296 hnae3_get_bit(loop_en, HCLGE_MAC_LINE_LP_B)); 297 *pos += scnprintf(buf + *pos, len - *pos, "mac_fcs_tx_en: %#x\n", 298 hnae3_get_bit(loop_en, HCLGE_MAC_FCS_TX_B)); 299 *pos += scnprintf(buf + *pos, len - *pos, 300 "mac_rx_oversize_truncate_en: %#x\n", 301 hnae3_get_bit(loop_en, 302 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B)); 303 *pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_strip_en: %#x\n", 304 hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B)); 305 *pos += scnprintf(buf + *pos, len - *pos, "mac_rx_fcs_en: %#x\n", 306 hnae3_get_bit(loop_en, HCLGE_MAC_RX_FCS_B)); 307 *pos += scnprintf(buf + *pos, len - *pos, 308 "mac_tx_under_min_err_en: %#x\n", 309 hnae3_get_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B)); 310 *pos += scnprintf(buf + *pos, len - *pos, 311 "mac_tx_oversize_truncate_en: %#x\n", 312 hnae3_get_bit(loop_en, 313 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B)); 314 315 return 0; 316 } 317 318 static int hclge_dbg_dump_mac_frame_size(struct hclge_dev *hdev, char *buf, 319 int len, int *pos) 320 { 321 struct hclge_config_max_frm_size_cmd *req; 322 struct hclge_desc desc; 323 int ret; 324 325 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, true); 326 327 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 328 if (ret) { 329 dev_err(&hdev->pdev->dev, 330 "failed to dump mac frame size, ret = %d\n", ret); 331 return ret; 332 } 333 334 req = (struct hclge_config_max_frm_size_cmd *)desc.data; 335 336 *pos += scnprintf(buf + *pos, len - *pos, "max_frame_size: %u\n", 337 le16_to_cpu(req->max_frm_size)); 338 *pos += scnprintf(buf + *pos, len - *pos, "min_frame_size: %u\n", 339 req->min_frm_size); 340 341 return 0; 342 } 343 344 static int hclge_dbg_dump_mac_speed_duplex(struct hclge_dev *hdev, char *buf, 345 int len, int *pos) 346 { 347 #define HCLGE_MAC_SPEED_SHIFT 0 348 #define HCLGE_MAC_SPEED_MASK GENMASK(5, 0) 349 #define HCLGE_MAC_DUPLEX_SHIFT 7 350 351 struct hclge_config_mac_speed_dup_cmd *req; 352 struct hclge_desc desc; 353 int ret; 354 355 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, true); 356 357 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 358 if (ret) { 359 dev_err(&hdev->pdev->dev, 360 "failed to dump mac speed duplex, ret = %d\n", ret); 361 return ret; 362 } 363 364 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; 365 366 *pos += scnprintf(buf + *pos, len - *pos, "speed: %#lx\n", 367 hnae3_get_field(req->speed_dup, HCLGE_MAC_SPEED_MASK, 368 HCLGE_MAC_SPEED_SHIFT)); 369 *pos += scnprintf(buf + *pos, len - *pos, "duplex: %#x\n", 370 hnae3_get_bit(req->speed_dup, 371 HCLGE_MAC_DUPLEX_SHIFT)); 372 return 0; 373 } 374 375 static int hclge_dbg_dump_mac(struct hclge_dev *hdev, char *buf, int len) 376 { 377 int pos = 0; 378 int ret; 379 380 ret = hclge_dbg_dump_mac_enable_status(hdev, buf, len, &pos); 381 if (ret) 382 return ret; 383 384 ret = hclge_dbg_dump_mac_frame_size(hdev, buf, len, &pos); 385 if (ret) 386 return ret; 387 388 return hclge_dbg_dump_mac_speed_duplex(hdev, buf, len, &pos); 389 } 390 391 static int hclge_dbg_dump_dcb_qset(struct hclge_dev *hdev, char *buf, int len, 392 int *pos) 393 { 394 struct hclge_dbg_bitmap_cmd *bitmap; 395 struct hclge_desc desc; 396 u16 qset_id, qset_num; 397 int ret; 398 399 ret = hclge_tm_get_qset_num(hdev, &qset_num); 400 if (ret) 401 return ret; 402 403 *pos += scnprintf(buf + *pos, len - *pos, 404 "qset_id roce_qset_mask nic_qset_mask qset_shaping_pass qset_bp_status\n"); 405 for (qset_id = 0; qset_id < qset_num; qset_id++) { 406 ret = hclge_dbg_cmd_send(hdev, &desc, qset_id, 1, 407 HCLGE_OPC_QSET_DFX_STS); 408 if (ret) 409 return ret; 410 411 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 412 413 *pos += scnprintf(buf + *pos, len - *pos, 414 "%04u %#x %#x %#x %#x\n", 415 qset_id, bitmap->bit0, bitmap->bit1, 416 bitmap->bit2, bitmap->bit3); 417 } 418 419 return 0; 420 } 421 422 static int hclge_dbg_dump_dcb_pri(struct hclge_dev *hdev, char *buf, int len, 423 int *pos) 424 { 425 struct hclge_dbg_bitmap_cmd *bitmap; 426 struct hclge_desc desc; 427 u8 pri_id, pri_num; 428 int ret; 429 430 ret = hclge_tm_get_pri_num(hdev, &pri_num); 431 if (ret) 432 return ret; 433 434 *pos += scnprintf(buf + *pos, len - *pos, 435 "pri_id pri_mask pri_cshaping_pass pri_pshaping_pass\n"); 436 for (pri_id = 0; pri_id < pri_num; pri_id++) { 437 ret = hclge_dbg_cmd_send(hdev, &desc, pri_id, 1, 438 HCLGE_OPC_PRI_DFX_STS); 439 if (ret) 440 return ret; 441 442 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 443 444 *pos += scnprintf(buf + *pos, len - *pos, 445 "%03u %#x %#x %#x\n", 446 pri_id, bitmap->bit0, bitmap->bit1, 447 bitmap->bit2); 448 } 449 450 return 0; 451 } 452 453 static int hclge_dbg_dump_dcb_pg(struct hclge_dev *hdev, char *buf, int len, 454 int *pos) 455 { 456 struct hclge_dbg_bitmap_cmd *bitmap; 457 struct hclge_desc desc; 458 u8 pg_id; 459 int ret; 460 461 *pos += scnprintf(buf + *pos, len - *pos, 462 "pg_id pg_mask pg_cshaping_pass pg_pshaping_pass\n"); 463 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { 464 ret = hclge_dbg_cmd_send(hdev, &desc, pg_id, 1, 465 HCLGE_OPC_PG_DFX_STS); 466 if (ret) 467 return ret; 468 469 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 470 471 *pos += scnprintf(buf + *pos, len - *pos, 472 "%03u %#x %#x %#x\n", 473 pg_id, bitmap->bit0, bitmap->bit1, 474 bitmap->bit2); 475 } 476 477 return 0; 478 } 479 480 static int hclge_dbg_dump_dcb_queue(struct hclge_dev *hdev, char *buf, int len, 481 int *pos) 482 { 483 struct hclge_desc desc; 484 u16 nq_id; 485 int ret; 486 487 *pos += scnprintf(buf + *pos, len - *pos, 488 "nq_id sch_nic_queue_cnt sch_roce_queue_cnt\n"); 489 for (nq_id = 0; nq_id < hdev->num_tqps; nq_id++) { 490 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, 491 HCLGE_OPC_SCH_NQ_CNT); 492 if (ret) 493 return ret; 494 495 *pos += scnprintf(buf + *pos, len - *pos, "%04u %#x", 496 nq_id, le32_to_cpu(desc.data[1])); 497 498 ret = hclge_dbg_cmd_send(hdev, &desc, nq_id, 1, 499 HCLGE_OPC_SCH_RQ_CNT); 500 if (ret) 501 return ret; 502 503 *pos += scnprintf(buf + *pos, len - *pos, 504 " %#x\n", 505 le32_to_cpu(desc.data[1])); 506 } 507 508 return 0; 509 } 510 511 static int hclge_dbg_dump_dcb_port(struct hclge_dev *hdev, char *buf, int len, 512 int *pos) 513 { 514 struct hclge_dbg_bitmap_cmd *bitmap; 515 struct hclge_desc desc; 516 u8 port_id = 0; 517 int ret; 518 519 ret = hclge_dbg_cmd_send(hdev, &desc, port_id, 1, 520 HCLGE_OPC_PORT_DFX_STS); 521 if (ret) 522 return ret; 523 524 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc.data[1]; 525 526 *pos += scnprintf(buf + *pos, len - *pos, "port_mask: %#x\n", 527 bitmap->bit0); 528 *pos += scnprintf(buf + *pos, len - *pos, "port_shaping_pass: %#x\n", 529 bitmap->bit1); 530 531 return 0; 532 } 533 534 static int hclge_dbg_dump_dcb_tm(struct hclge_dev *hdev, char *buf, int len, 535 int *pos) 536 { 537 struct hclge_desc desc[2]; 538 u8 port_id = 0; 539 int ret; 540 541 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 542 HCLGE_OPC_TM_INTERNAL_CNT); 543 if (ret) 544 return ret; 545 546 *pos += scnprintf(buf + *pos, len - *pos, "SCH_NIC_NUM: %#x\n", 547 le32_to_cpu(desc[0].data[1])); 548 *pos += scnprintf(buf + *pos, len - *pos, "SCH_ROCE_NUM: %#x\n", 549 le32_to_cpu(desc[0].data[2])); 550 551 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 2, 552 HCLGE_OPC_TM_INTERNAL_STS); 553 if (ret) 554 return ret; 555 556 *pos += scnprintf(buf + *pos, len - *pos, "pri_bp: %#x\n", 557 le32_to_cpu(desc[0].data[1])); 558 *pos += scnprintf(buf + *pos, len - *pos, "fifo_dfx_info: %#x\n", 559 le32_to_cpu(desc[0].data[2])); 560 *pos += scnprintf(buf + *pos, len - *pos, 561 "sch_roce_fifo_afull_gap: %#x\n", 562 le32_to_cpu(desc[0].data[3])); 563 *pos += scnprintf(buf + *pos, len - *pos, 564 "tx_private_waterline: %#x\n", 565 le32_to_cpu(desc[0].data[4])); 566 *pos += scnprintf(buf + *pos, len - *pos, "tm_bypass_en: %#x\n", 567 le32_to_cpu(desc[0].data[5])); 568 *pos += scnprintf(buf + *pos, len - *pos, "SSU_TM_BYPASS_EN: %#x\n", 569 le32_to_cpu(desc[1].data[0])); 570 *pos += scnprintf(buf + *pos, len - *pos, "SSU_RESERVE_CFG: %#x\n", 571 le32_to_cpu(desc[1].data[1])); 572 573 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) 574 return 0; 575 576 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 577 HCLGE_OPC_TM_INTERNAL_STS_1); 578 if (ret) 579 return ret; 580 581 *pos += scnprintf(buf + *pos, len - *pos, "TC_MAP_SEL: %#x\n", 582 le32_to_cpu(desc[0].data[1])); 583 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PFC_PRI_EN: %#x\n", 584 le32_to_cpu(desc[0].data[2])); 585 *pos += scnprintf(buf + *pos, len - *pos, "MAC_PFC_PRI_EN: %#x\n", 586 le32_to_cpu(desc[0].data[3])); 587 *pos += scnprintf(buf + *pos, len - *pos, "IGU_PRI_MAP_TC_CFG: %#x\n", 588 le32_to_cpu(desc[0].data[4])); 589 *pos += scnprintf(buf + *pos, len - *pos, 590 "IGU_TX_PRI_MAP_TC_CFG: %#x\n", 591 le32_to_cpu(desc[0].data[5])); 592 593 return 0; 594 } 595 596 static int hclge_dbg_dump_dcb(struct hclge_dev *hdev, char *buf, int len) 597 { 598 int pos = 0; 599 int ret; 600 601 ret = hclge_dbg_dump_dcb_qset(hdev, buf, len, &pos); 602 if (ret) 603 return ret; 604 605 ret = hclge_dbg_dump_dcb_pri(hdev, buf, len, &pos); 606 if (ret) 607 return ret; 608 609 ret = hclge_dbg_dump_dcb_pg(hdev, buf, len, &pos); 610 if (ret) 611 return ret; 612 613 ret = hclge_dbg_dump_dcb_queue(hdev, buf, len, &pos); 614 if (ret) 615 return ret; 616 617 ret = hclge_dbg_dump_dcb_port(hdev, buf, len, &pos); 618 if (ret) 619 return ret; 620 621 return hclge_dbg_dump_dcb_tm(hdev, buf, len, &pos); 622 } 623 624 static int hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, 625 enum hnae3_dbg_cmd cmd, char *buf, int len) 626 { 627 const struct hclge_dbg_reg_type_info *reg_info; 628 int pos = 0, ret = 0; 629 int i; 630 631 for (i = 0; i < ARRAY_SIZE(hclge_dbg_reg_info); i++) { 632 reg_info = &hclge_dbg_reg_info[i]; 633 if (cmd == reg_info->cmd) { 634 if (cmd == HNAE3_DBG_CMD_REG_TQP) 635 return hclge_dbg_dump_reg_tqp(hdev, reg_info, 636 buf, len, &pos); 637 638 ret = hclge_dbg_dump_reg_common(hdev, reg_info, buf, 639 len, &pos); 640 if (ret) 641 break; 642 } 643 } 644 645 return ret; 646 } 647 648 static int hclge_dbg_dump_tc(struct hclge_dev *hdev, char *buf, int len) 649 { 650 struct hclge_ets_tc_weight_cmd *ets_weight; 651 struct hclge_desc desc; 652 char *sch_mode_str; 653 int pos = 0; 654 int ret; 655 u8 i; 656 657 if (!hnae3_dev_dcb_supported(hdev)) { 658 dev_err(&hdev->pdev->dev, 659 "Only DCB-supported dev supports tc\n"); 660 return -EOPNOTSUPP; 661 } 662 663 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true); 664 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 665 if (ret) { 666 dev_err(&hdev->pdev->dev, "failed to get tc weight, ret = %d\n", 667 ret); 668 return ret; 669 } 670 671 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 672 673 pos += scnprintf(buf + pos, len - pos, "enabled tc number: %u\n", 674 hdev->tm_info.num_tc); 675 pos += scnprintf(buf + pos, len - pos, "weight_offset: %u\n", 676 ets_weight->weight_offset); 677 678 pos += scnprintf(buf + pos, len - pos, "TC MODE WEIGHT\n"); 679 for (i = 0; i < HNAE3_MAX_TC; i++) { 680 sch_mode_str = ets_weight->tc_weight[i] ? "dwrr" : "sp"; 681 pos += scnprintf(buf + pos, len - pos, "%u %4s %3u\n", 682 i, sch_mode_str, 683 hdev->tm_info.pg_info[0].tc_dwrr[i]); 684 } 685 686 return 0; 687 } 688 689 static const struct hclge_dbg_item tm_pg_items[] = { 690 { "ID", 2 }, 691 { "PRI_MAP", 2 }, 692 { "MODE", 2 }, 693 { "DWRR", 2 }, 694 { "C_IR_B", 2 }, 695 { "C_IR_U", 2 }, 696 { "C_IR_S", 2 }, 697 { "C_BS_B", 2 }, 698 { "C_BS_S", 2 }, 699 { "C_FLAG", 2 }, 700 { "C_RATE(Mbps)", 2 }, 701 { "P_IR_B", 2 }, 702 { "P_IR_U", 2 }, 703 { "P_IR_S", 2 }, 704 { "P_BS_B", 2 }, 705 { "P_BS_S", 2 }, 706 { "P_FLAG", 2 }, 707 { "P_RATE(Mbps)", 0 } 708 }; 709 710 static void hclge_dbg_fill_shaper_content(struct hclge_tm_shaper_para *para, 711 char **result, u8 *index) 712 { 713 sprintf(result[(*index)++], "%3u", para->ir_b); 714 sprintf(result[(*index)++], "%3u", para->ir_u); 715 sprintf(result[(*index)++], "%3u", para->ir_s); 716 sprintf(result[(*index)++], "%3u", para->bs_b); 717 sprintf(result[(*index)++], "%3u", para->bs_s); 718 sprintf(result[(*index)++], "%3u", para->flag); 719 sprintf(result[(*index)++], "%6u", para->rate); 720 } 721 722 static int hclge_dbg_dump_tm_pg(struct hclge_dev *hdev, char *buf, int len) 723 { 724 char data_str[ARRAY_SIZE(tm_pg_items)][HCLGE_DBG_DATA_STR_LEN]; 725 struct hclge_tm_shaper_para c_shaper_para, p_shaper_para; 726 char *result[ARRAY_SIZE(tm_pg_items)], *sch_mode_str; 727 u8 pg_id, sch_mode, weight, pri_bit_map, i, j; 728 char content[HCLGE_DBG_TM_INFO_LEN]; 729 int pos = 0; 730 int ret; 731 732 for (i = 0; i < ARRAY_SIZE(tm_pg_items); i++) 733 result[i] = &data_str[i][0]; 734 735 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, 736 NULL, ARRAY_SIZE(tm_pg_items)); 737 pos += scnprintf(buf + pos, len - pos, "%s", content); 738 739 for (pg_id = 0; pg_id < hdev->tm_info.num_pg; pg_id++) { 740 ret = hclge_tm_get_pg_to_pri_map(hdev, pg_id, &pri_bit_map); 741 if (ret) 742 return ret; 743 744 ret = hclge_tm_get_pg_sch_mode(hdev, pg_id, &sch_mode); 745 if (ret) 746 return ret; 747 748 ret = hclge_tm_get_pg_weight(hdev, pg_id, &weight); 749 if (ret) 750 return ret; 751 752 ret = hclge_tm_get_pg_shaper(hdev, pg_id, 753 HCLGE_OPC_TM_PG_C_SHAPPING, 754 &c_shaper_para); 755 if (ret) 756 return ret; 757 758 ret = hclge_tm_get_pg_shaper(hdev, pg_id, 759 HCLGE_OPC_TM_PG_P_SHAPPING, 760 &p_shaper_para); 761 if (ret) 762 return ret; 763 764 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 765 "sp"; 766 767 j = 0; 768 sprintf(result[j++], "%02u", pg_id); 769 sprintf(result[j++], "0x%02x", pri_bit_map); 770 sprintf(result[j++], "%4s", sch_mode_str); 771 sprintf(result[j++], "%3u", weight); 772 hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j); 773 hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j); 774 775 hclge_dbg_fill_content(content, sizeof(content), tm_pg_items, 776 (const char **)result, 777 ARRAY_SIZE(tm_pg_items)); 778 pos += scnprintf(buf + pos, len - pos, "%s", content); 779 } 780 781 return 0; 782 } 783 784 static int hclge_dbg_dump_tm_port(struct hclge_dev *hdev, char *buf, int len) 785 { 786 struct hclge_tm_shaper_para shaper_para; 787 int pos = 0; 788 int ret; 789 790 ret = hclge_tm_get_port_shaper(hdev, &shaper_para); 791 if (ret) 792 return ret; 793 794 pos += scnprintf(buf + pos, len - pos, 795 "IR_B IR_U IR_S BS_B BS_S FLAG RATE(Mbps)\n"); 796 pos += scnprintf(buf + pos, len - pos, 797 "%3u %3u %3u %3u %3u %1u %6u\n", 798 shaper_para.ir_b, shaper_para.ir_u, shaper_para.ir_s, 799 shaper_para.bs_b, shaper_para.bs_s, shaper_para.flag, 800 shaper_para.rate); 801 802 return 0; 803 } 804 805 static int hclge_dbg_dump_tm_bp_qset_map(struct hclge_dev *hdev, u8 tc_id, 806 char *buf, int len) 807 { 808 u32 qset_mapping[HCLGE_BP_EXT_GRP_NUM]; 809 struct hclge_bp_to_qs_map_cmd *map; 810 struct hclge_desc desc; 811 int pos = 0; 812 u8 group_id; 813 u8 grp_num; 814 u16 i = 0; 815 int ret; 816 817 grp_num = hdev->num_tqps <= HCLGE_TQP_MAX_SIZE_DEV_V2 ? 818 HCLGE_BP_GRP_NUM : HCLGE_BP_EXT_GRP_NUM; 819 map = (struct hclge_bp_to_qs_map_cmd *)desc.data; 820 for (group_id = 0; group_id < grp_num; group_id++) { 821 hclge_cmd_setup_basic_desc(&desc, 822 HCLGE_OPC_TM_BP_TO_QSET_MAPPING, 823 true); 824 map->tc_id = tc_id; 825 map->qs_group_id = group_id; 826 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 827 if (ret) { 828 dev_err(&hdev->pdev->dev, 829 "failed to get bp to qset map, ret = %d\n", 830 ret); 831 return ret; 832 } 833 834 qset_mapping[group_id] = le32_to_cpu(map->qs_bit_map); 835 } 836 837 pos += scnprintf(buf + pos, len - pos, "INDEX | TM BP QSET MAPPING:\n"); 838 for (group_id = 0; group_id < grp_num / 8; group_id++) { 839 pos += scnprintf(buf + pos, len - pos, 840 "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", 841 group_id * 256, qset_mapping[i + 7], 842 qset_mapping[i + 6], qset_mapping[i + 5], 843 qset_mapping[i + 4], qset_mapping[i + 3], 844 qset_mapping[i + 2], qset_mapping[i + 1], 845 qset_mapping[i]); 846 i += 8; 847 } 848 849 return pos; 850 } 851 852 static int hclge_dbg_dump_tm_map(struct hclge_dev *hdev, char *buf, int len) 853 { 854 u16 queue_id; 855 u16 qset_id; 856 u8 link_vld; 857 int pos = 0; 858 u8 pri_id; 859 u8 tc_id; 860 int ret; 861 862 for (queue_id = 0; queue_id < hdev->num_tqps; queue_id++) { 863 ret = hclge_tm_get_q_to_qs_map(hdev, queue_id, &qset_id); 864 if (ret) 865 return ret; 866 867 ret = hclge_tm_get_qset_map_pri(hdev, qset_id, &pri_id, 868 &link_vld); 869 if (ret) 870 return ret; 871 872 ret = hclge_tm_get_q_to_tc(hdev, queue_id, &tc_id); 873 if (ret) 874 return ret; 875 876 pos += scnprintf(buf + pos, len - pos, 877 "QUEUE_ID QSET_ID PRI_ID TC_ID\n"); 878 pos += scnprintf(buf + pos, len - pos, 879 "%04u %4u %3u %2u\n", 880 queue_id, qset_id, pri_id, tc_id); 881 882 if (!hnae3_dev_dcb_supported(hdev)) 883 continue; 884 885 ret = hclge_dbg_dump_tm_bp_qset_map(hdev, tc_id, buf + pos, 886 len - pos); 887 if (ret < 0) 888 return ret; 889 pos += ret; 890 891 pos += scnprintf(buf + pos, len - pos, "\n"); 892 } 893 894 return 0; 895 } 896 897 static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) 898 { 899 struct hclge_tm_nodes_cmd *nodes; 900 struct hclge_desc desc; 901 int pos = 0; 902 int ret; 903 904 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NODES, true); 905 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 906 if (ret) { 907 dev_err(&hdev->pdev->dev, 908 "failed to dump tm nodes, ret = %d\n", ret); 909 return ret; 910 } 911 912 nodes = (struct hclge_tm_nodes_cmd *)desc.data; 913 914 pos += scnprintf(buf + pos, len - pos, " BASE_ID MAX_NUM\n"); 915 pos += scnprintf(buf + pos, len - pos, "PG %4u %4u\n", 916 nodes->pg_base_id, nodes->pg_num); 917 pos += scnprintf(buf + pos, len - pos, "PRI %4u %4u\n", 918 nodes->pri_base_id, nodes->pri_num); 919 pos += scnprintf(buf + pos, len - pos, "QSET %4u %4u\n", 920 le16_to_cpu(nodes->qset_base_id), 921 le16_to_cpu(nodes->qset_num)); 922 pos += scnprintf(buf + pos, len - pos, "QUEUE %4u %4u\n", 923 le16_to_cpu(nodes->queue_base_id), 924 le16_to_cpu(nodes->queue_num)); 925 926 return 0; 927 } 928 929 static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len) 930 { 931 struct hclge_tm_shaper_para c_shaper_para; 932 struct hclge_tm_shaper_para p_shaper_para; 933 u8 pri_num, sch_mode, weight; 934 char *sch_mode_str; 935 int pos = 0; 936 int ret; 937 u8 i; 938 939 ret = hclge_tm_get_pri_num(hdev, &pri_num); 940 if (ret) 941 return ret; 942 943 pos += scnprintf(buf + pos, len - pos, 944 "ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B "); 945 pos += scnprintf(buf + pos, len - pos, 946 "C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U "); 947 pos += scnprintf(buf + pos, len - pos, 948 "P_IR_S P_BS_B P_BS_S P_FLAG P_RATE(Mbps)\n"); 949 950 for (i = 0; i < pri_num; i++) { 951 ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode); 952 if (ret) 953 return ret; 954 955 ret = hclge_tm_get_pri_weight(hdev, i, &weight); 956 if (ret) 957 return ret; 958 959 ret = hclge_tm_get_pri_shaper(hdev, i, 960 HCLGE_OPC_TM_PRI_C_SHAPPING, 961 &c_shaper_para); 962 if (ret) 963 return ret; 964 965 ret = hclge_tm_get_pri_shaper(hdev, i, 966 HCLGE_OPC_TM_PRI_P_SHAPPING, 967 &p_shaper_para); 968 if (ret) 969 return ret; 970 971 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 972 "sp"; 973 974 pos += scnprintf(buf + pos, len - pos, 975 "%04u %4s %3u %3u %3u %3u ", 976 i, sch_mode_str, weight, c_shaper_para.ir_b, 977 c_shaper_para.ir_u, c_shaper_para.ir_s); 978 pos += scnprintf(buf + pos, len - pos, 979 "%3u %3u %1u %6u ", 980 c_shaper_para.bs_b, c_shaper_para.bs_s, 981 c_shaper_para.flag, c_shaper_para.rate); 982 pos += scnprintf(buf + pos, len - pos, 983 "%3u %3u %3u %3u %3u ", 984 p_shaper_para.ir_b, p_shaper_para.ir_u, 985 p_shaper_para.ir_s, p_shaper_para.bs_b, 986 p_shaper_para.bs_s); 987 pos += scnprintf(buf + pos, len - pos, "%1u %6u\n", 988 p_shaper_para.flag, p_shaper_para.rate); 989 } 990 991 return 0; 992 } 993 994 static const struct hclge_dbg_item tm_qset_items[] = { 995 { "ID", 4 }, 996 { "MAP_PRI", 2 }, 997 { "LINK_VLD", 2 }, 998 { "MODE", 2 }, 999 { "DWRR", 2 }, 1000 { "IR_B", 2 }, 1001 { "IR_U", 2 }, 1002 { "IR_S", 2 }, 1003 { "BS_B", 2 }, 1004 { "BS_S", 2 }, 1005 { "FLAG", 2 }, 1006 { "RATE(Mbps)", 0 } 1007 }; 1008 1009 static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len) 1010 { 1011 char data_str[ARRAY_SIZE(tm_qset_items)][HCLGE_DBG_DATA_STR_LEN]; 1012 char *result[ARRAY_SIZE(tm_qset_items)], *sch_mode_str; 1013 u8 priority, link_vld, sch_mode, weight; 1014 struct hclge_tm_shaper_para shaper_para; 1015 char content[HCLGE_DBG_TM_INFO_LEN]; 1016 u16 qset_num, i; 1017 int ret, pos; 1018 u8 j; 1019 1020 ret = hclge_tm_get_qset_num(hdev, &qset_num); 1021 if (ret) 1022 return ret; 1023 1024 for (i = 0; i < ARRAY_SIZE(tm_qset_items); i++) 1025 result[i] = &data_str[i][0]; 1026 1027 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, 1028 NULL, ARRAY_SIZE(tm_qset_items)); 1029 pos = scnprintf(buf, len, "%s", content); 1030 1031 for (i = 0; i < qset_num; i++) { 1032 ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld); 1033 if (ret) 1034 return ret; 1035 1036 ret = hclge_tm_get_qset_sch_mode(hdev, i, &sch_mode); 1037 if (ret) 1038 return ret; 1039 1040 ret = hclge_tm_get_qset_weight(hdev, i, &weight); 1041 if (ret) 1042 return ret; 1043 1044 ret = hclge_tm_get_qset_shaper(hdev, i, &shaper_para); 1045 if (ret) 1046 return ret; 1047 1048 sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" : 1049 "sp"; 1050 1051 j = 0; 1052 sprintf(result[j++], "%04u", i); 1053 sprintf(result[j++], "%4u", priority); 1054 sprintf(result[j++], "%4u", link_vld); 1055 sprintf(result[j++], "%4s", sch_mode_str); 1056 sprintf(result[j++], "%3u", weight); 1057 hclge_dbg_fill_shaper_content(&shaper_para, result, &j); 1058 1059 hclge_dbg_fill_content(content, sizeof(content), tm_qset_items, 1060 (const char **)result, 1061 ARRAY_SIZE(tm_qset_items)); 1062 pos += scnprintf(buf + pos, len - pos, "%s", content); 1063 } 1064 1065 return 0; 1066 } 1067 1068 static int hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev, char *buf, 1069 int len) 1070 { 1071 struct hclge_cfg_pause_param_cmd *pause_param; 1072 struct hclge_desc desc; 1073 int pos = 0; 1074 int ret; 1075 1076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 1077 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1078 if (ret) { 1079 dev_err(&hdev->pdev->dev, 1080 "failed to dump qos pause, ret = %d\n", ret); 1081 return ret; 1082 } 1083 1084 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 1085 1086 pos += scnprintf(buf + pos, len - pos, "pause_trans_gap: 0x%x\n", 1087 pause_param->pause_trans_gap); 1088 pos += scnprintf(buf + pos, len - pos, "pause_trans_time: 0x%x\n", 1089 le16_to_cpu(pause_param->pause_trans_time)); 1090 return 0; 1091 } 1092 1093 static int hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev, char *buf, 1094 int len) 1095 { 1096 #define HCLGE_DBG_TC_MASK 0x0F 1097 #define HCLGE_DBG_TC_BIT_WIDTH 4 1098 1099 struct hclge_qos_pri_map_cmd *pri_map; 1100 struct hclge_desc desc; 1101 int pos = 0; 1102 u8 *pri_tc; 1103 u8 tc, i; 1104 int ret; 1105 1106 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true); 1107 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1108 if (ret) { 1109 dev_err(&hdev->pdev->dev, 1110 "failed to dump qos pri map, ret = %d\n", ret); 1111 return ret; 1112 } 1113 1114 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; 1115 1116 pos += scnprintf(buf + pos, len - pos, "vlan_to_pri: 0x%x\n", 1117 pri_map->vlan_pri); 1118 pos += scnprintf(buf + pos, len - pos, "PRI TC\n"); 1119 1120 pri_tc = (u8 *)pri_map; 1121 for (i = 0; i < HNAE3_MAX_TC; i++) { 1122 tc = pri_tc[i >> 1] >> ((i & 1) * HCLGE_DBG_TC_BIT_WIDTH); 1123 tc &= HCLGE_DBG_TC_MASK; 1124 pos += scnprintf(buf + pos, len - pos, "%u %u\n", i, tc); 1125 } 1126 1127 return 0; 1128 } 1129 1130 static int hclge_dbg_dump_tx_buf_cfg(struct hclge_dev *hdev, char *buf, int len) 1131 { 1132 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; 1133 struct hclge_desc desc; 1134 int pos = 0; 1135 int i, ret; 1136 1137 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, true); 1138 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1139 if (ret) { 1140 dev_err(&hdev->pdev->dev, 1141 "failed to dump tx buf, ret = %d\n", ret); 1142 return ret; 1143 } 1144 1145 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc.data; 1146 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1147 pos += scnprintf(buf + pos, len - pos, 1148 "tx_packet_buf_tc_%d: 0x%x\n", i, 1149 le16_to_cpu(tx_buf_cmd->tx_pkt_buff[i])); 1150 1151 return pos; 1152 } 1153 1154 static int hclge_dbg_dump_rx_priv_buf_cfg(struct hclge_dev *hdev, char *buf, 1155 int len) 1156 { 1157 struct hclge_rx_priv_buff_cmd *rx_buf_cmd; 1158 struct hclge_desc desc; 1159 int pos = 0; 1160 int i, ret; 1161 1162 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, true); 1163 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1164 if (ret) { 1165 dev_err(&hdev->pdev->dev, 1166 "failed to dump rx priv buf, ret = %d\n", ret); 1167 return ret; 1168 } 1169 1170 pos += scnprintf(buf + pos, len - pos, "\n"); 1171 1172 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc.data; 1173 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 1174 pos += scnprintf(buf + pos, len - pos, 1175 "rx_packet_buf_tc_%d: 0x%x\n", i, 1176 le16_to_cpu(rx_buf_cmd->buf_num[i])); 1177 1178 pos += scnprintf(buf + pos, len - pos, "rx_share_buf: 0x%x\n", 1179 le16_to_cpu(rx_buf_cmd->shared_buf)); 1180 1181 return pos; 1182 } 1183 1184 static int hclge_dbg_dump_rx_common_wl_cfg(struct hclge_dev *hdev, char *buf, 1185 int len) 1186 { 1187 struct hclge_rx_com_wl *rx_com_wl; 1188 struct hclge_desc desc; 1189 int pos = 0; 1190 int ret; 1191 1192 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, true); 1193 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1194 if (ret) { 1195 dev_err(&hdev->pdev->dev, 1196 "failed to dump rx common wl, ret = %d\n", ret); 1197 return ret; 1198 } 1199 1200 rx_com_wl = (struct hclge_rx_com_wl *)desc.data; 1201 pos += scnprintf(buf + pos, len - pos, "\n"); 1202 pos += scnprintf(buf + pos, len - pos, 1203 "rx_com_wl: high: 0x%x, low: 0x%x\n", 1204 le16_to_cpu(rx_com_wl->com_wl.high), 1205 le16_to_cpu(rx_com_wl->com_wl.low)); 1206 1207 return pos; 1208 } 1209 1210 static int hclge_dbg_dump_rx_global_pkt_cnt(struct hclge_dev *hdev, char *buf, 1211 int len) 1212 { 1213 struct hclge_rx_com_wl *rx_packet_cnt; 1214 struct hclge_desc desc; 1215 int pos = 0; 1216 int ret; 1217 1218 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_GBL_PKT_CNT, true); 1219 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1220 if (ret) { 1221 dev_err(&hdev->pdev->dev, 1222 "failed to dump rx global pkt cnt, ret = %d\n", ret); 1223 return ret; 1224 } 1225 1226 rx_packet_cnt = (struct hclge_rx_com_wl *)desc.data; 1227 pos += scnprintf(buf + pos, len - pos, 1228 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", 1229 le16_to_cpu(rx_packet_cnt->com_wl.high), 1230 le16_to_cpu(rx_packet_cnt->com_wl.low)); 1231 1232 return pos; 1233 } 1234 1235 static int hclge_dbg_dump_rx_priv_wl_buf_cfg(struct hclge_dev *hdev, char *buf, 1236 int len) 1237 { 1238 struct hclge_rx_priv_wl_buf *rx_priv_wl; 1239 struct hclge_desc desc[2]; 1240 int pos = 0; 1241 int i, ret; 1242 1243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_PRIV_WL_ALLOC, true); 1244 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1245 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_PRIV_WL_ALLOC, true); 1246 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1247 if (ret) { 1248 dev_err(&hdev->pdev->dev, 1249 "failed to dump rx priv wl buf, ret = %d\n", ret); 1250 return ret; 1251 } 1252 1253 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; 1254 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1255 pos += scnprintf(buf + pos, len - pos, 1256 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, 1257 le16_to_cpu(rx_priv_wl->tc_wl[i].high), 1258 le16_to_cpu(rx_priv_wl->tc_wl[i].low)); 1259 1260 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; 1261 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1262 pos += scnprintf(buf + pos, len - pos, 1263 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", 1264 i + HCLGE_TC_NUM_ONE_DESC, 1265 le16_to_cpu(rx_priv_wl->tc_wl[i].high), 1266 le16_to_cpu(rx_priv_wl->tc_wl[i].low)); 1267 1268 return pos; 1269 } 1270 1271 static int hclge_dbg_dump_rx_common_threshold_cfg(struct hclge_dev *hdev, 1272 char *buf, int len) 1273 { 1274 struct hclge_rx_com_thrd *rx_com_thrd; 1275 struct hclge_desc desc[2]; 1276 int pos = 0; 1277 int i, ret; 1278 1279 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_RX_COM_THRD_ALLOC, true); 1280 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1281 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_RX_COM_THRD_ALLOC, true); 1282 ret = hclge_cmd_send(&hdev->hw, desc, 2); 1283 if (ret) { 1284 dev_err(&hdev->pdev->dev, 1285 "failed to dump rx common threshold, ret = %d\n", ret); 1286 return ret; 1287 } 1288 1289 pos += scnprintf(buf + pos, len - pos, "\n"); 1290 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; 1291 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1292 pos += scnprintf(buf + pos, len - pos, 1293 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, 1294 le16_to_cpu(rx_com_thrd->com_thrd[i].high), 1295 le16_to_cpu(rx_com_thrd->com_thrd[i].low)); 1296 1297 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; 1298 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 1299 pos += scnprintf(buf + pos, len - pos, 1300 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", 1301 i + HCLGE_TC_NUM_ONE_DESC, 1302 le16_to_cpu(rx_com_thrd->com_thrd[i].high), 1303 le16_to_cpu(rx_com_thrd->com_thrd[i].low)); 1304 1305 return pos; 1306 } 1307 1308 static int hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev, char *buf, 1309 int len) 1310 { 1311 int pos = 0; 1312 int ret; 1313 1314 ret = hclge_dbg_dump_tx_buf_cfg(hdev, buf + pos, len - pos); 1315 if (ret < 0) 1316 return ret; 1317 pos += ret; 1318 1319 ret = hclge_dbg_dump_rx_priv_buf_cfg(hdev, buf + pos, len - pos); 1320 if (ret < 0) 1321 return ret; 1322 pos += ret; 1323 1324 ret = hclge_dbg_dump_rx_common_wl_cfg(hdev, buf + pos, len - pos); 1325 if (ret < 0) 1326 return ret; 1327 pos += ret; 1328 1329 ret = hclge_dbg_dump_rx_global_pkt_cnt(hdev, buf + pos, len - pos); 1330 if (ret < 0) 1331 return ret; 1332 pos += ret; 1333 1334 pos += scnprintf(buf + pos, len - pos, "\n"); 1335 if (!hnae3_dev_dcb_supported(hdev)) 1336 return 0; 1337 1338 ret = hclge_dbg_dump_rx_priv_wl_buf_cfg(hdev, buf + pos, len - pos); 1339 if (ret < 0) 1340 return ret; 1341 pos += ret; 1342 1343 ret = hclge_dbg_dump_rx_common_threshold_cfg(hdev, buf + pos, 1344 len - pos); 1345 if (ret < 0) 1346 return ret; 1347 1348 return 0; 1349 } 1350 1351 static int hclge_dbg_dump_mng_table(struct hclge_dev *hdev, char *buf, int len) 1352 { 1353 struct hclge_mac_ethertype_idx_rd_cmd *req0; 1354 struct hclge_desc desc; 1355 u32 msg_egress_port; 1356 int pos = 0; 1357 int ret, i; 1358 1359 pos += scnprintf(buf + pos, len - pos, 1360 "entry mac_addr mask ether "); 1361 pos += scnprintf(buf + pos, len - pos, 1362 "mask vlan mask i_map i_dir e_type "); 1363 pos += scnprintf(buf + pos, len - pos, "pf_id vf_id q_id drop\n"); 1364 1365 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) { 1366 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD, 1367 true); 1368 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data; 1369 req0->index = cpu_to_le16(i); 1370 1371 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1372 if (ret) { 1373 dev_err(&hdev->pdev->dev, 1374 "failed to dump manage table, ret = %d\n", ret); 1375 return ret; 1376 } 1377 1378 if (!req0->resp_code) 1379 continue; 1380 1381 pos += scnprintf(buf + pos, len - pos, "%02u %pM ", 1382 le16_to_cpu(req0->index), req0->mac_addr); 1383 1384 pos += scnprintf(buf + pos, len - pos, 1385 "%x %04x %x %04x ", 1386 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), 1387 le16_to_cpu(req0->ethter_type), 1388 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), 1389 le16_to_cpu(req0->vlan_tag) & 1390 HCLGE_DBG_MNG_VLAN_TAG); 1391 1392 pos += scnprintf(buf + pos, len - pos, 1393 "%x %02x %02x ", 1394 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), 1395 req0->i_port_bitmap, req0->i_port_direction); 1396 1397 msg_egress_port = le16_to_cpu(req0->egress_port); 1398 pos += scnprintf(buf + pos, len - pos, 1399 "%x %x %02x %04x %x\n", 1400 !!(msg_egress_port & HCLGE_DBG_MNG_E_TYPE_B), 1401 msg_egress_port & HCLGE_DBG_MNG_PF_ID, 1402 (msg_egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, 1403 le16_to_cpu(req0->egress_queue), 1404 !!(msg_egress_port & HCLGE_DBG_MNG_DROP_B)); 1405 } 1406 1407 return 0; 1408 } 1409 1410 #define HCLGE_DBG_TCAM_BUF_SIZE 256 1411 1412 static int hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, bool sel_x, 1413 char *tcam_buf, 1414 struct hclge_dbg_tcam_msg tcam_msg) 1415 { 1416 struct hclge_fd_tcam_config_1_cmd *req1; 1417 struct hclge_fd_tcam_config_2_cmd *req2; 1418 struct hclge_fd_tcam_config_3_cmd *req3; 1419 struct hclge_desc desc[3]; 1420 int pos = 0; 1421 int ret, i; 1422 u32 *req; 1423 1424 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true); 1425 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1426 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true); 1427 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 1428 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true); 1429 1430 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 1431 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 1432 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 1433 1434 req1->stage = tcam_msg.stage; 1435 req1->xy_sel = sel_x ? 1 : 0; 1436 req1->index = cpu_to_le32(tcam_msg.loc); 1437 1438 ret = hclge_cmd_send(&hdev->hw, desc, 3); 1439 if (ret) 1440 return ret; 1441 1442 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1443 "read result tcam key %s(%u):\n", sel_x ? "x" : "y", 1444 tcam_msg.loc); 1445 1446 /* tcam_data0 ~ tcam_data1 */ 1447 req = (u32 *)req1->tcam_data; 1448 for (i = 0; i < 2; i++) 1449 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1450 "%08x\n", *req++); 1451 1452 /* tcam_data2 ~ tcam_data7 */ 1453 req = (u32 *)req2->tcam_data; 1454 for (i = 0; i < 6; i++) 1455 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1456 "%08x\n", *req++); 1457 1458 /* tcam_data8 ~ tcam_data12 */ 1459 req = (u32 *)req3->tcam_data; 1460 for (i = 0; i < 5; i++) 1461 pos += scnprintf(tcam_buf + pos, HCLGE_DBG_TCAM_BUF_SIZE - pos, 1462 "%08x\n", *req++); 1463 1464 return ret; 1465 } 1466 1467 static int hclge_dbg_get_rules_location(struct hclge_dev *hdev, u16 *rule_locs) 1468 { 1469 struct hclge_fd_rule *rule; 1470 struct hlist_node *node; 1471 int cnt = 0; 1472 1473 spin_lock_bh(&hdev->fd_rule_lock); 1474 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) { 1475 rule_locs[cnt] = rule->location; 1476 cnt++; 1477 } 1478 spin_unlock_bh(&hdev->fd_rule_lock); 1479 1480 if (cnt != hdev->hclge_fd_rule_num || cnt == 0) 1481 return -EINVAL; 1482 1483 return cnt; 1484 } 1485 1486 static int hclge_dbg_dump_fd_tcam(struct hclge_dev *hdev, char *buf, int len) 1487 { 1488 u32 rule_num = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1]; 1489 struct hclge_dbg_tcam_msg tcam_msg; 1490 int i, ret, rule_cnt; 1491 u16 *rule_locs; 1492 char *tcam_buf; 1493 int pos = 0; 1494 1495 if (!hnae3_dev_fd_supported(hdev)) { 1496 dev_err(&hdev->pdev->dev, 1497 "Only FD-supported dev supports dump fd tcam\n"); 1498 return -EOPNOTSUPP; 1499 } 1500 1501 if (!hdev->hclge_fd_rule_num || !rule_num) 1502 return 0; 1503 1504 rule_locs = kcalloc(rule_num, sizeof(u16), GFP_KERNEL); 1505 if (!rule_locs) 1506 return -ENOMEM; 1507 1508 tcam_buf = kzalloc(HCLGE_DBG_TCAM_BUF_SIZE, GFP_KERNEL); 1509 if (!tcam_buf) { 1510 kfree(rule_locs); 1511 return -ENOMEM; 1512 } 1513 1514 rule_cnt = hclge_dbg_get_rules_location(hdev, rule_locs); 1515 if (rule_cnt < 0) { 1516 ret = rule_cnt; 1517 dev_err(&hdev->pdev->dev, 1518 "failed to get rule number, ret = %d\n", ret); 1519 goto out; 1520 } 1521 1522 ret = 0; 1523 for (i = 0; i < rule_cnt; i++) { 1524 tcam_msg.stage = HCLGE_FD_STAGE_1; 1525 tcam_msg.loc = rule_locs[i]; 1526 1527 ret = hclge_dbg_fd_tcam_read(hdev, true, tcam_buf, tcam_msg); 1528 if (ret) { 1529 dev_err(&hdev->pdev->dev, 1530 "failed to get fd tcam key x, ret = %d\n", ret); 1531 goto out; 1532 } 1533 1534 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); 1535 1536 ret = hclge_dbg_fd_tcam_read(hdev, false, tcam_buf, tcam_msg); 1537 if (ret) { 1538 dev_err(&hdev->pdev->dev, 1539 "failed to get fd tcam key y, ret = %d\n", ret); 1540 goto out; 1541 } 1542 1543 pos += scnprintf(buf + pos, len - pos, "%s", tcam_buf); 1544 } 1545 1546 out: 1547 kfree(tcam_buf); 1548 kfree(rule_locs); 1549 return ret; 1550 } 1551 1552 static int hclge_dbg_dump_fd_counter(struct hclge_dev *hdev, char *buf, int len) 1553 { 1554 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 1555 struct hclge_fd_ad_cnt_read_cmd *req; 1556 char str_id[HCLGE_DBG_ID_LEN]; 1557 struct hclge_desc desc; 1558 int pos = 0; 1559 int ret; 1560 u64 cnt; 1561 u8 i; 1562 1563 pos += scnprintf(buf + pos, len - pos, 1564 "func_id\thit_times\n"); 1565 1566 for (i = 0; i < func_num; i++) { 1567 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_CNT_OP, true); 1568 req = (struct hclge_fd_ad_cnt_read_cmd *)desc.data; 1569 req->index = cpu_to_le16(i); 1570 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1571 if (ret) { 1572 dev_err(&hdev->pdev->dev, "failed to get fd counter, ret = %d\n", 1573 ret); 1574 return ret; 1575 } 1576 cnt = le64_to_cpu(req->cnt); 1577 hclge_dbg_get_func_id_str(str_id, i); 1578 pos += scnprintf(buf + pos, len - pos, 1579 "%s\t%llu\n", str_id, cnt); 1580 } 1581 1582 return 0; 1583 } 1584 1585 int hclge_dbg_dump_rst_info(struct hclge_dev *hdev, char *buf, int len) 1586 { 1587 int pos = 0; 1588 1589 pos += scnprintf(buf + pos, len - pos, "PF reset count: %u\n", 1590 hdev->rst_stats.pf_rst_cnt); 1591 pos += scnprintf(buf + pos, len - pos, "FLR reset count: %u\n", 1592 hdev->rst_stats.flr_rst_cnt); 1593 pos += scnprintf(buf + pos, len - pos, "GLOBAL reset count: %u\n", 1594 hdev->rst_stats.global_rst_cnt); 1595 pos += scnprintf(buf + pos, len - pos, "IMP reset count: %u\n", 1596 hdev->rst_stats.imp_rst_cnt); 1597 pos += scnprintf(buf + pos, len - pos, "reset done count: %u\n", 1598 hdev->rst_stats.reset_done_cnt); 1599 pos += scnprintf(buf + pos, len - pos, "HW reset done count: %u\n", 1600 hdev->rst_stats.hw_reset_done_cnt); 1601 pos += scnprintf(buf + pos, len - pos, "reset count: %u\n", 1602 hdev->rst_stats.reset_cnt); 1603 pos += scnprintf(buf + pos, len - pos, "reset fail count: %u\n", 1604 hdev->rst_stats.reset_fail_cnt); 1605 pos += scnprintf(buf + pos, len - pos, 1606 "vector0 interrupt enable status: 0x%x\n", 1607 hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_REG_BASE)); 1608 pos += scnprintf(buf + pos, len - pos, "reset interrupt source: 0x%x\n", 1609 hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG)); 1610 pos += scnprintf(buf + pos, len - pos, "reset interrupt status: 0x%x\n", 1611 hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS)); 1612 pos += scnprintf(buf + pos, len - pos, "RAS interrupt status: 0x%x\n", 1613 hclge_read_dev(&hdev->hw, 1614 HCLGE_RAS_PF_OTHER_INT_STS_REG)); 1615 pos += scnprintf(buf + pos, len - pos, "hardware reset status: 0x%x\n", 1616 hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG)); 1617 pos += scnprintf(buf + pos, len - pos, "handshake status: 0x%x\n", 1618 hclge_read_dev(&hdev->hw, HCLGE_NIC_CSQ_DEPTH_REG)); 1619 pos += scnprintf(buf + pos, len - pos, "function reset status: 0x%x\n", 1620 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING)); 1621 pos += scnprintf(buf + pos, len - pos, "hdev state: 0x%lx\n", 1622 hdev->state); 1623 1624 return 0; 1625 } 1626 1627 static int hclge_dbg_dump_serv_info(struct hclge_dev *hdev, char *buf, int len) 1628 { 1629 unsigned long rem_nsec; 1630 int pos = 0; 1631 u64 lc; 1632 1633 lc = local_clock(); 1634 rem_nsec = do_div(lc, HCLGE_BILLION_NANO_SECONDS); 1635 1636 pos += scnprintf(buf + pos, len - pos, "local_clock: [%5lu.%06lu]\n", 1637 (unsigned long)lc, rem_nsec / 1000); 1638 pos += scnprintf(buf + pos, len - pos, "delta: %u(ms)\n", 1639 jiffies_to_msecs(jiffies - hdev->last_serv_processed)); 1640 pos += scnprintf(buf + pos, len - pos, 1641 "last_service_task_processed: %lu(jiffies)\n", 1642 hdev->last_serv_processed); 1643 pos += scnprintf(buf + pos, len - pos, "last_service_task_cnt: %lu\n", 1644 hdev->serv_processed_cnt); 1645 1646 return 0; 1647 } 1648 1649 static int hclge_dbg_dump_interrupt(struct hclge_dev *hdev, char *buf, int len) 1650 { 1651 int pos = 0; 1652 1653 pos += scnprintf(buf + pos, len - pos, "num_nic_msi: %u\n", 1654 hdev->num_nic_msi); 1655 pos += scnprintf(buf + pos, len - pos, "num_roce_msi: %u\n", 1656 hdev->num_roce_msi); 1657 pos += scnprintf(buf + pos, len - pos, "num_msi_used: %u\n", 1658 hdev->num_msi_used); 1659 pos += scnprintf(buf + pos, len - pos, "num_msi_left: %u\n", 1660 hdev->num_msi_left); 1661 1662 return 0; 1663 } 1664 1665 static void hclge_dbg_imp_info_data_print(struct hclge_desc *desc_src, 1666 char *buf, int len, u32 bd_num) 1667 { 1668 #define HCLGE_DBG_IMP_INFO_PRINT_OFFSET 0x2 1669 1670 struct hclge_desc *desc_index = desc_src; 1671 u32 offset = 0; 1672 int pos = 0; 1673 u32 i, j; 1674 1675 pos += scnprintf(buf + pos, len - pos, "offset | data\n"); 1676 1677 for (i = 0; i < bd_num; i++) { 1678 j = 0; 1679 while (j < HCLGE_DESC_DATA_LEN - 1) { 1680 pos += scnprintf(buf + pos, len - pos, "0x%04x | ", 1681 offset); 1682 pos += scnprintf(buf + pos, len - pos, "0x%08x ", 1683 le32_to_cpu(desc_index->data[j++])); 1684 pos += scnprintf(buf + pos, len - pos, "0x%08x\n", 1685 le32_to_cpu(desc_index->data[j++])); 1686 offset += sizeof(u32) * HCLGE_DBG_IMP_INFO_PRINT_OFFSET; 1687 } 1688 desc_index++; 1689 } 1690 } 1691 1692 static int 1693 hclge_dbg_get_imp_stats_info(struct hclge_dev *hdev, char *buf, int len) 1694 { 1695 struct hclge_get_imp_bd_cmd *req; 1696 struct hclge_desc *desc_src; 1697 struct hclge_desc desc; 1698 u32 bd_num; 1699 int ret; 1700 1701 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_IMP_STATS_BD, true); 1702 1703 req = (struct hclge_get_imp_bd_cmd *)desc.data; 1704 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1705 if (ret) { 1706 dev_err(&hdev->pdev->dev, 1707 "failed to get imp statistics bd number, ret = %d\n", 1708 ret); 1709 return ret; 1710 } 1711 1712 bd_num = le32_to_cpu(req->bd_num); 1713 1714 desc_src = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL); 1715 if (!desc_src) 1716 return -ENOMEM; 1717 1718 ret = hclge_dbg_cmd_send(hdev, desc_src, 0, bd_num, 1719 HCLGE_OPC_IMP_STATS_INFO); 1720 if (ret) { 1721 kfree(desc_src); 1722 dev_err(&hdev->pdev->dev, 1723 "failed to get imp statistics, ret = %d\n", ret); 1724 return ret; 1725 } 1726 1727 hclge_dbg_imp_info_data_print(desc_src, buf, len, bd_num); 1728 1729 kfree(desc_src); 1730 1731 return 0; 1732 } 1733 1734 #define HCLGE_CMD_NCL_CONFIG_BD_NUM 5 1735 #define HCLGE_MAX_NCL_CONFIG_LENGTH 16384 1736 1737 static void hclge_ncl_config_data_print(struct hclge_desc *desc, int *index, 1738 char *buf, int *len, int *pos) 1739 { 1740 #define HCLGE_CMD_DATA_NUM 6 1741 1742 int offset = HCLGE_MAX_NCL_CONFIG_LENGTH - *index; 1743 int i, j; 1744 1745 for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) { 1746 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) { 1747 if (i == 0 && j == 0) 1748 continue; 1749 1750 *pos += scnprintf(buf + *pos, *len - *pos, 1751 "0x%04x | 0x%08x\n", offset, 1752 le32_to_cpu(desc[i].data[j])); 1753 1754 offset += sizeof(u32); 1755 *index -= sizeof(u32); 1756 1757 if (*index <= 0) 1758 return; 1759 } 1760 } 1761 } 1762 1763 static int 1764 hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, char *buf, int len) 1765 { 1766 #define HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD (20 + 24 * 4) 1767 1768 struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM]; 1769 int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM; 1770 int index = HCLGE_MAX_NCL_CONFIG_LENGTH; 1771 int pos = 0; 1772 u32 data0; 1773 int ret; 1774 1775 pos += scnprintf(buf + pos, len - pos, "offset | data\n"); 1776 1777 while (index > 0) { 1778 data0 = HCLGE_MAX_NCL_CONFIG_LENGTH - index; 1779 if (index >= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD) 1780 data0 |= HCLGE_NCL_CONFIG_LENGTH_IN_EACH_CMD << 16; 1781 else 1782 data0 |= (u32)index << 16; 1783 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num, 1784 HCLGE_OPC_QUERY_NCL_CONFIG); 1785 if (ret) 1786 return ret; 1787 1788 hclge_ncl_config_data_print(desc, &index, buf, &len, &pos); 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int hclge_dbg_dump_loopback(struct hclge_dev *hdev, char *buf, int len) 1795 { 1796 struct phy_device *phydev = hdev->hw.mac.phydev; 1797 struct hclge_config_mac_mode_cmd *req_app; 1798 struct hclge_common_lb_cmd *req_common; 1799 struct hclge_desc desc; 1800 u8 loopback_en; 1801 int pos = 0; 1802 int ret; 1803 1804 req_app = (struct hclge_config_mac_mode_cmd *)desc.data; 1805 req_common = (struct hclge_common_lb_cmd *)desc.data; 1806 1807 pos += scnprintf(buf + pos, len - pos, "mac id: %u\n", 1808 hdev->hw.mac.mac_id); 1809 1810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); 1811 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1812 if (ret) { 1813 dev_err(&hdev->pdev->dev, 1814 "failed to dump app loopback status, ret = %d\n", ret); 1815 return ret; 1816 } 1817 1818 loopback_en = hnae3_get_bit(le32_to_cpu(req_app->txrx_pad_fcs_loop_en), 1819 HCLGE_MAC_APP_LP_B); 1820 pos += scnprintf(buf + pos, len - pos, "app loopback: %s\n", 1821 state_str[loopback_en]); 1822 1823 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_COMMON_LOOPBACK, true); 1824 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1825 if (ret) { 1826 dev_err(&hdev->pdev->dev, 1827 "failed to dump common loopback status, ret = %d\n", 1828 ret); 1829 return ret; 1830 } 1831 1832 loopback_en = req_common->enable & HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B; 1833 pos += scnprintf(buf + pos, len - pos, "serdes serial loopback: %s\n", 1834 state_str[loopback_en]); 1835 1836 loopback_en = req_common->enable & 1837 HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B ? 1 : 0; 1838 pos += scnprintf(buf + pos, len - pos, "serdes parallel loopback: %s\n", 1839 state_str[loopback_en]); 1840 1841 if (phydev) { 1842 loopback_en = phydev->loopback_enabled; 1843 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", 1844 state_str[loopback_en]); 1845 } else if (hnae3_dev_phy_imp_supported(hdev)) { 1846 loopback_en = req_common->enable & 1847 HCLGE_CMD_GE_PHY_INNER_LOOP_B; 1848 pos += scnprintf(buf + pos, len - pos, "phy loopback: %s\n", 1849 state_str[loopback_en]); 1850 } 1851 1852 return 0; 1853 } 1854 1855 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt 1856 * @hdev: pointer to struct hclge_dev 1857 */ 1858 static int 1859 hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev, char *buf, int len) 1860 { 1861 struct hclge_mac_tnl_stats stats; 1862 unsigned long rem_nsec; 1863 int pos = 0; 1864 1865 pos += scnprintf(buf + pos, len - pos, 1866 "Recently generated mac tnl interruption:\n"); 1867 1868 while (kfifo_get(&hdev->mac_tnl_log, &stats)) { 1869 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS); 1870 1871 pos += scnprintf(buf + pos, len - pos, 1872 "[%07lu.%03lu] status = 0x%x\n", 1873 (unsigned long)stats.time, rem_nsec / 1000, 1874 stats.status); 1875 } 1876 1877 return 0; 1878 } 1879 1880 1881 static const struct hclge_dbg_item mac_list_items[] = { 1882 { "FUNC_ID", 2 }, 1883 { "MAC_ADDR", 12 }, 1884 { "STATE", 2 }, 1885 }; 1886 1887 static void hclge_dbg_dump_mac_list(struct hclge_dev *hdev, char *buf, int len, 1888 bool is_unicast) 1889 { 1890 char data_str[ARRAY_SIZE(mac_list_items)][HCLGE_DBG_DATA_STR_LEN]; 1891 char content[HCLGE_DBG_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; 1892 char *result[ARRAY_SIZE(mac_list_items)]; 1893 struct hclge_mac_node *mac_node, *tmp; 1894 struct hclge_vport *vport; 1895 struct list_head *list; 1896 u32 func_id; 1897 int pos = 0; 1898 int i; 1899 1900 for (i = 0; i < ARRAY_SIZE(mac_list_items); i++) 1901 result[i] = &data_str[i][0]; 1902 1903 pos += scnprintf(buf + pos, len - pos, "%s MAC_LIST:\n", 1904 is_unicast ? "UC" : "MC"); 1905 hclge_dbg_fill_content(content, sizeof(content), mac_list_items, 1906 NULL, ARRAY_SIZE(mac_list_items)); 1907 pos += scnprintf(buf + pos, len - pos, "%s", content); 1908 1909 for (func_id = 0; func_id < hdev->num_alloc_vport; func_id++) { 1910 vport = &hdev->vport[func_id]; 1911 list = is_unicast ? &vport->uc_mac_list : &vport->mc_mac_list; 1912 spin_lock_bh(&vport->mac_list_lock); 1913 list_for_each_entry_safe(mac_node, tmp, list, node) { 1914 i = 0; 1915 result[i++] = hclge_dbg_get_func_id_str(str_id, 1916 func_id); 1917 sprintf(result[i++], "%pM", mac_node->mac_addr); 1918 sprintf(result[i++], "%5s", 1919 hclge_mac_state_str[mac_node->state]); 1920 hclge_dbg_fill_content(content, sizeof(content), 1921 mac_list_items, 1922 (const char **)result, 1923 ARRAY_SIZE(mac_list_items)); 1924 pos += scnprintf(buf + pos, len - pos, "%s", content); 1925 } 1926 spin_unlock_bh(&vport->mac_list_lock); 1927 } 1928 } 1929 1930 static int hclge_dbg_dump_umv_info(struct hclge_dev *hdev, char *buf, int len) 1931 { 1932 u8 func_num = pci_num_vf(hdev->pdev) + 1; 1933 struct hclge_vport *vport; 1934 int pos = 0; 1935 u8 i; 1936 1937 pos += scnprintf(buf, len, "num_alloc_vport : %u\n", 1938 hdev->num_alloc_vport); 1939 pos += scnprintf(buf + pos, len - pos, "max_umv_size : %u\n", 1940 hdev->max_umv_size); 1941 pos += scnprintf(buf + pos, len - pos, "wanted_umv_size : %u\n", 1942 hdev->wanted_umv_size); 1943 pos += scnprintf(buf + pos, len - pos, "priv_umv_size : %u\n", 1944 hdev->priv_umv_size); 1945 1946 mutex_lock(&hdev->vport_lock); 1947 pos += scnprintf(buf + pos, len - pos, "share_umv_size : %u\n", 1948 hdev->share_umv_size); 1949 for (i = 0; i < func_num; i++) { 1950 vport = &hdev->vport[i]; 1951 pos += scnprintf(buf + pos, len - pos, 1952 "vport(%u) used_umv_num : %u\n", 1953 i, vport->used_umv_num); 1954 } 1955 mutex_unlock(&hdev->vport_lock); 1956 1957 return 0; 1958 } 1959 1960 static int hclge_get_vlan_rx_offload_cfg(struct hclge_dev *hdev, u8 vf_id, 1961 struct hclge_dbg_vlan_cfg *vlan_cfg) 1962 { 1963 struct hclge_vport_vtag_rx_cfg_cmd *req; 1964 struct hclge_desc desc; 1965 u16 bmap_index; 1966 u8 rx_cfg; 1967 int ret; 1968 1969 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, true); 1970 1971 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; 1972 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD; 1973 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE; 1974 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE); 1975 1976 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 1977 if (ret) { 1978 dev_err(&hdev->pdev->dev, 1979 "failed to get vport%u rxvlan cfg, ret = %d\n", 1980 vf_id, ret); 1981 return ret; 1982 } 1983 1984 rx_cfg = req->vport_vlan_cfg; 1985 vlan_cfg->strip_tag1 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG1_EN_B); 1986 vlan_cfg->strip_tag2 = hnae3_get_bit(rx_cfg, HCLGE_REM_TAG2_EN_B); 1987 vlan_cfg->drop_tag1 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG1_EN_B); 1988 vlan_cfg->drop_tag2 = hnae3_get_bit(rx_cfg, HCLGE_DISCARD_TAG2_EN_B); 1989 vlan_cfg->pri_only1 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG1_EN_B); 1990 vlan_cfg->pri_only2 = hnae3_get_bit(rx_cfg, HCLGE_SHOW_TAG2_EN_B); 1991 1992 return 0; 1993 } 1994 1995 static int hclge_get_vlan_tx_offload_cfg(struct hclge_dev *hdev, u8 vf_id, 1996 struct hclge_dbg_vlan_cfg *vlan_cfg) 1997 { 1998 struct hclge_vport_vtag_tx_cfg_cmd *req; 1999 struct hclge_desc desc; 2000 u16 bmap_index; 2001 u8 tx_cfg; 2002 int ret; 2003 2004 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, true); 2005 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; 2006 req->vf_offset = vf_id / HCLGE_VF_NUM_PER_CMD; 2007 bmap_index = vf_id % HCLGE_VF_NUM_PER_CMD / HCLGE_VF_NUM_PER_BYTE; 2008 req->vf_bitmap[bmap_index] = 1U << (vf_id % HCLGE_VF_NUM_PER_BYTE); 2009 2010 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2011 if (ret) { 2012 dev_err(&hdev->pdev->dev, 2013 "failed to get vport%u txvlan cfg, ret = %d\n", 2014 vf_id, ret); 2015 return ret; 2016 } 2017 2018 tx_cfg = req->vport_vlan_cfg; 2019 vlan_cfg->pvid = le16_to_cpu(req->def_vlan_tag1); 2020 2021 vlan_cfg->accept_tag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG1_B); 2022 vlan_cfg->accept_tag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_TAG2_B); 2023 vlan_cfg->accept_untag1 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG1_B); 2024 vlan_cfg->accept_untag2 = hnae3_get_bit(tx_cfg, HCLGE_ACCEPT_UNTAG2_B); 2025 vlan_cfg->insert_tag1 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG1_EN_B); 2026 vlan_cfg->insert_tag2 = hnae3_get_bit(tx_cfg, HCLGE_PORT_INS_TAG2_EN_B); 2027 vlan_cfg->shift_tag = hnae3_get_bit(tx_cfg, HCLGE_TAG_SHIFT_MODE_EN_B); 2028 2029 return 0; 2030 } 2031 2032 static int hclge_get_vlan_filter_config_cmd(struct hclge_dev *hdev, 2033 u8 vlan_type, u8 vf_id, 2034 struct hclge_desc *desc) 2035 { 2036 struct hclge_vlan_filter_ctrl_cmd *req; 2037 int ret; 2038 2039 hclge_cmd_setup_basic_desc(desc, HCLGE_OPC_VLAN_FILTER_CTRL, true); 2040 req = (struct hclge_vlan_filter_ctrl_cmd *)desc->data; 2041 req->vlan_type = vlan_type; 2042 req->vf_id = vf_id; 2043 2044 ret = hclge_cmd_send(&hdev->hw, desc, 1); 2045 if (ret) 2046 dev_err(&hdev->pdev->dev, 2047 "failed to get vport%u vlan filter config, ret = %d.\n", 2048 vf_id, ret); 2049 2050 return ret; 2051 } 2052 2053 static int hclge_get_vlan_filter_state(struct hclge_dev *hdev, u8 vlan_type, 2054 u8 vf_id, u8 *vlan_fe) 2055 { 2056 struct hclge_vlan_filter_ctrl_cmd *req; 2057 struct hclge_desc desc; 2058 int ret; 2059 2060 ret = hclge_get_vlan_filter_config_cmd(hdev, vlan_type, vf_id, &desc); 2061 if (ret) 2062 return ret; 2063 2064 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; 2065 *vlan_fe = req->vlan_fe; 2066 2067 return 0; 2068 } 2069 2070 static int hclge_get_port_vlan_filter_bypass_state(struct hclge_dev *hdev, 2071 u8 vf_id, u8 *bypass_en) 2072 { 2073 struct hclge_port_vlan_filter_bypass_cmd *req; 2074 struct hclge_desc desc; 2075 int ret; 2076 2077 if (!test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, hdev->ae_dev->caps)) 2078 return 0; 2079 2080 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PORT_VLAN_BYPASS, true); 2081 req = (struct hclge_port_vlan_filter_bypass_cmd *)desc.data; 2082 req->vf_id = vf_id; 2083 2084 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 2085 if (ret) { 2086 dev_err(&hdev->pdev->dev, 2087 "failed to get vport%u port vlan filter bypass state, ret = %d.\n", 2088 vf_id, ret); 2089 return ret; 2090 } 2091 2092 *bypass_en = hnae3_get_bit(req->bypass_state, HCLGE_INGRESS_BYPASS_B); 2093 2094 return 0; 2095 } 2096 2097 static const struct hclge_dbg_item vlan_filter_items[] = { 2098 { "FUNC_ID", 2 }, 2099 { "I_VF_VLAN_FILTER", 2 }, 2100 { "E_VF_VLAN_FILTER", 2 }, 2101 { "PORT_VLAN_FILTER_BYPASS", 0 } 2102 }; 2103 2104 static const struct hclge_dbg_item vlan_offload_items[] = { 2105 { "FUNC_ID", 2 }, 2106 { "PVID", 4 }, 2107 { "ACCEPT_TAG1", 2 }, 2108 { "ACCEPT_TAG2", 2 }, 2109 { "ACCEPT_UNTAG1", 2 }, 2110 { "ACCEPT_UNTAG2", 2 }, 2111 { "INSERT_TAG1", 2 }, 2112 { "INSERT_TAG2", 2 }, 2113 { "SHIFT_TAG", 2 }, 2114 { "STRIP_TAG1", 2 }, 2115 { "STRIP_TAG2", 2 }, 2116 { "DROP_TAG1", 2 }, 2117 { "DROP_TAG2", 2 }, 2118 { "PRI_ONLY_TAG1", 2 }, 2119 { "PRI_ONLY_TAG2", 0 } 2120 }; 2121 2122 static int hclge_dbg_dump_vlan_filter_config(struct hclge_dev *hdev, char *buf, 2123 int len, int *pos) 2124 { 2125 char content[HCLGE_DBG_VLAN_FLTR_INFO_LEN], str_id[HCLGE_DBG_ID_LEN]; 2126 const char *result[ARRAY_SIZE(vlan_filter_items)]; 2127 u8 i, j, vlan_fe, bypass, ingress, egress; 2128 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 2129 int ret; 2130 2131 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_PORT, 0, 2132 &vlan_fe); 2133 if (ret) 2134 return ret; 2135 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B; 2136 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0; 2137 2138 *pos += scnprintf(buf, len, "I_PORT_VLAN_FILTER: %s\n", 2139 state_str[ingress]); 2140 *pos += scnprintf(buf + *pos, len - *pos, "E_PORT_VLAN_FILTER: %s\n", 2141 state_str[egress]); 2142 2143 hclge_dbg_fill_content(content, sizeof(content), vlan_filter_items, 2144 NULL, ARRAY_SIZE(vlan_filter_items)); 2145 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2146 2147 for (i = 0; i < func_num; i++) { 2148 ret = hclge_get_vlan_filter_state(hdev, HCLGE_FILTER_TYPE_VF, i, 2149 &vlan_fe); 2150 if (ret) 2151 return ret; 2152 2153 ingress = vlan_fe & HCLGE_FILTER_FE_NIC_INGRESS_B; 2154 egress = vlan_fe & HCLGE_FILTER_FE_NIC_EGRESS_B ? 1 : 0; 2155 ret = hclge_get_port_vlan_filter_bypass_state(hdev, i, &bypass); 2156 if (ret) 2157 return ret; 2158 j = 0; 2159 result[j++] = hclge_dbg_get_func_id_str(str_id, i); 2160 result[j++] = state_str[ingress]; 2161 result[j++] = state_str[egress]; 2162 result[j++] = 2163 test_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, 2164 hdev->ae_dev->caps) ? state_str[bypass] : "NA"; 2165 hclge_dbg_fill_content(content, sizeof(content), 2166 vlan_filter_items, result, 2167 ARRAY_SIZE(vlan_filter_items)); 2168 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2169 } 2170 *pos += scnprintf(buf + *pos, len - *pos, "\n"); 2171 2172 return 0; 2173 } 2174 2175 static int hclge_dbg_dump_vlan_offload_config(struct hclge_dev *hdev, char *buf, 2176 int len, int *pos) 2177 { 2178 char str_id[HCLGE_DBG_ID_LEN], str_pvid[HCLGE_DBG_ID_LEN]; 2179 const char *result[ARRAY_SIZE(vlan_offload_items)]; 2180 char content[HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN]; 2181 u8 func_num = pci_num_vf(hdev->pdev) + 1; /* pf and enabled vf num */ 2182 struct hclge_dbg_vlan_cfg vlan_cfg; 2183 int ret; 2184 u8 i, j; 2185 2186 hclge_dbg_fill_content(content, sizeof(content), vlan_offload_items, 2187 NULL, ARRAY_SIZE(vlan_offload_items)); 2188 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2189 2190 for (i = 0; i < func_num; i++) { 2191 ret = hclge_get_vlan_tx_offload_cfg(hdev, i, &vlan_cfg); 2192 if (ret) 2193 return ret; 2194 2195 ret = hclge_get_vlan_rx_offload_cfg(hdev, i, &vlan_cfg); 2196 if (ret) 2197 return ret; 2198 2199 sprintf(str_pvid, "%u", vlan_cfg.pvid); 2200 j = 0; 2201 result[j++] = hclge_dbg_get_func_id_str(str_id, i); 2202 result[j++] = str_pvid; 2203 result[j++] = state_str[vlan_cfg.accept_tag1]; 2204 result[j++] = state_str[vlan_cfg.accept_tag2]; 2205 result[j++] = state_str[vlan_cfg.accept_untag1]; 2206 result[j++] = state_str[vlan_cfg.accept_untag2]; 2207 result[j++] = state_str[vlan_cfg.insert_tag1]; 2208 result[j++] = state_str[vlan_cfg.insert_tag2]; 2209 result[j++] = state_str[vlan_cfg.shift_tag]; 2210 result[j++] = state_str[vlan_cfg.strip_tag1]; 2211 result[j++] = state_str[vlan_cfg.strip_tag2]; 2212 result[j++] = state_str[vlan_cfg.drop_tag1]; 2213 result[j++] = state_str[vlan_cfg.drop_tag2]; 2214 result[j++] = state_str[vlan_cfg.pri_only1]; 2215 result[j++] = state_str[vlan_cfg.pri_only2]; 2216 2217 hclge_dbg_fill_content(content, sizeof(content), 2218 vlan_offload_items, result, 2219 ARRAY_SIZE(vlan_offload_items)); 2220 *pos += scnprintf(buf + *pos, len - *pos, "%s", content); 2221 } 2222 2223 return 0; 2224 } 2225 2226 static int hclge_dbg_dump_vlan_config(struct hclge_dev *hdev, char *buf, 2227 int len) 2228 { 2229 int pos = 0; 2230 int ret; 2231 2232 ret = hclge_dbg_dump_vlan_filter_config(hdev, buf, len, &pos); 2233 if (ret) 2234 return ret; 2235 2236 return hclge_dbg_dump_vlan_offload_config(hdev, buf, len, &pos); 2237 } 2238 2239 static int hclge_dbg_dump_ptp_info(struct hclge_dev *hdev, char *buf, int len) 2240 { 2241 struct hclge_ptp *ptp = hdev->ptp; 2242 u32 sw_cfg = ptp->ptp_cfg; 2243 unsigned int tx_start; 2244 unsigned int last_rx; 2245 int pos = 0; 2246 u32 hw_cfg; 2247 int ret; 2248 2249 pos += scnprintf(buf + pos, len - pos, "phc %s's debug info:\n", 2250 ptp->info.name); 2251 pos += scnprintf(buf + pos, len - pos, "ptp enable: %s\n", 2252 test_bit(HCLGE_PTP_FLAG_EN, &ptp->flags) ? 2253 "yes" : "no"); 2254 pos += scnprintf(buf + pos, len - pos, "ptp tx enable: %s\n", 2255 test_bit(HCLGE_PTP_FLAG_TX_EN, &ptp->flags) ? 2256 "yes" : "no"); 2257 pos += scnprintf(buf + pos, len - pos, "ptp rx enable: %s\n", 2258 test_bit(HCLGE_PTP_FLAG_RX_EN, &ptp->flags) ? 2259 "yes" : "no"); 2260 2261 last_rx = jiffies_to_msecs(ptp->last_rx); 2262 pos += scnprintf(buf + pos, len - pos, "last rx time: %lu.%lu\n", 2263 last_rx / MSEC_PER_SEC, last_rx % MSEC_PER_SEC); 2264 pos += scnprintf(buf + pos, len - pos, "rx count: %lu\n", ptp->rx_cnt); 2265 2266 tx_start = jiffies_to_msecs(ptp->tx_start); 2267 pos += scnprintf(buf + pos, len - pos, "last tx start time: %lu.%lu\n", 2268 tx_start / MSEC_PER_SEC, tx_start % MSEC_PER_SEC); 2269 pos += scnprintf(buf + pos, len - pos, "tx count: %lu\n", ptp->tx_cnt); 2270 pos += scnprintf(buf + pos, len - pos, "tx skipped count: %lu\n", 2271 ptp->tx_skipped); 2272 pos += scnprintf(buf + pos, len - pos, "tx timeout count: %lu\n", 2273 ptp->tx_timeout); 2274 pos += scnprintf(buf + pos, len - pos, "last tx seqid: %u\n", 2275 ptp->last_tx_seqid); 2276 2277 ret = hclge_ptp_cfg_qry(hdev, &hw_cfg); 2278 if (ret) 2279 return ret; 2280 2281 pos += scnprintf(buf + pos, len - pos, "sw_cfg: %#x, hw_cfg: %#x\n", 2282 sw_cfg, hw_cfg); 2283 2284 pos += scnprintf(buf + pos, len - pos, "tx type: %d, rx filter: %d\n", 2285 ptp->ts_cfg.tx_type, ptp->ts_cfg.rx_filter); 2286 2287 return 0; 2288 } 2289 2290 static int hclge_dbg_dump_mac_uc(struct hclge_dev *hdev, char *buf, int len) 2291 { 2292 hclge_dbg_dump_mac_list(hdev, buf, len, true); 2293 2294 return 0; 2295 } 2296 2297 static int hclge_dbg_dump_mac_mc(struct hclge_dev *hdev, char *buf, int len) 2298 { 2299 hclge_dbg_dump_mac_list(hdev, buf, len, false); 2300 2301 return 0; 2302 } 2303 2304 static const struct hclge_dbg_func hclge_dbg_cmd_func[] = { 2305 { 2306 .cmd = HNAE3_DBG_CMD_TM_NODES, 2307 .dbg_dump = hclge_dbg_dump_tm_nodes, 2308 }, 2309 { 2310 .cmd = HNAE3_DBG_CMD_TM_PRI, 2311 .dbg_dump = hclge_dbg_dump_tm_pri, 2312 }, 2313 { 2314 .cmd = HNAE3_DBG_CMD_TM_QSET, 2315 .dbg_dump = hclge_dbg_dump_tm_qset, 2316 }, 2317 { 2318 .cmd = HNAE3_DBG_CMD_TM_MAP, 2319 .dbg_dump = hclge_dbg_dump_tm_map, 2320 }, 2321 { 2322 .cmd = HNAE3_DBG_CMD_TM_PG, 2323 .dbg_dump = hclge_dbg_dump_tm_pg, 2324 }, 2325 { 2326 .cmd = HNAE3_DBG_CMD_TM_PORT, 2327 .dbg_dump = hclge_dbg_dump_tm_port, 2328 }, 2329 { 2330 .cmd = HNAE3_DBG_CMD_TC_SCH_INFO, 2331 .dbg_dump = hclge_dbg_dump_tc, 2332 }, 2333 { 2334 .cmd = HNAE3_DBG_CMD_QOS_PAUSE_CFG, 2335 .dbg_dump = hclge_dbg_dump_qos_pause_cfg, 2336 }, 2337 { 2338 .cmd = HNAE3_DBG_CMD_QOS_PRI_MAP, 2339 .dbg_dump = hclge_dbg_dump_qos_pri_map, 2340 }, 2341 { 2342 .cmd = HNAE3_DBG_CMD_QOS_BUF_CFG, 2343 .dbg_dump = hclge_dbg_dump_qos_buf_cfg, 2344 }, 2345 { 2346 .cmd = HNAE3_DBG_CMD_MAC_UC, 2347 .dbg_dump = hclge_dbg_dump_mac_uc, 2348 }, 2349 { 2350 .cmd = HNAE3_DBG_CMD_MAC_MC, 2351 .dbg_dump = hclge_dbg_dump_mac_mc, 2352 }, 2353 { 2354 .cmd = HNAE3_DBG_CMD_MNG_TBL, 2355 .dbg_dump = hclge_dbg_dump_mng_table, 2356 }, 2357 { 2358 .cmd = HNAE3_DBG_CMD_LOOPBACK, 2359 .dbg_dump = hclge_dbg_dump_loopback, 2360 }, 2361 { 2362 .cmd = HNAE3_DBG_CMD_PTP_INFO, 2363 .dbg_dump = hclge_dbg_dump_ptp_info, 2364 }, 2365 { 2366 .cmd = HNAE3_DBG_CMD_INTERRUPT_INFO, 2367 .dbg_dump = hclge_dbg_dump_interrupt, 2368 }, 2369 { 2370 .cmd = HNAE3_DBG_CMD_RESET_INFO, 2371 .dbg_dump = hclge_dbg_dump_rst_info, 2372 }, 2373 { 2374 .cmd = HNAE3_DBG_CMD_IMP_INFO, 2375 .dbg_dump = hclge_dbg_get_imp_stats_info, 2376 }, 2377 { 2378 .cmd = HNAE3_DBG_CMD_NCL_CONFIG, 2379 .dbg_dump = hclge_dbg_dump_ncl_config, 2380 }, 2381 { 2382 .cmd = HNAE3_DBG_CMD_REG_BIOS_COMMON, 2383 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2384 }, 2385 { 2386 .cmd = HNAE3_DBG_CMD_REG_SSU, 2387 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2388 }, 2389 { 2390 .cmd = HNAE3_DBG_CMD_REG_IGU_EGU, 2391 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2392 }, 2393 { 2394 .cmd = HNAE3_DBG_CMD_REG_RPU, 2395 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2396 }, 2397 { 2398 .cmd = HNAE3_DBG_CMD_REG_NCSI, 2399 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2400 }, 2401 { 2402 .cmd = HNAE3_DBG_CMD_REG_RTC, 2403 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2404 }, 2405 { 2406 .cmd = HNAE3_DBG_CMD_REG_PPP, 2407 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2408 }, 2409 { 2410 .cmd = HNAE3_DBG_CMD_REG_RCB, 2411 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2412 }, 2413 { 2414 .cmd = HNAE3_DBG_CMD_REG_TQP, 2415 .dbg_dump_reg = hclge_dbg_dump_reg_cmd, 2416 }, 2417 { 2418 .cmd = HNAE3_DBG_CMD_REG_MAC, 2419 .dbg_dump = hclge_dbg_dump_mac, 2420 }, 2421 { 2422 .cmd = HNAE3_DBG_CMD_REG_DCB, 2423 .dbg_dump = hclge_dbg_dump_dcb, 2424 }, 2425 { 2426 .cmd = HNAE3_DBG_CMD_FD_TCAM, 2427 .dbg_dump = hclge_dbg_dump_fd_tcam, 2428 }, 2429 { 2430 .cmd = HNAE3_DBG_CMD_MAC_TNL_STATUS, 2431 .dbg_dump = hclge_dbg_dump_mac_tnl_status, 2432 }, 2433 { 2434 .cmd = HNAE3_DBG_CMD_SERV_INFO, 2435 .dbg_dump = hclge_dbg_dump_serv_info, 2436 }, 2437 { 2438 .cmd = HNAE3_DBG_CMD_VLAN_CONFIG, 2439 .dbg_dump = hclge_dbg_dump_vlan_config, 2440 }, 2441 { 2442 .cmd = HNAE3_DBG_CMD_FD_COUNTER, 2443 .dbg_dump = hclge_dbg_dump_fd_counter, 2444 }, 2445 { 2446 .cmd = HNAE3_DBG_CMD_UMV_INFO, 2447 .dbg_dump = hclge_dbg_dump_umv_info, 2448 }, 2449 }; 2450 2451 int hclge_dbg_read_cmd(struct hnae3_handle *handle, enum hnae3_dbg_cmd cmd, 2452 char *buf, int len) 2453 { 2454 struct hclge_vport *vport = hclge_get_vport(handle); 2455 const struct hclge_dbg_func *cmd_func; 2456 struct hclge_dev *hdev = vport->back; 2457 u32 i; 2458 2459 for (i = 0; i < ARRAY_SIZE(hclge_dbg_cmd_func); i++) { 2460 if (cmd == hclge_dbg_cmd_func[i].cmd) { 2461 cmd_func = &hclge_dbg_cmd_func[i]; 2462 if (cmd_func->dbg_dump) 2463 return cmd_func->dbg_dump(hdev, buf, len); 2464 else 2465 return cmd_func->dbg_dump_reg(hdev, cmd, buf, 2466 len); 2467 } 2468 } 2469 2470 dev_err(&hdev->pdev->dev, "invalid command(%d)\n", cmd); 2471 return -EINVAL; 2472 } 2473