1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) 2018-2019 Hisilicon Limited. */ 3 4 #include <linux/device.h> 5 6 #include "hclge_debugfs.h" 7 #include "hclge_cmd.h" 8 #include "hclge_main.h" 9 #include "hclge_tm.h" 10 #include "hnae3.h" 11 12 static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev, int offset) 13 { 14 struct hclge_desc desc[4]; 15 int ret; 16 17 ret = hclge_query_bd_num_cmd_send(hdev, desc); 18 if (ret) { 19 dev_err(&hdev->pdev->dev, 20 "get dfx bdnum fail, status is %d.\n", ret); 21 return ret; 22 } 23 24 return (int)desc[offset / 6].data[offset % 6]; 25 } 26 27 static int hclge_dbg_cmd_send(struct hclge_dev *hdev, 28 struct hclge_desc *desc_src, 29 int index, int bd_num, 30 enum hclge_opcode_type cmd) 31 { 32 struct hclge_desc *desc = desc_src; 33 int ret, i; 34 35 hclge_cmd_setup_basic_desc(desc, cmd, true); 36 desc->data[0] = cpu_to_le32(index); 37 38 for (i = 1; i < bd_num; i++) { 39 desc->flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 40 desc++; 41 hclge_cmd_setup_basic_desc(desc, cmd, true); 42 } 43 44 ret = hclge_cmd_send(&hdev->hw, desc_src, bd_num); 45 if (ret) { 46 dev_err(&hdev->pdev->dev, 47 "read reg cmd send fail, status is %d.\n", ret); 48 return ret; 49 } 50 51 return ret; 52 } 53 54 static void hclge_dbg_dump_reg_common(struct hclge_dev *hdev, 55 struct hclge_dbg_dfx_message *dfx_message, 56 const char *cmd_buf, int msg_num, 57 int offset, enum hclge_opcode_type cmd) 58 { 59 #define BD_DATA_NUM 6 60 61 struct hclge_desc *desc_src; 62 struct hclge_desc *desc; 63 int bd_num, buf_len; 64 int ret, i; 65 int index; 66 int max; 67 68 ret = kstrtouint(cmd_buf, 10, &index); 69 index = (ret != 0) ? 0 : index; 70 71 bd_num = hclge_dbg_get_dfx_bd_num(hdev, offset); 72 if (bd_num <= 0) 73 return; 74 75 buf_len = sizeof(struct hclge_desc) * bd_num; 76 desc_src = kzalloc(buf_len, GFP_KERNEL); 77 if (!desc_src) { 78 dev_err(&hdev->pdev->dev, "call kzalloc failed\n"); 79 return; 80 } 81 82 desc = desc_src; 83 ret = hclge_dbg_cmd_send(hdev, desc, index, bd_num, cmd); 84 if (ret != HCLGE_CMD_EXEC_SUCCESS) { 85 kfree(desc_src); 86 return; 87 } 88 89 max = (bd_num * BD_DATA_NUM) <= msg_num ? 90 (bd_num * BD_DATA_NUM) : msg_num; 91 92 desc = desc_src; 93 for (i = 0; i < max; i++) { 94 ((i > 0) && ((i % BD_DATA_NUM) == 0)) ? desc++ : desc; 95 if (dfx_message->flag) 96 dev_info(&hdev->pdev->dev, "%s: 0x%x\n", 97 dfx_message->message, 98 desc->data[i % BD_DATA_NUM]); 99 100 dfx_message++; 101 } 102 103 kfree(desc_src); 104 } 105 106 static void hclge_dbg_dump_dcb(struct hclge_dev *hdev, const char *cmd_buf) 107 { 108 struct device *dev = &hdev->pdev->dev; 109 struct hclge_dbg_bitmap_cmd *bitmap; 110 int rq_id, pri_id, qset_id; 111 int port_id, nq_id, pg_id; 112 struct hclge_desc desc[2]; 113 114 int cnt, ret; 115 116 cnt = sscanf(cmd_buf, "%i %i %i %i %i %i", 117 &port_id, &pri_id, &pg_id, &rq_id, &nq_id, &qset_id); 118 if (cnt != 6) { 119 dev_err(&hdev->pdev->dev, 120 "dump dcb: bad command parameter, cnt=%d\n", cnt); 121 return; 122 } 123 124 ret = hclge_dbg_cmd_send(hdev, desc, qset_id, 1, 125 HCLGE_OPC_QSET_DFX_STS); 126 if (ret) 127 return; 128 129 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 130 dev_info(dev, "roce_qset_mask: 0x%x\n", bitmap->bit0); 131 dev_info(dev, "nic_qs_mask: 0x%x\n", bitmap->bit1); 132 dev_info(dev, "qs_shaping_pass: 0x%x\n", bitmap->bit2); 133 dev_info(dev, "qs_bp_sts: 0x%x\n", bitmap->bit3); 134 135 ret = hclge_dbg_cmd_send(hdev, desc, pri_id, 1, HCLGE_OPC_PRI_DFX_STS); 136 if (ret) 137 return; 138 139 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 140 dev_info(dev, "pri_mask: 0x%x\n", bitmap->bit0); 141 dev_info(dev, "pri_cshaping_pass: 0x%x\n", bitmap->bit1); 142 dev_info(dev, "pri_pshaping_pass: 0x%x\n", bitmap->bit2); 143 144 ret = hclge_dbg_cmd_send(hdev, desc, pg_id, 1, HCLGE_OPC_PG_DFX_STS); 145 if (ret) 146 return; 147 148 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 149 dev_info(dev, "pg_mask: 0x%x\n", bitmap->bit0); 150 dev_info(dev, "pg_cshaping_pass: 0x%x\n", bitmap->bit1); 151 dev_info(dev, "pg_pshaping_pass: 0x%x\n", bitmap->bit2); 152 153 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 154 HCLGE_OPC_PORT_DFX_STS); 155 if (ret) 156 return; 157 158 bitmap = (struct hclge_dbg_bitmap_cmd *)&desc[0].data[1]; 159 dev_info(dev, "port_mask: 0x%x\n", bitmap->bit0); 160 dev_info(dev, "port_shaping_pass: 0x%x\n", bitmap->bit1); 161 162 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_NQ_CNT); 163 if (ret) 164 return; 165 166 dev_info(dev, "sch_nq_cnt: 0x%x\n", desc[0].data[1]); 167 168 ret = hclge_dbg_cmd_send(hdev, desc, nq_id, 1, HCLGE_OPC_SCH_RQ_CNT); 169 if (ret) 170 return; 171 172 dev_info(dev, "sch_rq_cnt: 0x%x\n", desc[0].data[1]); 173 174 ret = hclge_dbg_cmd_send(hdev, desc, 0, 2, HCLGE_OPC_TM_INTERNAL_STS); 175 if (ret) 176 return; 177 178 dev_info(dev, "pri_bp: 0x%x\n", desc[0].data[1]); 179 dev_info(dev, "fifo_dfx_info: 0x%x\n", desc[0].data[2]); 180 dev_info(dev, "sch_roce_fifo_afull_gap: 0x%x\n", desc[0].data[3]); 181 dev_info(dev, "tx_private_waterline: 0x%x\n", desc[0].data[4]); 182 dev_info(dev, "tm_bypass_en: 0x%x\n", desc[0].data[5]); 183 dev_info(dev, "SSU_TM_BYPASS_EN: 0x%x\n", desc[1].data[0]); 184 dev_info(dev, "SSU_RESERVE_CFG: 0x%x\n", desc[1].data[1]); 185 186 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 187 HCLGE_OPC_TM_INTERNAL_CNT); 188 if (ret) 189 return; 190 191 dev_info(dev, "SCH_NIC_NUM: 0x%x\n", desc[0].data[1]); 192 dev_info(dev, "SCH_ROCE_NUM: 0x%x\n", desc[0].data[2]); 193 194 ret = hclge_dbg_cmd_send(hdev, desc, port_id, 1, 195 HCLGE_OPC_TM_INTERNAL_STS_1); 196 if (ret) 197 return; 198 199 dev_info(dev, "TC_MAP_SEL: 0x%x\n", desc[0].data[1]); 200 dev_info(dev, "IGU_PFC_PRI_EN: 0x%x\n", desc[0].data[2]); 201 dev_info(dev, "MAC_PFC_PRI_EN: 0x%x\n", desc[0].data[3]); 202 dev_info(dev, "IGU_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[4]); 203 dev_info(dev, "IGU_TX_PRI_MAP_TC_CFG: 0x%x\n", desc[0].data[5]); 204 } 205 206 static void hclge_dbg_dump_reg_cmd(struct hclge_dev *hdev, const char *cmd_buf) 207 { 208 int msg_num; 209 210 if (strncmp(&cmd_buf[9], "bios common", 11) == 0) { 211 msg_num = sizeof(hclge_dbg_bios_common_reg) / 212 sizeof(struct hclge_dbg_dfx_message); 213 hclge_dbg_dump_reg_common(hdev, hclge_dbg_bios_common_reg, 214 &cmd_buf[21], msg_num, 215 HCLGE_DBG_DFX_BIOS_OFFSET, 216 HCLGE_OPC_DFX_BIOS_COMMON_REG); 217 } else if (strncmp(&cmd_buf[9], "ssu", 3) == 0) { 218 msg_num = sizeof(hclge_dbg_ssu_reg_0) / 219 sizeof(struct hclge_dbg_dfx_message); 220 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_0, 221 &cmd_buf[13], msg_num, 222 HCLGE_DBG_DFX_SSU_0_OFFSET, 223 HCLGE_OPC_DFX_SSU_REG_0); 224 225 msg_num = sizeof(hclge_dbg_ssu_reg_1) / 226 sizeof(struct hclge_dbg_dfx_message); 227 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_1, 228 &cmd_buf[13], msg_num, 229 HCLGE_DBG_DFX_SSU_1_OFFSET, 230 HCLGE_OPC_DFX_SSU_REG_1); 231 232 msg_num = sizeof(hclge_dbg_ssu_reg_2) / 233 sizeof(struct hclge_dbg_dfx_message); 234 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ssu_reg_2, 235 &cmd_buf[13], msg_num, 236 HCLGE_DBG_DFX_SSU_2_OFFSET, 237 HCLGE_OPC_DFX_SSU_REG_2); 238 } else if (strncmp(&cmd_buf[9], "igu egu", 7) == 0) { 239 msg_num = sizeof(hclge_dbg_igu_egu_reg) / 240 sizeof(struct hclge_dbg_dfx_message); 241 hclge_dbg_dump_reg_common(hdev, hclge_dbg_igu_egu_reg, 242 &cmd_buf[17], msg_num, 243 HCLGE_DBG_DFX_IGU_OFFSET, 244 HCLGE_OPC_DFX_IGU_EGU_REG); 245 } else if (strncmp(&cmd_buf[9], "rpu", 3) == 0) { 246 msg_num = sizeof(hclge_dbg_rpu_reg_0) / 247 sizeof(struct hclge_dbg_dfx_message); 248 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_0, 249 &cmd_buf[13], msg_num, 250 HCLGE_DBG_DFX_RPU_0_OFFSET, 251 HCLGE_OPC_DFX_RPU_REG_0); 252 253 msg_num = sizeof(hclge_dbg_rpu_reg_1) / 254 sizeof(struct hclge_dbg_dfx_message); 255 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rpu_reg_1, 256 &cmd_buf[13], msg_num, 257 HCLGE_DBG_DFX_RPU_1_OFFSET, 258 HCLGE_OPC_DFX_RPU_REG_1); 259 } else if (strncmp(&cmd_buf[9], "ncsi", 4) == 0) { 260 msg_num = sizeof(hclge_dbg_ncsi_reg) / 261 sizeof(struct hclge_dbg_dfx_message); 262 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ncsi_reg, 263 &cmd_buf[14], msg_num, 264 HCLGE_DBG_DFX_NCSI_OFFSET, 265 HCLGE_OPC_DFX_NCSI_REG); 266 } else if (strncmp(&cmd_buf[9], "rtc", 3) == 0) { 267 msg_num = sizeof(hclge_dbg_rtc_reg) / 268 sizeof(struct hclge_dbg_dfx_message); 269 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rtc_reg, 270 &cmd_buf[13], msg_num, 271 HCLGE_DBG_DFX_RTC_OFFSET, 272 HCLGE_OPC_DFX_RTC_REG); 273 } else if (strncmp(&cmd_buf[9], "ppp", 3) == 0) { 274 msg_num = sizeof(hclge_dbg_ppp_reg) / 275 sizeof(struct hclge_dbg_dfx_message); 276 hclge_dbg_dump_reg_common(hdev, hclge_dbg_ppp_reg, 277 &cmd_buf[13], msg_num, 278 HCLGE_DBG_DFX_PPP_OFFSET, 279 HCLGE_OPC_DFX_PPP_REG); 280 } else if (strncmp(&cmd_buf[9], "rcb", 3) == 0) { 281 msg_num = sizeof(hclge_dbg_rcb_reg) / 282 sizeof(struct hclge_dbg_dfx_message); 283 hclge_dbg_dump_reg_common(hdev, hclge_dbg_rcb_reg, 284 &cmd_buf[13], msg_num, 285 HCLGE_DBG_DFX_RCB_OFFSET, 286 HCLGE_OPC_DFX_RCB_REG); 287 } else if (strncmp(&cmd_buf[9], "tqp", 3) == 0) { 288 msg_num = sizeof(hclge_dbg_tqp_reg) / 289 sizeof(struct hclge_dbg_dfx_message); 290 hclge_dbg_dump_reg_common(hdev, hclge_dbg_tqp_reg, 291 &cmd_buf[13], msg_num, 292 HCLGE_DBG_DFX_TQP_OFFSET, 293 HCLGE_OPC_DFX_TQP_REG); 294 } else if (strncmp(&cmd_buf[9], "dcb", 3) == 0) { 295 hclge_dbg_dump_dcb(hdev, &cmd_buf[13]); 296 } else { 297 dev_info(&hdev->pdev->dev, "unknown command\n"); 298 return; 299 } 300 } 301 302 static void hclge_title_idx_print(struct hclge_dev *hdev, bool flag, int index, 303 char *title_buf, char *true_buf, 304 char *false_buf) 305 { 306 if (flag) 307 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 308 true_buf); 309 else 310 dev_info(&hdev->pdev->dev, "%s(%d): %s\n", title_buf, index, 311 false_buf); 312 } 313 314 static void hclge_dbg_dump_tc(struct hclge_dev *hdev) 315 { 316 struct hclge_ets_tc_weight_cmd *ets_weight; 317 struct hclge_desc desc; 318 int i, ret; 319 320 if (!hnae3_dev_dcb_supported(hdev)) { 321 dev_info(&hdev->pdev->dev, 322 "Only DCB-supported dev supports tc\n"); 323 return; 324 } 325 326 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, true); 327 328 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 329 if (ret) { 330 dev_err(&hdev->pdev->dev, "dump tc fail, status is %d.\n", ret); 331 return; 332 } 333 334 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data; 335 336 dev_info(&hdev->pdev->dev, "dump tc\n"); 337 dev_info(&hdev->pdev->dev, "weight_offset: %u\n", 338 ets_weight->weight_offset); 339 340 for (i = 0; i < HNAE3_MAX_TC; i++) 341 hclge_title_idx_print(hdev, ets_weight->tc_weight[i], i, 342 "tc", "no sp mode", "sp mode"); 343 } 344 345 static void hclge_dbg_dump_tm_pg(struct hclge_dev *hdev) 346 { 347 struct hclge_port_shapping_cmd *port_shap_cfg_cmd; 348 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 349 struct hclge_pg_shapping_cmd *pg_shap_cfg_cmd; 350 enum hclge_opcode_type cmd; 351 struct hclge_desc desc; 352 int ret; 353 354 cmd = HCLGE_OPC_TM_PG_C_SHAPPING; 355 hclge_cmd_setup_basic_desc(&desc, cmd, true); 356 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 357 if (ret) 358 goto err_tm_pg_cmd_send; 359 360 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 361 dev_info(&hdev->pdev->dev, "PG_C pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 362 dev_info(&hdev->pdev->dev, "PG_C pg_shapping: 0x%x\n", 363 pg_shap_cfg_cmd->pg_shapping_para); 364 365 cmd = HCLGE_OPC_TM_PG_P_SHAPPING; 366 hclge_cmd_setup_basic_desc(&desc, cmd, true); 367 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 368 if (ret) 369 goto err_tm_pg_cmd_send; 370 371 pg_shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data; 372 dev_info(&hdev->pdev->dev, "PG_P pg_id: %u\n", pg_shap_cfg_cmd->pg_id); 373 dev_info(&hdev->pdev->dev, "PG_P pg_shapping: 0x%x\n", 374 pg_shap_cfg_cmd->pg_shapping_para); 375 376 cmd = HCLGE_OPC_TM_PORT_SHAPPING; 377 hclge_cmd_setup_basic_desc(&desc, cmd, true); 378 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 379 if (ret) 380 goto err_tm_pg_cmd_send; 381 382 port_shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data; 383 dev_info(&hdev->pdev->dev, "PORT port_shapping: 0x%x\n", 384 port_shap_cfg_cmd->port_shapping_para); 385 386 cmd = HCLGE_OPC_TM_PG_SCH_MODE_CFG; 387 hclge_cmd_setup_basic_desc(&desc, cmd, true); 388 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 389 if (ret) 390 goto err_tm_pg_cmd_send; 391 392 dev_info(&hdev->pdev->dev, "PG_SCH pg_id: %u\n", desc.data[0]); 393 394 cmd = HCLGE_OPC_TM_PRI_SCH_MODE_CFG; 395 hclge_cmd_setup_basic_desc(&desc, cmd, true); 396 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 397 if (ret) 398 goto err_tm_pg_cmd_send; 399 400 dev_info(&hdev->pdev->dev, "PRI_SCH pri_id: %u\n", desc.data[0]); 401 402 cmd = HCLGE_OPC_TM_QS_SCH_MODE_CFG; 403 hclge_cmd_setup_basic_desc(&desc, cmd, true); 404 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 405 if (ret) 406 goto err_tm_pg_cmd_send; 407 408 dev_info(&hdev->pdev->dev, "QS_SCH qs_id: %u\n", desc.data[0]); 409 410 if (!hnae3_dev_dcb_supported(hdev)) { 411 dev_info(&hdev->pdev->dev, 412 "Only DCB-supported dev supports tm mapping\n"); 413 return; 414 } 415 416 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING; 417 hclge_cmd_setup_basic_desc(&desc, cmd, true); 418 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 419 if (ret) 420 goto err_tm_pg_cmd_send; 421 422 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 423 dev_info(&hdev->pdev->dev, "BP_TO_QSET tc_id: %u\n", 424 bp_to_qs_map_cmd->tc_id); 425 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_group_id: 0x%x\n", 426 bp_to_qs_map_cmd->qs_group_id); 427 dev_info(&hdev->pdev->dev, "BP_TO_QSET qs_bit_map: 0x%x\n", 428 bp_to_qs_map_cmd->qs_bit_map); 429 return; 430 431 err_tm_pg_cmd_send: 432 dev_err(&hdev->pdev->dev, "dump tm_pg fail(0x%x), status is %d\n", 433 cmd, ret); 434 } 435 436 static void hclge_dbg_dump_tm(struct hclge_dev *hdev) 437 { 438 struct hclge_priority_weight_cmd *priority_weight; 439 struct hclge_pg_to_pri_link_cmd *pg_to_pri_map; 440 struct hclge_qs_to_pri_link_cmd *qs_to_pri_map; 441 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map; 442 struct hclge_pri_shapping_cmd *shap_cfg_cmd; 443 struct hclge_pg_weight_cmd *pg_weight; 444 struct hclge_qs_weight_cmd *qs_weight; 445 enum hclge_opcode_type cmd; 446 struct hclge_desc desc; 447 int ret; 448 449 cmd = HCLGE_OPC_TM_PG_TO_PRI_LINK; 450 hclge_cmd_setup_basic_desc(&desc, cmd, true); 451 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 452 if (ret) 453 goto err_tm_cmd_send; 454 455 pg_to_pri_map = (struct hclge_pg_to_pri_link_cmd *)desc.data; 456 dev_info(&hdev->pdev->dev, "dump tm\n"); 457 dev_info(&hdev->pdev->dev, "PG_TO_PRI gp_id: %u\n", 458 pg_to_pri_map->pg_id); 459 dev_info(&hdev->pdev->dev, "PG_TO_PRI map: 0x%x\n", 460 pg_to_pri_map->pri_bit_map); 461 462 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; 463 hclge_cmd_setup_basic_desc(&desc, cmd, true); 464 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 465 if (ret) 466 goto err_tm_cmd_send; 467 468 qs_to_pri_map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 469 dev_info(&hdev->pdev->dev, "QS_TO_PRI qs_id: %u\n", 470 qs_to_pri_map->qs_id); 471 dev_info(&hdev->pdev->dev, "QS_TO_PRI priority: %u\n", 472 qs_to_pri_map->priority); 473 dev_info(&hdev->pdev->dev, "QS_TO_PRI link_vld: %u\n", 474 qs_to_pri_map->link_vld); 475 476 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK; 477 hclge_cmd_setup_basic_desc(&desc, cmd, true); 478 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 479 if (ret) 480 goto err_tm_cmd_send; 481 482 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 483 dev_info(&hdev->pdev->dev, "NQ_TO_QS nq_id: %u\n", nq_to_qs_map->nq_id); 484 dev_info(&hdev->pdev->dev, "NQ_TO_QS qset_id: 0x%x\n", 485 nq_to_qs_map->qset_id); 486 487 cmd = HCLGE_OPC_TM_PG_WEIGHT; 488 hclge_cmd_setup_basic_desc(&desc, cmd, true); 489 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 490 if (ret) 491 goto err_tm_cmd_send; 492 493 pg_weight = (struct hclge_pg_weight_cmd *)desc.data; 494 dev_info(&hdev->pdev->dev, "PG pg_id: %u\n", pg_weight->pg_id); 495 dev_info(&hdev->pdev->dev, "PG dwrr: %u\n", pg_weight->dwrr); 496 497 cmd = HCLGE_OPC_TM_QS_WEIGHT; 498 hclge_cmd_setup_basic_desc(&desc, cmd, true); 499 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 500 if (ret) 501 goto err_tm_cmd_send; 502 503 qs_weight = (struct hclge_qs_weight_cmd *)desc.data; 504 dev_info(&hdev->pdev->dev, "QS qs_id: %u\n", qs_weight->qs_id); 505 dev_info(&hdev->pdev->dev, "QS dwrr: %u\n", qs_weight->dwrr); 506 507 cmd = HCLGE_OPC_TM_PRI_WEIGHT; 508 hclge_cmd_setup_basic_desc(&desc, cmd, true); 509 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 510 if (ret) 511 goto err_tm_cmd_send; 512 513 priority_weight = (struct hclge_priority_weight_cmd *)desc.data; 514 dev_info(&hdev->pdev->dev, "PRI pri_id: %u\n", priority_weight->pri_id); 515 dev_info(&hdev->pdev->dev, "PRI dwrr: %u\n", priority_weight->dwrr); 516 517 cmd = HCLGE_OPC_TM_PRI_C_SHAPPING; 518 hclge_cmd_setup_basic_desc(&desc, cmd, true); 519 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 520 if (ret) 521 goto err_tm_cmd_send; 522 523 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 524 dev_info(&hdev->pdev->dev, "PRI_C pri_id: %u\n", shap_cfg_cmd->pri_id); 525 dev_info(&hdev->pdev->dev, "PRI_C pri_shapping: 0x%x\n", 526 shap_cfg_cmd->pri_shapping_para); 527 528 cmd = HCLGE_OPC_TM_PRI_P_SHAPPING; 529 hclge_cmd_setup_basic_desc(&desc, cmd, true); 530 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 531 if (ret) 532 goto err_tm_cmd_send; 533 534 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; 535 dev_info(&hdev->pdev->dev, "PRI_P pri_id: %u\n", shap_cfg_cmd->pri_id); 536 dev_info(&hdev->pdev->dev, "PRI_P pri_shapping: 0x%x\n", 537 shap_cfg_cmd->pri_shapping_para); 538 539 hclge_dbg_dump_tm_pg(hdev); 540 541 return; 542 543 err_tm_cmd_send: 544 dev_err(&hdev->pdev->dev, "dump tm fail(0x%x), status is %d\n", 545 cmd, ret); 546 } 547 548 static void hclge_dbg_dump_tm_map(struct hclge_dev *hdev, 549 const char *cmd_buf) 550 { 551 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd; 552 struct hclge_nq_to_qs_link_cmd *nq_to_qs_map; 553 struct hclge_qs_to_pri_link_cmd *map; 554 struct hclge_tqp_tx_queue_tc_cmd *tc; 555 enum hclge_opcode_type cmd; 556 struct hclge_desc desc; 557 int queue_id, group_id; 558 u32 qset_maping[32]; 559 int tc_id, qset_id; 560 int pri_id, ret; 561 u32 i; 562 563 ret = kstrtouint(&cmd_buf[12], 10, &queue_id); 564 queue_id = (ret != 0) ? 0 : queue_id; 565 566 cmd = HCLGE_OPC_TM_NQ_TO_QS_LINK; 567 nq_to_qs_map = (struct hclge_nq_to_qs_link_cmd *)desc.data; 568 hclge_cmd_setup_basic_desc(&desc, cmd, true); 569 nq_to_qs_map->nq_id = cpu_to_le16(queue_id); 570 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 571 if (ret) 572 goto err_tm_map_cmd_send; 573 qset_id = nq_to_qs_map->qset_id & 0x3FF; 574 575 cmd = HCLGE_OPC_TM_QS_TO_PRI_LINK; 576 map = (struct hclge_qs_to_pri_link_cmd *)desc.data; 577 hclge_cmd_setup_basic_desc(&desc, cmd, true); 578 map->qs_id = cpu_to_le16(qset_id); 579 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 580 if (ret) 581 goto err_tm_map_cmd_send; 582 pri_id = map->priority; 583 584 cmd = HCLGE_OPC_TQP_TX_QUEUE_TC; 585 tc = (struct hclge_tqp_tx_queue_tc_cmd *)desc.data; 586 hclge_cmd_setup_basic_desc(&desc, cmd, true); 587 tc->queue_id = cpu_to_le16(queue_id); 588 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 589 if (ret) 590 goto err_tm_map_cmd_send; 591 tc_id = tc->tc_id & 0x7; 592 593 dev_info(&hdev->pdev->dev, "queue_id | qset_id | pri_id | tc_id\n"); 594 dev_info(&hdev->pdev->dev, "%04d | %04d | %02d | %02d\n", 595 queue_id, qset_id, pri_id, tc_id); 596 597 if (!hnae3_dev_dcb_supported(hdev)) { 598 dev_info(&hdev->pdev->dev, 599 "Only DCB-supported dev supports tm mapping\n"); 600 return; 601 } 602 603 cmd = HCLGE_OPC_TM_BP_TO_QSET_MAPPING; 604 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data; 605 for (group_id = 0; group_id < 32; group_id++) { 606 hclge_cmd_setup_basic_desc(&desc, cmd, true); 607 bp_to_qs_map_cmd->tc_id = tc_id; 608 bp_to_qs_map_cmd->qs_group_id = group_id; 609 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 610 if (ret) 611 goto err_tm_map_cmd_send; 612 613 qset_maping[group_id] = bp_to_qs_map_cmd->qs_bit_map; 614 } 615 616 dev_info(&hdev->pdev->dev, "index | tm bp qset maping:\n"); 617 618 i = 0; 619 for (group_id = 0; group_id < 4; group_id++) { 620 dev_info(&hdev->pdev->dev, 621 "%04d | %08x:%08x:%08x:%08x:%08x:%08x:%08x:%08x\n", 622 group_id * 256, qset_maping[(u32)(i + 7)], 623 qset_maping[(u32)(i + 6)], qset_maping[(u32)(i + 5)], 624 qset_maping[(u32)(i + 4)], qset_maping[(u32)(i + 3)], 625 qset_maping[(u32)(i + 2)], qset_maping[(u32)(i + 1)], 626 qset_maping[i]); 627 i += 8; 628 } 629 630 return; 631 632 err_tm_map_cmd_send: 633 dev_err(&hdev->pdev->dev, "dump tqp map fail(0x%x), status is %d\n", 634 cmd, ret); 635 } 636 637 static void hclge_dbg_dump_qos_pause_cfg(struct hclge_dev *hdev) 638 { 639 struct hclge_cfg_pause_param_cmd *pause_param; 640 struct hclge_desc desc; 641 int ret; 642 643 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true); 644 645 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 646 if (ret) { 647 dev_err(&hdev->pdev->dev, "dump checksum fail, status is %d.\n", 648 ret); 649 return; 650 } 651 652 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data; 653 dev_info(&hdev->pdev->dev, "dump qos pause cfg\n"); 654 dev_info(&hdev->pdev->dev, "pause_trans_gap: 0x%x\n", 655 pause_param->pause_trans_gap); 656 dev_info(&hdev->pdev->dev, "pause_trans_time: 0x%x\n", 657 pause_param->pause_trans_time); 658 } 659 660 static void hclge_dbg_dump_qos_pri_map(struct hclge_dev *hdev) 661 { 662 struct hclge_qos_pri_map_cmd *pri_map; 663 struct hclge_desc desc; 664 int ret; 665 666 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, true); 667 668 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 669 if (ret) { 670 dev_err(&hdev->pdev->dev, 671 "dump qos pri map fail, status is %d.\n", ret); 672 return; 673 } 674 675 pri_map = (struct hclge_qos_pri_map_cmd *)desc.data; 676 dev_info(&hdev->pdev->dev, "dump qos pri map\n"); 677 dev_info(&hdev->pdev->dev, "vlan_to_pri: 0x%x\n", pri_map->vlan_pri); 678 dev_info(&hdev->pdev->dev, "pri_0_to_tc: 0x%x\n", pri_map->pri0_tc); 679 dev_info(&hdev->pdev->dev, "pri_1_to_tc: 0x%x\n", pri_map->pri1_tc); 680 dev_info(&hdev->pdev->dev, "pri_2_to_tc: 0x%x\n", pri_map->pri2_tc); 681 dev_info(&hdev->pdev->dev, "pri_3_to_tc: 0x%x\n", pri_map->pri3_tc); 682 dev_info(&hdev->pdev->dev, "pri_4_to_tc: 0x%x\n", pri_map->pri4_tc); 683 dev_info(&hdev->pdev->dev, "pri_5_to_tc: 0x%x\n", pri_map->pri5_tc); 684 dev_info(&hdev->pdev->dev, "pri_6_to_tc: 0x%x\n", pri_map->pri6_tc); 685 dev_info(&hdev->pdev->dev, "pri_7_to_tc: 0x%x\n", pri_map->pri7_tc); 686 } 687 688 static void hclge_dbg_dump_qos_buf_cfg(struct hclge_dev *hdev) 689 { 690 struct hclge_tx_buff_alloc_cmd *tx_buf_cmd; 691 struct hclge_rx_priv_buff_cmd *rx_buf_cmd; 692 struct hclge_rx_priv_wl_buf *rx_priv_wl; 693 struct hclge_rx_com_wl *rx_packet_cnt; 694 struct hclge_rx_com_thrd *rx_com_thrd; 695 struct hclge_rx_com_wl *rx_com_wl; 696 enum hclge_opcode_type cmd; 697 struct hclge_desc desc[2]; 698 int i, ret; 699 700 cmd = HCLGE_OPC_TX_BUFF_ALLOC; 701 hclge_cmd_setup_basic_desc(desc, cmd, true); 702 ret = hclge_cmd_send(&hdev->hw, desc, 1); 703 if (ret) 704 goto err_qos_cmd_send; 705 706 dev_info(&hdev->pdev->dev, "dump qos buf cfg\n"); 707 708 tx_buf_cmd = (struct hclge_tx_buff_alloc_cmd *)desc[0].data; 709 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 710 dev_info(&hdev->pdev->dev, "tx_packet_buf_tc_%d: 0x%x\n", i, 711 tx_buf_cmd->tx_pkt_buff[i]); 712 713 cmd = HCLGE_OPC_RX_PRIV_BUFF_ALLOC; 714 hclge_cmd_setup_basic_desc(desc, cmd, true); 715 ret = hclge_cmd_send(&hdev->hw, desc, 1); 716 if (ret) 717 goto err_qos_cmd_send; 718 719 dev_info(&hdev->pdev->dev, "\n"); 720 rx_buf_cmd = (struct hclge_rx_priv_buff_cmd *)desc[0].data; 721 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) 722 dev_info(&hdev->pdev->dev, "rx_packet_buf_tc_%d: 0x%x\n", i, 723 rx_buf_cmd->buf_num[i]); 724 725 dev_info(&hdev->pdev->dev, "rx_share_buf: 0x%x\n", 726 rx_buf_cmd->shared_buf); 727 728 cmd = HCLGE_OPC_RX_COM_WL_ALLOC; 729 hclge_cmd_setup_basic_desc(desc, cmd, true); 730 ret = hclge_cmd_send(&hdev->hw, desc, 1); 731 if (ret) 732 goto err_qos_cmd_send; 733 734 rx_com_wl = (struct hclge_rx_com_wl *)desc[0].data; 735 dev_info(&hdev->pdev->dev, "\n"); 736 dev_info(&hdev->pdev->dev, "rx_com_wl: high: 0x%x, low: 0x%x\n", 737 rx_com_wl->com_wl.high, rx_com_wl->com_wl.low); 738 739 cmd = HCLGE_OPC_RX_GBL_PKT_CNT; 740 hclge_cmd_setup_basic_desc(desc, cmd, true); 741 ret = hclge_cmd_send(&hdev->hw, desc, 1); 742 if (ret) 743 goto err_qos_cmd_send; 744 745 rx_packet_cnt = (struct hclge_rx_com_wl *)desc[0].data; 746 dev_info(&hdev->pdev->dev, 747 "rx_global_packet_cnt: high: 0x%x, low: 0x%x\n", 748 rx_packet_cnt->com_wl.high, rx_packet_cnt->com_wl.low); 749 dev_info(&hdev->pdev->dev, "\n"); 750 751 if (!hnae3_dev_dcb_supported(hdev)) { 752 dev_info(&hdev->pdev->dev, 753 "Only DCB-supported dev supports rx priv wl\n"); 754 return; 755 } 756 cmd = HCLGE_OPC_RX_PRIV_WL_ALLOC; 757 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 758 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 759 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 760 ret = hclge_cmd_send(&hdev->hw, desc, 2); 761 if (ret) 762 goto err_qos_cmd_send; 763 764 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[0].data; 765 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 766 dev_info(&hdev->pdev->dev, 767 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i, 768 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 769 770 rx_priv_wl = (struct hclge_rx_priv_wl_buf *)desc[1].data; 771 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 772 dev_info(&hdev->pdev->dev, 773 "rx_priv_wl_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 774 rx_priv_wl->tc_wl[i].high, rx_priv_wl->tc_wl[i].low); 775 776 cmd = HCLGE_OPC_RX_COM_THRD_ALLOC; 777 hclge_cmd_setup_basic_desc(&desc[0], cmd, true); 778 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 779 hclge_cmd_setup_basic_desc(&desc[1], cmd, true); 780 ret = hclge_cmd_send(&hdev->hw, desc, 2); 781 if (ret) 782 goto err_qos_cmd_send; 783 784 dev_info(&hdev->pdev->dev, "\n"); 785 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[0].data; 786 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 787 dev_info(&hdev->pdev->dev, 788 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i, 789 rx_com_thrd->com_thrd[i].high, 790 rx_com_thrd->com_thrd[i].low); 791 792 rx_com_thrd = (struct hclge_rx_com_thrd *)desc[1].data; 793 for (i = 0; i < HCLGE_TC_NUM_ONE_DESC; i++) 794 dev_info(&hdev->pdev->dev, 795 "rx_com_thrd_tc_%d: high: 0x%x, low: 0x%x\n", i + 4, 796 rx_com_thrd->com_thrd[i].high, 797 rx_com_thrd->com_thrd[i].low); 798 return; 799 800 err_qos_cmd_send: 801 dev_err(&hdev->pdev->dev, 802 "dump qos buf cfg fail(0x%x), status is %d\n", cmd, ret); 803 } 804 805 static void hclge_dbg_dump_mng_table(struct hclge_dev *hdev) 806 { 807 struct hclge_mac_ethertype_idx_rd_cmd *req0; 808 char printf_buf[HCLGE_DBG_BUF_LEN]; 809 struct hclge_desc desc; 810 int ret, i; 811 812 dev_info(&hdev->pdev->dev, "mng tab:\n"); 813 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN); 814 strncat(printf_buf, 815 "entry|mac_addr |mask|ether|mask|vlan|mask", 816 HCLGE_DBG_BUF_LEN - 1); 817 strncat(printf_buf + strlen(printf_buf), 818 "|i_map|i_dir|e_type|pf_id|vf_id|q_id|drop\n", 819 HCLGE_DBG_BUF_LEN - strlen(printf_buf) - 1); 820 821 dev_info(&hdev->pdev->dev, "%s", printf_buf); 822 823 for (i = 0; i < HCLGE_DBG_MNG_TBL_MAX; i++) { 824 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_ETHERTYPE_IDX_RD, 825 true); 826 req0 = (struct hclge_mac_ethertype_idx_rd_cmd *)&desc.data; 827 req0->index = cpu_to_le16(i); 828 829 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 830 if (ret) { 831 dev_err(&hdev->pdev->dev, 832 "call hclge_cmd_send fail, ret = %d\n", ret); 833 return; 834 } 835 836 if (!req0->resp_code) 837 continue; 838 839 memset(printf_buf, 0, HCLGE_DBG_BUF_LEN); 840 snprintf(printf_buf, HCLGE_DBG_BUF_LEN, 841 "%02u |%02x:%02x:%02x:%02x:%02x:%02x|", 842 req0->index, req0->mac_addr[0], req0->mac_addr[1], 843 req0->mac_addr[2], req0->mac_addr[3], 844 req0->mac_addr[4], req0->mac_addr[5]); 845 846 snprintf(printf_buf + strlen(printf_buf), 847 HCLGE_DBG_BUF_LEN - strlen(printf_buf), 848 "%x |%04x |%x |%04x|%x |%02x |%02x |", 849 !!(req0->flags & HCLGE_DBG_MNG_MAC_MASK_B), 850 req0->ethter_type, 851 !!(req0->flags & HCLGE_DBG_MNG_ETHER_MASK_B), 852 req0->vlan_tag & HCLGE_DBG_MNG_VLAN_TAG, 853 !!(req0->flags & HCLGE_DBG_MNG_VLAN_MASK_B), 854 req0->i_port_bitmap, req0->i_port_direction); 855 856 snprintf(printf_buf + strlen(printf_buf), 857 HCLGE_DBG_BUF_LEN - strlen(printf_buf), 858 "%d |%d |%02d |%04d|%x\n", 859 !!(req0->egress_port & HCLGE_DBG_MNG_E_TYPE_B), 860 req0->egress_port & HCLGE_DBG_MNG_PF_ID, 861 (req0->egress_port >> 3) & HCLGE_DBG_MNG_VF_ID, 862 req0->egress_queue, 863 !!(req0->egress_port & HCLGE_DBG_MNG_DROP_B)); 864 865 dev_info(&hdev->pdev->dev, "%s", printf_buf); 866 } 867 } 868 869 static void hclge_dbg_fd_tcam_read(struct hclge_dev *hdev, u8 stage, 870 bool sel_x, u32 loc) 871 { 872 struct hclge_fd_tcam_config_1_cmd *req1; 873 struct hclge_fd_tcam_config_2_cmd *req2; 874 struct hclge_fd_tcam_config_3_cmd *req3; 875 struct hclge_desc desc[3]; 876 int ret, i; 877 u32 *req; 878 879 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, true); 880 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 881 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, true); 882 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); 883 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, true); 884 885 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data; 886 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data; 887 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data; 888 889 req1->stage = stage; 890 req1->xy_sel = sel_x ? 1 : 0; 891 req1->index = cpu_to_le32(loc); 892 893 ret = hclge_cmd_send(&hdev->hw, desc, 3); 894 if (ret) 895 return; 896 897 dev_info(&hdev->pdev->dev, " read result tcam key %s(%u):\n", 898 sel_x ? "x" : "y", loc); 899 900 req = (u32 *)req1->tcam_data; 901 for (i = 0; i < 2; i++) 902 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 903 904 req = (u32 *)req2->tcam_data; 905 for (i = 0; i < 6; i++) 906 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 907 908 req = (u32 *)req3->tcam_data; 909 for (i = 0; i < 5; i++) 910 dev_info(&hdev->pdev->dev, "%08x\n", *req++); 911 } 912 913 static void hclge_dbg_fd_tcam(struct hclge_dev *hdev) 914 { 915 u32 i; 916 917 for (i = 0; i < hdev->fd_cfg.rule_num[0]; i++) { 918 hclge_dbg_fd_tcam_read(hdev, 0, true, i); 919 hclge_dbg_fd_tcam_read(hdev, 0, false, i); 920 } 921 } 922 923 static void hclge_dbg_dump_rst_info(struct hclge_dev *hdev) 924 { 925 dev_info(&hdev->pdev->dev, "PF reset count: %d\n", 926 hdev->rst_stats.pf_rst_cnt); 927 dev_info(&hdev->pdev->dev, "FLR reset count: %d\n", 928 hdev->rst_stats.flr_rst_cnt); 929 dev_info(&hdev->pdev->dev, "CORE reset count: %d\n", 930 hdev->rst_stats.core_rst_cnt); 931 dev_info(&hdev->pdev->dev, "GLOBAL reset count: %d\n", 932 hdev->rst_stats.global_rst_cnt); 933 dev_info(&hdev->pdev->dev, "IMP reset count: %d\n", 934 hdev->rst_stats.imp_rst_cnt); 935 dev_info(&hdev->pdev->dev, "reset done count: %d\n", 936 hdev->rst_stats.reset_done_cnt); 937 dev_info(&hdev->pdev->dev, "HW reset done count: %d\n", 938 hdev->rst_stats.hw_reset_done_cnt); 939 dev_info(&hdev->pdev->dev, "reset count: %d\n", 940 hdev->rst_stats.reset_cnt); 941 } 942 943 void hclge_dbg_get_m7_stats_info(struct hclge_dev *hdev) 944 { 945 struct hclge_desc *desc_src, *desc_tmp; 946 struct hclge_get_m7_bd_cmd *req; 947 struct hclge_desc desc; 948 u32 bd_num, buf_len; 949 int ret, i; 950 951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_M7_STATS_BD, true); 952 953 req = (struct hclge_get_m7_bd_cmd *)desc.data; 954 ret = hclge_cmd_send(&hdev->hw, &desc, 1); 955 if (ret) { 956 dev_err(&hdev->pdev->dev, 957 "get firmware statistics bd number failed, ret=%d\n", 958 ret); 959 return; 960 } 961 962 bd_num = le32_to_cpu(req->bd_num); 963 964 buf_len = sizeof(struct hclge_desc) * bd_num; 965 desc_src = kzalloc(buf_len, GFP_KERNEL); 966 if (!desc_src) { 967 dev_err(&hdev->pdev->dev, 968 "allocate desc for get_m7_stats failed\n"); 969 return; 970 } 971 972 desc_tmp = desc_src; 973 ret = hclge_dbg_cmd_send(hdev, desc_tmp, 0, bd_num, 974 HCLGE_OPC_M7_STATS_INFO); 975 if (ret) { 976 kfree(desc_src); 977 dev_err(&hdev->pdev->dev, 978 "get firmware statistics failed, ret=%d\n", ret); 979 return; 980 } 981 982 for (i = 0; i < bd_num; i++) { 983 dev_info(&hdev->pdev->dev, "0x%08x 0x%08x 0x%08x\n", 984 le32_to_cpu(desc_tmp->data[0]), 985 le32_to_cpu(desc_tmp->data[1]), 986 le32_to_cpu(desc_tmp->data[2])); 987 dev_info(&hdev->pdev->dev, "0x%08x 0x%08x 0x%08x\n", 988 le32_to_cpu(desc_tmp->data[3]), 989 le32_to_cpu(desc_tmp->data[4]), 990 le32_to_cpu(desc_tmp->data[5])); 991 992 desc_tmp++; 993 } 994 995 kfree(desc_src); 996 } 997 998 #define HCLGE_CMD_NCL_CONFIG_BD_NUM 5 999 1000 static void hclge_ncl_config_data_print(struct hclge_dev *hdev, 1001 struct hclge_desc *desc, int *offset, 1002 int *length) 1003 { 1004 #define HCLGE_CMD_DATA_NUM 6 1005 1006 int i; 1007 int j; 1008 1009 for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) { 1010 for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) { 1011 if (i == 0 && j == 0) 1012 continue; 1013 1014 dev_info(&hdev->pdev->dev, "0x%04x | 0x%08x\n", 1015 *offset, 1016 le32_to_cpu(desc[i].data[j])); 1017 *offset += sizeof(u32); 1018 *length -= sizeof(u32); 1019 if (*length <= 0) 1020 return; 1021 } 1022 } 1023 } 1024 1025 /* hclge_dbg_dump_ncl_config: print specified range of NCL_CONFIG file 1026 * @hdev: pointer to struct hclge_dev 1027 * @cmd_buf: string that contains offset and length 1028 */ 1029 static void hclge_dbg_dump_ncl_config(struct hclge_dev *hdev, 1030 const char *cmd_buf) 1031 { 1032 #define HCLGE_MAX_NCL_CONFIG_OFFSET 4096 1033 #define HCLGE_MAX_NCL_CONFIG_LENGTH (20 + 24 * 4) 1034 1035 struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM]; 1036 int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM; 1037 int offset; 1038 int length; 1039 int data0; 1040 int ret; 1041 1042 ret = sscanf(cmd_buf, "%x %x", &offset, &length); 1043 if (ret != 2 || offset >= HCLGE_MAX_NCL_CONFIG_OFFSET || 1044 length > HCLGE_MAX_NCL_CONFIG_OFFSET - offset) { 1045 dev_err(&hdev->pdev->dev, "Invalid offset or length.\n"); 1046 return; 1047 } 1048 if (offset < 0 || length <= 0) { 1049 dev_err(&hdev->pdev->dev, "Non-positive offset or length.\n"); 1050 return; 1051 } 1052 1053 dev_info(&hdev->pdev->dev, "offset | data\n"); 1054 1055 while (length > 0) { 1056 data0 = offset; 1057 if (length >= HCLGE_MAX_NCL_CONFIG_LENGTH) 1058 data0 |= HCLGE_MAX_NCL_CONFIG_LENGTH << 16; 1059 else 1060 data0 |= length << 16; 1061 ret = hclge_dbg_cmd_send(hdev, desc, data0, bd_num, 1062 HCLGE_OPC_QUERY_NCL_CONFIG); 1063 if (ret) 1064 return; 1065 1066 hclge_ncl_config_data_print(hdev, desc, &offset, &length); 1067 } 1068 } 1069 1070 /* hclge_dbg_dump_mac_tnl_status: print message about mac tnl interrupt 1071 * @hdev: pointer to struct hclge_dev 1072 */ 1073 static void hclge_dbg_dump_mac_tnl_status(struct hclge_dev *hdev) 1074 { 1075 #define HCLGE_BILLION_NANO_SECONDS 1000000000 1076 1077 struct hclge_mac_tnl_stats stats; 1078 unsigned long rem_nsec; 1079 1080 dev_info(&hdev->pdev->dev, "Recently generated mac tnl interruption:\n"); 1081 1082 while (kfifo_get(&hdev->mac_tnl_log, &stats)) { 1083 rem_nsec = do_div(stats.time, HCLGE_BILLION_NANO_SECONDS); 1084 dev_info(&hdev->pdev->dev, "[%07lu.%03lu] status = 0x%x\n", 1085 (unsigned long)stats.time, rem_nsec / 1000, 1086 stats.status); 1087 } 1088 } 1089 1090 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf) 1091 { 1092 struct hclge_vport *vport = hclge_get_vport(handle); 1093 struct hclge_dev *hdev = vport->back; 1094 1095 if (strncmp(cmd_buf, "dump fd tcam", 12) == 0) { 1096 hclge_dbg_fd_tcam(hdev); 1097 } else if (strncmp(cmd_buf, "dump tc", 7) == 0) { 1098 hclge_dbg_dump_tc(hdev); 1099 } else if (strncmp(cmd_buf, "dump tm map", 11) == 0) { 1100 hclge_dbg_dump_tm_map(hdev, cmd_buf); 1101 } else if (strncmp(cmd_buf, "dump tm", 7) == 0) { 1102 hclge_dbg_dump_tm(hdev); 1103 } else if (strncmp(cmd_buf, "dump qos pause cfg", 18) == 0) { 1104 hclge_dbg_dump_qos_pause_cfg(hdev); 1105 } else if (strncmp(cmd_buf, "dump qos pri map", 16) == 0) { 1106 hclge_dbg_dump_qos_pri_map(hdev); 1107 } else if (strncmp(cmd_buf, "dump qos buf cfg", 16) == 0) { 1108 hclge_dbg_dump_qos_buf_cfg(hdev); 1109 } else if (strncmp(cmd_buf, "dump mng tbl", 12) == 0) { 1110 hclge_dbg_dump_mng_table(hdev); 1111 } else if (strncmp(cmd_buf, "dump reg", 8) == 0) { 1112 hclge_dbg_dump_reg_cmd(hdev, cmd_buf); 1113 } else if (strncmp(cmd_buf, "dump reset info", 15) == 0) { 1114 hclge_dbg_dump_rst_info(hdev); 1115 } else if (strncmp(cmd_buf, "dump m7 info", 12) == 0) { 1116 hclge_dbg_get_m7_stats_info(hdev); 1117 } else if (strncmp(cmd_buf, "dump ncl_config", 15) == 0) { 1118 hclge_dbg_dump_ncl_config(hdev, 1119 &cmd_buf[sizeof("dump ncl_config")]); 1120 } else if (strncmp(cmd_buf, "dump mac tnl status", 19) == 0) { 1121 hclge_dbg_dump_mac_tnl_status(hdev); 1122 } else { 1123 dev_info(&hdev->pdev->dev, "unknown command\n"); 1124 return -EINVAL; 1125 } 1126 1127 return 0; 1128 } 1129