1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <net/addrconf.h> 66 #include <linux/uaccess.h> 67 #include <linux/crash_dump.h> 68 #include <net/udp_tunnel.h> 69 70 #include "cxgb4.h" 71 #include "cxgb4_filter.h" 72 #include "t4_regs.h" 73 #include "t4_values.h" 74 #include "t4_msg.h" 75 #include "t4fw_api.h" 76 #include "t4fw_version.h" 77 #include "cxgb4_dcb.h" 78 #include "srq.h" 79 #include "cxgb4_debugfs.h" 80 #include "clip_tbl.h" 81 #include "l2t.h" 82 #include "smt.h" 83 #include "sched.h" 84 #include "cxgb4_tc_u32.h" 85 #include "cxgb4_tc_flower.h" 86 #include "cxgb4_ptp.h" 87 #include "cxgb4_cudbg.h" 88 89 char cxgb4_driver_name[] = KBUILD_MODNAME; 90 91 #ifdef DRV_VERSION 92 #undef DRV_VERSION 93 #endif 94 #define DRV_VERSION "2.0.0-ko" 95 const char cxgb4_driver_version[] = DRV_VERSION; 96 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 97 98 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 99 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 100 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 101 102 /* Macros needed to support the PCI Device ID Table ... 103 */ 104 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 105 static const struct pci_device_id cxgb4_pci_tbl[] = { 106 #define CXGB4_UNIFIED_PF 0x4 107 108 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF 109 110 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 111 * called for both. 112 */ 113 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 114 115 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 116 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF} 117 118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 119 { 0, } \ 120 } 121 122 #include "t4_pci_id_tbl.h" 123 124 #define FW4_FNAME "cxgb4/t4fw.bin" 125 #define FW5_FNAME "cxgb4/t5fw.bin" 126 #define FW6_FNAME "cxgb4/t6fw.bin" 127 #define FW4_CFNAME "cxgb4/t4-config.txt" 128 #define FW5_CFNAME "cxgb4/t5-config.txt" 129 #define FW6_CFNAME "cxgb4/t6-config.txt" 130 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 131 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 132 #define PHY_AQ1202_DEVICEID 0x4409 133 #define PHY_BCM84834_DEVICEID 0x4486 134 135 MODULE_DESCRIPTION(DRV_DESC); 136 MODULE_AUTHOR("Chelsio Communications"); 137 MODULE_LICENSE("Dual BSD/GPL"); 138 MODULE_VERSION(DRV_VERSION); 139 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 140 MODULE_FIRMWARE(FW4_FNAME); 141 MODULE_FIRMWARE(FW5_FNAME); 142 MODULE_FIRMWARE(FW6_FNAME); 143 144 /* 145 * The driver uses the best interrupt scheme available on a platform in the 146 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 147 * of these schemes the driver may consider as follows: 148 * 149 * msi = 2: choose from among all three options 150 * msi = 1: only consider MSI and INTx interrupts 151 * msi = 0: force INTx interrupts 152 */ 153 static int msi = 2; 154 155 module_param(msi, int, 0644); 156 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 157 158 /* 159 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 160 * offset by 2 bytes in order to have the IP headers line up on 4-byte 161 * boundaries. This is a requirement for many architectures which will throw 162 * a machine check fault if an attempt is made to access one of the 4-byte IP 163 * header fields on a non-4-byte boundary. And it's a major performance issue 164 * even on some architectures which allow it like some implementations of the 165 * x86 ISA. However, some architectures don't mind this and for some very 166 * edge-case performance sensitive applications (like forwarding large volumes 167 * of small packets), setting this DMA offset to 0 will decrease the number of 168 * PCI-E Bus transfers enough to measurably affect performance. 169 */ 170 static int rx_dma_offset = 2; 171 172 /* TX Queue select used to determine what algorithm to use for selecting TX 173 * queue. Select between the kernel provided function (select_queue=0) or user 174 * cxgb_select_queue function (select_queue=1) 175 * 176 * Default: select_queue=0 177 */ 178 static int select_queue; 179 module_param(select_queue, int, 0644); 180 MODULE_PARM_DESC(select_queue, 181 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 182 183 static struct dentry *cxgb4_debugfs_root; 184 185 LIST_HEAD(adapter_list); 186 DEFINE_MUTEX(uld_mutex); 187 188 static void link_report(struct net_device *dev) 189 { 190 if (!netif_carrier_ok(dev)) 191 netdev_info(dev, "link down\n"); 192 else { 193 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 194 195 const char *s; 196 const struct port_info *p = netdev_priv(dev); 197 198 switch (p->link_cfg.speed) { 199 case 100: 200 s = "100Mbps"; 201 break; 202 case 1000: 203 s = "1Gbps"; 204 break; 205 case 10000: 206 s = "10Gbps"; 207 break; 208 case 25000: 209 s = "25Gbps"; 210 break; 211 case 40000: 212 s = "40Gbps"; 213 break; 214 case 50000: 215 s = "50Gbps"; 216 break; 217 case 100000: 218 s = "100Gbps"; 219 break; 220 default: 221 pr_info("%s: unsupported speed: %d\n", 222 dev->name, p->link_cfg.speed); 223 return; 224 } 225 226 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 227 fc[p->link_cfg.fc]); 228 } 229 } 230 231 #ifdef CONFIG_CHELSIO_T4_DCB 232 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 233 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 234 { 235 struct port_info *pi = netdev_priv(dev); 236 struct adapter *adap = pi->adapter; 237 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 238 int i; 239 240 /* We use a simple mapping of Port TX Queue Index to DCB 241 * Priority when we're enabling DCB. 242 */ 243 for (i = 0; i < pi->nqsets; i++, txq++) { 244 u32 name, value; 245 int err; 246 247 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 248 FW_PARAMS_PARAM_X_V( 249 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 250 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 251 value = enable ? i : 0xffffffff; 252 253 /* Since we can be called while atomic (from "interrupt 254 * level") we need to issue the Set Parameters Commannd 255 * without sleeping (timeout < 0). 256 */ 257 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 258 &name, &value, 259 -FW_CMD_MAX_TIMEOUT); 260 261 if (err) 262 dev_err(adap->pdev_dev, 263 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 264 enable ? "set" : "unset", pi->port_id, i, -err); 265 else 266 txq->dcb_prio = value; 267 } 268 } 269 270 static int cxgb4_dcb_enabled(const struct net_device *dev) 271 { 272 struct port_info *pi = netdev_priv(dev); 273 274 if (!pi->dcb.enabled) 275 return 0; 276 277 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 278 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 279 } 280 #endif /* CONFIG_CHELSIO_T4_DCB */ 281 282 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 283 { 284 struct net_device *dev = adapter->port[port_id]; 285 286 /* Skip changes from disabled ports. */ 287 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 288 if (link_stat) 289 netif_carrier_on(dev); 290 else { 291 #ifdef CONFIG_CHELSIO_T4_DCB 292 if (cxgb4_dcb_enabled(dev)) { 293 cxgb4_dcb_reset(dev); 294 dcb_tx_queue_prio_enable(dev, false); 295 } 296 #endif /* CONFIG_CHELSIO_T4_DCB */ 297 netif_carrier_off(dev); 298 } 299 300 link_report(dev); 301 } 302 } 303 304 void t4_os_portmod_changed(struct adapter *adap, int port_id) 305 { 306 static const char *mod_str[] = { 307 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 308 }; 309 310 struct net_device *dev = adap->port[port_id]; 311 struct port_info *pi = netdev_priv(dev); 312 313 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 314 netdev_info(dev, "port module unplugged\n"); 315 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 316 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 317 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 318 netdev_info(dev, "%s: unsupported port module inserted\n", 319 dev->name); 320 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 321 netdev_info(dev, "%s: unknown port module inserted\n", 322 dev->name); 323 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 324 netdev_info(dev, "%s: transceiver module error\n", dev->name); 325 else 326 netdev_info(dev, "%s: unknown module type %d inserted\n", 327 dev->name, pi->mod_type); 328 329 /* If the interface is running, then we'll need any "sticky" Link 330 * Parameters redone with a new Transceiver Module. 331 */ 332 pi->link_cfg.redo_l1cfg = netif_running(dev); 333 } 334 335 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 336 module_param(dbfifo_int_thresh, int, 0644); 337 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 338 339 /* 340 * usecs to sleep while draining the dbfifo 341 */ 342 static int dbfifo_drain_delay = 1000; 343 module_param(dbfifo_drain_delay, int, 0644); 344 MODULE_PARM_DESC(dbfifo_drain_delay, 345 "usecs to sleep while draining the dbfifo"); 346 347 static inline int cxgb4_set_addr_hash(struct port_info *pi) 348 { 349 struct adapter *adap = pi->adapter; 350 u64 vec = 0; 351 bool ucast = false; 352 struct hash_mac_addr *entry; 353 354 /* Calculate the hash vector for the updated list and program it */ 355 list_for_each_entry(entry, &adap->mac_hlist, list) { 356 ucast |= is_unicast_ether_addr(entry->addr); 357 vec |= (1ULL << hash_mac_addr(entry->addr)); 358 } 359 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 360 vec, false); 361 } 362 363 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 364 { 365 struct port_info *pi = netdev_priv(netdev); 366 struct adapter *adap = pi->adapter; 367 int ret; 368 u64 mhash = 0; 369 u64 uhash = 0; 370 bool free = false; 371 bool ucast = is_unicast_ether_addr(mac_addr); 372 const u8 *maclist[1] = {mac_addr}; 373 struct hash_mac_addr *new_entry; 374 375 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, 376 NULL, ucast ? &uhash : &mhash, false); 377 if (ret < 0) 378 goto out; 379 /* if hash != 0, then add the addr to hash addr list 380 * so on the end we will calculate the hash for the 381 * list and program it 382 */ 383 if (uhash || mhash) { 384 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 385 if (!new_entry) 386 return -ENOMEM; 387 ether_addr_copy(new_entry->addr, mac_addr); 388 list_add_tail(&new_entry->list, &adap->mac_hlist); 389 ret = cxgb4_set_addr_hash(pi); 390 } 391 out: 392 return ret < 0 ? ret : 0; 393 } 394 395 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 396 { 397 struct port_info *pi = netdev_priv(netdev); 398 struct adapter *adap = pi->adapter; 399 int ret; 400 const u8 *maclist[1] = {mac_addr}; 401 struct hash_mac_addr *entry, *tmp; 402 403 /* If the MAC address to be removed is in the hash addr 404 * list, delete it from the list and update hash vector 405 */ 406 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 407 if (ether_addr_equal(entry->addr, mac_addr)) { 408 list_del(&entry->list); 409 kfree(entry); 410 return cxgb4_set_addr_hash(pi); 411 } 412 } 413 414 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); 415 return ret < 0 ? -EINVAL : 0; 416 } 417 418 /* 419 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 420 * If @mtu is -1 it is left unchanged. 421 */ 422 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 423 { 424 struct port_info *pi = netdev_priv(dev); 425 struct adapter *adapter = pi->adapter; 426 427 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 428 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 429 430 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, 431 (dev->flags & IFF_PROMISC) ? 1 : 0, 432 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 433 sleep_ok); 434 } 435 436 /** 437 * link_start - enable a port 438 * @dev: the port to enable 439 * 440 * Performs the MAC and PHY actions needed to enable a port. 441 */ 442 static int link_start(struct net_device *dev) 443 { 444 int ret; 445 struct port_info *pi = netdev_priv(dev); 446 unsigned int mb = pi->adapter->pf; 447 448 /* 449 * We do not set address filters and promiscuity here, the stack does 450 * that step explicitly. 451 */ 452 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 453 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 454 if (ret == 0) { 455 ret = t4_change_mac(pi->adapter, mb, pi->viid, 456 pi->xact_addr_filt, dev->dev_addr, true, 457 true); 458 if (ret >= 0) { 459 pi->xact_addr_filt = ret; 460 ret = 0; 461 } 462 } 463 if (ret == 0) 464 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 465 &pi->link_cfg); 466 if (ret == 0) { 467 local_bh_disable(); 468 ret = t4_enable_pi_params(pi->adapter, mb, pi, true, 469 true, CXGB4_DCB_ENABLED); 470 local_bh_enable(); 471 } 472 473 return ret; 474 } 475 476 #ifdef CONFIG_CHELSIO_T4_DCB 477 /* Handle a Data Center Bridging update message from the firmware. */ 478 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 479 { 480 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 481 struct net_device *dev = adap->port[adap->chan_map[port]]; 482 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 483 int new_dcb_enabled; 484 485 cxgb4_dcb_handle_fw_update(adap, pcmd); 486 new_dcb_enabled = cxgb4_dcb_enabled(dev); 487 488 /* If the DCB has become enabled or disabled on the port then we're 489 * going to need to set up/tear down DCB Priority parameters for the 490 * TX Queues associated with the port. 491 */ 492 if (new_dcb_enabled != old_dcb_enabled) 493 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 494 } 495 #endif /* CONFIG_CHELSIO_T4_DCB */ 496 497 /* Response queue handler for the FW event queue. 498 */ 499 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 500 const struct pkt_gl *gl) 501 { 502 u8 opcode = ((const struct rss_header *)rsp)->opcode; 503 504 rsp++; /* skip RSS header */ 505 506 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 507 */ 508 if (unlikely(opcode == CPL_FW4_MSG && 509 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 510 rsp++; 511 opcode = ((const struct rss_header *)rsp)->opcode; 512 rsp++; 513 if (opcode != CPL_SGE_EGR_UPDATE) { 514 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 515 , opcode); 516 goto out; 517 } 518 } 519 520 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 521 const struct cpl_sge_egr_update *p = (void *)rsp; 522 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 523 struct sge_txq *txq; 524 525 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 526 txq->restarts++; 527 if (txq->q_type == CXGB4_TXQ_ETH) { 528 struct sge_eth_txq *eq; 529 530 eq = container_of(txq, struct sge_eth_txq, q); 531 netif_tx_wake_queue(eq->txq); 532 } else { 533 struct sge_uld_txq *oq; 534 535 oq = container_of(txq, struct sge_uld_txq, q); 536 tasklet_schedule(&oq->qresume_tsk); 537 } 538 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 539 const struct cpl_fw6_msg *p = (void *)rsp; 540 541 #ifdef CONFIG_CHELSIO_T4_DCB 542 const struct fw_port_cmd *pcmd = (const void *)p->data; 543 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 544 unsigned int action = 545 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 546 547 if (cmd == FW_PORT_CMD && 548 (action == FW_PORT_ACTION_GET_PORT_INFO || 549 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 550 int port = FW_PORT_CMD_PORTID_G( 551 be32_to_cpu(pcmd->op_to_portid)); 552 struct net_device *dev; 553 int dcbxdis, state_input; 554 555 dev = q->adap->port[q->adap->chan_map[port]]; 556 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 557 ? !!(pcmd->u.info.dcbxdis_pkd & 558 FW_PORT_CMD_DCBXDIS_F) 559 : !!(pcmd->u.info32.lstatus32_to_cbllen32 & 560 FW_PORT_CMD_DCBXDIS32_F)); 561 state_input = (dcbxdis 562 ? CXGB4_DCB_INPUT_FW_DISABLED 563 : CXGB4_DCB_INPUT_FW_ENABLED); 564 565 cxgb4_dcb_state_fsm(dev, state_input); 566 } 567 568 if (cmd == FW_PORT_CMD && 569 action == FW_PORT_ACTION_L2_DCB_CFG) 570 dcb_rpl(q->adap, pcmd); 571 else 572 #endif 573 if (p->type == 0) 574 t4_handle_fw_rpl(q->adap, p->data); 575 } else if (opcode == CPL_L2T_WRITE_RPL) { 576 const struct cpl_l2t_write_rpl *p = (void *)rsp; 577 578 do_l2t_write_rpl(q->adap, p); 579 } else if (opcode == CPL_SMT_WRITE_RPL) { 580 const struct cpl_smt_write_rpl *p = (void *)rsp; 581 582 do_smt_write_rpl(q->adap, p); 583 } else if (opcode == CPL_SET_TCB_RPL) { 584 const struct cpl_set_tcb_rpl *p = (void *)rsp; 585 586 filter_rpl(q->adap, p); 587 } else if (opcode == CPL_ACT_OPEN_RPL) { 588 const struct cpl_act_open_rpl *p = (void *)rsp; 589 590 hash_filter_rpl(q->adap, p); 591 } else if (opcode == CPL_ABORT_RPL_RSS) { 592 const struct cpl_abort_rpl_rss *p = (void *)rsp; 593 594 hash_del_filter_rpl(q->adap, p); 595 } else if (opcode == CPL_SRQ_TABLE_RPL) { 596 const struct cpl_srq_table_rpl *p = (void *)rsp; 597 598 do_srq_table_rpl(q->adap, p); 599 } else 600 dev_err(q->adap->pdev_dev, 601 "unexpected CPL %#x on FW event queue\n", opcode); 602 out: 603 return 0; 604 } 605 606 static void disable_msi(struct adapter *adapter) 607 { 608 if (adapter->flags & USING_MSIX) { 609 pci_disable_msix(adapter->pdev); 610 adapter->flags &= ~USING_MSIX; 611 } else if (adapter->flags & USING_MSI) { 612 pci_disable_msi(adapter->pdev); 613 adapter->flags &= ~USING_MSI; 614 } 615 } 616 617 /* 618 * Interrupt handler for non-data events used with MSI-X. 619 */ 620 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 621 { 622 struct adapter *adap = cookie; 623 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 624 625 if (v & PFSW_F) { 626 adap->swintr = 1; 627 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 628 } 629 if (adap->flags & MASTER_PF) 630 t4_slow_intr_handler(adap); 631 return IRQ_HANDLED; 632 } 633 634 /* 635 * Name the MSI-X interrupts. 636 */ 637 static void name_msix_vecs(struct adapter *adap) 638 { 639 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 640 641 /* non-data interrupts */ 642 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 643 644 /* FW events */ 645 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 646 adap->port[0]->name); 647 648 /* Ethernet queues */ 649 for_each_port(adap, j) { 650 struct net_device *d = adap->port[j]; 651 const struct port_info *pi = netdev_priv(d); 652 653 for (i = 0; i < pi->nqsets; i++, msi_idx++) 654 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 655 d->name, i); 656 } 657 } 658 659 static int request_msix_queue_irqs(struct adapter *adap) 660 { 661 struct sge *s = &adap->sge; 662 int err, ethqidx; 663 int msi_index = 2; 664 665 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 666 adap->msix_info[1].desc, &s->fw_evtq); 667 if (err) 668 return err; 669 670 for_each_ethrxq(s, ethqidx) { 671 err = request_irq(adap->msix_info[msi_index].vec, 672 t4_sge_intr_msix, 0, 673 adap->msix_info[msi_index].desc, 674 &s->ethrxq[ethqidx].rspq); 675 if (err) 676 goto unwind; 677 msi_index++; 678 } 679 return 0; 680 681 unwind: 682 while (--ethqidx >= 0) 683 free_irq(adap->msix_info[--msi_index].vec, 684 &s->ethrxq[ethqidx].rspq); 685 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 686 return err; 687 } 688 689 static void free_msix_queue_irqs(struct adapter *adap) 690 { 691 int i, msi_index = 2; 692 struct sge *s = &adap->sge; 693 694 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 695 for_each_ethrxq(s, i) 696 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); 697 } 698 699 /** 700 * cxgb4_write_rss - write the RSS table for a given port 701 * @pi: the port 702 * @queues: array of queue indices for RSS 703 * 704 * Sets up the portion of the HW RSS table for the port's VI to distribute 705 * packets to the Rx queues in @queues. 706 * Should never be called before setting up sge eth rx queues 707 */ 708 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 709 { 710 u16 *rss; 711 int i, err; 712 struct adapter *adapter = pi->adapter; 713 const struct sge_eth_rxq *rxq; 714 715 rxq = &adapter->sge.ethrxq[pi->first_qset]; 716 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL); 717 if (!rss) 718 return -ENOMEM; 719 720 /* map the queue indices to queue ids */ 721 for (i = 0; i < pi->rss_size; i++, queues++) 722 rss[i] = rxq[*queues].rspq.abs_id; 723 724 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 725 pi->rss_size, rss, pi->rss_size); 726 /* If Tunnel All Lookup isn't specified in the global RSS 727 * Configuration, then we need to specify a default Ingress 728 * Queue for any ingress packets which aren't hashed. We'll 729 * use our first ingress queue ... 730 */ 731 if (!err) 732 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 733 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 734 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 735 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 736 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 737 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 738 rss[0]); 739 kfree(rss); 740 return err; 741 } 742 743 /** 744 * setup_rss - configure RSS 745 * @adap: the adapter 746 * 747 * Sets up RSS for each port. 748 */ 749 static int setup_rss(struct adapter *adap) 750 { 751 int i, j, err; 752 753 for_each_port(adap, i) { 754 const struct port_info *pi = adap2pinfo(adap, i); 755 756 /* Fill default values with equal distribution */ 757 for (j = 0; j < pi->rss_size; j++) 758 pi->rss[j] = j % pi->nqsets; 759 760 err = cxgb4_write_rss(pi, pi->rss); 761 if (err) 762 return err; 763 } 764 return 0; 765 } 766 767 /* 768 * Return the channel of the ingress queue with the given qid. 769 */ 770 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 771 { 772 qid -= p->ingr_start; 773 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 774 } 775 776 /* 777 * Wait until all NAPI handlers are descheduled. 778 */ 779 static void quiesce_rx(struct adapter *adap) 780 { 781 int i; 782 783 for (i = 0; i < adap->sge.ingr_sz; i++) { 784 struct sge_rspq *q = adap->sge.ingr_map[i]; 785 786 if (q && q->handler) 787 napi_disable(&q->napi); 788 } 789 } 790 791 /* Disable interrupt and napi handler */ 792 static void disable_interrupts(struct adapter *adap) 793 { 794 if (adap->flags & FULL_INIT_DONE) { 795 t4_intr_disable(adap); 796 if (adap->flags & USING_MSIX) { 797 free_msix_queue_irqs(adap); 798 free_irq(adap->msix_info[0].vec, adap); 799 } else { 800 free_irq(adap->pdev->irq, adap); 801 } 802 quiesce_rx(adap); 803 } 804 } 805 806 /* 807 * Enable NAPI scheduling and interrupt generation for all Rx queues. 808 */ 809 static void enable_rx(struct adapter *adap) 810 { 811 int i; 812 813 for (i = 0; i < adap->sge.ingr_sz; i++) { 814 struct sge_rspq *q = adap->sge.ingr_map[i]; 815 816 if (!q) 817 continue; 818 if (q->handler) 819 napi_enable(&q->napi); 820 821 /* 0-increment GTS to start the timer and enable interrupts */ 822 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 823 SEINTARM_V(q->intr_params) | 824 INGRESSQID_V(q->cntxt_id)); 825 } 826 } 827 828 829 static int setup_fw_sge_queues(struct adapter *adap) 830 { 831 struct sge *s = &adap->sge; 832 int err = 0; 833 834 bitmap_zero(s->starving_fl, s->egr_sz); 835 bitmap_zero(s->txq_maperr, s->egr_sz); 836 837 if (adap->flags & USING_MSIX) 838 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ 839 else { 840 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 841 NULL, NULL, NULL, -1); 842 if (err) 843 return err; 844 adap->msi_idx = -((int)s->intrq.abs_id + 1); 845 } 846 847 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 848 adap->msi_idx, NULL, fwevtq_handler, NULL, -1); 849 return err; 850 } 851 852 /** 853 * setup_sge_queues - configure SGE Tx/Rx/response queues 854 * @adap: the adapter 855 * 856 * Determines how many sets of SGE queues to use and initializes them. 857 * We support multiple queue sets per port if we have MSI-X, otherwise 858 * just one queue set per port. 859 */ 860 static int setup_sge_queues(struct adapter *adap) 861 { 862 int err, i, j; 863 struct sge *s = &adap->sge; 864 struct sge_uld_rxq_info *rxq_info = NULL; 865 unsigned int cmplqid = 0; 866 867 if (is_uld(adap)) 868 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 869 870 for_each_port(adap, i) { 871 struct net_device *dev = adap->port[i]; 872 struct port_info *pi = netdev_priv(dev); 873 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 874 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 875 876 for (j = 0; j < pi->nqsets; j++, q++) { 877 if (adap->msi_idx > 0) 878 adap->msi_idx++; 879 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 880 adap->msi_idx, &q->fl, 881 t4_ethrx_handler, 882 NULL, 883 t4_get_tp_ch_map(adap, 884 pi->tx_chan)); 885 if (err) 886 goto freeout; 887 q->rspq.idx = j; 888 memset(&q->stats, 0, sizeof(q->stats)); 889 } 890 for (j = 0; j < pi->nqsets; j++, t++) { 891 err = t4_sge_alloc_eth_txq(adap, t, dev, 892 netdev_get_tx_queue(dev, j), 893 s->fw_evtq.cntxt_id); 894 if (err) 895 goto freeout; 896 } 897 } 898 899 for_each_port(adap, i) { 900 /* Note that cmplqid below is 0 if we don't 901 * have RDMA queues, and that's the right value. 902 */ 903 if (rxq_info) 904 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 905 906 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 907 s->fw_evtq.cntxt_id, cmplqid); 908 if (err) 909 goto freeout; 910 } 911 912 if (!is_t4(adap->params.chip)) { 913 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 914 netdev_get_tx_queue(adap->port[0], 0) 915 , s->fw_evtq.cntxt_id); 916 if (err) 917 goto freeout; 918 } 919 920 t4_write_reg(adap, is_t4(adap->params.chip) ? 921 MPS_TRC_RSS_CONTROL_A : 922 MPS_T5_TRC_RSS_CONTROL_A, 923 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 924 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 925 return 0; 926 freeout: 927 t4_free_sge_resources(adap); 928 return err; 929 } 930 931 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 932 void *accel_priv, select_queue_fallback_t fallback) 933 { 934 int txq; 935 936 #ifdef CONFIG_CHELSIO_T4_DCB 937 /* If a Data Center Bridging has been successfully negotiated on this 938 * link then we'll use the skb's priority to map it to a TX Queue. 939 * The skb's priority is determined via the VLAN Tag Priority Code 940 * Point field. 941 */ 942 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 943 u16 vlan_tci; 944 int err; 945 946 err = vlan_get_tag(skb, &vlan_tci); 947 if (unlikely(err)) { 948 if (net_ratelimit()) 949 netdev_warn(dev, 950 "TX Packet without VLAN Tag on DCB Link\n"); 951 txq = 0; 952 } else { 953 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 954 #ifdef CONFIG_CHELSIO_T4_FCOE 955 if (skb->protocol == htons(ETH_P_FCOE)) 956 txq = skb->priority & 0x7; 957 #endif /* CONFIG_CHELSIO_T4_FCOE */ 958 } 959 return txq; 960 } 961 #endif /* CONFIG_CHELSIO_T4_DCB */ 962 963 if (select_queue) { 964 txq = (skb_rx_queue_recorded(skb) 965 ? skb_get_rx_queue(skb) 966 : smp_processor_id()); 967 968 while (unlikely(txq >= dev->real_num_tx_queues)) 969 txq -= dev->real_num_tx_queues; 970 971 return txq; 972 } 973 974 return fallback(dev, skb) % dev->real_num_tx_queues; 975 } 976 977 static int closest_timer(const struct sge *s, int time) 978 { 979 int i, delta, match = 0, min_delta = INT_MAX; 980 981 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 982 delta = time - s->timer_val[i]; 983 if (delta < 0) 984 delta = -delta; 985 if (delta < min_delta) { 986 min_delta = delta; 987 match = i; 988 } 989 } 990 return match; 991 } 992 993 static int closest_thres(const struct sge *s, int thres) 994 { 995 int i, delta, match = 0, min_delta = INT_MAX; 996 997 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 998 delta = thres - s->counter_val[i]; 999 if (delta < 0) 1000 delta = -delta; 1001 if (delta < min_delta) { 1002 min_delta = delta; 1003 match = i; 1004 } 1005 } 1006 return match; 1007 } 1008 1009 /** 1010 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1011 * @q: the Rx queue 1012 * @us: the hold-off time in us, or 0 to disable timer 1013 * @cnt: the hold-off packet count, or 0 to disable counter 1014 * 1015 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1016 * one of the two needs to be enabled for the queue to generate interrupts. 1017 */ 1018 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1019 unsigned int us, unsigned int cnt) 1020 { 1021 struct adapter *adap = q->adap; 1022 1023 if ((us | cnt) == 0) 1024 cnt = 1; 1025 1026 if (cnt) { 1027 int err; 1028 u32 v, new_idx; 1029 1030 new_idx = closest_thres(&adap->sge, cnt); 1031 if (q->desc && q->pktcnt_idx != new_idx) { 1032 /* the queue has already been created, update it */ 1033 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1034 FW_PARAMS_PARAM_X_V( 1035 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1036 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1037 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1038 &v, &new_idx); 1039 if (err) 1040 return err; 1041 } 1042 q->pktcnt_idx = new_idx; 1043 } 1044 1045 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1046 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1047 return 0; 1048 } 1049 1050 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1051 { 1052 const struct port_info *pi = netdev_priv(dev); 1053 netdev_features_t changed = dev->features ^ features; 1054 int err; 1055 1056 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1057 return 0; 1058 1059 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1060 -1, -1, -1, 1061 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1062 if (unlikely(err)) 1063 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1064 return err; 1065 } 1066 1067 static int setup_debugfs(struct adapter *adap) 1068 { 1069 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1070 return -1; 1071 1072 #ifdef CONFIG_DEBUG_FS 1073 t4_setup_debugfs(adap); 1074 #endif 1075 return 0; 1076 } 1077 1078 /* 1079 * upper-layer driver support 1080 */ 1081 1082 /* 1083 * Allocate an active-open TID and set it to the supplied value. 1084 */ 1085 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1086 { 1087 int atid = -1; 1088 1089 spin_lock_bh(&t->atid_lock); 1090 if (t->afree) { 1091 union aopen_entry *p = t->afree; 1092 1093 atid = (p - t->atid_tab) + t->atid_base; 1094 t->afree = p->next; 1095 p->data = data; 1096 t->atids_in_use++; 1097 } 1098 spin_unlock_bh(&t->atid_lock); 1099 return atid; 1100 } 1101 EXPORT_SYMBOL(cxgb4_alloc_atid); 1102 1103 /* 1104 * Release an active-open TID. 1105 */ 1106 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1107 { 1108 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1109 1110 spin_lock_bh(&t->atid_lock); 1111 p->next = t->afree; 1112 t->afree = p; 1113 t->atids_in_use--; 1114 spin_unlock_bh(&t->atid_lock); 1115 } 1116 EXPORT_SYMBOL(cxgb4_free_atid); 1117 1118 /* 1119 * Allocate a server TID and set it to the supplied value. 1120 */ 1121 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1122 { 1123 int stid; 1124 1125 spin_lock_bh(&t->stid_lock); 1126 if (family == PF_INET) { 1127 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1128 if (stid < t->nstids) 1129 __set_bit(stid, t->stid_bmap); 1130 else 1131 stid = -1; 1132 } else { 1133 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1134 if (stid < 0) 1135 stid = -1; 1136 } 1137 if (stid >= 0) { 1138 t->stid_tab[stid].data = data; 1139 stid += t->stid_base; 1140 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1141 * This is equivalent to 4 TIDs. With CLIP enabled it 1142 * needs 2 TIDs. 1143 */ 1144 if (family == PF_INET6) { 1145 t->stids_in_use += 2; 1146 t->v6_stids_in_use += 2; 1147 } else { 1148 t->stids_in_use++; 1149 } 1150 } 1151 spin_unlock_bh(&t->stid_lock); 1152 return stid; 1153 } 1154 EXPORT_SYMBOL(cxgb4_alloc_stid); 1155 1156 /* Allocate a server filter TID and set it to the supplied value. 1157 */ 1158 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1159 { 1160 int stid; 1161 1162 spin_lock_bh(&t->stid_lock); 1163 if (family == PF_INET) { 1164 stid = find_next_zero_bit(t->stid_bmap, 1165 t->nstids + t->nsftids, t->nstids); 1166 if (stid < (t->nstids + t->nsftids)) 1167 __set_bit(stid, t->stid_bmap); 1168 else 1169 stid = -1; 1170 } else { 1171 stid = -1; 1172 } 1173 if (stid >= 0) { 1174 t->stid_tab[stid].data = data; 1175 stid -= t->nstids; 1176 stid += t->sftid_base; 1177 t->sftids_in_use++; 1178 } 1179 spin_unlock_bh(&t->stid_lock); 1180 return stid; 1181 } 1182 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1183 1184 /* Release a server TID. 1185 */ 1186 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1187 { 1188 /* Is it a server filter TID? */ 1189 if (t->nsftids && (stid >= t->sftid_base)) { 1190 stid -= t->sftid_base; 1191 stid += t->nstids; 1192 } else { 1193 stid -= t->stid_base; 1194 } 1195 1196 spin_lock_bh(&t->stid_lock); 1197 if (family == PF_INET) 1198 __clear_bit(stid, t->stid_bmap); 1199 else 1200 bitmap_release_region(t->stid_bmap, stid, 1); 1201 t->stid_tab[stid].data = NULL; 1202 if (stid < t->nstids) { 1203 if (family == PF_INET6) { 1204 t->stids_in_use -= 2; 1205 t->v6_stids_in_use -= 2; 1206 } else { 1207 t->stids_in_use--; 1208 } 1209 } else { 1210 t->sftids_in_use--; 1211 } 1212 1213 spin_unlock_bh(&t->stid_lock); 1214 } 1215 EXPORT_SYMBOL(cxgb4_free_stid); 1216 1217 /* 1218 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1219 */ 1220 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1221 unsigned int tid) 1222 { 1223 struct cpl_tid_release *req; 1224 1225 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1226 req = __skb_put(skb, sizeof(*req)); 1227 INIT_TP_WR(req, tid); 1228 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1229 } 1230 1231 /* 1232 * Queue a TID release request and if necessary schedule a work queue to 1233 * process it. 1234 */ 1235 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1236 unsigned int tid) 1237 { 1238 void **p = &t->tid_tab[tid]; 1239 struct adapter *adap = container_of(t, struct adapter, tids); 1240 1241 spin_lock_bh(&adap->tid_release_lock); 1242 *p = adap->tid_release_head; 1243 /* Low 2 bits encode the Tx channel number */ 1244 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1245 if (!adap->tid_release_task_busy) { 1246 adap->tid_release_task_busy = true; 1247 queue_work(adap->workq, &adap->tid_release_task); 1248 } 1249 spin_unlock_bh(&adap->tid_release_lock); 1250 } 1251 1252 /* 1253 * Process the list of pending TID release requests. 1254 */ 1255 static void process_tid_release_list(struct work_struct *work) 1256 { 1257 struct sk_buff *skb; 1258 struct adapter *adap; 1259 1260 adap = container_of(work, struct adapter, tid_release_task); 1261 1262 spin_lock_bh(&adap->tid_release_lock); 1263 while (adap->tid_release_head) { 1264 void **p = adap->tid_release_head; 1265 unsigned int chan = (uintptr_t)p & 3; 1266 p = (void *)p - chan; 1267 1268 adap->tid_release_head = *p; 1269 *p = NULL; 1270 spin_unlock_bh(&adap->tid_release_lock); 1271 1272 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1273 GFP_KERNEL))) 1274 schedule_timeout_uninterruptible(1); 1275 1276 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1277 t4_ofld_send(adap, skb); 1278 spin_lock_bh(&adap->tid_release_lock); 1279 } 1280 adap->tid_release_task_busy = false; 1281 spin_unlock_bh(&adap->tid_release_lock); 1282 } 1283 1284 /* 1285 * Release a TID and inform HW. If we are unable to allocate the release 1286 * message we defer to a work queue. 1287 */ 1288 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1289 unsigned short family) 1290 { 1291 struct sk_buff *skb; 1292 struct adapter *adap = container_of(t, struct adapter, tids); 1293 1294 WARN_ON(tid >= t->ntids); 1295 1296 if (t->tid_tab[tid]) { 1297 t->tid_tab[tid] = NULL; 1298 atomic_dec(&t->conns_in_use); 1299 if (t->hash_base && (tid >= t->hash_base)) { 1300 if (family == AF_INET6) 1301 atomic_sub(2, &t->hash_tids_in_use); 1302 else 1303 atomic_dec(&t->hash_tids_in_use); 1304 } else { 1305 if (family == AF_INET6) 1306 atomic_sub(2, &t->tids_in_use); 1307 else 1308 atomic_dec(&t->tids_in_use); 1309 } 1310 } 1311 1312 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1313 if (likely(skb)) { 1314 mk_tid_release(skb, chan, tid); 1315 t4_ofld_send(adap, skb); 1316 } else 1317 cxgb4_queue_tid_release(t, chan, tid); 1318 } 1319 EXPORT_SYMBOL(cxgb4_remove_tid); 1320 1321 /* 1322 * Allocate and initialize the TID tables. Returns 0 on success. 1323 */ 1324 static int tid_init(struct tid_info *t) 1325 { 1326 struct adapter *adap = container_of(t, struct adapter, tids); 1327 unsigned int max_ftids = t->nftids + t->nsftids; 1328 unsigned int natids = t->natids; 1329 unsigned int stid_bmap_size; 1330 unsigned int ftid_bmap_size; 1331 size_t size; 1332 1333 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1334 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1335 size = t->ntids * sizeof(*t->tid_tab) + 1336 natids * sizeof(*t->atid_tab) + 1337 t->nstids * sizeof(*t->stid_tab) + 1338 t->nsftids * sizeof(*t->stid_tab) + 1339 stid_bmap_size * sizeof(long) + 1340 max_ftids * sizeof(*t->ftid_tab) + 1341 ftid_bmap_size * sizeof(long); 1342 1343 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1344 if (!t->tid_tab) 1345 return -ENOMEM; 1346 1347 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1348 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1349 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1350 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1351 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1352 spin_lock_init(&t->stid_lock); 1353 spin_lock_init(&t->atid_lock); 1354 spin_lock_init(&t->ftid_lock); 1355 1356 t->stids_in_use = 0; 1357 t->v6_stids_in_use = 0; 1358 t->sftids_in_use = 0; 1359 t->afree = NULL; 1360 t->atids_in_use = 0; 1361 atomic_set(&t->tids_in_use, 0); 1362 atomic_set(&t->conns_in_use, 0); 1363 atomic_set(&t->hash_tids_in_use, 0); 1364 1365 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1366 if (natids) { 1367 while (--natids) 1368 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1369 t->afree = t->atid_tab; 1370 } 1371 1372 if (is_offload(adap)) { 1373 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1374 /* Reserve stid 0 for T4/T5 adapters */ 1375 if (!t->stid_base && 1376 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1377 __set_bit(0, t->stid_bmap); 1378 } 1379 1380 bitmap_zero(t->ftid_bmap, t->nftids); 1381 return 0; 1382 } 1383 1384 /** 1385 * cxgb4_create_server - create an IP server 1386 * @dev: the device 1387 * @stid: the server TID 1388 * @sip: local IP address to bind server to 1389 * @sport: the server's TCP port 1390 * @queue: queue to direct messages from this server to 1391 * 1392 * Create an IP server for the given port and address. 1393 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1394 */ 1395 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1396 __be32 sip, __be16 sport, __be16 vlan, 1397 unsigned int queue) 1398 { 1399 unsigned int chan; 1400 struct sk_buff *skb; 1401 struct adapter *adap; 1402 struct cpl_pass_open_req *req; 1403 int ret; 1404 1405 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1406 if (!skb) 1407 return -ENOMEM; 1408 1409 adap = netdev2adap(dev); 1410 req = __skb_put(skb, sizeof(*req)); 1411 INIT_TP_WR(req, 0); 1412 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1413 req->local_port = sport; 1414 req->peer_port = htons(0); 1415 req->local_ip = sip; 1416 req->peer_ip = htonl(0); 1417 chan = rxq_to_chan(&adap->sge, queue); 1418 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1419 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1420 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1421 ret = t4_mgmt_tx(adap, skb); 1422 return net_xmit_eval(ret); 1423 } 1424 EXPORT_SYMBOL(cxgb4_create_server); 1425 1426 /* cxgb4_create_server6 - create an IPv6 server 1427 * @dev: the device 1428 * @stid: the server TID 1429 * @sip: local IPv6 address to bind server to 1430 * @sport: the server's TCP port 1431 * @queue: queue to direct messages from this server to 1432 * 1433 * Create an IPv6 server for the given port and address. 1434 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1435 */ 1436 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1437 const struct in6_addr *sip, __be16 sport, 1438 unsigned int queue) 1439 { 1440 unsigned int chan; 1441 struct sk_buff *skb; 1442 struct adapter *adap; 1443 struct cpl_pass_open_req6 *req; 1444 int ret; 1445 1446 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1447 if (!skb) 1448 return -ENOMEM; 1449 1450 adap = netdev2adap(dev); 1451 req = __skb_put(skb, sizeof(*req)); 1452 INIT_TP_WR(req, 0); 1453 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1454 req->local_port = sport; 1455 req->peer_port = htons(0); 1456 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1457 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1458 req->peer_ip_hi = cpu_to_be64(0); 1459 req->peer_ip_lo = cpu_to_be64(0); 1460 chan = rxq_to_chan(&adap->sge, queue); 1461 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1462 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1463 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1464 ret = t4_mgmt_tx(adap, skb); 1465 return net_xmit_eval(ret); 1466 } 1467 EXPORT_SYMBOL(cxgb4_create_server6); 1468 1469 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1470 unsigned int queue, bool ipv6) 1471 { 1472 struct sk_buff *skb; 1473 struct adapter *adap; 1474 struct cpl_close_listsvr_req *req; 1475 int ret; 1476 1477 adap = netdev2adap(dev); 1478 1479 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1480 if (!skb) 1481 return -ENOMEM; 1482 1483 req = __skb_put(skb, sizeof(*req)); 1484 INIT_TP_WR(req, 0); 1485 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1486 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1487 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1488 ret = t4_mgmt_tx(adap, skb); 1489 return net_xmit_eval(ret); 1490 } 1491 EXPORT_SYMBOL(cxgb4_remove_server); 1492 1493 /** 1494 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1495 * @mtus: the HW MTU table 1496 * @mtu: the target MTU 1497 * @idx: index of selected entry in the MTU table 1498 * 1499 * Returns the index and the value in the HW MTU table that is closest to 1500 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1501 * table, in which case that smallest available value is selected. 1502 */ 1503 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1504 unsigned int *idx) 1505 { 1506 unsigned int i = 0; 1507 1508 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1509 ++i; 1510 if (idx) 1511 *idx = i; 1512 return mtus[i]; 1513 } 1514 EXPORT_SYMBOL(cxgb4_best_mtu); 1515 1516 /** 1517 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1518 * @mtus: the HW MTU table 1519 * @header_size: Header Size 1520 * @data_size_max: maximum Data Segment Size 1521 * @data_size_align: desired Data Segment Size Alignment (2^N) 1522 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1523 * 1524 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1525 * MTU Table based solely on a Maximum MTU parameter, we break that 1526 * parameter up into a Header Size and Maximum Data Segment Size, and 1527 * provide a desired Data Segment Size Alignment. If we find an MTU in 1528 * the Hardware MTU Table which will result in a Data Segment Size with 1529 * the requested alignment _and_ that MTU isn't "too far" from the 1530 * closest MTU, then we'll return that rather than the closest MTU. 1531 */ 1532 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1533 unsigned short header_size, 1534 unsigned short data_size_max, 1535 unsigned short data_size_align, 1536 unsigned int *mtu_idxp) 1537 { 1538 unsigned short max_mtu = header_size + data_size_max; 1539 unsigned short data_size_align_mask = data_size_align - 1; 1540 int mtu_idx, aligned_mtu_idx; 1541 1542 /* Scan the MTU Table till we find an MTU which is larger than our 1543 * Maximum MTU or we reach the end of the table. Along the way, 1544 * record the last MTU found, if any, which will result in a Data 1545 * Segment Length matching the requested alignment. 1546 */ 1547 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1548 unsigned short data_size = mtus[mtu_idx] - header_size; 1549 1550 /* If this MTU minus the Header Size would result in a 1551 * Data Segment Size of the desired alignment, remember it. 1552 */ 1553 if ((data_size & data_size_align_mask) == 0) 1554 aligned_mtu_idx = mtu_idx; 1555 1556 /* If we're not at the end of the Hardware MTU Table and the 1557 * next element is larger than our Maximum MTU, drop out of 1558 * the loop. 1559 */ 1560 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1561 break; 1562 } 1563 1564 /* If we fell out of the loop because we ran to the end of the table, 1565 * then we just have to use the last [largest] entry. 1566 */ 1567 if (mtu_idx == NMTUS) 1568 mtu_idx--; 1569 1570 /* If we found an MTU which resulted in the requested Data Segment 1571 * Length alignment and that's "not far" from the largest MTU which is 1572 * less than or equal to the maximum MTU, then use that. 1573 */ 1574 if (aligned_mtu_idx >= 0 && 1575 mtu_idx - aligned_mtu_idx <= 1) 1576 mtu_idx = aligned_mtu_idx; 1577 1578 /* If the caller has passed in an MTU Index pointer, pass the 1579 * MTU Index back. Return the MTU value. 1580 */ 1581 if (mtu_idxp) 1582 *mtu_idxp = mtu_idx; 1583 return mtus[mtu_idx]; 1584 } 1585 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1586 1587 /** 1588 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI 1589 * @chip: chip type 1590 * @viid: VI id of the given port 1591 * 1592 * Return the SMT index for this VI. 1593 */ 1594 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) 1595 { 1596 /* In T4/T5, SMT contains 256 SMAC entries organized in 1597 * 128 rows of 2 entries each. 1598 * In T6, SMT contains 256 SMAC entries in 256 rows. 1599 * TODO: The below code needs to be updated when we add support 1600 * for 256 VFs. 1601 */ 1602 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 1603 return ((viid & 0x7f) << 1); 1604 else 1605 return (viid & 0x7f); 1606 } 1607 EXPORT_SYMBOL(cxgb4_tp_smt_idx); 1608 1609 /** 1610 * cxgb4_port_chan - get the HW channel of a port 1611 * @dev: the net device for the port 1612 * 1613 * Return the HW Tx channel of the given port. 1614 */ 1615 unsigned int cxgb4_port_chan(const struct net_device *dev) 1616 { 1617 return netdev2pinfo(dev)->tx_chan; 1618 } 1619 EXPORT_SYMBOL(cxgb4_port_chan); 1620 1621 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1622 { 1623 struct adapter *adap = netdev2adap(dev); 1624 u32 v1, v2, lp_count, hp_count; 1625 1626 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1627 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1628 if (is_t4(adap->params.chip)) { 1629 lp_count = LP_COUNT_G(v1); 1630 hp_count = HP_COUNT_G(v1); 1631 } else { 1632 lp_count = LP_COUNT_T5_G(v1); 1633 hp_count = HP_COUNT_T5_G(v2); 1634 } 1635 return lpfifo ? lp_count : hp_count; 1636 } 1637 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1638 1639 /** 1640 * cxgb4_port_viid - get the VI id of a port 1641 * @dev: the net device for the port 1642 * 1643 * Return the VI id of the given port. 1644 */ 1645 unsigned int cxgb4_port_viid(const struct net_device *dev) 1646 { 1647 return netdev2pinfo(dev)->viid; 1648 } 1649 EXPORT_SYMBOL(cxgb4_port_viid); 1650 1651 /** 1652 * cxgb4_port_idx - get the index of a port 1653 * @dev: the net device for the port 1654 * 1655 * Return the index of the given port. 1656 */ 1657 unsigned int cxgb4_port_idx(const struct net_device *dev) 1658 { 1659 return netdev2pinfo(dev)->port_id; 1660 } 1661 EXPORT_SYMBOL(cxgb4_port_idx); 1662 1663 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1664 struct tp_tcp_stats *v6) 1665 { 1666 struct adapter *adap = pci_get_drvdata(pdev); 1667 1668 spin_lock(&adap->stats_lock); 1669 t4_tp_get_tcp_stats(adap, v4, v6, false); 1670 spin_unlock(&adap->stats_lock); 1671 } 1672 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1673 1674 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1675 const unsigned int *pgsz_order) 1676 { 1677 struct adapter *adap = netdev2adap(dev); 1678 1679 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1680 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1681 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 1682 HPZ3_V(pgsz_order[3])); 1683 } 1684 EXPORT_SYMBOL(cxgb4_iscsi_init); 1685 1686 int cxgb4_flush_eq_cache(struct net_device *dev) 1687 { 1688 struct adapter *adap = netdev2adap(dev); 1689 1690 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS); 1691 } 1692 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 1693 1694 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 1695 { 1696 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 1697 __be64 indices; 1698 int ret; 1699 1700 spin_lock(&adap->win0_lock); 1701 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 1702 sizeof(indices), (__be32 *)&indices, 1703 T4_MEMORY_READ); 1704 spin_unlock(&adap->win0_lock); 1705 if (!ret) { 1706 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 1707 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 1708 } 1709 return ret; 1710 } 1711 1712 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 1713 u16 size) 1714 { 1715 struct adapter *adap = netdev2adap(dev); 1716 u16 hw_pidx, hw_cidx; 1717 int ret; 1718 1719 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 1720 if (ret) 1721 goto out; 1722 1723 if (pidx != hw_pidx) { 1724 u16 delta; 1725 u32 val; 1726 1727 if (pidx >= hw_pidx) 1728 delta = pidx - hw_pidx; 1729 else 1730 delta = size - hw_pidx + pidx; 1731 1732 if (is_t4(adap->params.chip)) 1733 val = PIDX_V(delta); 1734 else 1735 val = PIDX_T5_V(delta); 1736 wmb(); 1737 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1738 QID_V(qid) | val); 1739 } 1740 out: 1741 return ret; 1742 } 1743 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 1744 1745 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 1746 { 1747 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 1748 u32 edc0_end, edc1_end, mc0_end, mc1_end; 1749 u32 offset, memtype, memaddr; 1750 struct adapter *adap; 1751 u32 hma_size = 0; 1752 int ret; 1753 1754 adap = netdev2adap(dev); 1755 1756 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 1757 1758 /* Figure out where the offset lands in the Memory Type/Address scheme. 1759 * This code assumes that the memory is laid out starting at offset 0 1760 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 1761 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 1762 * MC0, and some have both MC0 and MC1. 1763 */ 1764 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 1765 edc0_size = EDRAM0_SIZE_G(size) << 20; 1766 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 1767 edc1_size = EDRAM1_SIZE_G(size) << 20; 1768 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 1769 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 1770 1771 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { 1772 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1773 hma_size = EXT_MEM1_SIZE_G(size) << 20; 1774 } 1775 edc0_end = edc0_size; 1776 edc1_end = edc0_end + edc1_size; 1777 mc0_end = edc1_end + mc0_size; 1778 1779 if (offset < edc0_end) { 1780 memtype = MEM_EDC0; 1781 memaddr = offset; 1782 } else if (offset < edc1_end) { 1783 memtype = MEM_EDC1; 1784 memaddr = offset - edc0_end; 1785 } else { 1786 if (hma_size && (offset < (edc1_end + hma_size))) { 1787 memtype = MEM_HMA; 1788 memaddr = offset - edc1_end; 1789 } else if (offset < mc0_end) { 1790 memtype = MEM_MC0; 1791 memaddr = offset - edc1_end; 1792 } else if (is_t5(adap->params.chip)) { 1793 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1794 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 1795 mc1_end = mc0_end + mc1_size; 1796 if (offset < mc1_end) { 1797 memtype = MEM_MC1; 1798 memaddr = offset - mc0_end; 1799 } else { 1800 /* offset beyond the end of any memory */ 1801 goto err; 1802 } 1803 } else { 1804 /* T4/T6 only has a single memory channel */ 1805 goto err; 1806 } 1807 } 1808 1809 spin_lock(&adap->win0_lock); 1810 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 1811 spin_unlock(&adap->win0_lock); 1812 return ret; 1813 1814 err: 1815 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 1816 stag, offset); 1817 return -EINVAL; 1818 } 1819 EXPORT_SYMBOL(cxgb4_read_tpte); 1820 1821 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 1822 { 1823 u32 hi, lo; 1824 struct adapter *adap; 1825 1826 adap = netdev2adap(dev); 1827 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 1828 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 1829 1830 return ((u64)hi << 32) | (u64)lo; 1831 } 1832 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 1833 1834 int cxgb4_bar2_sge_qregs(struct net_device *dev, 1835 unsigned int qid, 1836 enum cxgb4_bar2_qtype qtype, 1837 int user, 1838 u64 *pbar2_qoffset, 1839 unsigned int *pbar2_qid) 1840 { 1841 return t4_bar2_sge_qregs(netdev2adap(dev), 1842 qid, 1843 (qtype == CXGB4_BAR2_QTYPE_EGRESS 1844 ? T4_BAR2_QTYPE_EGRESS 1845 : T4_BAR2_QTYPE_INGRESS), 1846 user, 1847 pbar2_qoffset, 1848 pbar2_qid); 1849 } 1850 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 1851 1852 static struct pci_driver cxgb4_driver; 1853 1854 static void check_neigh_update(struct neighbour *neigh) 1855 { 1856 const struct device *parent; 1857 const struct net_device *netdev = neigh->dev; 1858 1859 if (is_vlan_dev(netdev)) 1860 netdev = vlan_dev_real_dev(netdev); 1861 parent = netdev->dev.parent; 1862 if (parent && parent->driver == &cxgb4_driver.driver) 1863 t4_l2t_update(dev_get_drvdata(parent), neigh); 1864 } 1865 1866 static int netevent_cb(struct notifier_block *nb, unsigned long event, 1867 void *data) 1868 { 1869 switch (event) { 1870 case NETEVENT_NEIGH_UPDATE: 1871 check_neigh_update(data); 1872 break; 1873 case NETEVENT_REDIRECT: 1874 default: 1875 break; 1876 } 1877 return 0; 1878 } 1879 1880 static bool netevent_registered; 1881 static struct notifier_block cxgb4_netevent_nb = { 1882 .notifier_call = netevent_cb 1883 }; 1884 1885 static void drain_db_fifo(struct adapter *adap, int usecs) 1886 { 1887 u32 v1, v2, lp_count, hp_count; 1888 1889 do { 1890 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1891 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1892 if (is_t4(adap->params.chip)) { 1893 lp_count = LP_COUNT_G(v1); 1894 hp_count = HP_COUNT_G(v1); 1895 } else { 1896 lp_count = LP_COUNT_T5_G(v1); 1897 hp_count = HP_COUNT_T5_G(v2); 1898 } 1899 1900 if (lp_count == 0 && hp_count == 0) 1901 break; 1902 set_current_state(TASK_UNINTERRUPTIBLE); 1903 schedule_timeout(usecs_to_jiffies(usecs)); 1904 } while (1); 1905 } 1906 1907 static void disable_txq_db(struct sge_txq *q) 1908 { 1909 unsigned long flags; 1910 1911 spin_lock_irqsave(&q->db_lock, flags); 1912 q->db_disabled = 1; 1913 spin_unlock_irqrestore(&q->db_lock, flags); 1914 } 1915 1916 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 1917 { 1918 spin_lock_irq(&q->db_lock); 1919 if (q->db_pidx_inc) { 1920 /* Make sure that all writes to the TX descriptors 1921 * are committed before we tell HW about them. 1922 */ 1923 wmb(); 1924 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1925 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 1926 q->db_pidx_inc = 0; 1927 } 1928 q->db_disabled = 0; 1929 spin_unlock_irq(&q->db_lock); 1930 } 1931 1932 static void disable_dbs(struct adapter *adap) 1933 { 1934 int i; 1935 1936 for_each_ethrxq(&adap->sge, i) 1937 disable_txq_db(&adap->sge.ethtxq[i].q); 1938 if (is_offload(adap)) { 1939 struct sge_uld_txq_info *txq_info = 1940 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1941 1942 if (txq_info) { 1943 for_each_ofldtxq(&adap->sge, i) { 1944 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1945 1946 disable_txq_db(&txq->q); 1947 } 1948 } 1949 } 1950 for_each_port(adap, i) 1951 disable_txq_db(&adap->sge.ctrlq[i].q); 1952 } 1953 1954 static void enable_dbs(struct adapter *adap) 1955 { 1956 int i; 1957 1958 for_each_ethrxq(&adap->sge, i) 1959 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 1960 if (is_offload(adap)) { 1961 struct sge_uld_txq_info *txq_info = 1962 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1963 1964 if (txq_info) { 1965 for_each_ofldtxq(&adap->sge, i) { 1966 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1967 1968 enable_txq_db(adap, &txq->q); 1969 } 1970 } 1971 } 1972 for_each_port(adap, i) 1973 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 1974 } 1975 1976 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 1977 { 1978 enum cxgb4_uld type = CXGB4_ULD_RDMA; 1979 1980 if (adap->uld && adap->uld[type].handle) 1981 adap->uld[type].control(adap->uld[type].handle, cmd); 1982 } 1983 1984 static void process_db_full(struct work_struct *work) 1985 { 1986 struct adapter *adap; 1987 1988 adap = container_of(work, struct adapter, db_full_task); 1989 1990 drain_db_fifo(adap, dbfifo_drain_delay); 1991 enable_dbs(adap); 1992 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 1993 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1994 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1995 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 1996 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 1997 else 1998 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1999 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2000 } 2001 2002 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2003 { 2004 u16 hw_pidx, hw_cidx; 2005 int ret; 2006 2007 spin_lock_irq(&q->db_lock); 2008 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2009 if (ret) 2010 goto out; 2011 if (q->db_pidx != hw_pidx) { 2012 u16 delta; 2013 u32 val; 2014 2015 if (q->db_pidx >= hw_pidx) 2016 delta = q->db_pidx - hw_pidx; 2017 else 2018 delta = q->size - hw_pidx + q->db_pidx; 2019 2020 if (is_t4(adap->params.chip)) 2021 val = PIDX_V(delta); 2022 else 2023 val = PIDX_T5_V(delta); 2024 wmb(); 2025 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2026 QID_V(q->cntxt_id) | val); 2027 } 2028 out: 2029 q->db_disabled = 0; 2030 q->db_pidx_inc = 0; 2031 spin_unlock_irq(&q->db_lock); 2032 if (ret) 2033 CH_WARN(adap, "DB drop recovery failed.\n"); 2034 } 2035 2036 static void recover_all_queues(struct adapter *adap) 2037 { 2038 int i; 2039 2040 for_each_ethrxq(&adap->sge, i) 2041 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2042 if (is_offload(adap)) { 2043 struct sge_uld_txq_info *txq_info = 2044 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2045 if (txq_info) { 2046 for_each_ofldtxq(&adap->sge, i) { 2047 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2048 2049 sync_txq_pidx(adap, &txq->q); 2050 } 2051 } 2052 } 2053 for_each_port(adap, i) 2054 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2055 } 2056 2057 static void process_db_drop(struct work_struct *work) 2058 { 2059 struct adapter *adap; 2060 2061 adap = container_of(work, struct adapter, db_drop_task); 2062 2063 if (is_t4(adap->params.chip)) { 2064 drain_db_fifo(adap, dbfifo_drain_delay); 2065 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2066 drain_db_fifo(adap, dbfifo_drain_delay); 2067 recover_all_queues(adap); 2068 drain_db_fifo(adap, dbfifo_drain_delay); 2069 enable_dbs(adap); 2070 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2071 } else if (is_t5(adap->params.chip)) { 2072 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2073 u16 qid = (dropped_db >> 15) & 0x1ffff; 2074 u16 pidx_inc = dropped_db & 0x1fff; 2075 u64 bar2_qoffset; 2076 unsigned int bar2_qid; 2077 int ret; 2078 2079 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2080 0, &bar2_qoffset, &bar2_qid); 2081 if (ret) 2082 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2083 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2084 else 2085 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2086 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2087 2088 /* Re-enable BAR2 WC */ 2089 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2090 } 2091 2092 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2093 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2094 } 2095 2096 void t4_db_full(struct adapter *adap) 2097 { 2098 if (is_t4(adap->params.chip)) { 2099 disable_dbs(adap); 2100 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2101 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2102 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2103 queue_work(adap->workq, &adap->db_full_task); 2104 } 2105 } 2106 2107 void t4_db_dropped(struct adapter *adap) 2108 { 2109 if (is_t4(adap->params.chip)) { 2110 disable_dbs(adap); 2111 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2112 } 2113 queue_work(adap->workq, &adap->db_drop_task); 2114 } 2115 2116 void t4_register_netevent_notifier(void) 2117 { 2118 if (!netevent_registered) { 2119 register_netevent_notifier(&cxgb4_netevent_nb); 2120 netevent_registered = true; 2121 } 2122 } 2123 2124 static void detach_ulds(struct adapter *adap) 2125 { 2126 unsigned int i; 2127 2128 mutex_lock(&uld_mutex); 2129 list_del(&adap->list_node); 2130 2131 for (i = 0; i < CXGB4_ULD_MAX; i++) 2132 if (adap->uld && adap->uld[i].handle) 2133 adap->uld[i].state_change(adap->uld[i].handle, 2134 CXGB4_STATE_DETACH); 2135 2136 if (netevent_registered && list_empty(&adapter_list)) { 2137 unregister_netevent_notifier(&cxgb4_netevent_nb); 2138 netevent_registered = false; 2139 } 2140 mutex_unlock(&uld_mutex); 2141 } 2142 2143 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2144 { 2145 unsigned int i; 2146 2147 mutex_lock(&uld_mutex); 2148 for (i = 0; i < CXGB4_ULD_MAX; i++) 2149 if (adap->uld && adap->uld[i].handle) 2150 adap->uld[i].state_change(adap->uld[i].handle, 2151 new_state); 2152 mutex_unlock(&uld_mutex); 2153 } 2154 2155 #if IS_ENABLED(CONFIG_IPV6) 2156 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2157 unsigned long event, void *data) 2158 { 2159 struct inet6_ifaddr *ifa = data; 2160 struct net_device *event_dev = ifa->idev->dev; 2161 const struct device *parent = NULL; 2162 #if IS_ENABLED(CONFIG_BONDING) 2163 struct adapter *adap; 2164 #endif 2165 if (is_vlan_dev(event_dev)) 2166 event_dev = vlan_dev_real_dev(event_dev); 2167 #if IS_ENABLED(CONFIG_BONDING) 2168 if (event_dev->flags & IFF_MASTER) { 2169 list_for_each_entry(adap, &adapter_list, list_node) { 2170 switch (event) { 2171 case NETDEV_UP: 2172 cxgb4_clip_get(adap->port[0], 2173 (const u32 *)ifa, 1); 2174 break; 2175 case NETDEV_DOWN: 2176 cxgb4_clip_release(adap->port[0], 2177 (const u32 *)ifa, 1); 2178 break; 2179 default: 2180 break; 2181 } 2182 } 2183 return NOTIFY_OK; 2184 } 2185 #endif 2186 2187 if (event_dev) 2188 parent = event_dev->dev.parent; 2189 2190 if (parent && parent->driver == &cxgb4_driver.driver) { 2191 switch (event) { 2192 case NETDEV_UP: 2193 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2194 break; 2195 case NETDEV_DOWN: 2196 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2197 break; 2198 default: 2199 break; 2200 } 2201 } 2202 return NOTIFY_OK; 2203 } 2204 2205 static bool inet6addr_registered; 2206 static struct notifier_block cxgb4_inet6addr_notifier = { 2207 .notifier_call = cxgb4_inet6addr_handler 2208 }; 2209 2210 static void update_clip(const struct adapter *adap) 2211 { 2212 int i; 2213 struct net_device *dev; 2214 int ret; 2215 2216 rcu_read_lock(); 2217 2218 for (i = 0; i < MAX_NPORTS; i++) { 2219 dev = adap->port[i]; 2220 ret = 0; 2221 2222 if (dev) 2223 ret = cxgb4_update_root_dev_clip(dev); 2224 2225 if (ret < 0) 2226 break; 2227 } 2228 rcu_read_unlock(); 2229 } 2230 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2231 2232 /** 2233 * cxgb_up - enable the adapter 2234 * @adap: adapter being enabled 2235 * 2236 * Called when the first port is enabled, this function performs the 2237 * actions necessary to make an adapter operational, such as completing 2238 * the initialization of HW modules, and enabling interrupts. 2239 * 2240 * Must be called with the rtnl lock held. 2241 */ 2242 static int cxgb_up(struct adapter *adap) 2243 { 2244 int err; 2245 2246 mutex_lock(&uld_mutex); 2247 err = setup_sge_queues(adap); 2248 if (err) 2249 goto rel_lock; 2250 err = setup_rss(adap); 2251 if (err) 2252 goto freeq; 2253 2254 if (adap->flags & USING_MSIX) { 2255 name_msix_vecs(adap); 2256 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2257 adap->msix_info[0].desc, adap); 2258 if (err) 2259 goto irq_err; 2260 err = request_msix_queue_irqs(adap); 2261 if (err) { 2262 free_irq(adap->msix_info[0].vec, adap); 2263 goto irq_err; 2264 } 2265 } else { 2266 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2267 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, 2268 adap->port[0]->name, adap); 2269 if (err) 2270 goto irq_err; 2271 } 2272 2273 enable_rx(adap); 2274 t4_sge_start(adap); 2275 t4_intr_enable(adap); 2276 adap->flags |= FULL_INIT_DONE; 2277 mutex_unlock(&uld_mutex); 2278 2279 notify_ulds(adap, CXGB4_STATE_UP); 2280 #if IS_ENABLED(CONFIG_IPV6) 2281 update_clip(adap); 2282 #endif 2283 /* Initialize hash mac addr list*/ 2284 INIT_LIST_HEAD(&adap->mac_hlist); 2285 return err; 2286 2287 irq_err: 2288 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2289 freeq: 2290 t4_free_sge_resources(adap); 2291 rel_lock: 2292 mutex_unlock(&uld_mutex); 2293 return err; 2294 } 2295 2296 static void cxgb_down(struct adapter *adapter) 2297 { 2298 cancel_work_sync(&adapter->tid_release_task); 2299 cancel_work_sync(&adapter->db_full_task); 2300 cancel_work_sync(&adapter->db_drop_task); 2301 adapter->tid_release_task_busy = false; 2302 adapter->tid_release_head = NULL; 2303 2304 t4_sge_stop(adapter); 2305 t4_free_sge_resources(adapter); 2306 adapter->flags &= ~FULL_INIT_DONE; 2307 } 2308 2309 /* 2310 * net_device operations 2311 */ 2312 static int cxgb_open(struct net_device *dev) 2313 { 2314 int err; 2315 struct port_info *pi = netdev_priv(dev); 2316 struct adapter *adapter = pi->adapter; 2317 2318 netif_carrier_off(dev); 2319 2320 if (!(adapter->flags & FULL_INIT_DONE)) { 2321 err = cxgb_up(adapter); 2322 if (err < 0) 2323 return err; 2324 } 2325 2326 /* It's possible that the basic port information could have 2327 * changed since we first read it. 2328 */ 2329 err = t4_update_port_info(pi); 2330 if (err < 0) 2331 return err; 2332 2333 err = link_start(dev); 2334 if (!err) 2335 netif_tx_start_all_queues(dev); 2336 return err; 2337 } 2338 2339 static int cxgb_close(struct net_device *dev) 2340 { 2341 struct port_info *pi = netdev_priv(dev); 2342 struct adapter *adapter = pi->adapter; 2343 int ret; 2344 2345 netif_tx_stop_all_queues(dev); 2346 netif_carrier_off(dev); 2347 ret = t4_enable_pi_params(adapter, adapter->pf, pi, 2348 false, false, false); 2349 #ifdef CONFIG_CHELSIO_T4_DCB 2350 cxgb4_dcb_reset(dev); 2351 dcb_tx_queue_prio_enable(dev, false); 2352 #endif 2353 return ret; 2354 } 2355 2356 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2357 __be32 sip, __be16 sport, __be16 vlan, 2358 unsigned int queue, unsigned char port, unsigned char mask) 2359 { 2360 int ret; 2361 struct filter_entry *f; 2362 struct adapter *adap; 2363 int i; 2364 u8 *val; 2365 2366 adap = netdev2adap(dev); 2367 2368 /* Adjust stid to correct filter index */ 2369 stid -= adap->tids.sftid_base; 2370 stid += adap->tids.nftids; 2371 2372 /* Check to make sure the filter requested is writable ... 2373 */ 2374 f = &adap->tids.ftid_tab[stid]; 2375 ret = writable_filter(f); 2376 if (ret) 2377 return ret; 2378 2379 /* Clear out any old resources being used by the filter before 2380 * we start constructing the new filter. 2381 */ 2382 if (f->valid) 2383 clear_filter(adap, f); 2384 2385 /* Clear out filter specifications */ 2386 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2387 f->fs.val.lport = cpu_to_be16(sport); 2388 f->fs.mask.lport = ~0; 2389 val = (u8 *)&sip; 2390 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2391 for (i = 0; i < 4; i++) { 2392 f->fs.val.lip[i] = val[i]; 2393 f->fs.mask.lip[i] = ~0; 2394 } 2395 if (adap->params.tp.vlan_pri_map & PORT_F) { 2396 f->fs.val.iport = port; 2397 f->fs.mask.iport = mask; 2398 } 2399 } 2400 2401 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2402 f->fs.val.proto = IPPROTO_TCP; 2403 f->fs.mask.proto = ~0; 2404 } 2405 2406 f->fs.dirsteer = 1; 2407 f->fs.iq = queue; 2408 /* Mark filter as locked */ 2409 f->locked = 1; 2410 f->fs.rpttid = 1; 2411 2412 /* Save the actual tid. We need this to get the corresponding 2413 * filter entry structure in filter_rpl. 2414 */ 2415 f->tid = stid + adap->tids.ftid_base; 2416 ret = set_filter_wr(adap, stid); 2417 if (ret) { 2418 clear_filter(adap, f); 2419 return ret; 2420 } 2421 2422 return 0; 2423 } 2424 EXPORT_SYMBOL(cxgb4_create_server_filter); 2425 2426 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2427 unsigned int queue, bool ipv6) 2428 { 2429 struct filter_entry *f; 2430 struct adapter *adap; 2431 2432 adap = netdev2adap(dev); 2433 2434 /* Adjust stid to correct filter index */ 2435 stid -= adap->tids.sftid_base; 2436 stid += adap->tids.nftids; 2437 2438 f = &adap->tids.ftid_tab[stid]; 2439 /* Unlock the filter */ 2440 f->locked = 0; 2441 2442 return delete_filter(adap, stid); 2443 } 2444 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2445 2446 static void cxgb_get_stats(struct net_device *dev, 2447 struct rtnl_link_stats64 *ns) 2448 { 2449 struct port_stats stats; 2450 struct port_info *p = netdev_priv(dev); 2451 struct adapter *adapter = p->adapter; 2452 2453 /* Block retrieving statistics during EEH error 2454 * recovery. Otherwise, the recovery might fail 2455 * and the PCI device will be removed permanently 2456 */ 2457 spin_lock(&adapter->stats_lock); 2458 if (!netif_device_present(dev)) { 2459 spin_unlock(&adapter->stats_lock); 2460 return; 2461 } 2462 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2463 &p->stats_base); 2464 spin_unlock(&adapter->stats_lock); 2465 2466 ns->tx_bytes = stats.tx_octets; 2467 ns->tx_packets = stats.tx_frames; 2468 ns->rx_bytes = stats.rx_octets; 2469 ns->rx_packets = stats.rx_frames; 2470 ns->multicast = stats.rx_mcast_frames; 2471 2472 /* detailed rx_errors */ 2473 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2474 stats.rx_runt; 2475 ns->rx_over_errors = 0; 2476 ns->rx_crc_errors = stats.rx_fcs_err; 2477 ns->rx_frame_errors = stats.rx_symbol_err; 2478 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 2479 stats.rx_ovflow2 + stats.rx_ovflow3 + 2480 stats.rx_trunc0 + stats.rx_trunc1 + 2481 stats.rx_trunc2 + stats.rx_trunc3; 2482 ns->rx_missed_errors = 0; 2483 2484 /* detailed tx_errors */ 2485 ns->tx_aborted_errors = 0; 2486 ns->tx_carrier_errors = 0; 2487 ns->tx_fifo_errors = 0; 2488 ns->tx_heartbeat_errors = 0; 2489 ns->tx_window_errors = 0; 2490 2491 ns->tx_errors = stats.tx_error_frames; 2492 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2493 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2494 } 2495 2496 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2497 { 2498 unsigned int mbox; 2499 int ret = 0, prtad, devad; 2500 struct port_info *pi = netdev_priv(dev); 2501 struct adapter *adapter = pi->adapter; 2502 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2503 2504 switch (cmd) { 2505 case SIOCGMIIPHY: 2506 if (pi->mdio_addr < 0) 2507 return -EOPNOTSUPP; 2508 data->phy_id = pi->mdio_addr; 2509 break; 2510 case SIOCGMIIREG: 2511 case SIOCSMIIREG: 2512 if (mdio_phy_id_is_c45(data->phy_id)) { 2513 prtad = mdio_phy_id_prtad(data->phy_id); 2514 devad = mdio_phy_id_devad(data->phy_id); 2515 } else if (data->phy_id < 32) { 2516 prtad = data->phy_id; 2517 devad = 0; 2518 data->reg_num &= 0x1f; 2519 } else 2520 return -EINVAL; 2521 2522 mbox = pi->adapter->pf; 2523 if (cmd == SIOCGMIIREG) 2524 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2525 data->reg_num, &data->val_out); 2526 else 2527 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2528 data->reg_num, data->val_in); 2529 break; 2530 case SIOCGHWTSTAMP: 2531 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2532 sizeof(pi->tstamp_config)) ? 2533 -EFAULT : 0; 2534 case SIOCSHWTSTAMP: 2535 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 2536 sizeof(pi->tstamp_config))) 2537 return -EFAULT; 2538 2539 if (!is_t4(adapter->params.chip)) { 2540 switch (pi->tstamp_config.tx_type) { 2541 case HWTSTAMP_TX_OFF: 2542 case HWTSTAMP_TX_ON: 2543 break; 2544 default: 2545 return -ERANGE; 2546 } 2547 2548 switch (pi->tstamp_config.rx_filter) { 2549 case HWTSTAMP_FILTER_NONE: 2550 pi->rxtstamp = false; 2551 break; 2552 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2553 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2554 cxgb4_ptprx_timestamping(pi, pi->port_id, 2555 PTP_TS_L4); 2556 break; 2557 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2558 cxgb4_ptprx_timestamping(pi, pi->port_id, 2559 PTP_TS_L2_L4); 2560 break; 2561 case HWTSTAMP_FILTER_ALL: 2562 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2563 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2564 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2565 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2566 pi->rxtstamp = true; 2567 break; 2568 default: 2569 pi->tstamp_config.rx_filter = 2570 HWTSTAMP_FILTER_NONE; 2571 return -ERANGE; 2572 } 2573 2574 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 2575 (pi->tstamp_config.rx_filter == 2576 HWTSTAMP_FILTER_NONE)) { 2577 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 2578 pi->ptp_enable = false; 2579 } 2580 2581 if (pi->tstamp_config.rx_filter != 2582 HWTSTAMP_FILTER_NONE) { 2583 if (cxgb4_ptp_redirect_rx_packet(adapter, 2584 pi) >= 0) 2585 pi->ptp_enable = true; 2586 } 2587 } else { 2588 /* For T4 Adapters */ 2589 switch (pi->tstamp_config.rx_filter) { 2590 case HWTSTAMP_FILTER_NONE: 2591 pi->rxtstamp = false; 2592 break; 2593 case HWTSTAMP_FILTER_ALL: 2594 pi->rxtstamp = true; 2595 break; 2596 default: 2597 pi->tstamp_config.rx_filter = 2598 HWTSTAMP_FILTER_NONE; 2599 return -ERANGE; 2600 } 2601 } 2602 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2603 sizeof(pi->tstamp_config)) ? 2604 -EFAULT : 0; 2605 default: 2606 return -EOPNOTSUPP; 2607 } 2608 return ret; 2609 } 2610 2611 static void cxgb_set_rxmode(struct net_device *dev) 2612 { 2613 /* unfortunately we can't return errors to the stack */ 2614 set_rxmode(dev, -1, false); 2615 } 2616 2617 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2618 { 2619 int ret; 2620 struct port_info *pi = netdev_priv(dev); 2621 2622 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2623 -1, -1, -1, true); 2624 if (!ret) 2625 dev->mtu = new_mtu; 2626 return ret; 2627 } 2628 2629 #ifdef CONFIG_PCI_IOV 2630 static int cxgb4_mgmt_open(struct net_device *dev) 2631 { 2632 /* Turn carrier off since we don't have to transmit anything on this 2633 * interface. 2634 */ 2635 netif_carrier_off(dev); 2636 return 0; 2637 } 2638 2639 /* Fill MAC address that will be assigned by the FW */ 2640 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap) 2641 { 2642 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 2643 unsigned int i, vf, nvfs; 2644 u16 a, b; 2645 int err; 2646 u8 *na; 2647 2648 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev, 2649 PCI_CAP_ID_VPD); 2650 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 2651 if (err) 2652 return; 2653 2654 na = adap->params.vpd.na; 2655 for (i = 0; i < ETH_ALEN; i++) 2656 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 2657 hex2val(na[2 * i + 1])); 2658 2659 a = (hw_addr[0] << 8) | hw_addr[1]; 2660 b = (hw_addr[1] << 8) | hw_addr[2]; 2661 a ^= b; 2662 a |= 0x0200; /* locally assigned Ethernet MAC address */ 2663 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 2664 macaddr[0] = a >> 8; 2665 macaddr[1] = a & 0xff; 2666 2667 for (i = 2; i < 5; i++) 2668 macaddr[i] = hw_addr[i + 1]; 2669 2670 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev); 2671 vf < nvfs; vf++) { 2672 macaddr[5] = adap->pf * 16 + vf; 2673 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr); 2674 } 2675 } 2676 2677 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 2678 { 2679 struct port_info *pi = netdev_priv(dev); 2680 struct adapter *adap = pi->adapter; 2681 int ret; 2682 2683 /* verify MAC addr is valid */ 2684 if (!is_valid_ether_addr(mac)) { 2685 dev_err(pi->adapter->pdev_dev, 2686 "Invalid Ethernet address %pM for VF %d\n", 2687 mac, vf); 2688 return -EINVAL; 2689 } 2690 2691 dev_info(pi->adapter->pdev_dev, 2692 "Setting MAC %pM on VF %d\n", mac, vf); 2693 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 2694 if (!ret) 2695 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 2696 return ret; 2697 } 2698 2699 static int cxgb4_mgmt_get_vf_config(struct net_device *dev, 2700 int vf, struct ifla_vf_info *ivi) 2701 { 2702 struct port_info *pi = netdev_priv(dev); 2703 struct adapter *adap = pi->adapter; 2704 struct vf_info *vfinfo; 2705 2706 if (vf >= adap->num_vfs) 2707 return -EINVAL; 2708 vfinfo = &adap->vfinfo[vf]; 2709 2710 ivi->vf = vf; 2711 ivi->max_tx_rate = vfinfo->tx_rate; 2712 ivi->min_tx_rate = 0; 2713 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr); 2714 ivi->vlan = vfinfo->vlan; 2715 return 0; 2716 } 2717 2718 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev, 2719 struct netdev_phys_item_id *ppid) 2720 { 2721 struct port_info *pi = netdev_priv(dev); 2722 unsigned int phy_port_id; 2723 2724 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 2725 ppid->id_len = sizeof(phy_port_id); 2726 memcpy(ppid->id, &phy_port_id, ppid->id_len); 2727 return 0; 2728 } 2729 2730 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf, 2731 int min_tx_rate, int max_tx_rate) 2732 { 2733 struct port_info *pi = netdev_priv(dev); 2734 struct adapter *adap = pi->adapter; 2735 unsigned int link_ok, speed, mtu; 2736 u32 fw_pfvf, fw_class; 2737 int class_id = vf; 2738 int ret; 2739 u16 pktsize; 2740 2741 if (vf >= adap->num_vfs) 2742 return -EINVAL; 2743 2744 if (min_tx_rate) { 2745 dev_err(adap->pdev_dev, 2746 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 2747 min_tx_rate, vf); 2748 return -EINVAL; 2749 } 2750 2751 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 2752 if (ret != FW_SUCCESS) { 2753 dev_err(adap->pdev_dev, 2754 "Failed to get link information for VF %d\n", vf); 2755 return -EINVAL; 2756 } 2757 2758 if (!link_ok) { 2759 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 2760 return -EINVAL; 2761 } 2762 2763 if (max_tx_rate > speed) { 2764 dev_err(adap->pdev_dev, 2765 "Max tx rate %d for VF %d can't be > link-speed %u", 2766 max_tx_rate, vf, speed); 2767 return -EINVAL; 2768 } 2769 2770 pktsize = mtu; 2771 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 2772 pktsize = pktsize - sizeof(struct ethhdr) - 4; 2773 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 2774 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 2775 /* configure Traffic Class for rate-limiting */ 2776 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 2777 SCHED_CLASS_LEVEL_CL_RL, 2778 SCHED_CLASS_MODE_CLASS, 2779 SCHED_CLASS_RATEUNIT_BITS, 2780 SCHED_CLASS_RATEMODE_ABS, 2781 pi->tx_chan, class_id, 0, 2782 max_tx_rate * 1000, 0, pktsize); 2783 if (ret) { 2784 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 2785 ret); 2786 return -EINVAL; 2787 } 2788 dev_info(adap->pdev_dev, 2789 "Class %d with MSS %u configured with rate %u\n", 2790 class_id, pktsize, max_tx_rate); 2791 2792 /* bind VF to configured Traffic Class */ 2793 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2794 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2795 fw_class = class_id; 2796 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 2797 &fw_class); 2798 if (ret) { 2799 dev_err(adap->pdev_dev, 2800 "Err %d in binding VF %d to Traffic Class %d\n", 2801 ret, vf, class_id); 2802 return -EINVAL; 2803 } 2804 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 2805 adap->pf, vf, class_id); 2806 adap->vfinfo[vf].tx_rate = max_tx_rate; 2807 return 0; 2808 } 2809 2810 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf, 2811 u16 vlan, u8 qos, __be16 vlan_proto) 2812 { 2813 struct port_info *pi = netdev_priv(dev); 2814 struct adapter *adap = pi->adapter; 2815 int ret; 2816 2817 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7) 2818 return -EINVAL; 2819 2820 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0) 2821 return -EPROTONOSUPPORT; 2822 2823 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan); 2824 if (!ret) { 2825 adap->vfinfo[vf].vlan = vlan; 2826 return 0; 2827 } 2828 2829 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n", 2830 ret, (vlan ? "setting" : "clearing"), adap->pf, vf); 2831 return ret; 2832 } 2833 #endif /* CONFIG_PCI_IOV */ 2834 2835 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2836 { 2837 int ret; 2838 struct sockaddr *addr = p; 2839 struct port_info *pi = netdev_priv(dev); 2840 2841 if (!is_valid_ether_addr(addr->sa_data)) 2842 return -EADDRNOTAVAIL; 2843 2844 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, 2845 pi->xact_addr_filt, addr->sa_data, true, true); 2846 if (ret < 0) 2847 return ret; 2848 2849 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2850 pi->xact_addr_filt = ret; 2851 return 0; 2852 } 2853 2854 #ifdef CONFIG_NET_POLL_CONTROLLER 2855 static void cxgb_netpoll(struct net_device *dev) 2856 { 2857 struct port_info *pi = netdev_priv(dev); 2858 struct adapter *adap = pi->adapter; 2859 2860 if (adap->flags & USING_MSIX) { 2861 int i; 2862 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 2863 2864 for (i = pi->nqsets; i; i--, rx++) 2865 t4_sge_intr_msix(0, &rx->rspq); 2866 } else 2867 t4_intr_handler(adap)(0, adap); 2868 } 2869 #endif 2870 2871 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 2872 { 2873 struct port_info *pi = netdev_priv(dev); 2874 struct adapter *adap = pi->adapter; 2875 struct sched_class *e; 2876 struct ch_sched_params p; 2877 struct ch_sched_queue qe; 2878 u32 req_rate; 2879 int err = 0; 2880 2881 if (!can_sched(dev)) 2882 return -ENOTSUPP; 2883 2884 if (index < 0 || index > pi->nqsets - 1) 2885 return -EINVAL; 2886 2887 if (!(adap->flags & FULL_INIT_DONE)) { 2888 dev_err(adap->pdev_dev, 2889 "Failed to rate limit on queue %d. Link Down?\n", 2890 index); 2891 return -EINVAL; 2892 } 2893 2894 /* Convert from Mbps to Kbps */ 2895 req_rate = rate * 1000; 2896 2897 /* Max rate is 100 Gbps */ 2898 if (req_rate > SCHED_MAX_RATE_KBPS) { 2899 dev_err(adap->pdev_dev, 2900 "Invalid rate %u Mbps, Max rate is %u Mbps\n", 2901 rate, SCHED_MAX_RATE_KBPS / 1000); 2902 return -ERANGE; 2903 } 2904 2905 /* First unbind the queue from any existing class */ 2906 memset(&qe, 0, sizeof(qe)); 2907 qe.queue = index; 2908 qe.class = SCHED_CLS_NONE; 2909 2910 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 2911 if (err) { 2912 dev_err(adap->pdev_dev, 2913 "Unbinding Queue %d on port %d fail. Err: %d\n", 2914 index, pi->port_id, err); 2915 return err; 2916 } 2917 2918 /* Queue already unbound */ 2919 if (!req_rate) 2920 return 0; 2921 2922 /* Fetch any available unused or matching scheduling class */ 2923 memset(&p, 0, sizeof(p)); 2924 p.type = SCHED_CLASS_TYPE_PACKET; 2925 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 2926 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 2927 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 2928 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 2929 p.u.params.channel = pi->tx_chan; 2930 p.u.params.class = SCHED_CLS_NONE; 2931 p.u.params.minrate = 0; 2932 p.u.params.maxrate = req_rate; 2933 p.u.params.weight = 0; 2934 p.u.params.pktsize = dev->mtu; 2935 2936 e = cxgb4_sched_class_alloc(dev, &p); 2937 if (!e) 2938 return -ENOMEM; 2939 2940 /* Bind the queue to a scheduling class */ 2941 memset(&qe, 0, sizeof(qe)); 2942 qe.queue = index; 2943 qe.class = e->idx; 2944 2945 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 2946 if (err) 2947 dev_err(adap->pdev_dev, 2948 "Queue rate limiting failed. Err: %d\n", err); 2949 return err; 2950 } 2951 2952 static int cxgb_setup_tc_flower(struct net_device *dev, 2953 struct tc_cls_flower_offload *cls_flower) 2954 { 2955 switch (cls_flower->command) { 2956 case TC_CLSFLOWER_REPLACE: 2957 return cxgb4_tc_flower_replace(dev, cls_flower); 2958 case TC_CLSFLOWER_DESTROY: 2959 return cxgb4_tc_flower_destroy(dev, cls_flower); 2960 case TC_CLSFLOWER_STATS: 2961 return cxgb4_tc_flower_stats(dev, cls_flower); 2962 default: 2963 return -EOPNOTSUPP; 2964 } 2965 } 2966 2967 static int cxgb_setup_tc_cls_u32(struct net_device *dev, 2968 struct tc_cls_u32_offload *cls_u32) 2969 { 2970 switch (cls_u32->command) { 2971 case TC_CLSU32_NEW_KNODE: 2972 case TC_CLSU32_REPLACE_KNODE: 2973 return cxgb4_config_knode(dev, cls_u32); 2974 case TC_CLSU32_DELETE_KNODE: 2975 return cxgb4_delete_knode(dev, cls_u32); 2976 default: 2977 return -EOPNOTSUPP; 2978 } 2979 } 2980 2981 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2982 void *cb_priv) 2983 { 2984 struct net_device *dev = cb_priv; 2985 struct port_info *pi = netdev2pinfo(dev); 2986 struct adapter *adap = netdev2adap(dev); 2987 2988 if (!(adap->flags & FULL_INIT_DONE)) { 2989 dev_err(adap->pdev_dev, 2990 "Failed to setup tc on port %d. Link Down?\n", 2991 pi->port_id); 2992 return -EINVAL; 2993 } 2994 2995 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 2996 return -EOPNOTSUPP; 2997 2998 switch (type) { 2999 case TC_SETUP_CLSU32: 3000 return cxgb_setup_tc_cls_u32(dev, type_data); 3001 case TC_SETUP_CLSFLOWER: 3002 return cxgb_setup_tc_flower(dev, type_data); 3003 default: 3004 return -EOPNOTSUPP; 3005 } 3006 } 3007 3008 static int cxgb_setup_tc_block(struct net_device *dev, 3009 struct tc_block_offload *f) 3010 { 3011 struct port_info *pi = netdev2pinfo(dev); 3012 3013 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 3014 return -EOPNOTSUPP; 3015 3016 switch (f->command) { 3017 case TC_BLOCK_BIND: 3018 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb, 3019 pi, dev); 3020 case TC_BLOCK_UNBIND: 3021 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi); 3022 return 0; 3023 default: 3024 return -EOPNOTSUPP; 3025 } 3026 } 3027 3028 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 3029 void *type_data) 3030 { 3031 switch (type) { 3032 case TC_SETUP_BLOCK: 3033 return cxgb_setup_tc_block(dev, type_data); 3034 default: 3035 return -EOPNOTSUPP; 3036 } 3037 } 3038 3039 static void cxgb_del_udp_tunnel(struct net_device *netdev, 3040 struct udp_tunnel_info *ti) 3041 { 3042 struct port_info *pi = netdev_priv(netdev); 3043 struct adapter *adapter = pi->adapter; 3044 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3045 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3046 int ret = 0, i; 3047 3048 if (chip_ver < CHELSIO_T6) 3049 return; 3050 3051 switch (ti->type) { 3052 case UDP_TUNNEL_TYPE_VXLAN: 3053 if (!adapter->vxlan_port_cnt || 3054 adapter->vxlan_port != ti->port) 3055 return; /* Invalid VxLAN destination port */ 3056 3057 adapter->vxlan_port_cnt--; 3058 if (adapter->vxlan_port_cnt) 3059 return; 3060 3061 adapter->vxlan_port = 0; 3062 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0); 3063 break; 3064 case UDP_TUNNEL_TYPE_GENEVE: 3065 if (!adapter->geneve_port_cnt || 3066 adapter->geneve_port != ti->port) 3067 return; /* Invalid GENEVE destination port */ 3068 3069 adapter->geneve_port_cnt--; 3070 if (adapter->geneve_port_cnt) 3071 return; 3072 3073 adapter->geneve_port = 0; 3074 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0); 3075 default: 3076 return; 3077 } 3078 3079 /* Matchall mac entries can be deleted only after all tunnel ports 3080 * are brought down or removed. 3081 */ 3082 if (!adapter->rawf_cnt) 3083 return; 3084 for_each_port(adapter, i) { 3085 pi = adap2pinfo(adapter, i); 3086 ret = t4_free_raw_mac_filt(adapter, pi->viid, 3087 match_all_mac, match_all_mac, 3088 adapter->rawf_start + 3089 pi->port_id, 3090 1, pi->port_id, false); 3091 if (ret < 0) { 3092 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n", 3093 i); 3094 return; 3095 } 3096 atomic_dec(&adapter->mps_encap[adapter->rawf_start + 3097 pi->port_id].refcnt); 3098 } 3099 } 3100 3101 static void cxgb_add_udp_tunnel(struct net_device *netdev, 3102 struct udp_tunnel_info *ti) 3103 { 3104 struct port_info *pi = netdev_priv(netdev); 3105 struct adapter *adapter = pi->adapter; 3106 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3107 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3108 int i, ret; 3109 3110 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt) 3111 return; 3112 3113 switch (ti->type) { 3114 case UDP_TUNNEL_TYPE_VXLAN: 3115 /* Callback for adding vxlan port can be called with the same 3116 * port for both IPv4 and IPv6. We should not disable the 3117 * offloading when the same port for both protocols is added 3118 * and later one of them is removed. 3119 */ 3120 if (adapter->vxlan_port_cnt && 3121 adapter->vxlan_port == ti->port) { 3122 adapter->vxlan_port_cnt++; 3123 return; 3124 } 3125 3126 /* We will support only one VxLAN port */ 3127 if (adapter->vxlan_port_cnt) { 3128 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3129 be16_to_cpu(adapter->vxlan_port), 3130 be16_to_cpu(ti->port)); 3131 return; 3132 } 3133 3134 adapter->vxlan_port = ti->port; 3135 adapter->vxlan_port_cnt = 1; 3136 3137 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 3138 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F); 3139 break; 3140 case UDP_TUNNEL_TYPE_GENEVE: 3141 if (adapter->geneve_port_cnt && 3142 adapter->geneve_port == ti->port) { 3143 adapter->geneve_port_cnt++; 3144 return; 3145 } 3146 3147 /* We will support only one GENEVE port */ 3148 if (adapter->geneve_port_cnt) { 3149 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3150 be16_to_cpu(adapter->geneve_port), 3151 be16_to_cpu(ti->port)); 3152 return; 3153 } 3154 3155 adapter->geneve_port = ti->port; 3156 adapter->geneve_port_cnt = 1; 3157 3158 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 3159 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F); 3160 default: 3161 return; 3162 } 3163 3164 /* Create a 'match all' mac filter entry for inner mac, 3165 * if raw mac interface is supported. Once the linux kernel provides 3166 * driver entry points for adding/deleting the inner mac addresses, 3167 * we will remove this 'match all' entry and fallback to adding 3168 * exact match filters. 3169 */ 3170 for_each_port(adapter, i) { 3171 pi = adap2pinfo(adapter, i); 3172 3173 ret = t4_alloc_raw_mac_filt(adapter, pi->viid, 3174 match_all_mac, 3175 match_all_mac, 3176 adapter->rawf_start + 3177 pi->port_id, 3178 1, pi->port_id, false); 3179 if (ret < 0) { 3180 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n", 3181 be16_to_cpu(ti->port)); 3182 cxgb_del_udp_tunnel(netdev, ti); 3183 return; 3184 } 3185 atomic_inc(&adapter->mps_encap[ret].refcnt); 3186 } 3187 } 3188 3189 static netdev_features_t cxgb_features_check(struct sk_buff *skb, 3190 struct net_device *dev, 3191 netdev_features_t features) 3192 { 3193 struct port_info *pi = netdev_priv(dev); 3194 struct adapter *adapter = pi->adapter; 3195 3196 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3197 return features; 3198 3199 /* Check if hw supports offload for this packet */ 3200 if (!skb->encapsulation || cxgb_encap_offload_supported(skb)) 3201 return features; 3202 3203 /* Offload is not supported for this encapsulated packet */ 3204 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3205 } 3206 3207 static netdev_features_t cxgb_fix_features(struct net_device *dev, 3208 netdev_features_t features) 3209 { 3210 /* Disable GRO, if RX_CSUM is disabled */ 3211 if (!(features & NETIF_F_RXCSUM)) 3212 features &= ~NETIF_F_GRO; 3213 3214 return features; 3215 } 3216 3217 static const struct net_device_ops cxgb4_netdev_ops = { 3218 .ndo_open = cxgb_open, 3219 .ndo_stop = cxgb_close, 3220 .ndo_start_xmit = t4_eth_xmit, 3221 .ndo_select_queue = cxgb_select_queue, 3222 .ndo_get_stats64 = cxgb_get_stats, 3223 .ndo_set_rx_mode = cxgb_set_rxmode, 3224 .ndo_set_mac_address = cxgb_set_mac_addr, 3225 .ndo_set_features = cxgb_set_features, 3226 .ndo_validate_addr = eth_validate_addr, 3227 .ndo_do_ioctl = cxgb_ioctl, 3228 .ndo_change_mtu = cxgb_change_mtu, 3229 #ifdef CONFIG_NET_POLL_CONTROLLER 3230 .ndo_poll_controller = cxgb_netpoll, 3231 #endif 3232 #ifdef CONFIG_CHELSIO_T4_FCOE 3233 .ndo_fcoe_enable = cxgb_fcoe_enable, 3234 .ndo_fcoe_disable = cxgb_fcoe_disable, 3235 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3236 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 3237 .ndo_setup_tc = cxgb_setup_tc, 3238 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel, 3239 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel, 3240 .ndo_features_check = cxgb_features_check, 3241 .ndo_fix_features = cxgb_fix_features, 3242 }; 3243 3244 #ifdef CONFIG_PCI_IOV 3245 static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 3246 .ndo_open = cxgb4_mgmt_open, 3247 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac, 3248 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config, 3249 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate, 3250 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id, 3251 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan, 3252 }; 3253 #endif 3254 3255 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev, 3256 struct ethtool_drvinfo *info) 3257 { 3258 struct adapter *adapter = netdev2adap(dev); 3259 3260 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 3261 strlcpy(info->version, cxgb4_driver_version, 3262 sizeof(info->version)); 3263 strlcpy(info->bus_info, pci_name(adapter->pdev), 3264 sizeof(info->bus_info)); 3265 } 3266 3267 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 3268 .get_drvinfo = cxgb4_mgmt_get_drvinfo, 3269 }; 3270 3271 static void notify_fatal_err(struct work_struct *work) 3272 { 3273 struct adapter *adap; 3274 3275 adap = container_of(work, struct adapter, fatal_err_notify_task); 3276 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR); 3277 } 3278 3279 void t4_fatal_err(struct adapter *adap) 3280 { 3281 int port; 3282 3283 if (pci_channel_offline(adap->pdev)) 3284 return; 3285 3286 /* Disable the SGE since ULDs are going to free resources that 3287 * could be exposed to the adapter. RDMA MWs for example... 3288 */ 3289 t4_shutdown_adapter(adap); 3290 for_each_port(adap, port) { 3291 struct net_device *dev = adap->port[port]; 3292 3293 /* If we get here in very early initialization the network 3294 * devices may not have been set up yet. 3295 */ 3296 if (!dev) 3297 continue; 3298 3299 netif_tx_stop_all_queues(dev); 3300 netif_carrier_off(dev); 3301 } 3302 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3303 queue_work(adap->workq, &adap->fatal_err_notify_task); 3304 } 3305 3306 static void setup_memwin(struct adapter *adap) 3307 { 3308 u32 nic_win_base = t4_get_util_window(adap); 3309 3310 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3311 } 3312 3313 static void setup_memwin_rdma(struct adapter *adap) 3314 { 3315 if (adap->vres.ocq.size) { 3316 u32 start; 3317 unsigned int sz_kb; 3318 3319 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3320 start &= PCI_BASE_ADDRESS_MEM_MASK; 3321 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3322 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3323 t4_write_reg(adap, 3324 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3325 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3326 t4_write_reg(adap, 3327 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3328 adap->vres.ocq.start); 3329 t4_read_reg(adap, 3330 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3331 } 3332 } 3333 3334 /* HMA Definitions */ 3335 3336 /* The maximum number of address that can be send in a single FW cmd */ 3337 #define HMA_MAX_ADDR_IN_CMD 5 3338 3339 #define HMA_PAGE_SIZE PAGE_SIZE 3340 3341 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */ 3342 3343 #define HMA_PAGE_ORDER \ 3344 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \ 3345 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0) 3346 3347 /* The minimum and maximum possible HMA sizes that can be specified in the FW 3348 * configuration(in units of MB). 3349 */ 3350 #define HMA_MIN_TOTAL_SIZE 1 3351 #define HMA_MAX_TOTAL_SIZE \ 3352 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \ 3353 HMA_MAX_NO_FW_ADDRESS) >> 20) 3354 3355 static void adap_free_hma_mem(struct adapter *adapter) 3356 { 3357 struct scatterlist *iter; 3358 struct page *page; 3359 int i; 3360 3361 if (!adapter->hma.sgt) 3362 return; 3363 3364 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) { 3365 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl, 3366 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL); 3367 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG; 3368 } 3369 3370 for_each_sg(adapter->hma.sgt->sgl, iter, 3371 adapter->hma.sgt->orig_nents, i) { 3372 page = sg_page(iter); 3373 if (page) 3374 __free_pages(page, HMA_PAGE_ORDER); 3375 } 3376 3377 kfree(adapter->hma.phy_addr); 3378 sg_free_table(adapter->hma.sgt); 3379 kfree(adapter->hma.sgt); 3380 adapter->hma.sgt = NULL; 3381 } 3382 3383 static int adap_config_hma(struct adapter *adapter) 3384 { 3385 struct scatterlist *sgl, *iter; 3386 struct sg_table *sgt; 3387 struct page *newpage; 3388 unsigned int i, j, k; 3389 u32 param, hma_size; 3390 unsigned int ncmds; 3391 size_t page_size; 3392 u32 page_order; 3393 int node, ret; 3394 3395 /* HMA is supported only for T6+ cards. 3396 * Avoid initializing HMA in kdump kernels. 3397 */ 3398 if (is_kdump_kernel() || 3399 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3400 return 0; 3401 3402 /* Get the HMA region size required by fw */ 3403 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3404 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE)); 3405 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3406 1, ¶m, &hma_size); 3407 /* An error means card has its own memory or HMA is not supported by 3408 * the firmware. Return without any errors. 3409 */ 3410 if (ret || !hma_size) 3411 return 0; 3412 3413 if (hma_size < HMA_MIN_TOTAL_SIZE || 3414 hma_size > HMA_MAX_TOTAL_SIZE) { 3415 dev_err(adapter->pdev_dev, 3416 "HMA size %uMB beyond bounds(%u-%lu)MB\n", 3417 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE); 3418 return -EINVAL; 3419 } 3420 3421 page_size = HMA_PAGE_SIZE; 3422 page_order = HMA_PAGE_ORDER; 3423 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL); 3424 if (unlikely(!adapter->hma.sgt)) { 3425 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n"); 3426 return -ENOMEM; 3427 } 3428 sgt = adapter->hma.sgt; 3429 /* FW returned value will be in MB's 3430 */ 3431 sgt->orig_nents = (hma_size << 20) / (page_size << page_order); 3432 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) { 3433 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n"); 3434 kfree(adapter->hma.sgt); 3435 adapter->hma.sgt = NULL; 3436 return -ENOMEM; 3437 } 3438 3439 sgl = adapter->hma.sgt->sgl; 3440 node = dev_to_node(adapter->pdev_dev); 3441 for_each_sg(sgl, iter, sgt->orig_nents, i) { 3442 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL | 3443 __GFP_ZERO, page_order); 3444 if (!newpage) { 3445 dev_err(adapter->pdev_dev, 3446 "Not enough memory for HMA page allocation\n"); 3447 ret = -ENOMEM; 3448 goto free_hma; 3449 } 3450 sg_set_page(iter, newpage, page_size << page_order, 0); 3451 } 3452 3453 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents, 3454 DMA_BIDIRECTIONAL); 3455 if (!sgt->nents) { 3456 dev_err(adapter->pdev_dev, 3457 "Not enough memory for HMA DMA mapping"); 3458 ret = -ENOMEM; 3459 goto free_hma; 3460 } 3461 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG; 3462 3463 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t), 3464 GFP_KERNEL); 3465 if (unlikely(!adapter->hma.phy_addr)) 3466 goto free_hma; 3467 3468 for_each_sg(sgl, iter, sgt->nents, i) { 3469 newpage = sg_page(iter); 3470 adapter->hma.phy_addr[i] = sg_dma_address(iter); 3471 } 3472 3473 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD); 3474 /* Pass on the addresses to firmware */ 3475 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { 3476 struct fw_hma_cmd hma_cmd; 3477 u8 naddr = HMA_MAX_ADDR_IN_CMD; 3478 u8 soc = 0, eoc = 0; 3479 u8 hma_mode = 1; /* Presently we support only Page table mode */ 3480 3481 soc = (i == 0) ? 1 : 0; 3482 eoc = (i == ncmds - 1) ? 1 : 0; 3483 3484 /* For last cmd, set naddr corresponding to remaining 3485 * addresses 3486 */ 3487 if (i == ncmds - 1) { 3488 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD; 3489 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD; 3490 } 3491 memset(&hma_cmd, 0, sizeof(hma_cmd)); 3492 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) | 3493 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3494 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd)); 3495 3496 hma_cmd.mode_to_pcie_params = 3497 htonl(FW_HMA_CMD_MODE_V(hma_mode) | 3498 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc)); 3499 3500 /* HMA cmd size specified in MB's */ 3501 hma_cmd.naddr_size = 3502 htonl(FW_HMA_CMD_SIZE_V(hma_size) | 3503 FW_HMA_CMD_NADDR_V(naddr)); 3504 3505 /* Total Page size specified in units of 4K */ 3506 hma_cmd.addr_size_pkd = 3507 htonl(FW_HMA_CMD_ADDR_SIZE_V 3508 ((page_size << page_order) >> 12)); 3509 3510 /* Fill the 5 addresses */ 3511 for (j = 0; j < naddr; j++) { 3512 hma_cmd.phy_address[j] = 3513 cpu_to_be64(adapter->hma.phy_addr[j + k]); 3514 } 3515 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd, 3516 sizeof(hma_cmd), &hma_cmd); 3517 if (ret) { 3518 dev_err(adapter->pdev_dev, 3519 "HMA FW command failed with err %d\n", ret); 3520 goto free_hma; 3521 } 3522 } 3523 3524 if (!ret) 3525 dev_info(adapter->pdev_dev, 3526 "Reserved %uMB host memory for HMA\n", hma_size); 3527 return ret; 3528 3529 free_hma: 3530 adap_free_hma_mem(adapter); 3531 return ret; 3532 } 3533 3534 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3535 { 3536 u32 v; 3537 int ret; 3538 3539 /* get device capabilities */ 3540 memset(c, 0, sizeof(*c)); 3541 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3542 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3543 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3544 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3545 if (ret < 0) 3546 return ret; 3547 3548 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3549 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3550 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3551 if (ret < 0) 3552 return ret; 3553 3554 ret = t4_config_glbl_rss(adap, adap->pf, 3555 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3556 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3557 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3558 if (ret < 0) 3559 return ret; 3560 3561 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3562 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3563 FW_CMD_CAP_PF); 3564 if (ret < 0) 3565 return ret; 3566 3567 t4_sge_init(adap); 3568 3569 /* tweak some settings */ 3570 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3571 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3572 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3573 v = t4_read_reg(adap, TP_PIO_DATA_A); 3574 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3575 3576 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3577 adap->params.tp.tx_modq_map = 0xE4; 3578 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3579 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3580 3581 /* associate each Tx modulation queue with consecutive Tx channels */ 3582 v = 0x84218421; 3583 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3584 &v, 1, TP_TX_SCHED_HDR_A); 3585 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3586 &v, 1, TP_TX_SCHED_FIFO_A); 3587 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3588 &v, 1, TP_TX_SCHED_PCMD_A); 3589 3590 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3591 if (is_offload(adap)) { 3592 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3593 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3594 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3595 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3596 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3597 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3598 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3599 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3600 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3601 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3602 } 3603 3604 /* get basic stuff going */ 3605 return t4_early_init(adap, adap->pf); 3606 } 3607 3608 /* 3609 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3610 */ 3611 #define MAX_ATIDS 8192U 3612 3613 /* 3614 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3615 * 3616 * If the firmware we're dealing with has Configuration File support, then 3617 * we use that to perform all configuration 3618 */ 3619 3620 /* 3621 * Tweak configuration based on module parameters, etc. Most of these have 3622 * defaults assigned to them by Firmware Configuration Files (if we're using 3623 * them) but need to be explicitly set if we're using hard-coded 3624 * initialization. But even in the case of using Firmware Configuration 3625 * Files, we'd like to expose the ability to change these via module 3626 * parameters so these are essentially common tweaks/settings for 3627 * Configuration Files and hard-coded initialization ... 3628 */ 3629 static int adap_init0_tweaks(struct adapter *adapter) 3630 { 3631 /* 3632 * Fix up various Host-Dependent Parameters like Page Size, Cache 3633 * Line Size, etc. The firmware default is for a 4KB Page Size and 3634 * 64B Cache Line Size ... 3635 */ 3636 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3637 3638 /* 3639 * Process module parameters which affect early initialization. 3640 */ 3641 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3642 dev_err(&adapter->pdev->dev, 3643 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3644 rx_dma_offset); 3645 rx_dma_offset = 2; 3646 } 3647 t4_set_reg_field(adapter, SGE_CONTROL_A, 3648 PKTSHIFT_V(PKTSHIFT_M), 3649 PKTSHIFT_V(rx_dma_offset)); 3650 3651 /* 3652 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3653 * adds the pseudo header itself. 3654 */ 3655 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3656 CSUM_HAS_PSEUDO_HDR_F, 0); 3657 3658 return 0; 3659 } 3660 3661 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3662 * unto themselves and they contain their own firmware to perform their 3663 * tasks ... 3664 */ 3665 static int phy_aq1202_version(const u8 *phy_fw_data, 3666 size_t phy_fw_size) 3667 { 3668 int offset; 3669 3670 /* At offset 0x8 you're looking for the primary image's 3671 * starting offset which is 3 Bytes wide 3672 * 3673 * At offset 0xa of the primary image, you look for the offset 3674 * of the DRAM segment which is 3 Bytes wide. 3675 * 3676 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3677 * wide 3678 */ 3679 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3680 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3681 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3682 3683 offset = le24(phy_fw_data + 0x8) << 12; 3684 offset = le24(phy_fw_data + offset + 0xa); 3685 return be16(phy_fw_data + offset + 0x27e); 3686 3687 #undef be16 3688 #undef le16 3689 #undef le24 3690 } 3691 3692 static struct info_10gbt_phy_fw { 3693 unsigned int phy_fw_id; /* PCI Device ID */ 3694 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3695 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3696 int phy_flash; /* Has FLASH for PHY Firmware */ 3697 } phy_info_array[] = { 3698 { 3699 PHY_AQ1202_DEVICEID, 3700 PHY_AQ1202_FIRMWARE, 3701 phy_aq1202_version, 3702 1, 3703 }, 3704 { 3705 PHY_BCM84834_DEVICEID, 3706 PHY_BCM84834_FIRMWARE, 3707 NULL, 3708 0, 3709 }, 3710 { 0, NULL, NULL }, 3711 }; 3712 3713 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3714 { 3715 int i; 3716 3717 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3718 if (phy_info_array[i].phy_fw_id == devid) 3719 return &phy_info_array[i]; 3720 } 3721 return NULL; 3722 } 3723 3724 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3725 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3726 * we return a negative error number. If we transfer new firmware we return 1 3727 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3728 */ 3729 static int adap_init0_phy(struct adapter *adap) 3730 { 3731 const struct firmware *phyf; 3732 int ret; 3733 struct info_10gbt_phy_fw *phy_info; 3734 3735 /* Use the device ID to determine which PHY file to flash. 3736 */ 3737 phy_info = find_phy_info(adap->pdev->device); 3738 if (!phy_info) { 3739 dev_warn(adap->pdev_dev, 3740 "No PHY Firmware file found for this PHY\n"); 3741 return -EOPNOTSUPP; 3742 } 3743 3744 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3745 * use that. The adapter firmware provides us with a memory buffer 3746 * where we can load a PHY firmware file from the host if we want to 3747 * override the PHY firmware File in flash. 3748 */ 3749 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3750 adap->pdev_dev); 3751 if (ret < 0) { 3752 /* For adapters without FLASH attached to PHY for their 3753 * firmware, it's obviously a fatal error if we can't get the 3754 * firmware to the adapter. For adapters with PHY firmware 3755 * FLASH storage, it's worth a warning if we can't find the 3756 * PHY Firmware but we'll neuter the error ... 3757 */ 3758 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3759 "/lib/firmware/%s, error %d\n", 3760 phy_info->phy_fw_file, -ret); 3761 if (phy_info->phy_flash) { 3762 int cur_phy_fw_ver = 0; 3763 3764 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3765 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3766 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3767 ret = 0; 3768 } 3769 3770 return ret; 3771 } 3772 3773 /* Load PHY Firmware onto adapter. 3774 */ 3775 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3776 phy_info->phy_fw_version, 3777 (u8 *)phyf->data, phyf->size); 3778 if (ret < 0) 3779 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3780 -ret); 3781 else if (ret > 0) { 3782 int new_phy_fw_ver = 0; 3783 3784 if (phy_info->phy_fw_version) 3785 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3786 phyf->size); 3787 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3788 "Firmware /lib/firmware/%s, version %#x\n", 3789 phy_info->phy_fw_file, new_phy_fw_ver); 3790 } 3791 3792 release_firmware(phyf); 3793 3794 return ret; 3795 } 3796 3797 /* 3798 * Attempt to initialize the adapter via a Firmware Configuration File. 3799 */ 3800 static int adap_init0_config(struct adapter *adapter, int reset) 3801 { 3802 struct fw_caps_config_cmd caps_cmd; 3803 const struct firmware *cf; 3804 unsigned long mtype = 0, maddr = 0; 3805 u32 finiver, finicsum, cfcsum; 3806 int ret; 3807 int config_issued = 0; 3808 char *fw_config_file, fw_config_file_path[256]; 3809 char *config_name = NULL; 3810 3811 /* 3812 * Reset device if necessary. 3813 */ 3814 if (reset) { 3815 ret = t4_fw_reset(adapter, adapter->mbox, 3816 PIORSTMODE_F | PIORST_F); 3817 if (ret < 0) 3818 goto bye; 3819 } 3820 3821 /* If this is a 10Gb/s-BT adapter make sure the chip-external 3822 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 3823 * to be performed after any global adapter RESET above since some 3824 * PHYs only have local RAM copies of the PHY firmware. 3825 */ 3826 if (is_10gbt_device(adapter->pdev->device)) { 3827 ret = adap_init0_phy(adapter); 3828 if (ret < 0) 3829 goto bye; 3830 } 3831 /* 3832 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 3833 * then use that. Otherwise, use the configuration file stored 3834 * in the adapter flash ... 3835 */ 3836 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 3837 case CHELSIO_T4: 3838 fw_config_file = FW4_CFNAME; 3839 break; 3840 case CHELSIO_T5: 3841 fw_config_file = FW5_CFNAME; 3842 break; 3843 case CHELSIO_T6: 3844 fw_config_file = FW6_CFNAME; 3845 break; 3846 default: 3847 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3848 adapter->pdev->device); 3849 ret = -EINVAL; 3850 goto bye; 3851 } 3852 3853 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 3854 if (ret < 0) { 3855 config_name = "On FLASH"; 3856 mtype = FW_MEMTYPE_CF_FLASH; 3857 maddr = t4_flash_cfg_addr(adapter); 3858 } else { 3859 u32 params[7], val[7]; 3860 3861 sprintf(fw_config_file_path, 3862 "/lib/firmware/%s", fw_config_file); 3863 config_name = fw_config_file_path; 3864 3865 if (cf->size >= FLASH_CFG_MAX_SIZE) 3866 ret = -ENOMEM; 3867 else { 3868 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3869 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3870 ret = t4_query_params(adapter, adapter->mbox, 3871 adapter->pf, 0, 1, params, val); 3872 if (ret == 0) { 3873 /* 3874 * For t4_memory_rw() below addresses and 3875 * sizes have to be in terms of multiples of 4 3876 * bytes. So, if the Configuration File isn't 3877 * a multiple of 4 bytes in length we'll have 3878 * to write that out separately since we can't 3879 * guarantee that the bytes following the 3880 * residual byte in the buffer returned by 3881 * request_firmware() are zeroed out ... 3882 */ 3883 size_t resid = cf->size & 0x3; 3884 size_t size = cf->size & ~0x3; 3885 __be32 *data = (__be32 *)cf->data; 3886 3887 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 3888 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 3889 3890 spin_lock(&adapter->win0_lock); 3891 ret = t4_memory_rw(adapter, 0, mtype, maddr, 3892 size, data, T4_MEMORY_WRITE); 3893 if (ret == 0 && resid != 0) { 3894 union { 3895 __be32 word; 3896 char buf[4]; 3897 } last; 3898 int i; 3899 3900 last.word = data[size >> 2]; 3901 for (i = resid; i < 4; i++) 3902 last.buf[i] = 0; 3903 ret = t4_memory_rw(adapter, 0, mtype, 3904 maddr + size, 3905 4, &last.word, 3906 T4_MEMORY_WRITE); 3907 } 3908 spin_unlock(&adapter->win0_lock); 3909 } 3910 } 3911 3912 release_firmware(cf); 3913 if (ret) 3914 goto bye; 3915 } 3916 3917 /* 3918 * Issue a Capability Configuration command to the firmware to get it 3919 * to parse the Configuration File. We don't use t4_fw_config_file() 3920 * because we want the ability to modify various features after we've 3921 * processed the configuration file ... 3922 */ 3923 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3924 caps_cmd.op_to_write = 3925 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3926 FW_CMD_REQUEST_F | 3927 FW_CMD_READ_F); 3928 caps_cmd.cfvalid_to_len16 = 3929 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 3930 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 3931 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 3932 FW_LEN16(caps_cmd)); 3933 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3934 &caps_cmd); 3935 3936 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 3937 * Configuration File in FLASH), our last gasp effort is to use the 3938 * Firmware Configuration File which is embedded in the firmware. A 3939 * very few early versions of the firmware didn't have one embedded 3940 * but we can ignore those. 3941 */ 3942 if (ret == -ENOENT) { 3943 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3944 caps_cmd.op_to_write = 3945 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3946 FW_CMD_REQUEST_F | 3947 FW_CMD_READ_F); 3948 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3949 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 3950 sizeof(caps_cmd), &caps_cmd); 3951 config_name = "Firmware Default"; 3952 } 3953 3954 config_issued = 1; 3955 if (ret < 0) 3956 goto bye; 3957 3958 finiver = ntohl(caps_cmd.finiver); 3959 finicsum = ntohl(caps_cmd.finicsum); 3960 cfcsum = ntohl(caps_cmd.cfcsum); 3961 if (finicsum != cfcsum) 3962 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 3963 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 3964 finicsum, cfcsum); 3965 3966 /* 3967 * And now tell the firmware to use the configuration we just loaded. 3968 */ 3969 caps_cmd.op_to_write = 3970 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3971 FW_CMD_REQUEST_F | 3972 FW_CMD_WRITE_F); 3973 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3974 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3975 NULL); 3976 if (ret < 0) 3977 goto bye; 3978 3979 /* 3980 * Tweak configuration based on system architecture, module 3981 * parameters, etc. 3982 */ 3983 ret = adap_init0_tweaks(adapter); 3984 if (ret < 0) 3985 goto bye; 3986 3987 /* We will proceed even if HMA init fails. */ 3988 ret = adap_config_hma(adapter); 3989 if (ret) 3990 dev_err(adapter->pdev_dev, 3991 "HMA configuration failed with error %d\n", ret); 3992 3993 /* 3994 * And finally tell the firmware to initialize itself using the 3995 * parameters from the Configuration File. 3996 */ 3997 ret = t4_fw_initialize(adapter, adapter->mbox); 3998 if (ret < 0) 3999 goto bye; 4000 4001 /* Emit Firmware Configuration File information and return 4002 * successfully. 4003 */ 4004 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 4005 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 4006 config_name, finiver, cfcsum); 4007 return 0; 4008 4009 /* 4010 * Something bad happened. Return the error ... (If the "error" 4011 * is that there's no Configuration File on the adapter we don't 4012 * want to issue a warning since this is fairly common.) 4013 */ 4014 bye: 4015 if (config_issued && ret != -ENOENT) 4016 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 4017 config_name, -ret); 4018 return ret; 4019 } 4020 4021 static struct fw_info fw_info_array[] = { 4022 { 4023 .chip = CHELSIO_T4, 4024 .fs_name = FW4_CFNAME, 4025 .fw_mod_name = FW4_FNAME, 4026 .fw_hdr = { 4027 .chip = FW_HDR_CHIP_T4, 4028 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 4029 .intfver_nic = FW_INTFVER(T4, NIC), 4030 .intfver_vnic = FW_INTFVER(T4, VNIC), 4031 .intfver_ri = FW_INTFVER(T4, RI), 4032 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4033 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4034 }, 4035 }, { 4036 .chip = CHELSIO_T5, 4037 .fs_name = FW5_CFNAME, 4038 .fw_mod_name = FW5_FNAME, 4039 .fw_hdr = { 4040 .chip = FW_HDR_CHIP_T5, 4041 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 4042 .intfver_nic = FW_INTFVER(T5, NIC), 4043 .intfver_vnic = FW_INTFVER(T5, VNIC), 4044 .intfver_ri = FW_INTFVER(T5, RI), 4045 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4046 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4047 }, 4048 }, { 4049 .chip = CHELSIO_T6, 4050 .fs_name = FW6_CFNAME, 4051 .fw_mod_name = FW6_FNAME, 4052 .fw_hdr = { 4053 .chip = FW_HDR_CHIP_T6, 4054 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 4055 .intfver_nic = FW_INTFVER(T6, NIC), 4056 .intfver_vnic = FW_INTFVER(T6, VNIC), 4057 .intfver_ofld = FW_INTFVER(T6, OFLD), 4058 .intfver_ri = FW_INTFVER(T6, RI), 4059 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4060 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4061 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4062 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4063 }, 4064 } 4065 4066 }; 4067 4068 static struct fw_info *find_fw_info(int chip) 4069 { 4070 int i; 4071 4072 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 4073 if (fw_info_array[i].chip == chip) 4074 return &fw_info_array[i]; 4075 } 4076 return NULL; 4077 } 4078 4079 /* 4080 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 4081 */ 4082 static int adap_init0(struct adapter *adap) 4083 { 4084 int ret; 4085 u32 v, port_vec; 4086 enum dev_state state; 4087 u32 params[7], val[7]; 4088 struct fw_caps_config_cmd caps_cmd; 4089 int reset = 1; 4090 4091 /* Grab Firmware Device Log parameters as early as possible so we have 4092 * access to it for debugging, etc. 4093 */ 4094 ret = t4_init_devlog_params(adap); 4095 if (ret < 0) 4096 return ret; 4097 4098 /* Contact FW, advertising Master capability */ 4099 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 4100 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 4101 if (ret < 0) { 4102 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 4103 ret); 4104 return ret; 4105 } 4106 if (ret == adap->mbox) 4107 adap->flags |= MASTER_PF; 4108 4109 /* 4110 * If we're the Master PF Driver and the device is uninitialized, 4111 * then let's consider upgrading the firmware ... (We always want 4112 * to check the firmware version number in order to A. get it for 4113 * later reporting and B. to warn if the currently loaded firmware 4114 * is excessively mismatched relative to the driver.) 4115 */ 4116 4117 t4_get_version_info(adap); 4118 ret = t4_check_fw_version(adap); 4119 /* If firmware is too old (not supported by driver) force an update. */ 4120 if (ret) 4121 state = DEV_STATE_UNINIT; 4122 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { 4123 struct fw_info *fw_info; 4124 struct fw_hdr *card_fw; 4125 const struct firmware *fw; 4126 const u8 *fw_data = NULL; 4127 unsigned int fw_size = 0; 4128 4129 /* This is the firmware whose headers the driver was compiled 4130 * against 4131 */ 4132 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 4133 if (fw_info == NULL) { 4134 dev_err(adap->pdev_dev, 4135 "unable to get firmware info for chip %d.\n", 4136 CHELSIO_CHIP_VERSION(adap->params.chip)); 4137 return -EINVAL; 4138 } 4139 4140 /* allocate memory to read the header of the firmware on the 4141 * card 4142 */ 4143 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 4144 if (!card_fw) { 4145 ret = -ENOMEM; 4146 goto bye; 4147 } 4148 4149 /* Get FW from from /lib/firmware/ */ 4150 ret = request_firmware(&fw, fw_info->fw_mod_name, 4151 adap->pdev_dev); 4152 if (ret < 0) { 4153 dev_err(adap->pdev_dev, 4154 "unable to load firmware image %s, error %d\n", 4155 fw_info->fw_mod_name, ret); 4156 } else { 4157 fw_data = fw->data; 4158 fw_size = fw->size; 4159 } 4160 4161 /* upgrade FW logic */ 4162 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 4163 state, &reset); 4164 4165 /* Cleaning up */ 4166 release_firmware(fw); 4167 kvfree(card_fw); 4168 4169 if (ret < 0) 4170 goto bye; 4171 } 4172 4173 /* 4174 * Grab VPD parameters. This should be done after we establish a 4175 * connection to the firmware since some of the VPD parameters 4176 * (notably the Core Clock frequency) are retrieved via requests to 4177 * the firmware. On the other hand, we need these fairly early on 4178 * so we do this right after getting ahold of the firmware. 4179 */ 4180 ret = t4_get_vpd_params(adap, &adap->params.vpd); 4181 if (ret < 0) 4182 goto bye; 4183 4184 /* 4185 * Find out what ports are available to us. Note that we need to do 4186 * this before calling adap_init0_no_config() since it needs nports 4187 * and portvec ... 4188 */ 4189 v = 4190 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4191 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 4192 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 4193 if (ret < 0) 4194 goto bye; 4195 4196 adap->params.nports = hweight32(port_vec); 4197 adap->params.portvec = port_vec; 4198 4199 /* If the firmware is initialized already, emit a simply note to that 4200 * effect. Otherwise, it's time to try initializing the adapter. 4201 */ 4202 if (state == DEV_STATE_INIT) { 4203 ret = adap_config_hma(adap); 4204 if (ret) 4205 dev_err(adap->pdev_dev, 4206 "HMA configuration failed with error %d\n", 4207 ret); 4208 dev_info(adap->pdev_dev, "Coming up as %s: "\ 4209 "Adapter already initialized\n", 4210 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 4211 } else { 4212 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 4213 "Initializing adapter\n"); 4214 4215 /* Find out whether we're dealing with a version of the 4216 * firmware which has configuration file support. 4217 */ 4218 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4219 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4220 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 4221 params, val); 4222 4223 /* If the firmware doesn't support Configuration Files, 4224 * return an error. 4225 */ 4226 if (ret < 0) { 4227 dev_err(adap->pdev_dev, "firmware doesn't support " 4228 "Firmware Configuration Files\n"); 4229 goto bye; 4230 } 4231 4232 /* The firmware provides us with a memory buffer where we can 4233 * load a Configuration File from the host if we want to 4234 * override the Configuration File in flash. 4235 */ 4236 ret = adap_init0_config(adap, reset); 4237 if (ret == -ENOENT) { 4238 dev_err(adap->pdev_dev, "no Configuration File " 4239 "present on adapter.\n"); 4240 goto bye; 4241 } 4242 if (ret < 0) { 4243 dev_err(adap->pdev_dev, "could not initialize " 4244 "adapter, error %d\n", -ret); 4245 goto bye; 4246 } 4247 } 4248 4249 /* Give the SGE code a chance to pull in anything that it needs ... 4250 * Note that this must be called after we retrieve our VPD parameters 4251 * in order to know how to convert core ticks to seconds, etc. 4252 */ 4253 ret = t4_sge_init(adap); 4254 if (ret < 0) 4255 goto bye; 4256 4257 if (is_bypass_device(adap->pdev->device)) 4258 adap->params.bypass = 1; 4259 4260 /* 4261 * Grab some of our basic fundamental operating parameters. 4262 */ 4263 #define FW_PARAM_DEV(param) \ 4264 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 4265 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 4266 4267 #define FW_PARAM_PFVF(param) \ 4268 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 4269 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 4270 FW_PARAMS_PARAM_Y_V(0) | \ 4271 FW_PARAMS_PARAM_Z_V(0) 4272 4273 params[0] = FW_PARAM_PFVF(EQ_START); 4274 params[1] = FW_PARAM_PFVF(L2T_START); 4275 params[2] = FW_PARAM_PFVF(L2T_END); 4276 params[3] = FW_PARAM_PFVF(FILTER_START); 4277 params[4] = FW_PARAM_PFVF(FILTER_END); 4278 params[5] = FW_PARAM_PFVF(IQFLINT_START); 4279 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 4280 if (ret < 0) 4281 goto bye; 4282 adap->sge.egr_start = val[0]; 4283 adap->l2t_start = val[1]; 4284 adap->l2t_end = val[2]; 4285 adap->tids.ftid_base = val[3]; 4286 adap->tids.nftids = val[4] - val[3] + 1; 4287 adap->sge.ingr_start = val[5]; 4288 4289 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 4290 /* Read the raw mps entries. In T6, the last 2 tcam entries 4291 * are reserved for raw mac addresses (rawf = 2, one per port). 4292 */ 4293 params[0] = FW_PARAM_PFVF(RAWF_START); 4294 params[1] = FW_PARAM_PFVF(RAWF_END); 4295 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4296 params, val); 4297 if (ret == 0) { 4298 adap->rawf_start = val[0]; 4299 adap->rawf_cnt = val[1] - val[0] + 1; 4300 } 4301 } 4302 4303 /* qids (ingress/egress) returned from firmware can be anywhere 4304 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 4305 * Hence driver needs to allocate memory for this range to 4306 * store the queue info. Get the highest IQFLINT/EQ index returned 4307 * in FW_EQ_*_CMD.alloc command. 4308 */ 4309 params[0] = FW_PARAM_PFVF(EQ_END); 4310 params[1] = FW_PARAM_PFVF(IQFLINT_END); 4311 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4312 if (ret < 0) 4313 goto bye; 4314 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 4315 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 4316 4317 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 4318 sizeof(*adap->sge.egr_map), GFP_KERNEL); 4319 if (!adap->sge.egr_map) { 4320 ret = -ENOMEM; 4321 goto bye; 4322 } 4323 4324 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 4325 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 4326 if (!adap->sge.ingr_map) { 4327 ret = -ENOMEM; 4328 goto bye; 4329 } 4330 4331 /* Allocate the memory for the vaious egress queue bitmaps 4332 * ie starving_fl, txq_maperr and blocked_fl. 4333 */ 4334 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4335 sizeof(long), GFP_KERNEL); 4336 if (!adap->sge.starving_fl) { 4337 ret = -ENOMEM; 4338 goto bye; 4339 } 4340 4341 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4342 sizeof(long), GFP_KERNEL); 4343 if (!adap->sge.txq_maperr) { 4344 ret = -ENOMEM; 4345 goto bye; 4346 } 4347 4348 #ifdef CONFIG_DEBUG_FS 4349 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4350 sizeof(long), GFP_KERNEL); 4351 if (!adap->sge.blocked_fl) { 4352 ret = -ENOMEM; 4353 goto bye; 4354 } 4355 #endif 4356 4357 params[0] = FW_PARAM_PFVF(CLIP_START); 4358 params[1] = FW_PARAM_PFVF(CLIP_END); 4359 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4360 if (ret < 0) 4361 goto bye; 4362 adap->clipt_start = val[0]; 4363 adap->clipt_end = val[1]; 4364 4365 /* We don't yet have a PARAMs calls to retrieve the number of Traffic 4366 * Classes supported by the hardware/firmware so we hard code it here 4367 * for now. 4368 */ 4369 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 4370 4371 /* query params related to active filter region */ 4372 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 4373 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 4374 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4375 /* If Active filter size is set we enable establishing 4376 * offload connection through firmware work request 4377 */ 4378 if ((val[0] != val[1]) && (ret >= 0)) { 4379 adap->flags |= FW_OFLD_CONN; 4380 adap->tids.aftid_base = val[0]; 4381 adap->tids.aftid_end = val[1]; 4382 } 4383 4384 /* If we're running on newer firmware, let it know that we're 4385 * prepared to deal with encapsulated CPL messages. Older 4386 * firmware won't understand this and we'll just get 4387 * unencapsulated messages ... 4388 */ 4389 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4390 val[0] = 1; 4391 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 4392 4393 /* 4394 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 4395 * capability. Earlier versions of the firmware didn't have the 4396 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 4397 * permission to use ULPTX MEMWRITE DSGL. 4398 */ 4399 if (is_t4(adap->params.chip)) { 4400 adap->params.ulptx_memwrite_dsgl = false; 4401 } else { 4402 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4403 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4404 1, params, val); 4405 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 4406 } 4407 4408 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 4409 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 4410 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4411 1, params, val); 4412 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 4413 4414 /* See if FW supports FW_FILTER2 work request */ 4415 if (is_t4(adap->params.chip)) { 4416 adap->params.filter2_wr_support = 0; 4417 } else { 4418 params[0] = FW_PARAM_DEV(FILTER2_WR); 4419 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4420 1, params, val); 4421 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 4422 } 4423 4424 /* 4425 * Get device capabilities so we can determine what resources we need 4426 * to manage. 4427 */ 4428 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4429 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4430 FW_CMD_REQUEST_F | FW_CMD_READ_F); 4431 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4432 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 4433 &caps_cmd); 4434 if (ret < 0) 4435 goto bye; 4436 4437 if (caps_cmd.ofldcaps || 4438 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) { 4439 /* query offload-related parameters */ 4440 params[0] = FW_PARAM_DEV(NTID); 4441 params[1] = FW_PARAM_PFVF(SERVER_START); 4442 params[2] = FW_PARAM_PFVF(SERVER_END); 4443 params[3] = FW_PARAM_PFVF(TDDP_START); 4444 params[4] = FW_PARAM_PFVF(TDDP_END); 4445 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4446 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4447 params, val); 4448 if (ret < 0) 4449 goto bye; 4450 adap->tids.ntids = val[0]; 4451 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 4452 adap->tids.stid_base = val[1]; 4453 adap->tids.nstids = val[2] - val[1] + 1; 4454 /* 4455 * Setup server filter region. Divide the available filter 4456 * region into two parts. Regular filters get 1/3rd and server 4457 * filters get 2/3rd part. This is only enabled if workarond 4458 * path is enabled. 4459 * 1. For regular filters. 4460 * 2. Server filter: This are special filters which are used 4461 * to redirect SYN packets to offload queue. 4462 */ 4463 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { 4464 adap->tids.sftid_base = adap->tids.ftid_base + 4465 DIV_ROUND_UP(adap->tids.nftids, 3); 4466 adap->tids.nsftids = adap->tids.nftids - 4467 DIV_ROUND_UP(adap->tids.nftids, 3); 4468 adap->tids.nftids = adap->tids.sftid_base - 4469 adap->tids.ftid_base; 4470 } 4471 adap->vres.ddp.start = val[3]; 4472 adap->vres.ddp.size = val[4] - val[3] + 1; 4473 adap->params.ofldq_wr_cred = val[5]; 4474 4475 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 4476 ret = init_hash_filter(adap); 4477 if (ret < 0) 4478 goto bye; 4479 } else { 4480 adap->params.offload = 1; 4481 adap->num_ofld_uld += 1; 4482 } 4483 } 4484 if (caps_cmd.rdmacaps) { 4485 params[0] = FW_PARAM_PFVF(STAG_START); 4486 params[1] = FW_PARAM_PFVF(STAG_END); 4487 params[2] = FW_PARAM_PFVF(RQ_START); 4488 params[3] = FW_PARAM_PFVF(RQ_END); 4489 params[4] = FW_PARAM_PFVF(PBL_START); 4490 params[5] = FW_PARAM_PFVF(PBL_END); 4491 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4492 params, val); 4493 if (ret < 0) 4494 goto bye; 4495 adap->vres.stag.start = val[0]; 4496 adap->vres.stag.size = val[1] - val[0] + 1; 4497 adap->vres.rq.start = val[2]; 4498 adap->vres.rq.size = val[3] - val[2] + 1; 4499 adap->vres.pbl.start = val[4]; 4500 adap->vres.pbl.size = val[5] - val[4] + 1; 4501 4502 params[0] = FW_PARAM_PFVF(SRQ_START); 4503 params[1] = FW_PARAM_PFVF(SRQ_END); 4504 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4505 params, val); 4506 if (!ret) { 4507 adap->vres.srq.start = val[0]; 4508 adap->vres.srq.size = val[1] - val[0] + 1; 4509 } 4510 if (adap->vres.srq.size) { 4511 adap->srq = t4_init_srq(adap->vres.srq.size); 4512 if (!adap->srq) 4513 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n"); 4514 } 4515 4516 params[0] = FW_PARAM_PFVF(SQRQ_START); 4517 params[1] = FW_PARAM_PFVF(SQRQ_END); 4518 params[2] = FW_PARAM_PFVF(CQ_START); 4519 params[3] = FW_PARAM_PFVF(CQ_END); 4520 params[4] = FW_PARAM_PFVF(OCQ_START); 4521 params[5] = FW_PARAM_PFVF(OCQ_END); 4522 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 4523 val); 4524 if (ret < 0) 4525 goto bye; 4526 adap->vres.qp.start = val[0]; 4527 adap->vres.qp.size = val[1] - val[0] + 1; 4528 adap->vres.cq.start = val[2]; 4529 adap->vres.cq.size = val[3] - val[2] + 1; 4530 adap->vres.ocq.start = val[4]; 4531 adap->vres.ocq.size = val[5] - val[4] + 1; 4532 4533 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4534 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4535 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4536 val); 4537 if (ret < 0) { 4538 adap->params.max_ordird_qp = 8; 4539 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4540 ret = 0; 4541 } else { 4542 adap->params.max_ordird_qp = val[0]; 4543 adap->params.max_ird_adapter = val[1]; 4544 } 4545 dev_info(adap->pdev_dev, 4546 "max_ordird_qp %d max_ird_adapter %d\n", 4547 adap->params.max_ordird_qp, 4548 adap->params.max_ird_adapter); 4549 4550 /* Enable write_with_immediate if FW supports it */ 4551 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM); 4552 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4553 val); 4554 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); 4555 4556 /* Enable write_cmpl if FW supports it */ 4557 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR); 4558 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4559 val); 4560 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); 4561 adap->num_ofld_uld += 2; 4562 } 4563 if (caps_cmd.iscsicaps) { 4564 params[0] = FW_PARAM_PFVF(ISCSI_START); 4565 params[1] = FW_PARAM_PFVF(ISCSI_END); 4566 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4567 params, val); 4568 if (ret < 0) 4569 goto bye; 4570 adap->vres.iscsi.start = val[0]; 4571 adap->vres.iscsi.size = val[1] - val[0] + 1; 4572 /* LIO target and cxgb4i initiaitor */ 4573 adap->num_ofld_uld += 2; 4574 } 4575 if (caps_cmd.cryptocaps) { 4576 if (ntohs(caps_cmd.cryptocaps) & 4577 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) { 4578 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 4579 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4580 2, params, val); 4581 if (ret < 0) { 4582 if (ret != -EINVAL) 4583 goto bye; 4584 } else { 4585 adap->vres.ncrypto_fc = val[0]; 4586 } 4587 adap->num_ofld_uld += 1; 4588 } 4589 if (ntohs(caps_cmd.cryptocaps) & 4590 FW_CAPS_CONFIG_TLS_INLINE) { 4591 params[0] = FW_PARAM_PFVF(TLS_START); 4592 params[1] = FW_PARAM_PFVF(TLS_END); 4593 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4594 2, params, val); 4595 if (ret < 0) 4596 goto bye; 4597 adap->vres.key.start = val[0]; 4598 adap->vres.key.size = val[1] - val[0] + 1; 4599 adap->num_uld += 1; 4600 } 4601 adap->params.crypto = ntohs(caps_cmd.cryptocaps); 4602 } 4603 #undef FW_PARAM_PFVF 4604 #undef FW_PARAM_DEV 4605 4606 /* The MTU/MSS Table is initialized by now, so load their values. If 4607 * we're initializing the adapter, then we'll make any modifications 4608 * we want to the MTU/MSS Table and also initialize the congestion 4609 * parameters. 4610 */ 4611 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4612 if (state != DEV_STATE_INIT) { 4613 int i; 4614 4615 /* The default MTU Table contains values 1492 and 1500. 4616 * However, for TCP, it's better to have two values which are 4617 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4618 * This allows us to have a TCP Data Payload which is a 4619 * multiple of 8 regardless of what combination of TCP Options 4620 * are in use (always a multiple of 4 bytes) which is 4621 * important for performance reasons. For instance, if no 4622 * options are in use, then we have a 20-byte IP header and a 4623 * 20-byte TCP header. In this case, a 1500-byte MSS would 4624 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4625 * which is not a multiple of 8. So using an MSS of 1488 in 4626 * this case results in a TCP Data Payload of 1448 bytes which 4627 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4628 * Stamps have been negotiated, then an MTU of 1500 bytes 4629 * results in a TCP Data Payload of 1448 bytes which, as 4630 * above, is a multiple of 8 bytes ... 4631 */ 4632 for (i = 0; i < NMTUS; i++) 4633 if (adap->params.mtus[i] == 1492) { 4634 adap->params.mtus[i] = 1488; 4635 break; 4636 } 4637 4638 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4639 adap->params.b_wnd); 4640 } 4641 t4_init_sge_params(adap); 4642 adap->flags |= FW_OK; 4643 t4_init_tp_params(adap, true); 4644 return 0; 4645 4646 /* 4647 * Something bad happened. If a command timed out or failed with EIO 4648 * FW does not operate within its spec or something catastrophic 4649 * happened to HW/FW, stop issuing commands. 4650 */ 4651 bye: 4652 adap_free_hma_mem(adap); 4653 kfree(adap->sge.egr_map); 4654 kfree(adap->sge.ingr_map); 4655 kfree(adap->sge.starving_fl); 4656 kfree(adap->sge.txq_maperr); 4657 #ifdef CONFIG_DEBUG_FS 4658 kfree(adap->sge.blocked_fl); 4659 #endif 4660 if (ret != -ETIMEDOUT && ret != -EIO) 4661 t4_fw_bye(adap, adap->mbox); 4662 return ret; 4663 } 4664 4665 /* EEH callbacks */ 4666 4667 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4668 pci_channel_state_t state) 4669 { 4670 int i; 4671 struct adapter *adap = pci_get_drvdata(pdev); 4672 4673 if (!adap) 4674 goto out; 4675 4676 rtnl_lock(); 4677 adap->flags &= ~FW_OK; 4678 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4679 spin_lock(&adap->stats_lock); 4680 for_each_port(adap, i) { 4681 struct net_device *dev = adap->port[i]; 4682 if (dev) { 4683 netif_device_detach(dev); 4684 netif_carrier_off(dev); 4685 } 4686 } 4687 spin_unlock(&adap->stats_lock); 4688 disable_interrupts(adap); 4689 if (adap->flags & FULL_INIT_DONE) 4690 cxgb_down(adap); 4691 rtnl_unlock(); 4692 if ((adap->flags & DEV_ENABLED)) { 4693 pci_disable_device(pdev); 4694 adap->flags &= ~DEV_ENABLED; 4695 } 4696 out: return state == pci_channel_io_perm_failure ? 4697 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4698 } 4699 4700 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4701 { 4702 int i, ret; 4703 struct fw_caps_config_cmd c; 4704 struct adapter *adap = pci_get_drvdata(pdev); 4705 4706 if (!adap) { 4707 pci_restore_state(pdev); 4708 pci_save_state(pdev); 4709 return PCI_ERS_RESULT_RECOVERED; 4710 } 4711 4712 if (!(adap->flags & DEV_ENABLED)) { 4713 if (pci_enable_device(pdev)) { 4714 dev_err(&pdev->dev, "Cannot reenable PCI " 4715 "device after reset\n"); 4716 return PCI_ERS_RESULT_DISCONNECT; 4717 } 4718 adap->flags |= DEV_ENABLED; 4719 } 4720 4721 pci_set_master(pdev); 4722 pci_restore_state(pdev); 4723 pci_save_state(pdev); 4724 pci_cleanup_aer_uncorrect_error_status(pdev); 4725 4726 if (t4_wait_dev_ready(adap->regs) < 0) 4727 return PCI_ERS_RESULT_DISCONNECT; 4728 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 4729 return PCI_ERS_RESULT_DISCONNECT; 4730 adap->flags |= FW_OK; 4731 if (adap_init1(adap, &c)) 4732 return PCI_ERS_RESULT_DISCONNECT; 4733 4734 for_each_port(adap, i) { 4735 struct port_info *p = adap2pinfo(adap, i); 4736 4737 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, 4738 NULL, NULL); 4739 if (ret < 0) 4740 return PCI_ERS_RESULT_DISCONNECT; 4741 p->viid = ret; 4742 p->xact_addr_filt = -1; 4743 } 4744 4745 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4746 adap->params.b_wnd); 4747 setup_memwin(adap); 4748 if (cxgb_up(adap)) 4749 return PCI_ERS_RESULT_DISCONNECT; 4750 return PCI_ERS_RESULT_RECOVERED; 4751 } 4752 4753 static void eeh_resume(struct pci_dev *pdev) 4754 { 4755 int i; 4756 struct adapter *adap = pci_get_drvdata(pdev); 4757 4758 if (!adap) 4759 return; 4760 4761 rtnl_lock(); 4762 for_each_port(adap, i) { 4763 struct net_device *dev = adap->port[i]; 4764 if (dev) { 4765 if (netif_running(dev)) { 4766 link_start(dev); 4767 cxgb_set_rxmode(dev); 4768 } 4769 netif_device_attach(dev); 4770 } 4771 } 4772 rtnl_unlock(); 4773 } 4774 4775 static const struct pci_error_handlers cxgb4_eeh = { 4776 .error_detected = eeh_err_detected, 4777 .slot_reset = eeh_slot_reset, 4778 .resume = eeh_resume, 4779 }; 4780 4781 /* Return true if the Link Configuration supports "High Speeds" (those greater 4782 * than 1Gb/s). 4783 */ 4784 static inline bool is_x_10g_port(const struct link_config *lc) 4785 { 4786 unsigned int speeds, high_speeds; 4787 4788 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 4789 high_speeds = speeds & 4790 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 4791 4792 return high_speeds != 0; 4793 } 4794 4795 /* 4796 * Perform default configuration of DMA queues depending on the number and type 4797 * of ports we found and the number of available CPUs. Most settings can be 4798 * modified by the admin prior to actual use. 4799 */ 4800 static void cfg_queues(struct adapter *adap) 4801 { 4802 struct sge *s = &adap->sge; 4803 int i = 0, n10g = 0, qidx = 0; 4804 #ifndef CONFIG_CHELSIO_T4_DCB 4805 int q10g = 0; 4806 #endif 4807 4808 /* Reduce memory usage in kdump environment, disable all offload. 4809 */ 4810 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 4811 adap->params.offload = 0; 4812 adap->params.crypto = 0; 4813 } 4814 4815 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 4816 #ifdef CONFIG_CHELSIO_T4_DCB 4817 /* For Data Center Bridging support we need to be able to support up 4818 * to 8 Traffic Priorities; each of which will be assigned to its 4819 * own TX Queue in order to prevent Head-Of-Line Blocking. 4820 */ 4821 if (adap->params.nports * 8 > MAX_ETH_QSETS) { 4822 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", 4823 MAX_ETH_QSETS, adap->params.nports * 8); 4824 BUG_ON(1); 4825 } 4826 4827 for_each_port(adap, i) { 4828 struct port_info *pi = adap2pinfo(adap, i); 4829 4830 pi->first_qset = qidx; 4831 pi->nqsets = is_kdump_kernel() ? 1 : 8; 4832 qidx += pi->nqsets; 4833 } 4834 #else /* !CONFIG_CHELSIO_T4_DCB */ 4835 /* 4836 * We default to 1 queue per non-10G port and up to # of cores queues 4837 * per 10G port. 4838 */ 4839 if (n10g) 4840 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; 4841 if (q10g > netif_get_num_default_rss_queues()) 4842 q10g = netif_get_num_default_rss_queues(); 4843 4844 if (is_kdump_kernel()) 4845 q10g = 1; 4846 4847 for_each_port(adap, i) { 4848 struct port_info *pi = adap2pinfo(adap, i); 4849 4850 pi->first_qset = qidx; 4851 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 4852 qidx += pi->nqsets; 4853 } 4854 #endif /* !CONFIG_CHELSIO_T4_DCB */ 4855 4856 s->ethqsets = qidx; 4857 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 4858 4859 if (is_uld(adap)) { 4860 /* 4861 * For offload we use 1 queue/channel if all ports are up to 1G, 4862 * otherwise we divide all available queues amongst the channels 4863 * capped by the number of available cores. 4864 */ 4865 if (n10g) { 4866 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); 4867 s->ofldqsets = roundup(i, adap->params.nports); 4868 } else { 4869 s->ofldqsets = adap->params.nports; 4870 } 4871 } 4872 4873 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 4874 struct sge_eth_rxq *r = &s->ethrxq[i]; 4875 4876 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 4877 r->fl.size = 72; 4878 } 4879 4880 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 4881 s->ethtxq[i].q.size = 1024; 4882 4883 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 4884 s->ctrlq[i].q.size = 512; 4885 4886 if (!is_t4(adap->params.chip)) 4887 s->ptptxq.q.size = 8; 4888 4889 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 4890 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 4891 } 4892 4893 /* 4894 * Reduce the number of Ethernet queues across all ports to at most n. 4895 * n provides at least one queue per port. 4896 */ 4897 static void reduce_ethqs(struct adapter *adap, int n) 4898 { 4899 int i; 4900 struct port_info *pi; 4901 4902 while (n < adap->sge.ethqsets) 4903 for_each_port(adap, i) { 4904 pi = adap2pinfo(adap, i); 4905 if (pi->nqsets > 1) { 4906 pi->nqsets--; 4907 adap->sge.ethqsets--; 4908 if (adap->sge.ethqsets <= n) 4909 break; 4910 } 4911 } 4912 4913 n = 0; 4914 for_each_port(adap, i) { 4915 pi = adap2pinfo(adap, i); 4916 pi->first_qset = n; 4917 n += pi->nqsets; 4918 } 4919 } 4920 4921 static int get_msix_info(struct adapter *adap) 4922 { 4923 struct uld_msix_info *msix_info; 4924 unsigned int max_ingq = 0; 4925 4926 if (is_offload(adap)) 4927 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; 4928 if (is_pci_uld(adap)) 4929 max_ingq += MAX_OFLD_QSETS * adap->num_uld; 4930 4931 if (!max_ingq) 4932 goto out; 4933 4934 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); 4935 if (!msix_info) 4936 return -ENOMEM; 4937 4938 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), 4939 sizeof(long), GFP_KERNEL); 4940 if (!adap->msix_bmap_ulds.msix_bmap) { 4941 kfree(msix_info); 4942 return -ENOMEM; 4943 } 4944 spin_lock_init(&adap->msix_bmap_ulds.lock); 4945 adap->msix_info_ulds = msix_info; 4946 out: 4947 return 0; 4948 } 4949 4950 static void free_msix_info(struct adapter *adap) 4951 { 4952 if (!(adap->num_uld && adap->num_ofld_uld)) 4953 return; 4954 4955 kfree(adap->msix_info_ulds); 4956 kfree(adap->msix_bmap_ulds.msix_bmap); 4957 } 4958 4959 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 4960 #define EXTRA_VECS 2 4961 4962 static int enable_msix(struct adapter *adap) 4963 { 4964 int ofld_need = 0, uld_need = 0; 4965 int i, j, want, need, allocated; 4966 struct sge *s = &adap->sge; 4967 unsigned int nchan = adap->params.nports; 4968 struct msix_entry *entries; 4969 int max_ingq = MAX_INGQ; 4970 4971 if (is_pci_uld(adap)) 4972 max_ingq += (MAX_OFLD_QSETS * adap->num_uld); 4973 if (is_offload(adap)) 4974 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); 4975 entries = kmalloc_array(max_ingq + 1, sizeof(*entries), 4976 GFP_KERNEL); 4977 if (!entries) 4978 return -ENOMEM; 4979 4980 /* map for msix */ 4981 if (get_msix_info(adap)) { 4982 adap->params.offload = 0; 4983 adap->params.crypto = 0; 4984 } 4985 4986 for (i = 0; i < max_ingq + 1; ++i) 4987 entries[i].entry = i; 4988 4989 want = s->max_ethqsets + EXTRA_VECS; 4990 if (is_offload(adap)) { 4991 want += adap->num_ofld_uld * s->ofldqsets; 4992 ofld_need = adap->num_ofld_uld * nchan; 4993 } 4994 if (is_pci_uld(adap)) { 4995 want += adap->num_uld * s->ofldqsets; 4996 uld_need = adap->num_uld * nchan; 4997 } 4998 #ifdef CONFIG_CHELSIO_T4_DCB 4999 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 5000 * each port. 5001 */ 5002 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 5003 #else 5004 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 5005 #endif 5006 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 5007 if (allocated < 0) { 5008 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 5009 " not using MSI-X\n"); 5010 kfree(entries); 5011 return allocated; 5012 } 5013 5014 /* Distribute available vectors to the various queue groups. 5015 * Every group gets its minimum requirement and NIC gets top 5016 * priority for leftovers. 5017 */ 5018 i = allocated - EXTRA_VECS - ofld_need - uld_need; 5019 if (i < s->max_ethqsets) { 5020 s->max_ethqsets = i; 5021 if (i < s->ethqsets) 5022 reduce_ethqs(adap, i); 5023 } 5024 if (is_uld(adap)) { 5025 if (allocated < want) 5026 s->nqs_per_uld = nchan; 5027 else 5028 s->nqs_per_uld = s->ofldqsets; 5029 } 5030 5031 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) 5032 adap->msix_info[i].vec = entries[i].vector; 5033 if (is_uld(adap)) { 5034 for (j = 0 ; i < allocated; ++i, j++) { 5035 adap->msix_info_ulds[j].vec = entries[i].vector; 5036 adap->msix_info_ulds[j].idx = i; 5037 } 5038 adap->msix_bmap_ulds.mapsize = j; 5039 } 5040 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " 5041 "nic %d per uld %d\n", 5042 allocated, s->max_ethqsets, s->nqs_per_uld); 5043 5044 kfree(entries); 5045 return 0; 5046 } 5047 5048 #undef EXTRA_VECS 5049 5050 static int init_rss(struct adapter *adap) 5051 { 5052 unsigned int i; 5053 int err; 5054 5055 err = t4_init_rss_mode(adap, adap->mbox); 5056 if (err) 5057 return err; 5058 5059 for_each_port(adap, i) { 5060 struct port_info *pi = adap2pinfo(adap, i); 5061 5062 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 5063 if (!pi->rss) 5064 return -ENOMEM; 5065 } 5066 return 0; 5067 } 5068 5069 /* Dump basic information about the adapter */ 5070 static void print_adapter_info(struct adapter *adapter) 5071 { 5072 /* Hardware/Firmware/etc. Version/Revision IDs */ 5073 t4_dump_version_info(adapter); 5074 5075 /* Software/Hardware configuration */ 5076 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 5077 is_offload(adapter) ? "R" : "", 5078 ((adapter->flags & USING_MSIX) ? "MSI-X" : 5079 (adapter->flags & USING_MSI) ? "MSI" : ""), 5080 is_offload(adapter) ? "Offload" : "non-Offload"); 5081 } 5082 5083 static void print_port_info(const struct net_device *dev) 5084 { 5085 char buf[80]; 5086 char *bufp = buf; 5087 const char *spd = ""; 5088 const struct port_info *pi = netdev_priv(dev); 5089 const struct adapter *adap = pi->adapter; 5090 5091 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) 5092 spd = " 2.5 GT/s"; 5093 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) 5094 spd = " 5 GT/s"; 5095 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) 5096 spd = " 8 GT/s"; 5097 5098 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 5099 bufp += sprintf(bufp, "100M/"); 5100 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 5101 bufp += sprintf(bufp, "1G/"); 5102 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 5103 bufp += sprintf(bufp, "10G/"); 5104 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 5105 bufp += sprintf(bufp, "25G/"); 5106 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 5107 bufp += sprintf(bufp, "40G/"); 5108 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 5109 bufp += sprintf(bufp, "50G/"); 5110 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 5111 bufp += sprintf(bufp, "100G/"); 5112 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 5113 bufp += sprintf(bufp, "200G/"); 5114 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 5115 bufp += sprintf(bufp, "400G/"); 5116 if (bufp != buf) 5117 --bufp; 5118 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 5119 5120 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 5121 dev->name, adap->params.vpd.id, adap->name, buf); 5122 } 5123 5124 /* 5125 * Free the following resources: 5126 * - memory used for tables 5127 * - MSI/MSI-X 5128 * - net devices 5129 * - resources FW is holding for us 5130 */ 5131 static void free_some_resources(struct adapter *adapter) 5132 { 5133 unsigned int i; 5134 5135 kvfree(adapter->mps_encap); 5136 kvfree(adapter->smt); 5137 kvfree(adapter->l2t); 5138 kvfree(adapter->srq); 5139 t4_cleanup_sched(adapter); 5140 kvfree(adapter->tids.tid_tab); 5141 cxgb4_cleanup_tc_flower(adapter); 5142 cxgb4_cleanup_tc_u32(adapter); 5143 kfree(adapter->sge.egr_map); 5144 kfree(adapter->sge.ingr_map); 5145 kfree(adapter->sge.starving_fl); 5146 kfree(adapter->sge.txq_maperr); 5147 #ifdef CONFIG_DEBUG_FS 5148 kfree(adapter->sge.blocked_fl); 5149 #endif 5150 disable_msi(adapter); 5151 5152 for_each_port(adapter, i) 5153 if (adapter->port[i]) { 5154 struct port_info *pi = adap2pinfo(adapter, i); 5155 5156 if (pi->viid != 0) 5157 t4_free_vi(adapter, adapter->mbox, adapter->pf, 5158 0, pi->viid); 5159 kfree(adap2pinfo(adapter, i)->rss); 5160 free_netdev(adapter->port[i]); 5161 } 5162 if (adapter->flags & FW_OK) 5163 t4_fw_bye(adapter, adapter->pf); 5164 } 5165 5166 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 5167 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 5168 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 5169 #define SEGMENT_SIZE 128 5170 5171 static int t4_get_chip_type(struct adapter *adap, int ver) 5172 { 5173 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A)); 5174 5175 switch (ver) { 5176 case CHELSIO_T4: 5177 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 5178 case CHELSIO_T5: 5179 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 5180 case CHELSIO_T6: 5181 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 5182 default: 5183 break; 5184 } 5185 return -EINVAL; 5186 } 5187 5188 #ifdef CONFIG_PCI_IOV 5189 static void cxgb4_mgmt_setup(struct net_device *dev) 5190 { 5191 dev->type = ARPHRD_NONE; 5192 dev->mtu = 0; 5193 dev->hard_header_len = 0; 5194 dev->addr_len = 0; 5195 dev->tx_queue_len = 0; 5196 dev->flags |= IFF_NOARP; 5197 dev->priv_flags |= IFF_NO_QUEUE; 5198 5199 /* Initialize the device structure. */ 5200 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 5201 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 5202 } 5203 5204 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 5205 { 5206 struct adapter *adap = pci_get_drvdata(pdev); 5207 int err = 0; 5208 int current_vfs = pci_num_vf(pdev); 5209 u32 pcie_fw; 5210 5211 pcie_fw = readl(adap->regs + PCIE_FW_A); 5212 /* Check if fw is initialized */ 5213 if (!(pcie_fw & PCIE_FW_INIT_F)) { 5214 dev_warn(&pdev->dev, "Device not initialized\n"); 5215 return -EOPNOTSUPP; 5216 } 5217 5218 /* If any of the VF's is already assigned to Guest OS, then 5219 * SRIOV for the same cannot be modified 5220 */ 5221 if (current_vfs && pci_vfs_assigned(pdev)) { 5222 dev_err(&pdev->dev, 5223 "Cannot modify SR-IOV while VFs are assigned\n"); 5224 return current_vfs; 5225 } 5226 /* Note that the upper-level code ensures that we're never called with 5227 * a non-zero "num_vfs" when we already have VFs instantiated. But 5228 * it never hurts to code defensively. 5229 */ 5230 if (num_vfs != 0 && current_vfs != 0) 5231 return -EBUSY; 5232 5233 /* Nothing to do for no change. */ 5234 if (num_vfs == current_vfs) 5235 return num_vfs; 5236 5237 /* Disable SRIOV when zero is passed. */ 5238 if (!num_vfs) { 5239 pci_disable_sriov(pdev); 5240 /* free VF Management Interface */ 5241 unregister_netdev(adap->port[0]); 5242 free_netdev(adap->port[0]); 5243 adap->port[0] = NULL; 5244 5245 /* free VF resources */ 5246 adap->num_vfs = 0; 5247 kfree(adap->vfinfo); 5248 adap->vfinfo = NULL; 5249 return 0; 5250 } 5251 5252 if (!current_vfs) { 5253 struct fw_pfvf_cmd port_cmd, port_rpl; 5254 struct net_device *netdev; 5255 unsigned int pmask, port; 5256 struct pci_dev *pbridge; 5257 struct port_info *pi; 5258 char name[IFNAMSIZ]; 5259 u32 devcap2; 5260 u16 flags; 5261 int pos; 5262 5263 /* If we want to instantiate Virtual Functions, then our 5264 * parent bridge's PCI-E needs to support Alternative Routing 5265 * ID (ARI) because our VFs will show up at function offset 8 5266 * and above. 5267 */ 5268 pbridge = pdev->bus->self; 5269 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP); 5270 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags); 5271 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2); 5272 5273 if ((flags & PCI_EXP_FLAGS_VERS) < 2 || 5274 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) { 5275 /* Our parent bridge does not support ARI so issue a 5276 * warning and skip instantiating the VFs. They 5277 * won't be reachable. 5278 */ 5279 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n", 5280 pbridge->bus->number, PCI_SLOT(pbridge->devfn), 5281 PCI_FUNC(pbridge->devfn)); 5282 return -ENOTSUPP; 5283 } 5284 memset(&port_cmd, 0, sizeof(port_cmd)); 5285 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | 5286 FW_CMD_REQUEST_F | 5287 FW_CMD_READ_F | 5288 FW_PFVF_CMD_PFN_V(adap->pf) | 5289 FW_PFVF_CMD_VFN_V(0)); 5290 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd)); 5291 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), 5292 &port_rpl); 5293 if (err) 5294 return err; 5295 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq)); 5296 port = ffs(pmask) - 1; 5297 /* Allocate VF Management Interface. */ 5298 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx, 5299 adap->pf); 5300 netdev = alloc_netdev(sizeof(struct port_info), 5301 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup); 5302 if (!netdev) 5303 return -ENOMEM; 5304 5305 pi = netdev_priv(netdev); 5306 pi->adapter = adap; 5307 pi->lport = port; 5308 pi->tx_chan = port; 5309 SET_NETDEV_DEV(netdev, &pdev->dev); 5310 5311 adap->port[0] = netdev; 5312 pi->port_id = 0; 5313 5314 err = register_netdev(adap->port[0]); 5315 if (err) { 5316 pr_info("Unable to register VF mgmt netdev %s\n", name); 5317 free_netdev(adap->port[0]); 5318 adap->port[0] = NULL; 5319 return err; 5320 } 5321 /* Allocate and set up VF Information. */ 5322 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev), 5323 sizeof(struct vf_info), GFP_KERNEL); 5324 if (!adap->vfinfo) { 5325 unregister_netdev(adap->port[0]); 5326 free_netdev(adap->port[0]); 5327 adap->port[0] = NULL; 5328 return -ENOMEM; 5329 } 5330 cxgb4_mgmt_fill_vf_station_mac_addr(adap); 5331 } 5332 /* Instantiate the requested number of VFs. */ 5333 err = pci_enable_sriov(pdev, num_vfs); 5334 if (err) { 5335 pr_info("Unable to instantiate %d VFs\n", num_vfs); 5336 if (!current_vfs) { 5337 unregister_netdev(adap->port[0]); 5338 free_netdev(adap->port[0]); 5339 adap->port[0] = NULL; 5340 kfree(adap->vfinfo); 5341 adap->vfinfo = NULL; 5342 } 5343 return err; 5344 } 5345 5346 adap->num_vfs = num_vfs; 5347 return num_vfs; 5348 } 5349 #endif /* CONFIG_PCI_IOV */ 5350 5351 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5352 { 5353 struct net_device *netdev; 5354 struct adapter *adapter; 5355 static int adap_idx = 1; 5356 int s_qpp, qpp, num_seg; 5357 struct port_info *pi; 5358 bool highdma = false; 5359 enum chip_type chip; 5360 void __iomem *regs; 5361 int func, chip_ver; 5362 u16 device_id; 5363 int i, err; 5364 u32 whoami; 5365 5366 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 5367 5368 err = pci_request_regions(pdev, KBUILD_MODNAME); 5369 if (err) { 5370 /* Just info, some other driver may have claimed the device. */ 5371 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 5372 return err; 5373 } 5374 5375 err = pci_enable_device(pdev); 5376 if (err) { 5377 dev_err(&pdev->dev, "cannot enable PCI device\n"); 5378 goto out_release_regions; 5379 } 5380 5381 regs = pci_ioremap_bar(pdev, 0); 5382 if (!regs) { 5383 dev_err(&pdev->dev, "cannot map device registers\n"); 5384 err = -ENOMEM; 5385 goto out_disable_device; 5386 } 5387 5388 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 5389 if (!adapter) { 5390 err = -ENOMEM; 5391 goto out_unmap_bar0; 5392 } 5393 5394 adapter->regs = regs; 5395 err = t4_wait_dev_ready(regs); 5396 if (err < 0) 5397 goto out_free_adapter; 5398 5399 /* We control everything through one PF */ 5400 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 5401 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 5402 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id)); 5403 if (chip < 0) { 5404 dev_err(&pdev->dev, "Device %d is not supported\n", device_id); 5405 err = chip; 5406 goto out_free_adapter; 5407 } 5408 chip_ver = CHELSIO_CHIP_VERSION(chip); 5409 func = chip_ver <= CHELSIO_T5 ? 5410 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 5411 5412 adapter->pdev = pdev; 5413 adapter->pdev_dev = &pdev->dev; 5414 adapter->name = pci_name(pdev); 5415 adapter->mbox = func; 5416 adapter->pf = func; 5417 adapter->params.chip = chip; 5418 adapter->adap_idx = adap_idx; 5419 adapter->msg_enable = DFLT_MSG_ENABLE; 5420 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 5421 (sizeof(struct mbox_cmd) * 5422 T4_OS_LOG_MBOX_CMDS), 5423 GFP_KERNEL); 5424 if (!adapter->mbox_log) { 5425 err = -ENOMEM; 5426 goto out_free_adapter; 5427 } 5428 spin_lock_init(&adapter->mbox_lock); 5429 INIT_LIST_HEAD(&adapter->mlist.list); 5430 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 5431 pci_set_drvdata(pdev, adapter); 5432 5433 if (func != ent->driver_data) { 5434 pci_disable_device(pdev); 5435 pci_save_state(pdev); /* to restore SR-IOV later */ 5436 return 0; 5437 } 5438 5439 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 5440 highdma = true; 5441 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 5442 if (err) { 5443 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 5444 "coherent allocations\n"); 5445 goto out_free_adapter; 5446 } 5447 } else { 5448 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 5449 if (err) { 5450 dev_err(&pdev->dev, "no usable DMA configuration\n"); 5451 goto out_free_adapter; 5452 } 5453 } 5454 5455 pci_enable_pcie_error_reporting(pdev); 5456 pci_set_master(pdev); 5457 pci_save_state(pdev); 5458 adap_idx++; 5459 adapter->workq = create_singlethread_workqueue("cxgb4"); 5460 if (!adapter->workq) { 5461 err = -ENOMEM; 5462 goto out_free_adapter; 5463 } 5464 5465 /* PCI device has been enabled */ 5466 adapter->flags |= DEV_ENABLED; 5467 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 5468 5469 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 5470 * Ingress Packet Data to Free List Buffers in order to allow for 5471 * chipset performance optimizations between the Root Complex and 5472 * Memory Controllers. (Messages to the associated Ingress Queue 5473 * notifying new Packet Placement in the Free Lists Buffers will be 5474 * send without the Relaxed Ordering Attribute thus guaranteeing that 5475 * all preceding PCIe Transaction Layer Packets will be processed 5476 * first.) But some Root Complexes have various issues with Upstream 5477 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 5478 * The PCIe devices which under the Root Complexes will be cleared the 5479 * Relaxed Ordering bit in the configuration space, So we check our 5480 * PCIe configuration space to see if it's flagged with advice against 5481 * using Relaxed Ordering. 5482 */ 5483 if (!pcie_relaxed_ordering_enabled(pdev)) 5484 adapter->flags |= ROOT_NO_RELAXED_ORDERING; 5485 5486 spin_lock_init(&adapter->stats_lock); 5487 spin_lock_init(&adapter->tid_release_lock); 5488 spin_lock_init(&adapter->win0_lock); 5489 5490 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 5491 INIT_WORK(&adapter->db_full_task, process_db_full); 5492 INIT_WORK(&adapter->db_drop_task, process_db_drop); 5493 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err); 5494 5495 err = t4_prep_adapter(adapter); 5496 if (err) 5497 goto out_free_adapter; 5498 5499 if (is_kdump_kernel()) { 5500 /* Collect hardware state and append to /proc/vmcore */ 5501 err = cxgb4_cudbg_vmcore_add_dump(adapter); 5502 if (err) { 5503 dev_warn(adapter->pdev_dev, 5504 "Fail collecting vmcore device dump, err: %d. Continuing\n", 5505 err); 5506 err = 0; 5507 } 5508 } 5509 5510 if (!is_t4(adapter->params.chip)) { 5511 s_qpp = (QUEUESPERPAGEPF0_S + 5512 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 5513 adapter->pf); 5514 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 5515 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 5516 num_seg = PAGE_SIZE / SEGMENT_SIZE; 5517 5518 /* Each segment size is 128B. Write coalescing is enabled only 5519 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 5520 * queue is less no of segments that can be accommodated in 5521 * a page size. 5522 */ 5523 if (qpp > num_seg) { 5524 dev_err(&pdev->dev, 5525 "Incorrect number of egress queues per page\n"); 5526 err = -EINVAL; 5527 goto out_free_adapter; 5528 } 5529 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 5530 pci_resource_len(pdev, 2)); 5531 if (!adapter->bar2) { 5532 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 5533 err = -ENOMEM; 5534 goto out_free_adapter; 5535 } 5536 } 5537 5538 setup_memwin(adapter); 5539 err = adap_init0(adapter); 5540 #ifdef CONFIG_DEBUG_FS 5541 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 5542 #endif 5543 setup_memwin_rdma(adapter); 5544 if (err) 5545 goto out_unmap_bar; 5546 5547 /* configure SGE_STAT_CFG_A to read WC stats */ 5548 if (!is_t4(adapter->params.chip)) 5549 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 5550 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 5551 T6_STATMODE_V(0))); 5552 5553 for_each_port(adapter, i) { 5554 netdev = alloc_etherdev_mq(sizeof(struct port_info), 5555 MAX_ETH_QSETS); 5556 if (!netdev) { 5557 err = -ENOMEM; 5558 goto out_free_dev; 5559 } 5560 5561 SET_NETDEV_DEV(netdev, &pdev->dev); 5562 5563 adapter->port[i] = netdev; 5564 pi = netdev_priv(netdev); 5565 pi->adapter = adapter; 5566 pi->xact_addr_filt = -1; 5567 pi->port_id = i; 5568 netdev->irq = pdev->irq; 5569 5570 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 5571 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5572 NETIF_F_RXCSUM | NETIF_F_RXHASH | 5573 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 5574 NETIF_F_HW_TC; 5575 5576 if (chip_ver > CHELSIO_T5) { 5577 netdev->hw_enc_features |= NETIF_F_IP_CSUM | 5578 NETIF_F_IPV6_CSUM | 5579 NETIF_F_RXCSUM | 5580 NETIF_F_GSO_UDP_TUNNEL | 5581 NETIF_F_TSO | NETIF_F_TSO6; 5582 5583 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL; 5584 } 5585 5586 if (highdma) 5587 netdev->hw_features |= NETIF_F_HIGHDMA; 5588 netdev->features |= netdev->hw_features; 5589 netdev->vlan_features = netdev->features & VLAN_FEAT; 5590 5591 netdev->priv_flags |= IFF_UNICAST_FLT; 5592 5593 /* MTU range: 81 - 9600 */ 5594 netdev->min_mtu = 81; /* accommodate SACK */ 5595 netdev->max_mtu = MAX_MTU; 5596 5597 netdev->netdev_ops = &cxgb4_netdev_ops; 5598 #ifdef CONFIG_CHELSIO_T4_DCB 5599 netdev->dcbnl_ops = &cxgb4_dcb_ops; 5600 cxgb4_dcb_state_init(netdev); 5601 #endif 5602 cxgb4_set_ethtool_ops(netdev); 5603 } 5604 5605 cxgb4_init_ethtool_dump(adapter); 5606 5607 pci_set_drvdata(pdev, adapter); 5608 5609 if (adapter->flags & FW_OK) { 5610 err = t4_port_init(adapter, func, func, 0); 5611 if (err) 5612 goto out_free_dev; 5613 } else if (adapter->params.nports == 1) { 5614 /* If we don't have a connection to the firmware -- possibly 5615 * because of an error -- grab the raw VPD parameters so we 5616 * can set the proper MAC Address on the debug network 5617 * interface that we've created. 5618 */ 5619 u8 hw_addr[ETH_ALEN]; 5620 u8 *na = adapter->params.vpd.na; 5621 5622 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 5623 if (!err) { 5624 for (i = 0; i < ETH_ALEN; i++) 5625 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 5626 hex2val(na[2 * i + 1])); 5627 t4_set_hw_addr(adapter, 0, hw_addr); 5628 } 5629 } 5630 5631 /* Configure queues and allocate tables now, they can be needed as 5632 * soon as the first register_netdev completes. 5633 */ 5634 cfg_queues(adapter); 5635 5636 adapter->smt = t4_init_smt(); 5637 if (!adapter->smt) { 5638 /* We tolerate a lack of SMT, giving up some functionality */ 5639 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); 5640 } 5641 5642 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 5643 if (!adapter->l2t) { 5644 /* We tolerate a lack of L2T, giving up some functionality */ 5645 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 5646 adapter->params.offload = 0; 5647 } 5648 5649 adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size, 5650 sizeof(struct mps_encap_entry), 5651 GFP_KERNEL); 5652 if (!adapter->mps_encap) 5653 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n"); 5654 5655 #if IS_ENABLED(CONFIG_IPV6) 5656 if (chip_ver <= CHELSIO_T5 && 5657 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 5658 /* CLIP functionality is not present in hardware, 5659 * hence disable all offload features 5660 */ 5661 dev_warn(&pdev->dev, 5662 "CLIP not enabled in hardware, continuing\n"); 5663 adapter->params.offload = 0; 5664 } else { 5665 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 5666 adapter->clipt_end); 5667 if (!adapter->clipt) { 5668 /* We tolerate a lack of clip_table, giving up 5669 * some functionality 5670 */ 5671 dev_warn(&pdev->dev, 5672 "could not allocate Clip table, continuing\n"); 5673 adapter->params.offload = 0; 5674 } 5675 } 5676 #endif 5677 5678 for_each_port(adapter, i) { 5679 pi = adap2pinfo(adapter, i); 5680 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 5681 if (!pi->sched_tbl) 5682 dev_warn(&pdev->dev, 5683 "could not activate scheduling on port %d\n", 5684 i); 5685 } 5686 5687 if (tid_init(&adapter->tids) < 0) { 5688 dev_warn(&pdev->dev, "could not allocate TID table, " 5689 "continuing\n"); 5690 adapter->params.offload = 0; 5691 } else { 5692 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 5693 if (!adapter->tc_u32) 5694 dev_warn(&pdev->dev, 5695 "could not offload tc u32, continuing\n"); 5696 5697 if (cxgb4_init_tc_flower(adapter)) 5698 dev_warn(&pdev->dev, 5699 "could not offload tc flower, continuing\n"); 5700 } 5701 5702 if (is_offload(adapter) || is_hashfilter(adapter)) { 5703 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 5704 u32 hash_base, hash_reg; 5705 5706 if (chip <= CHELSIO_T5) { 5707 hash_reg = LE_DB_TID_HASHBASE_A; 5708 hash_base = t4_read_reg(adapter, hash_reg); 5709 adapter->tids.hash_base = hash_base / 4; 5710 } else { 5711 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 5712 hash_base = t4_read_reg(adapter, hash_reg); 5713 adapter->tids.hash_base = hash_base; 5714 } 5715 } 5716 } 5717 5718 /* See what interrupts we'll be using */ 5719 if (msi > 1 && enable_msix(adapter) == 0) 5720 adapter->flags |= USING_MSIX; 5721 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 5722 adapter->flags |= USING_MSI; 5723 if (msi > 1) 5724 free_msix_info(adapter); 5725 } 5726 5727 /* check for PCI Express bandwidth capabiltites */ 5728 pcie_print_link_status(pdev); 5729 5730 err = init_rss(adapter); 5731 if (err) 5732 goto out_free_dev; 5733 5734 err = setup_fw_sge_queues(adapter); 5735 if (err) { 5736 dev_err(adapter->pdev_dev, 5737 "FW sge queue allocation failed, err %d", err); 5738 goto out_free_dev; 5739 } 5740 5741 /* 5742 * The card is now ready to go. If any errors occur during device 5743 * registration we do not fail the whole card but rather proceed only 5744 * with the ports we manage to register successfully. However we must 5745 * register at least one net device. 5746 */ 5747 for_each_port(adapter, i) { 5748 pi = adap2pinfo(adapter, i); 5749 adapter->port[i]->dev_port = pi->lport; 5750 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 5751 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 5752 5753 netif_carrier_off(adapter->port[i]); 5754 5755 err = register_netdev(adapter->port[i]); 5756 if (err) 5757 break; 5758 adapter->chan_map[pi->tx_chan] = i; 5759 print_port_info(adapter->port[i]); 5760 } 5761 if (i == 0) { 5762 dev_err(&pdev->dev, "could not register any net devices\n"); 5763 goto out_free_dev; 5764 } 5765 if (err) { 5766 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 5767 err = 0; 5768 } 5769 5770 if (cxgb4_debugfs_root) { 5771 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 5772 cxgb4_debugfs_root); 5773 setup_debugfs(adapter); 5774 } 5775 5776 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 5777 pdev->needs_freset = 1; 5778 5779 if (is_uld(adapter)) { 5780 mutex_lock(&uld_mutex); 5781 list_add_tail(&adapter->list_node, &adapter_list); 5782 mutex_unlock(&uld_mutex); 5783 } 5784 5785 if (!is_t4(adapter->params.chip)) 5786 cxgb4_ptp_init(adapter); 5787 5788 print_adapter_info(adapter); 5789 return 0; 5790 5791 out_free_dev: 5792 t4_free_sge_resources(adapter); 5793 free_some_resources(adapter); 5794 if (adapter->flags & USING_MSIX) 5795 free_msix_info(adapter); 5796 if (adapter->num_uld || adapter->num_ofld_uld) 5797 t4_uld_mem_free(adapter); 5798 out_unmap_bar: 5799 if (!is_t4(adapter->params.chip)) 5800 iounmap(adapter->bar2); 5801 out_free_adapter: 5802 if (adapter->workq) 5803 destroy_workqueue(adapter->workq); 5804 5805 kfree(adapter->mbox_log); 5806 kfree(adapter); 5807 out_unmap_bar0: 5808 iounmap(regs); 5809 out_disable_device: 5810 pci_disable_pcie_error_reporting(pdev); 5811 pci_disable_device(pdev); 5812 out_release_regions: 5813 pci_release_regions(pdev); 5814 return err; 5815 } 5816 5817 static void remove_one(struct pci_dev *pdev) 5818 { 5819 struct adapter *adapter = pci_get_drvdata(pdev); 5820 5821 if (!adapter) { 5822 pci_release_regions(pdev); 5823 return; 5824 } 5825 5826 adapter->flags |= SHUTTING_DOWN; 5827 5828 if (adapter->pf == 4) { 5829 int i; 5830 5831 /* Tear down per-adapter Work Queue first since it can contain 5832 * references to our adapter data structure. 5833 */ 5834 destroy_workqueue(adapter->workq); 5835 5836 if (is_uld(adapter)) { 5837 detach_ulds(adapter); 5838 t4_uld_clean_up(adapter); 5839 } 5840 5841 adap_free_hma_mem(adapter); 5842 5843 disable_interrupts(adapter); 5844 5845 for_each_port(adapter, i) 5846 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5847 unregister_netdev(adapter->port[i]); 5848 5849 debugfs_remove_recursive(adapter->debugfs_root); 5850 5851 if (!is_t4(adapter->params.chip)) 5852 cxgb4_ptp_stop(adapter); 5853 5854 /* If we allocated filters, free up state associated with any 5855 * valid filters ... 5856 */ 5857 clear_all_filters(adapter); 5858 5859 if (adapter->flags & FULL_INIT_DONE) 5860 cxgb_down(adapter); 5861 5862 if (adapter->flags & USING_MSIX) 5863 free_msix_info(adapter); 5864 if (adapter->num_uld || adapter->num_ofld_uld) 5865 t4_uld_mem_free(adapter); 5866 free_some_resources(adapter); 5867 #if IS_ENABLED(CONFIG_IPV6) 5868 t4_cleanup_clip_tbl(adapter); 5869 #endif 5870 if (!is_t4(adapter->params.chip)) 5871 iounmap(adapter->bar2); 5872 } 5873 #ifdef CONFIG_PCI_IOV 5874 else { 5875 cxgb4_iov_configure(adapter->pdev, 0); 5876 } 5877 #endif 5878 iounmap(adapter->regs); 5879 pci_disable_pcie_error_reporting(pdev); 5880 if ((adapter->flags & DEV_ENABLED)) { 5881 pci_disable_device(pdev); 5882 adapter->flags &= ~DEV_ENABLED; 5883 } 5884 pci_release_regions(pdev); 5885 kfree(adapter->mbox_log); 5886 synchronize_rcu(); 5887 kfree(adapter); 5888 } 5889 5890 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 5891 * delivery. This is essentially a stripped down version of the PCI remove() 5892 * function where we do the minimal amount of work necessary to shutdown any 5893 * further activity. 5894 */ 5895 static void shutdown_one(struct pci_dev *pdev) 5896 { 5897 struct adapter *adapter = pci_get_drvdata(pdev); 5898 5899 /* As with remove_one() above (see extended comment), we only want do 5900 * do cleanup on PCI Devices which went all the way through init_one() 5901 * ... 5902 */ 5903 if (!adapter) { 5904 pci_release_regions(pdev); 5905 return; 5906 } 5907 5908 adapter->flags |= SHUTTING_DOWN; 5909 5910 if (adapter->pf == 4) { 5911 int i; 5912 5913 for_each_port(adapter, i) 5914 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5915 cxgb_close(adapter->port[i]); 5916 5917 if (is_uld(adapter)) { 5918 detach_ulds(adapter); 5919 t4_uld_clean_up(adapter); 5920 } 5921 5922 disable_interrupts(adapter); 5923 disable_msi(adapter); 5924 5925 t4_sge_stop(adapter); 5926 if (adapter->flags & FW_OK) 5927 t4_fw_bye(adapter, adapter->mbox); 5928 } 5929 } 5930 5931 static struct pci_driver cxgb4_driver = { 5932 .name = KBUILD_MODNAME, 5933 .id_table = cxgb4_pci_tbl, 5934 .probe = init_one, 5935 .remove = remove_one, 5936 .shutdown = shutdown_one, 5937 #ifdef CONFIG_PCI_IOV 5938 .sriov_configure = cxgb4_iov_configure, 5939 #endif 5940 .err_handler = &cxgb4_eeh, 5941 }; 5942 5943 static int __init cxgb4_init_module(void) 5944 { 5945 int ret; 5946 5947 /* Debugfs support is optional, just warn if this fails */ 5948 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 5949 if (!cxgb4_debugfs_root) 5950 pr_warn("could not create debugfs entry, continuing\n"); 5951 5952 ret = pci_register_driver(&cxgb4_driver); 5953 if (ret < 0) 5954 debugfs_remove(cxgb4_debugfs_root); 5955 5956 #if IS_ENABLED(CONFIG_IPV6) 5957 if (!inet6addr_registered) { 5958 register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5959 inet6addr_registered = true; 5960 } 5961 #endif 5962 5963 return ret; 5964 } 5965 5966 static void __exit cxgb4_cleanup_module(void) 5967 { 5968 #if IS_ENABLED(CONFIG_IPV6) 5969 if (inet6addr_registered) { 5970 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5971 inet6addr_registered = false; 5972 } 5973 #endif 5974 pci_unregister_driver(&cxgb4_driver); 5975 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 5976 } 5977 5978 module_init(cxgb4_init_module); 5979 module_exit(cxgb4_cleanup_module); 5980