1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <net/addrconf.h> 66 #include <asm/uaccess.h> 67 68 #include "cxgb4.h" 69 #include "t4_regs.h" 70 #include "t4_values.h" 71 #include "t4_msg.h" 72 #include "t4fw_api.h" 73 #include "t4fw_version.h" 74 #include "cxgb4_dcb.h" 75 #include "cxgb4_debugfs.h" 76 #include "clip_tbl.h" 77 #include "l2t.h" 78 79 char cxgb4_driver_name[] = KBUILD_MODNAME; 80 81 #ifdef DRV_VERSION 82 #undef DRV_VERSION 83 #endif 84 #define DRV_VERSION "2.0.0-ko" 85 const char cxgb4_driver_version[] = DRV_VERSION; 86 #define DRV_DESC "Chelsio T4/T5 Network Driver" 87 88 /* Host shadow copy of ingress filter entry. This is in host native format 89 * and doesn't match the ordering or bit order, etc. of the hardware of the 90 * firmware command. The use of bit-field structure elements is purely to 91 * remind ourselves of the field size limitations and save memory in the case 92 * where the filter table is large. 93 */ 94 struct filter_entry { 95 /* Administrative fields for filter. 96 */ 97 u32 valid:1; /* filter allocated and valid */ 98 u32 locked:1; /* filter is administratively locked */ 99 100 u32 pending:1; /* filter action is pending firmware reply */ 101 u32 smtidx:8; /* Source MAC Table index for smac */ 102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */ 103 104 /* The filter itself. Most of this is a straight copy of information 105 * provided by the extended ioctl(). Some fields are translated to 106 * internal forms -- for instance the Ingress Queue ID passed in from 107 * the ioctl() is translated into the Absolute Ingress Queue ID. 108 */ 109 struct ch_filter_specification fs; 110 }; 111 112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 115 116 /* Macros needed to support the PCI Device ID Table ... 117 */ 118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 119 static const struct pci_device_id cxgb4_pci_tbl[] = { 120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 121 122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 123 * called for both. 124 */ 125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 126 127 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 128 {PCI_VDEVICE(CHELSIO, (devid)), 4} 129 130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 131 { 0, } \ 132 } 133 134 #include "t4_pci_id_tbl.h" 135 136 #define FW4_FNAME "cxgb4/t4fw.bin" 137 #define FW5_FNAME "cxgb4/t5fw.bin" 138 #define FW6_FNAME "cxgb4/t6fw.bin" 139 #define FW4_CFNAME "cxgb4/t4-config.txt" 140 #define FW5_CFNAME "cxgb4/t5-config.txt" 141 #define FW6_CFNAME "cxgb4/t6-config.txt" 142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 144 #define PHY_AQ1202_DEVICEID 0x4409 145 #define PHY_BCM84834_DEVICEID 0x4486 146 147 MODULE_DESCRIPTION(DRV_DESC); 148 MODULE_AUTHOR("Chelsio Communications"); 149 MODULE_LICENSE("Dual BSD/GPL"); 150 MODULE_VERSION(DRV_VERSION); 151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 152 MODULE_FIRMWARE(FW4_FNAME); 153 MODULE_FIRMWARE(FW5_FNAME); 154 155 /* 156 * Normally we're willing to become the firmware's Master PF but will be happy 157 * if another PF has already become the Master and initialized the adapter. 158 * Setting "force_init" will cause this driver to forcibly establish itself as 159 * the Master PF and initialize the adapter. 160 */ 161 static uint force_init; 162 163 module_param(force_init, uint, 0644); 164 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter"); 165 166 /* 167 * Normally if the firmware we connect to has Configuration File support, we 168 * use that and only fall back to the old Driver-based initialization if the 169 * Configuration File fails for some reason. If force_old_init is set, then 170 * we'll always use the old Driver-based initialization sequence. 171 */ 172 static uint force_old_init; 173 174 module_param(force_old_init, uint, 0644); 175 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated" 176 " parameter"); 177 178 static int dflt_msg_enable = DFLT_MSG_ENABLE; 179 180 module_param(dflt_msg_enable, int, 0644); 181 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap"); 182 183 /* 184 * The driver uses the best interrupt scheme available on a platform in the 185 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 186 * of these schemes the driver may consider as follows: 187 * 188 * msi = 2: choose from among all three options 189 * msi = 1: only consider MSI and INTx interrupts 190 * msi = 0: force INTx interrupts 191 */ 192 static int msi = 2; 193 194 module_param(msi, int, 0644); 195 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 196 197 /* 198 * Queue interrupt hold-off timer values. Queues default to the first of these 199 * upon creation. 200 */ 201 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 }; 202 203 module_param_array(intr_holdoff, uint, NULL, 0644); 204 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers " 205 "0..4 in microseconds, deprecated parameter"); 206 207 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 }; 208 209 module_param_array(intr_cnt, uint, NULL, 0644); 210 MODULE_PARM_DESC(intr_cnt, 211 "thresholds 1..3 for queue interrupt packet counters, " 212 "deprecated parameter"); 213 214 /* 215 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 216 * offset by 2 bytes in order to have the IP headers line up on 4-byte 217 * boundaries. This is a requirement for many architectures which will throw 218 * a machine check fault if an attempt is made to access one of the 4-byte IP 219 * header fields on a non-4-byte boundary. And it's a major performance issue 220 * even on some architectures which allow it like some implementations of the 221 * x86 ISA. However, some architectures don't mind this and for some very 222 * edge-case performance sensitive applications (like forwarding large volumes 223 * of small packets), setting this DMA offset to 0 will decrease the number of 224 * PCI-E Bus transfers enough to measurably affect performance. 225 */ 226 static int rx_dma_offset = 2; 227 228 static bool vf_acls; 229 230 #ifdef CONFIG_PCI_IOV 231 module_param(vf_acls, bool, 0644); 232 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, " 233 "deprecated parameter"); 234 235 /* Configure the number of PCI-E Virtual Function which are to be instantiated 236 * on SR-IOV Capable Physical Functions. 237 */ 238 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV]; 239 240 module_param_array(num_vf, uint, NULL, 0644); 241 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3"); 242 #endif 243 244 /* TX Queue select used to determine what algorithm to use for selecting TX 245 * queue. Select between the kernel provided function (select_queue=0) or user 246 * cxgb_select_queue function (select_queue=1) 247 * 248 * Default: select_queue=0 249 */ 250 static int select_queue; 251 module_param(select_queue, int, 0644); 252 MODULE_PARM_DESC(select_queue, 253 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 254 255 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC; 256 257 module_param(tp_vlan_pri_map, uint, 0644); 258 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, " 259 "deprecated parameter"); 260 261 static struct dentry *cxgb4_debugfs_root; 262 263 static LIST_HEAD(adapter_list); 264 static DEFINE_MUTEX(uld_mutex); 265 /* Adapter list to be accessed from atomic context */ 266 static LIST_HEAD(adap_rcu_list); 267 static DEFINE_SPINLOCK(adap_rcu_lock); 268 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX]; 269 static const char *uld_str[] = { "RDMA", "iSCSI" }; 270 271 static void link_report(struct net_device *dev) 272 { 273 if (!netif_carrier_ok(dev)) 274 netdev_info(dev, "link down\n"); 275 else { 276 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 277 278 const char *s = "10Mbps"; 279 const struct port_info *p = netdev_priv(dev); 280 281 switch (p->link_cfg.speed) { 282 case 10000: 283 s = "10Gbps"; 284 break; 285 case 1000: 286 s = "1000Mbps"; 287 break; 288 case 100: 289 s = "100Mbps"; 290 break; 291 case 40000: 292 s = "40Gbps"; 293 break; 294 } 295 296 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 297 fc[p->link_cfg.fc]); 298 } 299 } 300 301 #ifdef CONFIG_CHELSIO_T4_DCB 302 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 303 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 304 { 305 struct port_info *pi = netdev_priv(dev); 306 struct adapter *adap = pi->adapter; 307 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 308 int i; 309 310 /* We use a simple mapping of Port TX Queue Index to DCB 311 * Priority when we're enabling DCB. 312 */ 313 for (i = 0; i < pi->nqsets; i++, txq++) { 314 u32 name, value; 315 int err; 316 317 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 318 FW_PARAMS_PARAM_X_V( 319 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 320 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 321 value = enable ? i : 0xffffffff; 322 323 /* Since we can be called while atomic (from "interrupt 324 * level") we need to issue the Set Parameters Commannd 325 * without sleeping (timeout < 0). 326 */ 327 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 328 &name, &value, 329 -FW_CMD_MAX_TIMEOUT); 330 331 if (err) 332 dev_err(adap->pdev_dev, 333 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 334 enable ? "set" : "unset", pi->port_id, i, -err); 335 else 336 txq->dcb_prio = value; 337 } 338 } 339 #endif /* CONFIG_CHELSIO_T4_DCB */ 340 341 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 342 { 343 struct net_device *dev = adapter->port[port_id]; 344 345 /* Skip changes from disabled ports. */ 346 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 347 if (link_stat) 348 netif_carrier_on(dev); 349 else { 350 #ifdef CONFIG_CHELSIO_T4_DCB 351 cxgb4_dcb_state_init(dev); 352 dcb_tx_queue_prio_enable(dev, false); 353 #endif /* CONFIG_CHELSIO_T4_DCB */ 354 netif_carrier_off(dev); 355 } 356 357 link_report(dev); 358 } 359 } 360 361 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 362 { 363 static const char *mod_str[] = { 364 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 365 }; 366 367 const struct net_device *dev = adap->port[port_id]; 368 const struct port_info *pi = netdev_priv(dev); 369 370 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 371 netdev_info(dev, "port module unplugged\n"); 372 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 373 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 374 } 375 376 /* 377 * Configure the exact and hash address filters to handle a port's multicast 378 * and secondary unicast MAC addresses. 379 */ 380 static int set_addr_filters(const struct net_device *dev, bool sleep) 381 { 382 u64 mhash = 0; 383 u64 uhash = 0; 384 bool free = true; 385 u16 filt_idx[7]; 386 const u8 *addr[7]; 387 int ret, naddr = 0; 388 const struct netdev_hw_addr *ha; 389 int uc_cnt = netdev_uc_count(dev); 390 int mc_cnt = netdev_mc_count(dev); 391 const struct port_info *pi = netdev_priv(dev); 392 unsigned int mb = pi->adapter->pf; 393 394 /* first do the secondary unicast addresses */ 395 netdev_for_each_uc_addr(ha, dev) { 396 addr[naddr++] = ha->addr; 397 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { 398 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, 399 naddr, addr, filt_idx, &uhash, sleep); 400 if (ret < 0) 401 return ret; 402 403 free = false; 404 naddr = 0; 405 } 406 } 407 408 /* next set up the multicast addresses */ 409 netdev_for_each_mc_addr(ha, dev) { 410 addr[naddr++] = ha->addr; 411 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) { 412 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free, 413 naddr, addr, filt_idx, &mhash, sleep); 414 if (ret < 0) 415 return ret; 416 417 free = false; 418 naddr = 0; 419 } 420 } 421 422 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0, 423 uhash | mhash, sleep); 424 } 425 426 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 427 module_param(dbfifo_int_thresh, int, 0644); 428 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 429 430 /* 431 * usecs to sleep while draining the dbfifo 432 */ 433 static int dbfifo_drain_delay = 1000; 434 module_param(dbfifo_drain_delay, int, 0644); 435 MODULE_PARM_DESC(dbfifo_drain_delay, 436 "usecs to sleep while draining the dbfifo"); 437 438 /* 439 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 440 * If @mtu is -1 it is left unchanged. 441 */ 442 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 443 { 444 int ret; 445 struct port_info *pi = netdev_priv(dev); 446 447 ret = set_addr_filters(dev, sleep_ok); 448 if (ret == 0) 449 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu, 450 (dev->flags & IFF_PROMISC) ? 1 : 0, 451 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 452 sleep_ok); 453 return ret; 454 } 455 456 /** 457 * link_start - enable a port 458 * @dev: the port to enable 459 * 460 * Performs the MAC and PHY actions needed to enable a port. 461 */ 462 static int link_start(struct net_device *dev) 463 { 464 int ret; 465 struct port_info *pi = netdev_priv(dev); 466 unsigned int mb = pi->adapter->pf; 467 468 /* 469 * We do not set address filters and promiscuity here, the stack does 470 * that step explicitly. 471 */ 472 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 473 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 474 if (ret == 0) { 475 ret = t4_change_mac(pi->adapter, mb, pi->viid, 476 pi->xact_addr_filt, dev->dev_addr, true, 477 true); 478 if (ret >= 0) { 479 pi->xact_addr_filt = ret; 480 ret = 0; 481 } 482 } 483 if (ret == 0) 484 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 485 &pi->link_cfg); 486 if (ret == 0) { 487 local_bh_disable(); 488 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, 489 true, CXGB4_DCB_ENABLED); 490 local_bh_enable(); 491 } 492 493 return ret; 494 } 495 496 int cxgb4_dcb_enabled(const struct net_device *dev) 497 { 498 #ifdef CONFIG_CHELSIO_T4_DCB 499 struct port_info *pi = netdev_priv(dev); 500 501 if (!pi->dcb.enabled) 502 return 0; 503 504 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 505 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 506 #else 507 return 0; 508 #endif 509 } 510 EXPORT_SYMBOL(cxgb4_dcb_enabled); 511 512 #ifdef CONFIG_CHELSIO_T4_DCB 513 /* Handle a Data Center Bridging update message from the firmware. */ 514 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 515 { 516 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 517 struct net_device *dev = adap->port[port]; 518 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 519 int new_dcb_enabled; 520 521 cxgb4_dcb_handle_fw_update(adap, pcmd); 522 new_dcb_enabled = cxgb4_dcb_enabled(dev); 523 524 /* If the DCB has become enabled or disabled on the port then we're 525 * going to need to set up/tear down DCB Priority parameters for the 526 * TX Queues associated with the port. 527 */ 528 if (new_dcb_enabled != old_dcb_enabled) 529 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 530 } 531 #endif /* CONFIG_CHELSIO_T4_DCB */ 532 533 /* Clear a filter and release any of its resources that we own. This also 534 * clears the filter's "pending" status. 535 */ 536 static void clear_filter(struct adapter *adap, struct filter_entry *f) 537 { 538 /* If the new or old filter have loopback rewriteing rules then we'll 539 * need to free any existing Layer Two Table (L2T) entries of the old 540 * filter rule. The firmware will handle freeing up any Source MAC 541 * Table (SMT) entries used for rewriting Source MAC Addresses in 542 * loopback rules. 543 */ 544 if (f->l2t) 545 cxgb4_l2t_release(f->l2t); 546 547 /* The zeroing of the filter rule below clears the filter valid, 548 * pending, locked flags, l2t pointer, etc. so it's all we need for 549 * this operation. 550 */ 551 memset(f, 0, sizeof(*f)); 552 } 553 554 /* Handle a filter write/deletion reply. 555 */ 556 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl) 557 { 558 unsigned int idx = GET_TID(rpl); 559 unsigned int nidx = idx - adap->tids.ftid_base; 560 unsigned int ret; 561 struct filter_entry *f; 562 563 if (idx >= adap->tids.ftid_base && nidx < 564 (adap->tids.nftids + adap->tids.nsftids)) { 565 idx = nidx; 566 ret = TCB_COOKIE_G(rpl->cookie); 567 f = &adap->tids.ftid_tab[idx]; 568 569 if (ret == FW_FILTER_WR_FLT_DELETED) { 570 /* Clear the filter when we get confirmation from the 571 * hardware that the filter has been deleted. 572 */ 573 clear_filter(adap, f); 574 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) { 575 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n", 576 idx); 577 clear_filter(adap, f); 578 } else if (ret == FW_FILTER_WR_FLT_ADDED) { 579 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff; 580 f->pending = 0; /* asynchronous setup completed */ 581 f->valid = 1; 582 } else { 583 /* Something went wrong. Issue a warning about the 584 * problem and clear everything out. 585 */ 586 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n", 587 idx, ret); 588 clear_filter(adap, f); 589 } 590 } 591 } 592 593 /* Response queue handler for the FW event queue. 594 */ 595 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 596 const struct pkt_gl *gl) 597 { 598 u8 opcode = ((const struct rss_header *)rsp)->opcode; 599 600 rsp++; /* skip RSS header */ 601 602 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 603 */ 604 if (unlikely(opcode == CPL_FW4_MSG && 605 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 606 rsp++; 607 opcode = ((const struct rss_header *)rsp)->opcode; 608 rsp++; 609 if (opcode != CPL_SGE_EGR_UPDATE) { 610 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 611 , opcode); 612 goto out; 613 } 614 } 615 616 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 617 const struct cpl_sge_egr_update *p = (void *)rsp; 618 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 619 struct sge_txq *txq; 620 621 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 622 txq->restarts++; 623 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) { 624 struct sge_eth_txq *eq; 625 626 eq = container_of(txq, struct sge_eth_txq, q); 627 netif_tx_wake_queue(eq->txq); 628 } else { 629 struct sge_ofld_txq *oq; 630 631 oq = container_of(txq, struct sge_ofld_txq, q); 632 tasklet_schedule(&oq->qresume_tsk); 633 } 634 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 635 const struct cpl_fw6_msg *p = (void *)rsp; 636 637 #ifdef CONFIG_CHELSIO_T4_DCB 638 const struct fw_port_cmd *pcmd = (const void *)p->data; 639 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 640 unsigned int action = 641 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 642 643 if (cmd == FW_PORT_CMD && 644 action == FW_PORT_ACTION_GET_PORT_INFO) { 645 int port = FW_PORT_CMD_PORTID_G( 646 be32_to_cpu(pcmd->op_to_portid)); 647 struct net_device *dev = q->adap->port[port]; 648 int state_input = ((pcmd->u.info.dcbxdis_pkd & 649 FW_PORT_CMD_DCBXDIS_F) 650 ? CXGB4_DCB_INPUT_FW_DISABLED 651 : CXGB4_DCB_INPUT_FW_ENABLED); 652 653 cxgb4_dcb_state_fsm(dev, state_input); 654 } 655 656 if (cmd == FW_PORT_CMD && 657 action == FW_PORT_ACTION_L2_DCB_CFG) 658 dcb_rpl(q->adap, pcmd); 659 else 660 #endif 661 if (p->type == 0) 662 t4_handle_fw_rpl(q->adap, p->data); 663 } else if (opcode == CPL_L2T_WRITE_RPL) { 664 const struct cpl_l2t_write_rpl *p = (void *)rsp; 665 666 do_l2t_write_rpl(q->adap, p); 667 } else if (opcode == CPL_SET_TCB_RPL) { 668 const struct cpl_set_tcb_rpl *p = (void *)rsp; 669 670 filter_rpl(q->adap, p); 671 } else 672 dev_err(q->adap->pdev_dev, 673 "unexpected CPL %#x on FW event queue\n", opcode); 674 out: 675 return 0; 676 } 677 678 /** 679 * uldrx_handler - response queue handler for ULD queues 680 * @q: the response queue that received the packet 681 * @rsp: the response queue descriptor holding the offload message 682 * @gl: the gather list of packet fragments 683 * 684 * Deliver an ingress offload packet to a ULD. All processing is done by 685 * the ULD, we just maintain statistics. 686 */ 687 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp, 688 const struct pkt_gl *gl) 689 { 690 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq); 691 692 /* FW can send CPLs encapsulated in a CPL_FW4_MSG. 693 */ 694 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG && 695 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL) 696 rsp += 2; 697 698 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) { 699 rxq->stats.nomem++; 700 return -1; 701 } 702 if (gl == NULL) 703 rxq->stats.imm++; 704 else if (gl == CXGB4_MSG_AN) 705 rxq->stats.an++; 706 else 707 rxq->stats.pkts++; 708 return 0; 709 } 710 711 static void disable_msi(struct adapter *adapter) 712 { 713 if (adapter->flags & USING_MSIX) { 714 pci_disable_msix(adapter->pdev); 715 adapter->flags &= ~USING_MSIX; 716 } else if (adapter->flags & USING_MSI) { 717 pci_disable_msi(adapter->pdev); 718 adapter->flags &= ~USING_MSI; 719 } 720 } 721 722 /* 723 * Interrupt handler for non-data events used with MSI-X. 724 */ 725 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 726 { 727 struct adapter *adap = cookie; 728 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 729 730 if (v & PFSW_F) { 731 adap->swintr = 1; 732 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 733 } 734 if (adap->flags & MASTER_PF) 735 t4_slow_intr_handler(adap); 736 return IRQ_HANDLED; 737 } 738 739 /* 740 * Name the MSI-X interrupts. 741 */ 742 static void name_msix_vecs(struct adapter *adap) 743 { 744 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 745 746 /* non-data interrupts */ 747 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 748 749 /* FW events */ 750 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 751 adap->port[0]->name); 752 753 /* Ethernet queues */ 754 for_each_port(adap, j) { 755 struct net_device *d = adap->port[j]; 756 const struct port_info *pi = netdev_priv(d); 757 758 for (i = 0; i < pi->nqsets; i++, msi_idx++) 759 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 760 d->name, i); 761 } 762 763 /* offload queues */ 764 for_each_ofldrxq(&adap->sge, i) 765 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d", 766 adap->port[0]->name, i); 767 768 for_each_rdmarxq(&adap->sge, i) 769 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d", 770 adap->port[0]->name, i); 771 772 for_each_rdmaciq(&adap->sge, i) 773 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d", 774 adap->port[0]->name, i); 775 } 776 777 static int request_msix_queue_irqs(struct adapter *adap) 778 { 779 struct sge *s = &adap->sge; 780 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0; 781 int msi_index = 2; 782 783 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 784 adap->msix_info[1].desc, &s->fw_evtq); 785 if (err) 786 return err; 787 788 for_each_ethrxq(s, ethqidx) { 789 err = request_irq(adap->msix_info[msi_index].vec, 790 t4_sge_intr_msix, 0, 791 adap->msix_info[msi_index].desc, 792 &s->ethrxq[ethqidx].rspq); 793 if (err) 794 goto unwind; 795 msi_index++; 796 } 797 for_each_ofldrxq(s, ofldqidx) { 798 err = request_irq(adap->msix_info[msi_index].vec, 799 t4_sge_intr_msix, 0, 800 adap->msix_info[msi_index].desc, 801 &s->ofldrxq[ofldqidx].rspq); 802 if (err) 803 goto unwind; 804 msi_index++; 805 } 806 for_each_rdmarxq(s, rdmaqidx) { 807 err = request_irq(adap->msix_info[msi_index].vec, 808 t4_sge_intr_msix, 0, 809 adap->msix_info[msi_index].desc, 810 &s->rdmarxq[rdmaqidx].rspq); 811 if (err) 812 goto unwind; 813 msi_index++; 814 } 815 for_each_rdmaciq(s, rdmaciqqidx) { 816 err = request_irq(adap->msix_info[msi_index].vec, 817 t4_sge_intr_msix, 0, 818 adap->msix_info[msi_index].desc, 819 &s->rdmaciq[rdmaciqqidx].rspq); 820 if (err) 821 goto unwind; 822 msi_index++; 823 } 824 return 0; 825 826 unwind: 827 while (--rdmaciqqidx >= 0) 828 free_irq(adap->msix_info[--msi_index].vec, 829 &s->rdmaciq[rdmaciqqidx].rspq); 830 while (--rdmaqidx >= 0) 831 free_irq(adap->msix_info[--msi_index].vec, 832 &s->rdmarxq[rdmaqidx].rspq); 833 while (--ofldqidx >= 0) 834 free_irq(adap->msix_info[--msi_index].vec, 835 &s->ofldrxq[ofldqidx].rspq); 836 while (--ethqidx >= 0) 837 free_irq(adap->msix_info[--msi_index].vec, 838 &s->ethrxq[ethqidx].rspq); 839 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 840 return err; 841 } 842 843 static void free_msix_queue_irqs(struct adapter *adap) 844 { 845 int i, msi_index = 2; 846 struct sge *s = &adap->sge; 847 848 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 849 for_each_ethrxq(s, i) 850 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); 851 for_each_ofldrxq(s, i) 852 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq); 853 for_each_rdmarxq(s, i) 854 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq); 855 for_each_rdmaciq(s, i) 856 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq); 857 } 858 859 /** 860 * cxgb4_write_rss - write the RSS table for a given port 861 * @pi: the port 862 * @queues: array of queue indices for RSS 863 * 864 * Sets up the portion of the HW RSS table for the port's VI to distribute 865 * packets to the Rx queues in @queues. 866 * Should never be called before setting up sge eth rx queues 867 */ 868 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 869 { 870 u16 *rss; 871 int i, err; 872 struct adapter *adapter = pi->adapter; 873 const struct sge_eth_rxq *rxq; 874 875 rxq = &adapter->sge.ethrxq[pi->first_qset]; 876 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); 877 if (!rss) 878 return -ENOMEM; 879 880 /* map the queue indices to queue ids */ 881 for (i = 0; i < pi->rss_size; i++, queues++) 882 rss[i] = rxq[*queues].rspq.abs_id; 883 884 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 885 pi->rss_size, rss, pi->rss_size); 886 /* If Tunnel All Lookup isn't specified in the global RSS 887 * Configuration, then we need to specify a default Ingress 888 * Queue for any ingress packets which aren't hashed. We'll 889 * use our first ingress queue ... 890 */ 891 if (!err) 892 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 893 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 894 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 895 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 896 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 897 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 898 rss[0]); 899 kfree(rss); 900 return err; 901 } 902 903 /** 904 * setup_rss - configure RSS 905 * @adap: the adapter 906 * 907 * Sets up RSS for each port. 908 */ 909 static int setup_rss(struct adapter *adap) 910 { 911 int i, j, err; 912 913 for_each_port(adap, i) { 914 const struct port_info *pi = adap2pinfo(adap, i); 915 916 /* Fill default values with equal distribution */ 917 for (j = 0; j < pi->rss_size; j++) 918 pi->rss[j] = j % pi->nqsets; 919 920 err = cxgb4_write_rss(pi, pi->rss); 921 if (err) 922 return err; 923 } 924 return 0; 925 } 926 927 /* 928 * Return the channel of the ingress queue with the given qid. 929 */ 930 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 931 { 932 qid -= p->ingr_start; 933 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 934 } 935 936 /* 937 * Wait until all NAPI handlers are descheduled. 938 */ 939 static void quiesce_rx(struct adapter *adap) 940 { 941 int i; 942 943 for (i = 0; i < adap->sge.ingr_sz; i++) { 944 struct sge_rspq *q = adap->sge.ingr_map[i]; 945 946 if (q && q->handler) { 947 napi_disable(&q->napi); 948 local_bh_disable(); 949 while (!cxgb_poll_lock_napi(q)) 950 mdelay(1); 951 local_bh_enable(); 952 } 953 954 } 955 } 956 957 /* Disable interrupt and napi handler */ 958 static void disable_interrupts(struct adapter *adap) 959 { 960 if (adap->flags & FULL_INIT_DONE) { 961 t4_intr_disable(adap); 962 if (adap->flags & USING_MSIX) { 963 free_msix_queue_irqs(adap); 964 free_irq(adap->msix_info[0].vec, adap); 965 } else { 966 free_irq(adap->pdev->irq, adap); 967 } 968 quiesce_rx(adap); 969 } 970 } 971 972 /* 973 * Enable NAPI scheduling and interrupt generation for all Rx queues. 974 */ 975 static void enable_rx(struct adapter *adap) 976 { 977 int i; 978 979 for (i = 0; i < adap->sge.ingr_sz; i++) { 980 struct sge_rspq *q = adap->sge.ingr_map[i]; 981 982 if (!q) 983 continue; 984 if (q->handler) { 985 cxgb_busy_poll_init_lock(q); 986 napi_enable(&q->napi); 987 } 988 /* 0-increment GTS to start the timer and enable interrupts */ 989 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 990 SEINTARM_V(q->intr_params) | 991 INGRESSQID_V(q->cntxt_id)); 992 } 993 } 994 995 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q, 996 unsigned int nq, unsigned int per_chan, int msi_idx, 997 u16 *ids) 998 { 999 int i, err; 1000 1001 for (i = 0; i < nq; i++, q++) { 1002 if (msi_idx > 0) 1003 msi_idx++; 1004 err = t4_sge_alloc_rxq(adap, &q->rspq, false, 1005 adap->port[i / per_chan], 1006 msi_idx, q->fl.size ? &q->fl : NULL, 1007 uldrx_handler, 0); 1008 if (err) 1009 return err; 1010 memset(&q->stats, 0, sizeof(q->stats)); 1011 if (ids) 1012 ids[i] = q->rspq.abs_id; 1013 } 1014 return 0; 1015 } 1016 1017 /** 1018 * setup_sge_queues - configure SGE Tx/Rx/response queues 1019 * @adap: the adapter 1020 * 1021 * Determines how many sets of SGE queues to use and initializes them. 1022 * We support multiple queue sets per port if we have MSI-X, otherwise 1023 * just one queue set per port. 1024 */ 1025 static int setup_sge_queues(struct adapter *adap) 1026 { 1027 int err, msi_idx, i, j; 1028 struct sge *s = &adap->sge; 1029 1030 bitmap_zero(s->starving_fl, s->egr_sz); 1031 bitmap_zero(s->txq_maperr, s->egr_sz); 1032 1033 if (adap->flags & USING_MSIX) 1034 msi_idx = 1; /* vector 0 is for non-queue interrupts */ 1035 else { 1036 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 1037 NULL, NULL, -1); 1038 if (err) 1039 return err; 1040 msi_idx = -((int)s->intrq.abs_id + 1); 1041 } 1042 1043 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here, 1044 * don't forget to update the following which need to be 1045 * synchronized to and changes here. 1046 * 1047 * 1. The calculations of MAX_INGQ in cxgb4.h. 1048 * 1049 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs 1050 * to accommodate any new/deleted Ingress Queues 1051 * which need MSI-X Vectors. 1052 * 1053 * 3. Update sge_qinfo_show() to include information on the 1054 * new/deleted queues. 1055 */ 1056 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 1057 msi_idx, NULL, fwevtq_handler, -1); 1058 if (err) { 1059 freeout: t4_free_sge_resources(adap); 1060 return err; 1061 } 1062 1063 for_each_port(adap, i) { 1064 struct net_device *dev = adap->port[i]; 1065 struct port_info *pi = netdev_priv(dev); 1066 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 1067 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 1068 1069 for (j = 0; j < pi->nqsets; j++, q++) { 1070 if (msi_idx > 0) 1071 msi_idx++; 1072 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 1073 msi_idx, &q->fl, 1074 t4_ethrx_handler, 1075 t4_get_mps_bg_map(adap, 1076 pi->tx_chan)); 1077 if (err) 1078 goto freeout; 1079 q->rspq.idx = j; 1080 memset(&q->stats, 0, sizeof(q->stats)); 1081 } 1082 for (j = 0; j < pi->nqsets; j++, t++) { 1083 err = t4_sge_alloc_eth_txq(adap, t, dev, 1084 netdev_get_tx_queue(dev, j), 1085 s->fw_evtq.cntxt_id); 1086 if (err) 1087 goto freeout; 1088 } 1089 } 1090 1091 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */ 1092 for_each_ofldrxq(s, i) { 1093 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], 1094 adap->port[i / j], 1095 s->fw_evtq.cntxt_id); 1096 if (err) 1097 goto freeout; 1098 } 1099 1100 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \ 1101 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \ 1102 if (err) \ 1103 goto freeout; \ 1104 if (msi_idx > 0) \ 1105 msi_idx += nq; \ 1106 } while (0) 1107 1108 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq); 1109 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq); 1110 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */ 1111 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq); 1112 1113 #undef ALLOC_OFLD_RXQS 1114 1115 for_each_port(adap, i) { 1116 /* 1117 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't 1118 * have RDMA queues, and that's the right value. 1119 */ 1120 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 1121 s->fw_evtq.cntxt_id, 1122 s->rdmarxq[i].rspq.cntxt_id); 1123 if (err) 1124 goto freeout; 1125 } 1126 1127 t4_write_reg(adap, is_t4(adap->params.chip) ? 1128 MPS_TRC_RSS_CONTROL_A : 1129 MPS_T5_TRC_RSS_CONTROL_A, 1130 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 1131 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 1132 return 0; 1133 } 1134 1135 /* 1136 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc. 1137 * The allocated memory is cleared. 1138 */ 1139 void *t4_alloc_mem(size_t size) 1140 { 1141 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 1142 1143 if (!p) 1144 p = vzalloc(size); 1145 return p; 1146 } 1147 1148 /* 1149 * Free memory allocated through alloc_mem(). 1150 */ 1151 void t4_free_mem(void *addr) 1152 { 1153 kvfree(addr); 1154 } 1155 1156 /* Send a Work Request to write the filter at a specified index. We construct 1157 * a Firmware Filter Work Request to have the work done and put the indicated 1158 * filter into "pending" mode which will prevent any further actions against 1159 * it till we get a reply from the firmware on the completion status of the 1160 * request. 1161 */ 1162 static int set_filter_wr(struct adapter *adapter, int fidx) 1163 { 1164 struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; 1165 struct sk_buff *skb; 1166 struct fw_filter_wr *fwr; 1167 unsigned int ftid; 1168 1169 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL); 1170 if (!skb) 1171 return -ENOMEM; 1172 1173 /* If the new filter requires loopback Destination MAC and/or VLAN 1174 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for 1175 * the filter. 1176 */ 1177 if (f->fs.newdmac || f->fs.newvlan) { 1178 /* allocate L2T entry for new filter */ 1179 f->l2t = t4_l2t_alloc_switching(adapter->l2t); 1180 if (f->l2t == NULL) { 1181 kfree_skb(skb); 1182 return -EAGAIN; 1183 } 1184 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan, 1185 f->fs.eport, f->fs.dmac)) { 1186 cxgb4_l2t_release(f->l2t); 1187 f->l2t = NULL; 1188 kfree_skb(skb); 1189 return -ENOMEM; 1190 } 1191 } 1192 1193 ftid = adapter->tids.ftid_base + fidx; 1194 1195 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr)); 1196 memset(fwr, 0, sizeof(*fwr)); 1197 1198 /* It would be nice to put most of the following in t4_hw.c but most 1199 * of the work is translating the cxgbtool ch_filter_specification 1200 * into the Work Request and the definition of that structure is 1201 * currently in cxgbtool.h which isn't appropriate to pull into the 1202 * common code. We may eventually try to come up with a more neutral 1203 * filter specification structure but for now it's easiest to simply 1204 * put this fairly direct code in line ... 1205 */ 1206 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR)); 1207 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16)); 1208 fwr->tid_to_iq = 1209 htonl(FW_FILTER_WR_TID_V(ftid) | 1210 FW_FILTER_WR_RQTYPE_V(f->fs.type) | 1211 FW_FILTER_WR_NOREPLY_V(0) | 1212 FW_FILTER_WR_IQ_V(f->fs.iq)); 1213 fwr->del_filter_to_l2tix = 1214 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) | 1215 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) | 1216 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) | 1217 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) | 1218 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) | 1219 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) | 1220 FW_FILTER_WR_DMAC_V(f->fs.newdmac) | 1221 FW_FILTER_WR_SMAC_V(f->fs.newsmac) | 1222 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT || 1223 f->fs.newvlan == VLAN_REWRITE) | 1224 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE || 1225 f->fs.newvlan == VLAN_REWRITE) | 1226 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) | 1227 FW_FILTER_WR_TXCHAN_V(f->fs.eport) | 1228 FW_FILTER_WR_PRIO_V(f->fs.prio) | 1229 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0)); 1230 fwr->ethtype = htons(f->fs.val.ethtype); 1231 fwr->ethtypem = htons(f->fs.mask.ethtype); 1232 fwr->frag_to_ovlan_vldm = 1233 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) | 1234 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) | 1235 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) | 1236 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) | 1237 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) | 1238 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld)); 1239 fwr->smac_sel = 0; 1240 fwr->rx_chan_rx_rpl_iq = 1241 htons(FW_FILTER_WR_RX_CHAN_V(0) | 1242 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id)); 1243 fwr->maci_to_matchtypem = 1244 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) | 1245 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) | 1246 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) | 1247 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) | 1248 FW_FILTER_WR_PORT_V(f->fs.val.iport) | 1249 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) | 1250 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) | 1251 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype)); 1252 fwr->ptcl = f->fs.val.proto; 1253 fwr->ptclm = f->fs.mask.proto; 1254 fwr->ttyp = f->fs.val.tos; 1255 fwr->ttypm = f->fs.mask.tos; 1256 fwr->ivlan = htons(f->fs.val.ivlan); 1257 fwr->ivlanm = htons(f->fs.mask.ivlan); 1258 fwr->ovlan = htons(f->fs.val.ovlan); 1259 fwr->ovlanm = htons(f->fs.mask.ovlan); 1260 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip)); 1261 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm)); 1262 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip)); 1263 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm)); 1264 fwr->lp = htons(f->fs.val.lport); 1265 fwr->lpm = htons(f->fs.mask.lport); 1266 fwr->fp = htons(f->fs.val.fport); 1267 fwr->fpm = htons(f->fs.mask.fport); 1268 if (f->fs.newsmac) 1269 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma)); 1270 1271 /* Mark the filter as "pending" and ship off the Filter Work Request. 1272 * When we get the Work Request Reply we'll clear the pending status. 1273 */ 1274 f->pending = 1; 1275 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3); 1276 t4_ofld_send(adapter, skb); 1277 return 0; 1278 } 1279 1280 /* Delete the filter at a specified index. 1281 */ 1282 static int del_filter_wr(struct adapter *adapter, int fidx) 1283 { 1284 struct filter_entry *f = &adapter->tids.ftid_tab[fidx]; 1285 struct sk_buff *skb; 1286 struct fw_filter_wr *fwr; 1287 unsigned int len, ftid; 1288 1289 len = sizeof(*fwr); 1290 ftid = adapter->tids.ftid_base + fidx; 1291 1292 skb = alloc_skb(len, GFP_KERNEL); 1293 if (!skb) 1294 return -ENOMEM; 1295 1296 fwr = (struct fw_filter_wr *)__skb_put(skb, len); 1297 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id); 1298 1299 /* Mark the filter as "pending" and ship off the Filter Work Request. 1300 * When we get the Work Request Reply we'll clear the pending status. 1301 */ 1302 f->pending = 1; 1303 t4_mgmt_tx(adapter, skb); 1304 return 0; 1305 } 1306 1307 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 1308 void *accel_priv, select_queue_fallback_t fallback) 1309 { 1310 int txq; 1311 1312 #ifdef CONFIG_CHELSIO_T4_DCB 1313 /* If a Data Center Bridging has been successfully negotiated on this 1314 * link then we'll use the skb's priority to map it to a TX Queue. 1315 * The skb's priority is determined via the VLAN Tag Priority Code 1316 * Point field. 1317 */ 1318 if (cxgb4_dcb_enabled(dev)) { 1319 u16 vlan_tci; 1320 int err; 1321 1322 err = vlan_get_tag(skb, &vlan_tci); 1323 if (unlikely(err)) { 1324 if (net_ratelimit()) 1325 netdev_warn(dev, 1326 "TX Packet without VLAN Tag on DCB Link\n"); 1327 txq = 0; 1328 } else { 1329 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 1330 #ifdef CONFIG_CHELSIO_T4_FCOE 1331 if (skb->protocol == htons(ETH_P_FCOE)) 1332 txq = skb->priority & 0x7; 1333 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1334 } 1335 return txq; 1336 } 1337 #endif /* CONFIG_CHELSIO_T4_DCB */ 1338 1339 if (select_queue) { 1340 txq = (skb_rx_queue_recorded(skb) 1341 ? skb_get_rx_queue(skb) 1342 : smp_processor_id()); 1343 1344 while (unlikely(txq >= dev->real_num_tx_queues)) 1345 txq -= dev->real_num_tx_queues; 1346 1347 return txq; 1348 } 1349 1350 return fallback(dev, skb) % dev->real_num_tx_queues; 1351 } 1352 1353 static int closest_timer(const struct sge *s, int time) 1354 { 1355 int i, delta, match = 0, min_delta = INT_MAX; 1356 1357 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 1358 delta = time - s->timer_val[i]; 1359 if (delta < 0) 1360 delta = -delta; 1361 if (delta < min_delta) { 1362 min_delta = delta; 1363 match = i; 1364 } 1365 } 1366 return match; 1367 } 1368 1369 static int closest_thres(const struct sge *s, int thres) 1370 { 1371 int i, delta, match = 0, min_delta = INT_MAX; 1372 1373 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 1374 delta = thres - s->counter_val[i]; 1375 if (delta < 0) 1376 delta = -delta; 1377 if (delta < min_delta) { 1378 min_delta = delta; 1379 match = i; 1380 } 1381 } 1382 return match; 1383 } 1384 1385 /** 1386 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1387 * @q: the Rx queue 1388 * @us: the hold-off time in us, or 0 to disable timer 1389 * @cnt: the hold-off packet count, or 0 to disable counter 1390 * 1391 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1392 * one of the two needs to be enabled for the queue to generate interrupts. 1393 */ 1394 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1395 unsigned int us, unsigned int cnt) 1396 { 1397 struct adapter *adap = q->adap; 1398 1399 if ((us | cnt) == 0) 1400 cnt = 1; 1401 1402 if (cnt) { 1403 int err; 1404 u32 v, new_idx; 1405 1406 new_idx = closest_thres(&adap->sge, cnt); 1407 if (q->desc && q->pktcnt_idx != new_idx) { 1408 /* the queue has already been created, update it */ 1409 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1410 FW_PARAMS_PARAM_X_V( 1411 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1412 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1413 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1414 &v, &new_idx); 1415 if (err) 1416 return err; 1417 } 1418 q->pktcnt_idx = new_idx; 1419 } 1420 1421 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1422 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1423 return 0; 1424 } 1425 1426 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1427 { 1428 const struct port_info *pi = netdev_priv(dev); 1429 netdev_features_t changed = dev->features ^ features; 1430 int err; 1431 1432 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1433 return 0; 1434 1435 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1436 -1, -1, -1, 1437 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1438 if (unlikely(err)) 1439 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1440 return err; 1441 } 1442 1443 static int setup_debugfs(struct adapter *adap) 1444 { 1445 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1446 return -1; 1447 1448 #ifdef CONFIG_DEBUG_FS 1449 t4_setup_debugfs(adap); 1450 #endif 1451 return 0; 1452 } 1453 1454 /* 1455 * upper-layer driver support 1456 */ 1457 1458 /* 1459 * Allocate an active-open TID and set it to the supplied value. 1460 */ 1461 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1462 { 1463 int atid = -1; 1464 1465 spin_lock_bh(&t->atid_lock); 1466 if (t->afree) { 1467 union aopen_entry *p = t->afree; 1468 1469 atid = (p - t->atid_tab) + t->atid_base; 1470 t->afree = p->next; 1471 p->data = data; 1472 t->atids_in_use++; 1473 } 1474 spin_unlock_bh(&t->atid_lock); 1475 return atid; 1476 } 1477 EXPORT_SYMBOL(cxgb4_alloc_atid); 1478 1479 /* 1480 * Release an active-open TID. 1481 */ 1482 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1483 { 1484 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1485 1486 spin_lock_bh(&t->atid_lock); 1487 p->next = t->afree; 1488 t->afree = p; 1489 t->atids_in_use--; 1490 spin_unlock_bh(&t->atid_lock); 1491 } 1492 EXPORT_SYMBOL(cxgb4_free_atid); 1493 1494 /* 1495 * Allocate a server TID and set it to the supplied value. 1496 */ 1497 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1498 { 1499 int stid; 1500 1501 spin_lock_bh(&t->stid_lock); 1502 if (family == PF_INET) { 1503 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1504 if (stid < t->nstids) 1505 __set_bit(stid, t->stid_bmap); 1506 else 1507 stid = -1; 1508 } else { 1509 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2); 1510 if (stid < 0) 1511 stid = -1; 1512 } 1513 if (stid >= 0) { 1514 t->stid_tab[stid].data = data; 1515 stid += t->stid_base; 1516 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1517 * This is equivalent to 4 TIDs. With CLIP enabled it 1518 * needs 2 TIDs. 1519 */ 1520 if (family == PF_INET) 1521 t->stids_in_use++; 1522 else 1523 t->stids_in_use += 4; 1524 } 1525 spin_unlock_bh(&t->stid_lock); 1526 return stid; 1527 } 1528 EXPORT_SYMBOL(cxgb4_alloc_stid); 1529 1530 /* Allocate a server filter TID and set it to the supplied value. 1531 */ 1532 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1533 { 1534 int stid; 1535 1536 spin_lock_bh(&t->stid_lock); 1537 if (family == PF_INET) { 1538 stid = find_next_zero_bit(t->stid_bmap, 1539 t->nstids + t->nsftids, t->nstids); 1540 if (stid < (t->nstids + t->nsftids)) 1541 __set_bit(stid, t->stid_bmap); 1542 else 1543 stid = -1; 1544 } else { 1545 stid = -1; 1546 } 1547 if (stid >= 0) { 1548 t->stid_tab[stid].data = data; 1549 stid -= t->nstids; 1550 stid += t->sftid_base; 1551 t->sftids_in_use++; 1552 } 1553 spin_unlock_bh(&t->stid_lock); 1554 return stid; 1555 } 1556 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1557 1558 /* Release a server TID. 1559 */ 1560 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1561 { 1562 /* Is it a server filter TID? */ 1563 if (t->nsftids && (stid >= t->sftid_base)) { 1564 stid -= t->sftid_base; 1565 stid += t->nstids; 1566 } else { 1567 stid -= t->stid_base; 1568 } 1569 1570 spin_lock_bh(&t->stid_lock); 1571 if (family == PF_INET) 1572 __clear_bit(stid, t->stid_bmap); 1573 else 1574 bitmap_release_region(t->stid_bmap, stid, 2); 1575 t->stid_tab[stid].data = NULL; 1576 if (stid < t->nstids) { 1577 if (family == PF_INET) 1578 t->stids_in_use--; 1579 else 1580 t->stids_in_use -= 4; 1581 } else { 1582 t->sftids_in_use--; 1583 } 1584 spin_unlock_bh(&t->stid_lock); 1585 } 1586 EXPORT_SYMBOL(cxgb4_free_stid); 1587 1588 /* 1589 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1590 */ 1591 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1592 unsigned int tid) 1593 { 1594 struct cpl_tid_release *req; 1595 1596 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1597 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req)); 1598 INIT_TP_WR(req, tid); 1599 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1600 } 1601 1602 /* 1603 * Queue a TID release request and if necessary schedule a work queue to 1604 * process it. 1605 */ 1606 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1607 unsigned int tid) 1608 { 1609 void **p = &t->tid_tab[tid]; 1610 struct adapter *adap = container_of(t, struct adapter, tids); 1611 1612 spin_lock_bh(&adap->tid_release_lock); 1613 *p = adap->tid_release_head; 1614 /* Low 2 bits encode the Tx channel number */ 1615 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1616 if (!adap->tid_release_task_busy) { 1617 adap->tid_release_task_busy = true; 1618 queue_work(adap->workq, &adap->tid_release_task); 1619 } 1620 spin_unlock_bh(&adap->tid_release_lock); 1621 } 1622 1623 /* 1624 * Process the list of pending TID release requests. 1625 */ 1626 static void process_tid_release_list(struct work_struct *work) 1627 { 1628 struct sk_buff *skb; 1629 struct adapter *adap; 1630 1631 adap = container_of(work, struct adapter, tid_release_task); 1632 1633 spin_lock_bh(&adap->tid_release_lock); 1634 while (adap->tid_release_head) { 1635 void **p = adap->tid_release_head; 1636 unsigned int chan = (uintptr_t)p & 3; 1637 p = (void *)p - chan; 1638 1639 adap->tid_release_head = *p; 1640 *p = NULL; 1641 spin_unlock_bh(&adap->tid_release_lock); 1642 1643 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1644 GFP_KERNEL))) 1645 schedule_timeout_uninterruptible(1); 1646 1647 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1648 t4_ofld_send(adap, skb); 1649 spin_lock_bh(&adap->tid_release_lock); 1650 } 1651 adap->tid_release_task_busy = false; 1652 spin_unlock_bh(&adap->tid_release_lock); 1653 } 1654 1655 /* 1656 * Release a TID and inform HW. If we are unable to allocate the release 1657 * message we defer to a work queue. 1658 */ 1659 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid) 1660 { 1661 struct sk_buff *skb; 1662 struct adapter *adap = container_of(t, struct adapter, tids); 1663 1664 WARN_ON(tid >= t->ntids); 1665 1666 if (t->tid_tab[tid]) { 1667 t->tid_tab[tid] = NULL; 1668 if (t->hash_base && (tid >= t->hash_base)) 1669 atomic_dec(&t->hash_tids_in_use); 1670 else 1671 atomic_dec(&t->tids_in_use); 1672 } 1673 1674 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1675 if (likely(skb)) { 1676 mk_tid_release(skb, chan, tid); 1677 t4_ofld_send(adap, skb); 1678 } else 1679 cxgb4_queue_tid_release(t, chan, tid); 1680 } 1681 EXPORT_SYMBOL(cxgb4_remove_tid); 1682 1683 /* 1684 * Allocate and initialize the TID tables. Returns 0 on success. 1685 */ 1686 static int tid_init(struct tid_info *t) 1687 { 1688 size_t size; 1689 unsigned int stid_bmap_size; 1690 unsigned int natids = t->natids; 1691 struct adapter *adap = container_of(t, struct adapter, tids); 1692 1693 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1694 size = t->ntids * sizeof(*t->tid_tab) + 1695 natids * sizeof(*t->atid_tab) + 1696 t->nstids * sizeof(*t->stid_tab) + 1697 t->nsftids * sizeof(*t->stid_tab) + 1698 stid_bmap_size * sizeof(long) + 1699 t->nftids * sizeof(*t->ftid_tab) + 1700 t->nsftids * sizeof(*t->ftid_tab); 1701 1702 t->tid_tab = t4_alloc_mem(size); 1703 if (!t->tid_tab) 1704 return -ENOMEM; 1705 1706 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1707 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1708 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1709 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1710 spin_lock_init(&t->stid_lock); 1711 spin_lock_init(&t->atid_lock); 1712 1713 t->stids_in_use = 0; 1714 t->sftids_in_use = 0; 1715 t->afree = NULL; 1716 t->atids_in_use = 0; 1717 atomic_set(&t->tids_in_use, 0); 1718 atomic_set(&t->hash_tids_in_use, 0); 1719 1720 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1721 if (natids) { 1722 while (--natids) 1723 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1724 t->afree = t->atid_tab; 1725 } 1726 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1727 /* Reserve stid 0 for T4/T5 adapters */ 1728 if (!t->stid_base && 1729 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)) 1730 __set_bit(0, t->stid_bmap); 1731 1732 return 0; 1733 } 1734 1735 /** 1736 * cxgb4_create_server - create an IP server 1737 * @dev: the device 1738 * @stid: the server TID 1739 * @sip: local IP address to bind server to 1740 * @sport: the server's TCP port 1741 * @queue: queue to direct messages from this server to 1742 * 1743 * Create an IP server for the given port and address. 1744 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1745 */ 1746 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1747 __be32 sip, __be16 sport, __be16 vlan, 1748 unsigned int queue) 1749 { 1750 unsigned int chan; 1751 struct sk_buff *skb; 1752 struct adapter *adap; 1753 struct cpl_pass_open_req *req; 1754 int ret; 1755 1756 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1757 if (!skb) 1758 return -ENOMEM; 1759 1760 adap = netdev2adap(dev); 1761 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req)); 1762 INIT_TP_WR(req, 0); 1763 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1764 req->local_port = sport; 1765 req->peer_port = htons(0); 1766 req->local_ip = sip; 1767 req->peer_ip = htonl(0); 1768 chan = rxq_to_chan(&adap->sge, queue); 1769 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1770 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1771 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1772 ret = t4_mgmt_tx(adap, skb); 1773 return net_xmit_eval(ret); 1774 } 1775 EXPORT_SYMBOL(cxgb4_create_server); 1776 1777 /* cxgb4_create_server6 - create an IPv6 server 1778 * @dev: the device 1779 * @stid: the server TID 1780 * @sip: local IPv6 address to bind server to 1781 * @sport: the server's TCP port 1782 * @queue: queue to direct messages from this server to 1783 * 1784 * Create an IPv6 server for the given port and address. 1785 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1786 */ 1787 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1788 const struct in6_addr *sip, __be16 sport, 1789 unsigned int queue) 1790 { 1791 unsigned int chan; 1792 struct sk_buff *skb; 1793 struct adapter *adap; 1794 struct cpl_pass_open_req6 *req; 1795 int ret; 1796 1797 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1798 if (!skb) 1799 return -ENOMEM; 1800 1801 adap = netdev2adap(dev); 1802 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req)); 1803 INIT_TP_WR(req, 0); 1804 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1805 req->local_port = sport; 1806 req->peer_port = htons(0); 1807 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1808 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1809 req->peer_ip_hi = cpu_to_be64(0); 1810 req->peer_ip_lo = cpu_to_be64(0); 1811 chan = rxq_to_chan(&adap->sge, queue); 1812 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1813 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1814 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1815 ret = t4_mgmt_tx(adap, skb); 1816 return net_xmit_eval(ret); 1817 } 1818 EXPORT_SYMBOL(cxgb4_create_server6); 1819 1820 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1821 unsigned int queue, bool ipv6) 1822 { 1823 struct sk_buff *skb; 1824 struct adapter *adap; 1825 struct cpl_close_listsvr_req *req; 1826 int ret; 1827 1828 adap = netdev2adap(dev); 1829 1830 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1831 if (!skb) 1832 return -ENOMEM; 1833 1834 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req)); 1835 INIT_TP_WR(req, 0); 1836 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1837 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1838 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1839 ret = t4_mgmt_tx(adap, skb); 1840 return net_xmit_eval(ret); 1841 } 1842 EXPORT_SYMBOL(cxgb4_remove_server); 1843 1844 /** 1845 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1846 * @mtus: the HW MTU table 1847 * @mtu: the target MTU 1848 * @idx: index of selected entry in the MTU table 1849 * 1850 * Returns the index and the value in the HW MTU table that is closest to 1851 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1852 * table, in which case that smallest available value is selected. 1853 */ 1854 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1855 unsigned int *idx) 1856 { 1857 unsigned int i = 0; 1858 1859 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1860 ++i; 1861 if (idx) 1862 *idx = i; 1863 return mtus[i]; 1864 } 1865 EXPORT_SYMBOL(cxgb4_best_mtu); 1866 1867 /** 1868 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1869 * @mtus: the HW MTU table 1870 * @header_size: Header Size 1871 * @data_size_max: maximum Data Segment Size 1872 * @data_size_align: desired Data Segment Size Alignment (2^N) 1873 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1874 * 1875 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1876 * MTU Table based solely on a Maximum MTU parameter, we break that 1877 * parameter up into a Header Size and Maximum Data Segment Size, and 1878 * provide a desired Data Segment Size Alignment. If we find an MTU in 1879 * the Hardware MTU Table which will result in a Data Segment Size with 1880 * the requested alignment _and_ that MTU isn't "too far" from the 1881 * closest MTU, then we'll return that rather than the closest MTU. 1882 */ 1883 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1884 unsigned short header_size, 1885 unsigned short data_size_max, 1886 unsigned short data_size_align, 1887 unsigned int *mtu_idxp) 1888 { 1889 unsigned short max_mtu = header_size + data_size_max; 1890 unsigned short data_size_align_mask = data_size_align - 1; 1891 int mtu_idx, aligned_mtu_idx; 1892 1893 /* Scan the MTU Table till we find an MTU which is larger than our 1894 * Maximum MTU or we reach the end of the table. Along the way, 1895 * record the last MTU found, if any, which will result in a Data 1896 * Segment Length matching the requested alignment. 1897 */ 1898 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1899 unsigned short data_size = mtus[mtu_idx] - header_size; 1900 1901 /* If this MTU minus the Header Size would result in a 1902 * Data Segment Size of the desired alignment, remember it. 1903 */ 1904 if ((data_size & data_size_align_mask) == 0) 1905 aligned_mtu_idx = mtu_idx; 1906 1907 /* If we're not at the end of the Hardware MTU Table and the 1908 * next element is larger than our Maximum MTU, drop out of 1909 * the loop. 1910 */ 1911 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1912 break; 1913 } 1914 1915 /* If we fell out of the loop because we ran to the end of the table, 1916 * then we just have to use the last [largest] entry. 1917 */ 1918 if (mtu_idx == NMTUS) 1919 mtu_idx--; 1920 1921 /* If we found an MTU which resulted in the requested Data Segment 1922 * Length alignment and that's "not far" from the largest MTU which is 1923 * less than or equal to the maximum MTU, then use that. 1924 */ 1925 if (aligned_mtu_idx >= 0 && 1926 mtu_idx - aligned_mtu_idx <= 1) 1927 mtu_idx = aligned_mtu_idx; 1928 1929 /* If the caller has passed in an MTU Index pointer, pass the 1930 * MTU Index back. Return the MTU value. 1931 */ 1932 if (mtu_idxp) 1933 *mtu_idxp = mtu_idx; 1934 return mtus[mtu_idx]; 1935 } 1936 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1937 1938 /** 1939 * cxgb4_port_chan - get the HW channel of a port 1940 * @dev: the net device for the port 1941 * 1942 * Return the HW Tx channel of the given port. 1943 */ 1944 unsigned int cxgb4_port_chan(const struct net_device *dev) 1945 { 1946 return netdev2pinfo(dev)->tx_chan; 1947 } 1948 EXPORT_SYMBOL(cxgb4_port_chan); 1949 1950 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1951 { 1952 struct adapter *adap = netdev2adap(dev); 1953 u32 v1, v2, lp_count, hp_count; 1954 1955 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1956 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1957 if (is_t4(adap->params.chip)) { 1958 lp_count = LP_COUNT_G(v1); 1959 hp_count = HP_COUNT_G(v1); 1960 } else { 1961 lp_count = LP_COUNT_T5_G(v1); 1962 hp_count = HP_COUNT_T5_G(v2); 1963 } 1964 return lpfifo ? lp_count : hp_count; 1965 } 1966 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1967 1968 /** 1969 * cxgb4_port_viid - get the VI id of a port 1970 * @dev: the net device for the port 1971 * 1972 * Return the VI id of the given port. 1973 */ 1974 unsigned int cxgb4_port_viid(const struct net_device *dev) 1975 { 1976 return netdev2pinfo(dev)->viid; 1977 } 1978 EXPORT_SYMBOL(cxgb4_port_viid); 1979 1980 /** 1981 * cxgb4_port_idx - get the index of a port 1982 * @dev: the net device for the port 1983 * 1984 * Return the index of the given port. 1985 */ 1986 unsigned int cxgb4_port_idx(const struct net_device *dev) 1987 { 1988 return netdev2pinfo(dev)->port_id; 1989 } 1990 EXPORT_SYMBOL(cxgb4_port_idx); 1991 1992 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1993 struct tp_tcp_stats *v6) 1994 { 1995 struct adapter *adap = pci_get_drvdata(pdev); 1996 1997 spin_lock(&adap->stats_lock); 1998 t4_tp_get_tcp_stats(adap, v4, v6); 1999 spin_unlock(&adap->stats_lock); 2000 } 2001 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 2002 2003 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 2004 const unsigned int *pgsz_order) 2005 { 2006 struct adapter *adap = netdev2adap(dev); 2007 2008 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 2009 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 2010 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 2011 HPZ3_V(pgsz_order[3])); 2012 } 2013 EXPORT_SYMBOL(cxgb4_iscsi_init); 2014 2015 int cxgb4_flush_eq_cache(struct net_device *dev) 2016 { 2017 struct adapter *adap = netdev2adap(dev); 2018 2019 return t4_sge_ctxt_flush(adap, adap->mbox); 2020 } 2021 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 2022 2023 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 2024 { 2025 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 2026 __be64 indices; 2027 int ret; 2028 2029 spin_lock(&adap->win0_lock); 2030 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 2031 sizeof(indices), (__be32 *)&indices, 2032 T4_MEMORY_READ); 2033 spin_unlock(&adap->win0_lock); 2034 if (!ret) { 2035 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 2036 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 2037 } 2038 return ret; 2039 } 2040 2041 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 2042 u16 size) 2043 { 2044 struct adapter *adap = netdev2adap(dev); 2045 u16 hw_pidx, hw_cidx; 2046 int ret; 2047 2048 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 2049 if (ret) 2050 goto out; 2051 2052 if (pidx != hw_pidx) { 2053 u16 delta; 2054 u32 val; 2055 2056 if (pidx >= hw_pidx) 2057 delta = pidx - hw_pidx; 2058 else 2059 delta = size - hw_pidx + pidx; 2060 2061 if (is_t4(adap->params.chip)) 2062 val = PIDX_V(delta); 2063 else 2064 val = PIDX_T5_V(delta); 2065 wmb(); 2066 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2067 QID_V(qid) | val); 2068 } 2069 out: 2070 return ret; 2071 } 2072 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 2073 2074 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 2075 { 2076 struct adapter *adap; 2077 u32 offset, memtype, memaddr; 2078 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 2079 u32 edc0_end, edc1_end, mc0_end, mc1_end; 2080 int ret; 2081 2082 adap = netdev2adap(dev); 2083 2084 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 2085 2086 /* Figure out where the offset lands in the Memory Type/Address scheme. 2087 * This code assumes that the memory is laid out starting at offset 0 2088 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 2089 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 2090 * MC0, and some have both MC0 and MC1. 2091 */ 2092 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 2093 edc0_size = EDRAM0_SIZE_G(size) << 20; 2094 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 2095 edc1_size = EDRAM1_SIZE_G(size) << 20; 2096 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 2097 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 2098 2099 edc0_end = edc0_size; 2100 edc1_end = edc0_end + edc1_size; 2101 mc0_end = edc1_end + mc0_size; 2102 2103 if (offset < edc0_end) { 2104 memtype = MEM_EDC0; 2105 memaddr = offset; 2106 } else if (offset < edc1_end) { 2107 memtype = MEM_EDC1; 2108 memaddr = offset - edc0_end; 2109 } else { 2110 if (offset < mc0_end) { 2111 memtype = MEM_MC0; 2112 memaddr = offset - edc1_end; 2113 } else if (is_t5(adap->params.chip)) { 2114 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 2115 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 2116 mc1_end = mc0_end + mc1_size; 2117 if (offset < mc1_end) { 2118 memtype = MEM_MC1; 2119 memaddr = offset - mc0_end; 2120 } else { 2121 /* offset beyond the end of any memory */ 2122 goto err; 2123 } 2124 } else { 2125 /* T4/T6 only has a single memory channel */ 2126 goto err; 2127 } 2128 } 2129 2130 spin_lock(&adap->win0_lock); 2131 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 2132 spin_unlock(&adap->win0_lock); 2133 return ret; 2134 2135 err: 2136 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 2137 stag, offset); 2138 return -EINVAL; 2139 } 2140 EXPORT_SYMBOL(cxgb4_read_tpte); 2141 2142 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 2143 { 2144 u32 hi, lo; 2145 struct adapter *adap; 2146 2147 adap = netdev2adap(dev); 2148 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 2149 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 2150 2151 return ((u64)hi << 32) | (u64)lo; 2152 } 2153 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 2154 2155 int cxgb4_bar2_sge_qregs(struct net_device *dev, 2156 unsigned int qid, 2157 enum cxgb4_bar2_qtype qtype, 2158 int user, 2159 u64 *pbar2_qoffset, 2160 unsigned int *pbar2_qid) 2161 { 2162 return t4_bar2_sge_qregs(netdev2adap(dev), 2163 qid, 2164 (qtype == CXGB4_BAR2_QTYPE_EGRESS 2165 ? T4_BAR2_QTYPE_EGRESS 2166 : T4_BAR2_QTYPE_INGRESS), 2167 user, 2168 pbar2_qoffset, 2169 pbar2_qid); 2170 } 2171 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 2172 2173 static struct pci_driver cxgb4_driver; 2174 2175 static void check_neigh_update(struct neighbour *neigh) 2176 { 2177 const struct device *parent; 2178 const struct net_device *netdev = neigh->dev; 2179 2180 if (netdev->priv_flags & IFF_802_1Q_VLAN) 2181 netdev = vlan_dev_real_dev(netdev); 2182 parent = netdev->dev.parent; 2183 if (parent && parent->driver == &cxgb4_driver.driver) 2184 t4_l2t_update(dev_get_drvdata(parent), neigh); 2185 } 2186 2187 static int netevent_cb(struct notifier_block *nb, unsigned long event, 2188 void *data) 2189 { 2190 switch (event) { 2191 case NETEVENT_NEIGH_UPDATE: 2192 check_neigh_update(data); 2193 break; 2194 case NETEVENT_REDIRECT: 2195 default: 2196 break; 2197 } 2198 return 0; 2199 } 2200 2201 static bool netevent_registered; 2202 static struct notifier_block cxgb4_netevent_nb = { 2203 .notifier_call = netevent_cb 2204 }; 2205 2206 static void drain_db_fifo(struct adapter *adap, int usecs) 2207 { 2208 u32 v1, v2, lp_count, hp_count; 2209 2210 do { 2211 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2212 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2213 if (is_t4(adap->params.chip)) { 2214 lp_count = LP_COUNT_G(v1); 2215 hp_count = HP_COUNT_G(v1); 2216 } else { 2217 lp_count = LP_COUNT_T5_G(v1); 2218 hp_count = HP_COUNT_T5_G(v2); 2219 } 2220 2221 if (lp_count == 0 && hp_count == 0) 2222 break; 2223 set_current_state(TASK_UNINTERRUPTIBLE); 2224 schedule_timeout(usecs_to_jiffies(usecs)); 2225 } while (1); 2226 } 2227 2228 static void disable_txq_db(struct sge_txq *q) 2229 { 2230 unsigned long flags; 2231 2232 spin_lock_irqsave(&q->db_lock, flags); 2233 q->db_disabled = 1; 2234 spin_unlock_irqrestore(&q->db_lock, flags); 2235 } 2236 2237 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 2238 { 2239 spin_lock_irq(&q->db_lock); 2240 if (q->db_pidx_inc) { 2241 /* Make sure that all writes to the TX descriptors 2242 * are committed before we tell HW about them. 2243 */ 2244 wmb(); 2245 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2246 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 2247 q->db_pidx_inc = 0; 2248 } 2249 q->db_disabled = 0; 2250 spin_unlock_irq(&q->db_lock); 2251 } 2252 2253 static void disable_dbs(struct adapter *adap) 2254 { 2255 int i; 2256 2257 for_each_ethrxq(&adap->sge, i) 2258 disable_txq_db(&adap->sge.ethtxq[i].q); 2259 for_each_ofldrxq(&adap->sge, i) 2260 disable_txq_db(&adap->sge.ofldtxq[i].q); 2261 for_each_port(adap, i) 2262 disable_txq_db(&adap->sge.ctrlq[i].q); 2263 } 2264 2265 static void enable_dbs(struct adapter *adap) 2266 { 2267 int i; 2268 2269 for_each_ethrxq(&adap->sge, i) 2270 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 2271 for_each_ofldrxq(&adap->sge, i) 2272 enable_txq_db(adap, &adap->sge.ofldtxq[i].q); 2273 for_each_port(adap, i) 2274 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 2275 } 2276 2277 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 2278 { 2279 if (adap->uld_handle[CXGB4_ULD_RDMA]) 2280 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA], 2281 cmd); 2282 } 2283 2284 static void process_db_full(struct work_struct *work) 2285 { 2286 struct adapter *adap; 2287 2288 adap = container_of(work, struct adapter, db_full_task); 2289 2290 drain_db_fifo(adap, dbfifo_drain_delay); 2291 enable_dbs(adap); 2292 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2293 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2294 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2295 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2296 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2297 else 2298 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2299 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2300 } 2301 2302 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2303 { 2304 u16 hw_pidx, hw_cidx; 2305 int ret; 2306 2307 spin_lock_irq(&q->db_lock); 2308 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2309 if (ret) 2310 goto out; 2311 if (q->db_pidx != hw_pidx) { 2312 u16 delta; 2313 u32 val; 2314 2315 if (q->db_pidx >= hw_pidx) 2316 delta = q->db_pidx - hw_pidx; 2317 else 2318 delta = q->size - hw_pidx + q->db_pidx; 2319 2320 if (is_t4(adap->params.chip)) 2321 val = PIDX_V(delta); 2322 else 2323 val = PIDX_T5_V(delta); 2324 wmb(); 2325 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2326 QID_V(q->cntxt_id) | val); 2327 } 2328 out: 2329 q->db_disabled = 0; 2330 q->db_pidx_inc = 0; 2331 spin_unlock_irq(&q->db_lock); 2332 if (ret) 2333 CH_WARN(adap, "DB drop recovery failed.\n"); 2334 } 2335 static void recover_all_queues(struct adapter *adap) 2336 { 2337 int i; 2338 2339 for_each_ethrxq(&adap->sge, i) 2340 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2341 for_each_ofldrxq(&adap->sge, i) 2342 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q); 2343 for_each_port(adap, i) 2344 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2345 } 2346 2347 static void process_db_drop(struct work_struct *work) 2348 { 2349 struct adapter *adap; 2350 2351 adap = container_of(work, struct adapter, db_drop_task); 2352 2353 if (is_t4(adap->params.chip)) { 2354 drain_db_fifo(adap, dbfifo_drain_delay); 2355 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2356 drain_db_fifo(adap, dbfifo_drain_delay); 2357 recover_all_queues(adap); 2358 drain_db_fifo(adap, dbfifo_drain_delay); 2359 enable_dbs(adap); 2360 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2361 } else if (is_t5(adap->params.chip)) { 2362 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2363 u16 qid = (dropped_db >> 15) & 0x1ffff; 2364 u16 pidx_inc = dropped_db & 0x1fff; 2365 u64 bar2_qoffset; 2366 unsigned int bar2_qid; 2367 int ret; 2368 2369 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2370 0, &bar2_qoffset, &bar2_qid); 2371 if (ret) 2372 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2373 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2374 else 2375 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2376 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2377 2378 /* Re-enable BAR2 WC */ 2379 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2380 } 2381 2382 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2383 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2384 } 2385 2386 void t4_db_full(struct adapter *adap) 2387 { 2388 if (is_t4(adap->params.chip)) { 2389 disable_dbs(adap); 2390 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2391 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2392 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2393 queue_work(adap->workq, &adap->db_full_task); 2394 } 2395 } 2396 2397 void t4_db_dropped(struct adapter *adap) 2398 { 2399 if (is_t4(adap->params.chip)) { 2400 disable_dbs(adap); 2401 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2402 } 2403 queue_work(adap->workq, &adap->db_drop_task); 2404 } 2405 2406 static void uld_attach(struct adapter *adap, unsigned int uld) 2407 { 2408 void *handle; 2409 struct cxgb4_lld_info lli; 2410 unsigned short i; 2411 2412 lli.pdev = adap->pdev; 2413 lli.pf = adap->pf; 2414 lli.l2t = adap->l2t; 2415 lli.tids = &adap->tids; 2416 lli.ports = adap->port; 2417 lli.vr = &adap->vres; 2418 lli.mtus = adap->params.mtus; 2419 if (uld == CXGB4_ULD_RDMA) { 2420 lli.rxq_ids = adap->sge.rdma_rxq; 2421 lli.ciq_ids = adap->sge.rdma_ciq; 2422 lli.nrxq = adap->sge.rdmaqs; 2423 lli.nciq = adap->sge.rdmaciqs; 2424 } else if (uld == CXGB4_ULD_ISCSI) { 2425 lli.rxq_ids = adap->sge.ofld_rxq; 2426 lli.nrxq = adap->sge.ofldqsets; 2427 } 2428 lli.ntxq = adap->sge.ofldqsets; 2429 lli.nchan = adap->params.nports; 2430 lli.nports = adap->params.nports; 2431 lli.wr_cred = adap->params.ofldq_wr_cred; 2432 lli.adapter_type = adap->params.chip; 2433 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A)); 2434 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; 2435 lli.udb_density = 1 << adap->params.sge.eq_qpp; 2436 lli.ucq_density = 1 << adap->params.sge.iq_qpp; 2437 lli.filt_mode = adap->params.tp.vlan_pri_map; 2438 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */ 2439 for (i = 0; i < NCHAN; i++) 2440 lli.tx_modq[i] = i; 2441 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A); 2442 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A); 2443 lli.fw_vers = adap->params.fw_vers; 2444 lli.dbfifo_int_thresh = dbfifo_int_thresh; 2445 lli.sge_ingpadboundary = adap->sge.fl_align; 2446 lli.sge_egrstatuspagesize = adap->sge.stat_len; 2447 lli.sge_pktshift = adap->sge.pktshift; 2448 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN; 2449 lli.max_ordird_qp = adap->params.max_ordird_qp; 2450 lli.max_ird_adapter = adap->params.max_ird_adapter; 2451 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl; 2452 lli.nodeid = dev_to_node(adap->pdev_dev); 2453 2454 handle = ulds[uld].add(&lli); 2455 if (IS_ERR(handle)) { 2456 dev_warn(adap->pdev_dev, 2457 "could not attach to the %s driver, error %ld\n", 2458 uld_str[uld], PTR_ERR(handle)); 2459 return; 2460 } 2461 2462 adap->uld_handle[uld] = handle; 2463 2464 if (!netevent_registered) { 2465 register_netevent_notifier(&cxgb4_netevent_nb); 2466 netevent_registered = true; 2467 } 2468 2469 if (adap->flags & FULL_INIT_DONE) 2470 ulds[uld].state_change(handle, CXGB4_STATE_UP); 2471 } 2472 2473 static void attach_ulds(struct adapter *adap) 2474 { 2475 unsigned int i; 2476 2477 spin_lock(&adap_rcu_lock); 2478 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list); 2479 spin_unlock(&adap_rcu_lock); 2480 2481 mutex_lock(&uld_mutex); 2482 list_add_tail(&adap->list_node, &adapter_list); 2483 for (i = 0; i < CXGB4_ULD_MAX; i++) 2484 if (ulds[i].add) 2485 uld_attach(adap, i); 2486 mutex_unlock(&uld_mutex); 2487 } 2488 2489 static void detach_ulds(struct adapter *adap) 2490 { 2491 unsigned int i; 2492 2493 mutex_lock(&uld_mutex); 2494 list_del(&adap->list_node); 2495 for (i = 0; i < CXGB4_ULD_MAX; i++) 2496 if (adap->uld_handle[i]) { 2497 ulds[i].state_change(adap->uld_handle[i], 2498 CXGB4_STATE_DETACH); 2499 adap->uld_handle[i] = NULL; 2500 } 2501 if (netevent_registered && list_empty(&adapter_list)) { 2502 unregister_netevent_notifier(&cxgb4_netevent_nb); 2503 netevent_registered = false; 2504 } 2505 mutex_unlock(&uld_mutex); 2506 2507 spin_lock(&adap_rcu_lock); 2508 list_del_rcu(&adap->rcu_node); 2509 spin_unlock(&adap_rcu_lock); 2510 } 2511 2512 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2513 { 2514 unsigned int i; 2515 2516 mutex_lock(&uld_mutex); 2517 for (i = 0; i < CXGB4_ULD_MAX; i++) 2518 if (adap->uld_handle[i]) 2519 ulds[i].state_change(adap->uld_handle[i], new_state); 2520 mutex_unlock(&uld_mutex); 2521 } 2522 2523 /** 2524 * cxgb4_register_uld - register an upper-layer driver 2525 * @type: the ULD type 2526 * @p: the ULD methods 2527 * 2528 * Registers an upper-layer driver with this driver and notifies the ULD 2529 * about any presently available devices that support its type. Returns 2530 * %-EBUSY if a ULD of the same type is already registered. 2531 */ 2532 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p) 2533 { 2534 int ret = 0; 2535 struct adapter *adap; 2536 2537 if (type >= CXGB4_ULD_MAX) 2538 return -EINVAL; 2539 mutex_lock(&uld_mutex); 2540 if (ulds[type].add) { 2541 ret = -EBUSY; 2542 goto out; 2543 } 2544 ulds[type] = *p; 2545 list_for_each_entry(adap, &adapter_list, list_node) 2546 uld_attach(adap, type); 2547 out: mutex_unlock(&uld_mutex); 2548 return ret; 2549 } 2550 EXPORT_SYMBOL(cxgb4_register_uld); 2551 2552 /** 2553 * cxgb4_unregister_uld - unregister an upper-layer driver 2554 * @type: the ULD type 2555 * 2556 * Unregisters an existing upper-layer driver. 2557 */ 2558 int cxgb4_unregister_uld(enum cxgb4_uld type) 2559 { 2560 struct adapter *adap; 2561 2562 if (type >= CXGB4_ULD_MAX) 2563 return -EINVAL; 2564 mutex_lock(&uld_mutex); 2565 list_for_each_entry(adap, &adapter_list, list_node) 2566 adap->uld_handle[type] = NULL; 2567 ulds[type].add = NULL; 2568 mutex_unlock(&uld_mutex); 2569 return 0; 2570 } 2571 EXPORT_SYMBOL(cxgb4_unregister_uld); 2572 2573 #if IS_ENABLED(CONFIG_IPV6) 2574 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2575 unsigned long event, void *data) 2576 { 2577 struct inet6_ifaddr *ifa = data; 2578 struct net_device *event_dev = ifa->idev->dev; 2579 const struct device *parent = NULL; 2580 #if IS_ENABLED(CONFIG_BONDING) 2581 struct adapter *adap; 2582 #endif 2583 if (event_dev->priv_flags & IFF_802_1Q_VLAN) 2584 event_dev = vlan_dev_real_dev(event_dev); 2585 #if IS_ENABLED(CONFIG_BONDING) 2586 if (event_dev->flags & IFF_MASTER) { 2587 list_for_each_entry(adap, &adapter_list, list_node) { 2588 switch (event) { 2589 case NETDEV_UP: 2590 cxgb4_clip_get(adap->port[0], 2591 (const u32 *)ifa, 1); 2592 break; 2593 case NETDEV_DOWN: 2594 cxgb4_clip_release(adap->port[0], 2595 (const u32 *)ifa, 1); 2596 break; 2597 default: 2598 break; 2599 } 2600 } 2601 return NOTIFY_OK; 2602 } 2603 #endif 2604 2605 if (event_dev) 2606 parent = event_dev->dev.parent; 2607 2608 if (parent && parent->driver == &cxgb4_driver.driver) { 2609 switch (event) { 2610 case NETDEV_UP: 2611 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2612 break; 2613 case NETDEV_DOWN: 2614 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2615 break; 2616 default: 2617 break; 2618 } 2619 } 2620 return NOTIFY_OK; 2621 } 2622 2623 static bool inet6addr_registered; 2624 static struct notifier_block cxgb4_inet6addr_notifier = { 2625 .notifier_call = cxgb4_inet6addr_handler 2626 }; 2627 2628 static void update_clip(const struct adapter *adap) 2629 { 2630 int i; 2631 struct net_device *dev; 2632 int ret; 2633 2634 rcu_read_lock(); 2635 2636 for (i = 0; i < MAX_NPORTS; i++) { 2637 dev = adap->port[i]; 2638 ret = 0; 2639 2640 if (dev) 2641 ret = cxgb4_update_root_dev_clip(dev); 2642 2643 if (ret < 0) 2644 break; 2645 } 2646 rcu_read_unlock(); 2647 } 2648 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2649 2650 /** 2651 * cxgb_up - enable the adapter 2652 * @adap: adapter being enabled 2653 * 2654 * Called when the first port is enabled, this function performs the 2655 * actions necessary to make an adapter operational, such as completing 2656 * the initialization of HW modules, and enabling interrupts. 2657 * 2658 * Must be called with the rtnl lock held. 2659 */ 2660 static int cxgb_up(struct adapter *adap) 2661 { 2662 int err; 2663 2664 err = setup_sge_queues(adap); 2665 if (err) 2666 goto out; 2667 err = setup_rss(adap); 2668 if (err) 2669 goto freeq; 2670 2671 if (adap->flags & USING_MSIX) { 2672 name_msix_vecs(adap); 2673 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2674 adap->msix_info[0].desc, adap); 2675 if (err) 2676 goto irq_err; 2677 2678 err = request_msix_queue_irqs(adap); 2679 if (err) { 2680 free_irq(adap->msix_info[0].vec, adap); 2681 goto irq_err; 2682 } 2683 } else { 2684 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2685 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, 2686 adap->port[0]->name, adap); 2687 if (err) 2688 goto irq_err; 2689 } 2690 enable_rx(adap); 2691 t4_sge_start(adap); 2692 t4_intr_enable(adap); 2693 adap->flags |= FULL_INIT_DONE; 2694 notify_ulds(adap, CXGB4_STATE_UP); 2695 #if IS_ENABLED(CONFIG_IPV6) 2696 update_clip(adap); 2697 #endif 2698 out: 2699 return err; 2700 irq_err: 2701 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2702 freeq: 2703 t4_free_sge_resources(adap); 2704 goto out; 2705 } 2706 2707 static void cxgb_down(struct adapter *adapter) 2708 { 2709 cancel_work_sync(&adapter->tid_release_task); 2710 cancel_work_sync(&adapter->db_full_task); 2711 cancel_work_sync(&adapter->db_drop_task); 2712 adapter->tid_release_task_busy = false; 2713 adapter->tid_release_head = NULL; 2714 2715 t4_sge_stop(adapter); 2716 t4_free_sge_resources(adapter); 2717 adapter->flags &= ~FULL_INIT_DONE; 2718 } 2719 2720 /* 2721 * net_device operations 2722 */ 2723 static int cxgb_open(struct net_device *dev) 2724 { 2725 int err; 2726 struct port_info *pi = netdev_priv(dev); 2727 struct adapter *adapter = pi->adapter; 2728 2729 netif_carrier_off(dev); 2730 2731 if (!(adapter->flags & FULL_INIT_DONE)) { 2732 err = cxgb_up(adapter); 2733 if (err < 0) 2734 return err; 2735 } 2736 2737 err = link_start(dev); 2738 if (!err) 2739 netif_tx_start_all_queues(dev); 2740 return err; 2741 } 2742 2743 static int cxgb_close(struct net_device *dev) 2744 { 2745 struct port_info *pi = netdev_priv(dev); 2746 struct adapter *adapter = pi->adapter; 2747 2748 netif_tx_stop_all_queues(dev); 2749 netif_carrier_off(dev); 2750 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); 2751 } 2752 2753 /* Return an error number if the indicated filter isn't writable ... 2754 */ 2755 static int writable_filter(struct filter_entry *f) 2756 { 2757 if (f->locked) 2758 return -EPERM; 2759 if (f->pending) 2760 return -EBUSY; 2761 2762 return 0; 2763 } 2764 2765 /* Delete the filter at the specified index (if valid). The checks for all 2766 * the common problems with doing this like the filter being locked, currently 2767 * pending in another operation, etc. 2768 */ 2769 static int delete_filter(struct adapter *adapter, unsigned int fidx) 2770 { 2771 struct filter_entry *f; 2772 int ret; 2773 2774 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids) 2775 return -EINVAL; 2776 2777 f = &adapter->tids.ftid_tab[fidx]; 2778 ret = writable_filter(f); 2779 if (ret) 2780 return ret; 2781 if (f->valid) 2782 return del_filter_wr(adapter, fidx); 2783 2784 return 0; 2785 } 2786 2787 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2788 __be32 sip, __be16 sport, __be16 vlan, 2789 unsigned int queue, unsigned char port, unsigned char mask) 2790 { 2791 int ret; 2792 struct filter_entry *f; 2793 struct adapter *adap; 2794 int i; 2795 u8 *val; 2796 2797 adap = netdev2adap(dev); 2798 2799 /* Adjust stid to correct filter index */ 2800 stid -= adap->tids.sftid_base; 2801 stid += adap->tids.nftids; 2802 2803 /* Check to make sure the filter requested is writable ... 2804 */ 2805 f = &adap->tids.ftid_tab[stid]; 2806 ret = writable_filter(f); 2807 if (ret) 2808 return ret; 2809 2810 /* Clear out any old resources being used by the filter before 2811 * we start constructing the new filter. 2812 */ 2813 if (f->valid) 2814 clear_filter(adap, f); 2815 2816 /* Clear out filter specifications */ 2817 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2818 f->fs.val.lport = cpu_to_be16(sport); 2819 f->fs.mask.lport = ~0; 2820 val = (u8 *)&sip; 2821 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2822 for (i = 0; i < 4; i++) { 2823 f->fs.val.lip[i] = val[i]; 2824 f->fs.mask.lip[i] = ~0; 2825 } 2826 if (adap->params.tp.vlan_pri_map & PORT_F) { 2827 f->fs.val.iport = port; 2828 f->fs.mask.iport = mask; 2829 } 2830 } 2831 2832 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2833 f->fs.val.proto = IPPROTO_TCP; 2834 f->fs.mask.proto = ~0; 2835 } 2836 2837 f->fs.dirsteer = 1; 2838 f->fs.iq = queue; 2839 /* Mark filter as locked */ 2840 f->locked = 1; 2841 f->fs.rpttid = 1; 2842 2843 ret = set_filter_wr(adap, stid); 2844 if (ret) { 2845 clear_filter(adap, f); 2846 return ret; 2847 } 2848 2849 return 0; 2850 } 2851 EXPORT_SYMBOL(cxgb4_create_server_filter); 2852 2853 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2854 unsigned int queue, bool ipv6) 2855 { 2856 int ret; 2857 struct filter_entry *f; 2858 struct adapter *adap; 2859 2860 adap = netdev2adap(dev); 2861 2862 /* Adjust stid to correct filter index */ 2863 stid -= adap->tids.sftid_base; 2864 stid += adap->tids.nftids; 2865 2866 f = &adap->tids.ftid_tab[stid]; 2867 /* Unlock the filter */ 2868 f->locked = 0; 2869 2870 ret = delete_filter(adap, stid); 2871 if (ret) 2872 return ret; 2873 2874 return 0; 2875 } 2876 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2877 2878 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev, 2879 struct rtnl_link_stats64 *ns) 2880 { 2881 struct port_stats stats; 2882 struct port_info *p = netdev_priv(dev); 2883 struct adapter *adapter = p->adapter; 2884 2885 /* Block retrieving statistics during EEH error 2886 * recovery. Otherwise, the recovery might fail 2887 * and the PCI device will be removed permanently 2888 */ 2889 spin_lock(&adapter->stats_lock); 2890 if (!netif_device_present(dev)) { 2891 spin_unlock(&adapter->stats_lock); 2892 return ns; 2893 } 2894 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2895 &p->stats_base); 2896 spin_unlock(&adapter->stats_lock); 2897 2898 ns->tx_bytes = stats.tx_octets; 2899 ns->tx_packets = stats.tx_frames; 2900 ns->rx_bytes = stats.rx_octets; 2901 ns->rx_packets = stats.rx_frames; 2902 ns->multicast = stats.rx_mcast_frames; 2903 2904 /* detailed rx_errors */ 2905 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2906 stats.rx_runt; 2907 ns->rx_over_errors = 0; 2908 ns->rx_crc_errors = stats.rx_fcs_err; 2909 ns->rx_frame_errors = stats.rx_symbol_err; 2910 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 + 2911 stats.rx_ovflow2 + stats.rx_ovflow3 + 2912 stats.rx_trunc0 + stats.rx_trunc1 + 2913 stats.rx_trunc2 + stats.rx_trunc3; 2914 ns->rx_missed_errors = 0; 2915 2916 /* detailed tx_errors */ 2917 ns->tx_aborted_errors = 0; 2918 ns->tx_carrier_errors = 0; 2919 ns->tx_fifo_errors = 0; 2920 ns->tx_heartbeat_errors = 0; 2921 ns->tx_window_errors = 0; 2922 2923 ns->tx_errors = stats.tx_error_frames; 2924 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2925 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2926 return ns; 2927 } 2928 2929 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2930 { 2931 unsigned int mbox; 2932 int ret = 0, prtad, devad; 2933 struct port_info *pi = netdev_priv(dev); 2934 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2935 2936 switch (cmd) { 2937 case SIOCGMIIPHY: 2938 if (pi->mdio_addr < 0) 2939 return -EOPNOTSUPP; 2940 data->phy_id = pi->mdio_addr; 2941 break; 2942 case SIOCGMIIREG: 2943 case SIOCSMIIREG: 2944 if (mdio_phy_id_is_c45(data->phy_id)) { 2945 prtad = mdio_phy_id_prtad(data->phy_id); 2946 devad = mdio_phy_id_devad(data->phy_id); 2947 } else if (data->phy_id < 32) { 2948 prtad = data->phy_id; 2949 devad = 0; 2950 data->reg_num &= 0x1f; 2951 } else 2952 return -EINVAL; 2953 2954 mbox = pi->adapter->pf; 2955 if (cmd == SIOCGMIIREG) 2956 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2957 data->reg_num, &data->val_out); 2958 else 2959 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2960 data->reg_num, data->val_in); 2961 break; 2962 default: 2963 return -EOPNOTSUPP; 2964 } 2965 return ret; 2966 } 2967 2968 static void cxgb_set_rxmode(struct net_device *dev) 2969 { 2970 /* unfortunately we can't return errors to the stack */ 2971 set_rxmode(dev, -1, false); 2972 } 2973 2974 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2975 { 2976 int ret; 2977 struct port_info *pi = netdev_priv(dev); 2978 2979 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */ 2980 return -EINVAL; 2981 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2982 -1, -1, -1, true); 2983 if (!ret) 2984 dev->mtu = new_mtu; 2985 return ret; 2986 } 2987 2988 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2989 { 2990 int ret; 2991 struct sockaddr *addr = p; 2992 struct port_info *pi = netdev_priv(dev); 2993 2994 if (!is_valid_ether_addr(addr->sa_data)) 2995 return -EADDRNOTAVAIL; 2996 2997 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, 2998 pi->xact_addr_filt, addr->sa_data, true, true); 2999 if (ret < 0) 3000 return ret; 3001 3002 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3003 pi->xact_addr_filt = ret; 3004 return 0; 3005 } 3006 3007 #ifdef CONFIG_NET_POLL_CONTROLLER 3008 static void cxgb_netpoll(struct net_device *dev) 3009 { 3010 struct port_info *pi = netdev_priv(dev); 3011 struct adapter *adap = pi->adapter; 3012 3013 if (adap->flags & USING_MSIX) { 3014 int i; 3015 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 3016 3017 for (i = pi->nqsets; i; i--, rx++) 3018 t4_sge_intr_msix(0, &rx->rspq); 3019 } else 3020 t4_intr_handler(adap)(0, adap); 3021 } 3022 #endif 3023 3024 static const struct net_device_ops cxgb4_netdev_ops = { 3025 .ndo_open = cxgb_open, 3026 .ndo_stop = cxgb_close, 3027 .ndo_start_xmit = t4_eth_xmit, 3028 .ndo_select_queue = cxgb_select_queue, 3029 .ndo_get_stats64 = cxgb_get_stats, 3030 .ndo_set_rx_mode = cxgb_set_rxmode, 3031 .ndo_set_mac_address = cxgb_set_mac_addr, 3032 .ndo_set_features = cxgb_set_features, 3033 .ndo_validate_addr = eth_validate_addr, 3034 .ndo_do_ioctl = cxgb_ioctl, 3035 .ndo_change_mtu = cxgb_change_mtu, 3036 #ifdef CONFIG_NET_POLL_CONTROLLER 3037 .ndo_poll_controller = cxgb_netpoll, 3038 #endif 3039 #ifdef CONFIG_CHELSIO_T4_FCOE 3040 .ndo_fcoe_enable = cxgb_fcoe_enable, 3041 .ndo_fcoe_disable = cxgb_fcoe_disable, 3042 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3043 #ifdef CONFIG_NET_RX_BUSY_POLL 3044 .ndo_busy_poll = cxgb_busy_poll, 3045 #endif 3046 3047 }; 3048 3049 void t4_fatal_err(struct adapter *adap) 3050 { 3051 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0); 3052 t4_intr_disable(adap); 3053 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3054 } 3055 3056 static void setup_memwin(struct adapter *adap) 3057 { 3058 u32 nic_win_base = t4_get_util_window(adap); 3059 3060 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3061 } 3062 3063 static void setup_memwin_rdma(struct adapter *adap) 3064 { 3065 if (adap->vres.ocq.size) { 3066 u32 start; 3067 unsigned int sz_kb; 3068 3069 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3070 start &= PCI_BASE_ADDRESS_MEM_MASK; 3071 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3072 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3073 t4_write_reg(adap, 3074 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3075 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3076 t4_write_reg(adap, 3077 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3078 adap->vres.ocq.start); 3079 t4_read_reg(adap, 3080 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3081 } 3082 } 3083 3084 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3085 { 3086 u32 v; 3087 int ret; 3088 3089 /* get device capabilities */ 3090 memset(c, 0, sizeof(*c)); 3091 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3092 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3093 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3094 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3095 if (ret < 0) 3096 return ret; 3097 3098 /* select capabilities we'll be using */ 3099 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) { 3100 if (!vf_acls) 3101 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM); 3102 else 3103 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM); 3104 } else if (vf_acls) { 3105 dev_err(adap->pdev_dev, "virtualization ACLs not supported"); 3106 return ret; 3107 } 3108 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3109 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3110 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3111 if (ret < 0) 3112 return ret; 3113 3114 ret = t4_config_glbl_rss(adap, adap->pf, 3115 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3116 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3117 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3118 if (ret < 0) 3119 return ret; 3120 3121 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3122 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3123 FW_CMD_CAP_PF); 3124 if (ret < 0) 3125 return ret; 3126 3127 t4_sge_init(adap); 3128 3129 /* tweak some settings */ 3130 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3131 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3132 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3133 v = t4_read_reg(adap, TP_PIO_DATA_A); 3134 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3135 3136 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3137 adap->params.tp.tx_modq_map = 0xE4; 3138 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3139 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3140 3141 /* associate each Tx modulation queue with consecutive Tx channels */ 3142 v = 0x84218421; 3143 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3144 &v, 1, TP_TX_SCHED_HDR_A); 3145 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3146 &v, 1, TP_TX_SCHED_FIFO_A); 3147 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3148 &v, 1, TP_TX_SCHED_PCMD_A); 3149 3150 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3151 if (is_offload(adap)) { 3152 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3153 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3154 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3155 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3156 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3157 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3158 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3159 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3160 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3161 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3162 } 3163 3164 /* get basic stuff going */ 3165 return t4_early_init(adap, adap->pf); 3166 } 3167 3168 /* 3169 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3170 */ 3171 #define MAX_ATIDS 8192U 3172 3173 /* 3174 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3175 * 3176 * If the firmware we're dealing with has Configuration File support, then 3177 * we use that to perform all configuration 3178 */ 3179 3180 /* 3181 * Tweak configuration based on module parameters, etc. Most of these have 3182 * defaults assigned to them by Firmware Configuration Files (if we're using 3183 * them) but need to be explicitly set if we're using hard-coded 3184 * initialization. But even in the case of using Firmware Configuration 3185 * Files, we'd like to expose the ability to change these via module 3186 * parameters so these are essentially common tweaks/settings for 3187 * Configuration Files and hard-coded initialization ... 3188 */ 3189 static int adap_init0_tweaks(struct adapter *adapter) 3190 { 3191 /* 3192 * Fix up various Host-Dependent Parameters like Page Size, Cache 3193 * Line Size, etc. The firmware default is for a 4KB Page Size and 3194 * 64B Cache Line Size ... 3195 */ 3196 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3197 3198 /* 3199 * Process module parameters which affect early initialization. 3200 */ 3201 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3202 dev_err(&adapter->pdev->dev, 3203 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3204 rx_dma_offset); 3205 rx_dma_offset = 2; 3206 } 3207 t4_set_reg_field(adapter, SGE_CONTROL_A, 3208 PKTSHIFT_V(PKTSHIFT_M), 3209 PKTSHIFT_V(rx_dma_offset)); 3210 3211 /* 3212 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3213 * adds the pseudo header itself. 3214 */ 3215 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3216 CSUM_HAS_PSEUDO_HDR_F, 0); 3217 3218 return 0; 3219 } 3220 3221 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3222 * unto themselves and they contain their own firmware to perform their 3223 * tasks ... 3224 */ 3225 static int phy_aq1202_version(const u8 *phy_fw_data, 3226 size_t phy_fw_size) 3227 { 3228 int offset; 3229 3230 /* At offset 0x8 you're looking for the primary image's 3231 * starting offset which is 3 Bytes wide 3232 * 3233 * At offset 0xa of the primary image, you look for the offset 3234 * of the DRAM segment which is 3 Bytes wide. 3235 * 3236 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3237 * wide 3238 */ 3239 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3240 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3241 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3242 3243 offset = le24(phy_fw_data + 0x8) << 12; 3244 offset = le24(phy_fw_data + offset + 0xa); 3245 return be16(phy_fw_data + offset + 0x27e); 3246 3247 #undef be16 3248 #undef le16 3249 #undef le24 3250 } 3251 3252 static struct info_10gbt_phy_fw { 3253 unsigned int phy_fw_id; /* PCI Device ID */ 3254 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3255 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3256 int phy_flash; /* Has FLASH for PHY Firmware */ 3257 } phy_info_array[] = { 3258 { 3259 PHY_AQ1202_DEVICEID, 3260 PHY_AQ1202_FIRMWARE, 3261 phy_aq1202_version, 3262 1, 3263 }, 3264 { 3265 PHY_BCM84834_DEVICEID, 3266 PHY_BCM84834_FIRMWARE, 3267 NULL, 3268 0, 3269 }, 3270 { 0, NULL, NULL }, 3271 }; 3272 3273 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3274 { 3275 int i; 3276 3277 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3278 if (phy_info_array[i].phy_fw_id == devid) 3279 return &phy_info_array[i]; 3280 } 3281 return NULL; 3282 } 3283 3284 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3285 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3286 * we return a negative error number. If we transfer new firmware we return 1 3287 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3288 */ 3289 static int adap_init0_phy(struct adapter *adap) 3290 { 3291 const struct firmware *phyf; 3292 int ret; 3293 struct info_10gbt_phy_fw *phy_info; 3294 3295 /* Use the device ID to determine which PHY file to flash. 3296 */ 3297 phy_info = find_phy_info(adap->pdev->device); 3298 if (!phy_info) { 3299 dev_warn(adap->pdev_dev, 3300 "No PHY Firmware file found for this PHY\n"); 3301 return -EOPNOTSUPP; 3302 } 3303 3304 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3305 * use that. The adapter firmware provides us with a memory buffer 3306 * where we can load a PHY firmware file from the host if we want to 3307 * override the PHY firmware File in flash. 3308 */ 3309 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3310 adap->pdev_dev); 3311 if (ret < 0) { 3312 /* For adapters without FLASH attached to PHY for their 3313 * firmware, it's obviously a fatal error if we can't get the 3314 * firmware to the adapter. For adapters with PHY firmware 3315 * FLASH storage, it's worth a warning if we can't find the 3316 * PHY Firmware but we'll neuter the error ... 3317 */ 3318 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3319 "/lib/firmware/%s, error %d\n", 3320 phy_info->phy_fw_file, -ret); 3321 if (phy_info->phy_flash) { 3322 int cur_phy_fw_ver = 0; 3323 3324 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3325 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3326 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3327 ret = 0; 3328 } 3329 3330 return ret; 3331 } 3332 3333 /* Load PHY Firmware onto adapter. 3334 */ 3335 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3336 phy_info->phy_fw_version, 3337 (u8 *)phyf->data, phyf->size); 3338 if (ret < 0) 3339 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3340 -ret); 3341 else if (ret > 0) { 3342 int new_phy_fw_ver = 0; 3343 3344 if (phy_info->phy_fw_version) 3345 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3346 phyf->size); 3347 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3348 "Firmware /lib/firmware/%s, version %#x\n", 3349 phy_info->phy_fw_file, new_phy_fw_ver); 3350 } 3351 3352 release_firmware(phyf); 3353 3354 return ret; 3355 } 3356 3357 /* 3358 * Attempt to initialize the adapter via a Firmware Configuration File. 3359 */ 3360 static int adap_init0_config(struct adapter *adapter, int reset) 3361 { 3362 struct fw_caps_config_cmd caps_cmd; 3363 const struct firmware *cf; 3364 unsigned long mtype = 0, maddr = 0; 3365 u32 finiver, finicsum, cfcsum; 3366 int ret; 3367 int config_issued = 0; 3368 char *fw_config_file, fw_config_file_path[256]; 3369 char *config_name = NULL; 3370 3371 /* 3372 * Reset device if necessary. 3373 */ 3374 if (reset) { 3375 ret = t4_fw_reset(adapter, adapter->mbox, 3376 PIORSTMODE_F | PIORST_F); 3377 if (ret < 0) 3378 goto bye; 3379 } 3380 3381 /* If this is a 10Gb/s-BT adapter make sure the chip-external 3382 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 3383 * to be performed after any global adapter RESET above since some 3384 * PHYs only have local RAM copies of the PHY firmware. 3385 */ 3386 if (is_10gbt_device(adapter->pdev->device)) { 3387 ret = adap_init0_phy(adapter); 3388 if (ret < 0) 3389 goto bye; 3390 } 3391 /* 3392 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 3393 * then use that. Otherwise, use the configuration file stored 3394 * in the adapter flash ... 3395 */ 3396 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 3397 case CHELSIO_T4: 3398 fw_config_file = FW4_CFNAME; 3399 break; 3400 case CHELSIO_T5: 3401 fw_config_file = FW5_CFNAME; 3402 break; 3403 case CHELSIO_T6: 3404 fw_config_file = FW6_CFNAME; 3405 break; 3406 default: 3407 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3408 adapter->pdev->device); 3409 ret = -EINVAL; 3410 goto bye; 3411 } 3412 3413 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 3414 if (ret < 0) { 3415 config_name = "On FLASH"; 3416 mtype = FW_MEMTYPE_CF_FLASH; 3417 maddr = t4_flash_cfg_addr(adapter); 3418 } else { 3419 u32 params[7], val[7]; 3420 3421 sprintf(fw_config_file_path, 3422 "/lib/firmware/%s", fw_config_file); 3423 config_name = fw_config_file_path; 3424 3425 if (cf->size >= FLASH_CFG_MAX_SIZE) 3426 ret = -ENOMEM; 3427 else { 3428 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3429 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3430 ret = t4_query_params(adapter, adapter->mbox, 3431 adapter->pf, 0, 1, params, val); 3432 if (ret == 0) { 3433 /* 3434 * For t4_memory_rw() below addresses and 3435 * sizes have to be in terms of multiples of 4 3436 * bytes. So, if the Configuration File isn't 3437 * a multiple of 4 bytes in length we'll have 3438 * to write that out separately since we can't 3439 * guarantee that the bytes following the 3440 * residual byte in the buffer returned by 3441 * request_firmware() are zeroed out ... 3442 */ 3443 size_t resid = cf->size & 0x3; 3444 size_t size = cf->size & ~0x3; 3445 __be32 *data = (__be32 *)cf->data; 3446 3447 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 3448 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 3449 3450 spin_lock(&adapter->win0_lock); 3451 ret = t4_memory_rw(adapter, 0, mtype, maddr, 3452 size, data, T4_MEMORY_WRITE); 3453 if (ret == 0 && resid != 0) { 3454 union { 3455 __be32 word; 3456 char buf[4]; 3457 } last; 3458 int i; 3459 3460 last.word = data[size >> 2]; 3461 for (i = resid; i < 4; i++) 3462 last.buf[i] = 0; 3463 ret = t4_memory_rw(adapter, 0, mtype, 3464 maddr + size, 3465 4, &last.word, 3466 T4_MEMORY_WRITE); 3467 } 3468 spin_unlock(&adapter->win0_lock); 3469 } 3470 } 3471 3472 release_firmware(cf); 3473 if (ret) 3474 goto bye; 3475 } 3476 3477 /* 3478 * Issue a Capability Configuration command to the firmware to get it 3479 * to parse the Configuration File. We don't use t4_fw_config_file() 3480 * because we want the ability to modify various features after we've 3481 * processed the configuration file ... 3482 */ 3483 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3484 caps_cmd.op_to_write = 3485 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3486 FW_CMD_REQUEST_F | 3487 FW_CMD_READ_F); 3488 caps_cmd.cfvalid_to_len16 = 3489 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 3490 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 3491 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 3492 FW_LEN16(caps_cmd)); 3493 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3494 &caps_cmd); 3495 3496 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 3497 * Configuration File in FLASH), our last gasp effort is to use the 3498 * Firmware Configuration File which is embedded in the firmware. A 3499 * very few early versions of the firmware didn't have one embedded 3500 * but we can ignore those. 3501 */ 3502 if (ret == -ENOENT) { 3503 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3504 caps_cmd.op_to_write = 3505 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3506 FW_CMD_REQUEST_F | 3507 FW_CMD_READ_F); 3508 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3509 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 3510 sizeof(caps_cmd), &caps_cmd); 3511 config_name = "Firmware Default"; 3512 } 3513 3514 config_issued = 1; 3515 if (ret < 0) 3516 goto bye; 3517 3518 finiver = ntohl(caps_cmd.finiver); 3519 finicsum = ntohl(caps_cmd.finicsum); 3520 cfcsum = ntohl(caps_cmd.cfcsum); 3521 if (finicsum != cfcsum) 3522 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 3523 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 3524 finicsum, cfcsum); 3525 3526 /* 3527 * And now tell the firmware to use the configuration we just loaded. 3528 */ 3529 caps_cmd.op_to_write = 3530 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3531 FW_CMD_REQUEST_F | 3532 FW_CMD_WRITE_F); 3533 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3534 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3535 NULL); 3536 if (ret < 0) 3537 goto bye; 3538 3539 /* 3540 * Tweak configuration based on system architecture, module 3541 * parameters, etc. 3542 */ 3543 ret = adap_init0_tweaks(adapter); 3544 if (ret < 0) 3545 goto bye; 3546 3547 /* 3548 * And finally tell the firmware to initialize itself using the 3549 * parameters from the Configuration File. 3550 */ 3551 ret = t4_fw_initialize(adapter, adapter->mbox); 3552 if (ret < 0) 3553 goto bye; 3554 3555 /* Emit Firmware Configuration File information and return 3556 * successfully. 3557 */ 3558 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 3559 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 3560 config_name, finiver, cfcsum); 3561 return 0; 3562 3563 /* 3564 * Something bad happened. Return the error ... (If the "error" 3565 * is that there's no Configuration File on the adapter we don't 3566 * want to issue a warning since this is fairly common.) 3567 */ 3568 bye: 3569 if (config_issued && ret != -ENOENT) 3570 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 3571 config_name, -ret); 3572 return ret; 3573 } 3574 3575 static struct fw_info fw_info_array[] = { 3576 { 3577 .chip = CHELSIO_T4, 3578 .fs_name = FW4_CFNAME, 3579 .fw_mod_name = FW4_FNAME, 3580 .fw_hdr = { 3581 .chip = FW_HDR_CHIP_T4, 3582 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 3583 .intfver_nic = FW_INTFVER(T4, NIC), 3584 .intfver_vnic = FW_INTFVER(T4, VNIC), 3585 .intfver_ri = FW_INTFVER(T4, RI), 3586 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3587 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3588 }, 3589 }, { 3590 .chip = CHELSIO_T5, 3591 .fs_name = FW5_CFNAME, 3592 .fw_mod_name = FW5_FNAME, 3593 .fw_hdr = { 3594 .chip = FW_HDR_CHIP_T5, 3595 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 3596 .intfver_nic = FW_INTFVER(T5, NIC), 3597 .intfver_vnic = FW_INTFVER(T5, VNIC), 3598 .intfver_ri = FW_INTFVER(T5, RI), 3599 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3600 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3601 }, 3602 }, { 3603 .chip = CHELSIO_T6, 3604 .fs_name = FW6_CFNAME, 3605 .fw_mod_name = FW6_FNAME, 3606 .fw_hdr = { 3607 .chip = FW_HDR_CHIP_T6, 3608 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 3609 .intfver_nic = FW_INTFVER(T6, NIC), 3610 .intfver_vnic = FW_INTFVER(T6, VNIC), 3611 .intfver_ofld = FW_INTFVER(T6, OFLD), 3612 .intfver_ri = FW_INTFVER(T6, RI), 3613 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3614 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3615 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3616 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3617 }, 3618 } 3619 3620 }; 3621 3622 static struct fw_info *find_fw_info(int chip) 3623 { 3624 int i; 3625 3626 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 3627 if (fw_info_array[i].chip == chip) 3628 return &fw_info_array[i]; 3629 } 3630 return NULL; 3631 } 3632 3633 /* 3634 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3635 */ 3636 static int adap_init0(struct adapter *adap) 3637 { 3638 int ret; 3639 u32 v, port_vec; 3640 enum dev_state state; 3641 u32 params[7], val[7]; 3642 struct fw_caps_config_cmd caps_cmd; 3643 int reset = 1; 3644 3645 /* Grab Firmware Device Log parameters as early as possible so we have 3646 * access to it for debugging, etc. 3647 */ 3648 ret = t4_init_devlog_params(adap); 3649 if (ret < 0) 3650 return ret; 3651 3652 /* Contact FW, advertising Master capability */ 3653 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 3654 if (ret < 0) { 3655 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 3656 ret); 3657 return ret; 3658 } 3659 if (ret == adap->mbox) 3660 adap->flags |= MASTER_PF; 3661 3662 /* 3663 * If we're the Master PF Driver and the device is uninitialized, 3664 * then let's consider upgrading the firmware ... (We always want 3665 * to check the firmware version number in order to A. get it for 3666 * later reporting and B. to warn if the currently loaded firmware 3667 * is excessively mismatched relative to the driver.) 3668 */ 3669 t4_get_fw_version(adap, &adap->params.fw_vers); 3670 t4_get_tp_version(adap, &adap->params.tp_vers); 3671 ret = t4_check_fw_version(adap); 3672 /* If firmware is too old (not supported by driver) force an update. */ 3673 if (ret == -EFAULT) 3674 state = DEV_STATE_UNINIT; 3675 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { 3676 struct fw_info *fw_info; 3677 struct fw_hdr *card_fw; 3678 const struct firmware *fw; 3679 const u8 *fw_data = NULL; 3680 unsigned int fw_size = 0; 3681 3682 /* This is the firmware whose headers the driver was compiled 3683 * against 3684 */ 3685 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 3686 if (fw_info == NULL) { 3687 dev_err(adap->pdev_dev, 3688 "unable to get firmware info for chip %d.\n", 3689 CHELSIO_CHIP_VERSION(adap->params.chip)); 3690 return -EINVAL; 3691 } 3692 3693 /* allocate memory to read the header of the firmware on the 3694 * card 3695 */ 3696 card_fw = t4_alloc_mem(sizeof(*card_fw)); 3697 3698 /* Get FW from from /lib/firmware/ */ 3699 ret = request_firmware(&fw, fw_info->fw_mod_name, 3700 adap->pdev_dev); 3701 if (ret < 0) { 3702 dev_err(adap->pdev_dev, 3703 "unable to load firmware image %s, error %d\n", 3704 fw_info->fw_mod_name, ret); 3705 } else { 3706 fw_data = fw->data; 3707 fw_size = fw->size; 3708 } 3709 3710 /* upgrade FW logic */ 3711 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 3712 state, &reset); 3713 3714 /* Cleaning up */ 3715 release_firmware(fw); 3716 t4_free_mem(card_fw); 3717 3718 if (ret < 0) 3719 goto bye; 3720 } 3721 3722 /* 3723 * Grab VPD parameters. This should be done after we establish a 3724 * connection to the firmware since some of the VPD parameters 3725 * (notably the Core Clock frequency) are retrieved via requests to 3726 * the firmware. On the other hand, we need these fairly early on 3727 * so we do this right after getting ahold of the firmware. 3728 */ 3729 ret = t4_get_vpd_params(adap, &adap->params.vpd); 3730 if (ret < 0) 3731 goto bye; 3732 3733 /* 3734 * Find out what ports are available to us. Note that we need to do 3735 * this before calling adap_init0_no_config() since it needs nports 3736 * and portvec ... 3737 */ 3738 v = 3739 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3740 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 3741 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 3742 if (ret < 0) 3743 goto bye; 3744 3745 adap->params.nports = hweight32(port_vec); 3746 adap->params.portvec = port_vec; 3747 3748 /* If the firmware is initialized already, emit a simply note to that 3749 * effect. Otherwise, it's time to try initializing the adapter. 3750 */ 3751 if (state == DEV_STATE_INIT) { 3752 dev_info(adap->pdev_dev, "Coming up as %s: "\ 3753 "Adapter already initialized\n", 3754 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 3755 } else { 3756 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 3757 "Initializing adapter\n"); 3758 3759 /* Find out whether we're dealing with a version of the 3760 * firmware which has configuration file support. 3761 */ 3762 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3763 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3764 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 3765 params, val); 3766 3767 /* If the firmware doesn't support Configuration Files, 3768 * return an error. 3769 */ 3770 if (ret < 0) { 3771 dev_err(adap->pdev_dev, "firmware doesn't support " 3772 "Firmware Configuration Files\n"); 3773 goto bye; 3774 } 3775 3776 /* The firmware provides us with a memory buffer where we can 3777 * load a Configuration File from the host if we want to 3778 * override the Configuration File in flash. 3779 */ 3780 ret = adap_init0_config(adap, reset); 3781 if (ret == -ENOENT) { 3782 dev_err(adap->pdev_dev, "no Configuration File " 3783 "present on adapter.\n"); 3784 goto bye; 3785 } 3786 if (ret < 0) { 3787 dev_err(adap->pdev_dev, "could not initialize " 3788 "adapter, error %d\n", -ret); 3789 goto bye; 3790 } 3791 } 3792 3793 /* Give the SGE code a chance to pull in anything that it needs ... 3794 * Note that this must be called after we retrieve our VPD parameters 3795 * in order to know how to convert core ticks to seconds, etc. 3796 */ 3797 ret = t4_sge_init(adap); 3798 if (ret < 0) 3799 goto bye; 3800 3801 if (is_bypass_device(adap->pdev->device)) 3802 adap->params.bypass = 1; 3803 3804 /* 3805 * Grab some of our basic fundamental operating parameters. 3806 */ 3807 #define FW_PARAM_DEV(param) \ 3808 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 3809 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 3810 3811 #define FW_PARAM_PFVF(param) \ 3812 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 3813 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 3814 FW_PARAMS_PARAM_Y_V(0) | \ 3815 FW_PARAMS_PARAM_Z_V(0) 3816 3817 params[0] = FW_PARAM_PFVF(EQ_START); 3818 params[1] = FW_PARAM_PFVF(L2T_START); 3819 params[2] = FW_PARAM_PFVF(L2T_END); 3820 params[3] = FW_PARAM_PFVF(FILTER_START); 3821 params[4] = FW_PARAM_PFVF(FILTER_END); 3822 params[5] = FW_PARAM_PFVF(IQFLINT_START); 3823 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 3824 if (ret < 0) 3825 goto bye; 3826 adap->sge.egr_start = val[0]; 3827 adap->l2t_start = val[1]; 3828 adap->l2t_end = val[2]; 3829 adap->tids.ftid_base = val[3]; 3830 adap->tids.nftids = val[4] - val[3] + 1; 3831 adap->sge.ingr_start = val[5]; 3832 3833 /* qids (ingress/egress) returned from firmware can be anywhere 3834 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 3835 * Hence driver needs to allocate memory for this range to 3836 * store the queue info. Get the highest IQFLINT/EQ index returned 3837 * in FW_EQ_*_CMD.alloc command. 3838 */ 3839 params[0] = FW_PARAM_PFVF(EQ_END); 3840 params[1] = FW_PARAM_PFVF(IQFLINT_END); 3841 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3842 if (ret < 0) 3843 goto bye; 3844 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 3845 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 3846 3847 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 3848 sizeof(*adap->sge.egr_map), GFP_KERNEL); 3849 if (!adap->sge.egr_map) { 3850 ret = -ENOMEM; 3851 goto bye; 3852 } 3853 3854 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 3855 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 3856 if (!adap->sge.ingr_map) { 3857 ret = -ENOMEM; 3858 goto bye; 3859 } 3860 3861 /* Allocate the memory for the vaious egress queue bitmaps 3862 * ie starving_fl, txq_maperr and blocked_fl. 3863 */ 3864 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3865 sizeof(long), GFP_KERNEL); 3866 if (!adap->sge.starving_fl) { 3867 ret = -ENOMEM; 3868 goto bye; 3869 } 3870 3871 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3872 sizeof(long), GFP_KERNEL); 3873 if (!adap->sge.txq_maperr) { 3874 ret = -ENOMEM; 3875 goto bye; 3876 } 3877 3878 #ifdef CONFIG_DEBUG_FS 3879 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3880 sizeof(long), GFP_KERNEL); 3881 if (!adap->sge.blocked_fl) { 3882 ret = -ENOMEM; 3883 goto bye; 3884 } 3885 #endif 3886 3887 params[0] = FW_PARAM_PFVF(CLIP_START); 3888 params[1] = FW_PARAM_PFVF(CLIP_END); 3889 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3890 if (ret < 0) 3891 goto bye; 3892 adap->clipt_start = val[0]; 3893 adap->clipt_end = val[1]; 3894 3895 /* query params related to active filter region */ 3896 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 3897 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 3898 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3899 /* If Active filter size is set we enable establishing 3900 * offload connection through firmware work request 3901 */ 3902 if ((val[0] != val[1]) && (ret >= 0)) { 3903 adap->flags |= FW_OFLD_CONN; 3904 adap->tids.aftid_base = val[0]; 3905 adap->tids.aftid_end = val[1]; 3906 } 3907 3908 /* If we're running on newer firmware, let it know that we're 3909 * prepared to deal with encapsulated CPL messages. Older 3910 * firmware won't understand this and we'll just get 3911 * unencapsulated messages ... 3912 */ 3913 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3914 val[0] = 1; 3915 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 3916 3917 /* 3918 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 3919 * capability. Earlier versions of the firmware didn't have the 3920 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 3921 * permission to use ULPTX MEMWRITE DSGL. 3922 */ 3923 if (is_t4(adap->params.chip)) { 3924 adap->params.ulptx_memwrite_dsgl = false; 3925 } else { 3926 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 3927 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3928 1, params, val); 3929 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 3930 } 3931 3932 /* 3933 * Get device capabilities so we can determine what resources we need 3934 * to manage. 3935 */ 3936 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3937 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3938 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3939 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3940 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 3941 &caps_cmd); 3942 if (ret < 0) 3943 goto bye; 3944 3945 if (caps_cmd.ofldcaps) { 3946 /* query offload-related parameters */ 3947 params[0] = FW_PARAM_DEV(NTID); 3948 params[1] = FW_PARAM_PFVF(SERVER_START); 3949 params[2] = FW_PARAM_PFVF(SERVER_END); 3950 params[3] = FW_PARAM_PFVF(TDDP_START); 3951 params[4] = FW_PARAM_PFVF(TDDP_END); 3952 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3953 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3954 params, val); 3955 if (ret < 0) 3956 goto bye; 3957 adap->tids.ntids = val[0]; 3958 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 3959 adap->tids.stid_base = val[1]; 3960 adap->tids.nstids = val[2] - val[1] + 1; 3961 /* 3962 * Setup server filter region. Divide the available filter 3963 * region into two parts. Regular filters get 1/3rd and server 3964 * filters get 2/3rd part. This is only enabled if workarond 3965 * path is enabled. 3966 * 1. For regular filters. 3967 * 2. Server filter: This are special filters which are used 3968 * to redirect SYN packets to offload queue. 3969 */ 3970 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { 3971 adap->tids.sftid_base = adap->tids.ftid_base + 3972 DIV_ROUND_UP(adap->tids.nftids, 3); 3973 adap->tids.nsftids = adap->tids.nftids - 3974 DIV_ROUND_UP(adap->tids.nftids, 3); 3975 adap->tids.nftids = adap->tids.sftid_base - 3976 adap->tids.ftid_base; 3977 } 3978 adap->vres.ddp.start = val[3]; 3979 adap->vres.ddp.size = val[4] - val[3] + 1; 3980 adap->params.ofldq_wr_cred = val[5]; 3981 3982 adap->params.offload = 1; 3983 } 3984 if (caps_cmd.rdmacaps) { 3985 params[0] = FW_PARAM_PFVF(STAG_START); 3986 params[1] = FW_PARAM_PFVF(STAG_END); 3987 params[2] = FW_PARAM_PFVF(RQ_START); 3988 params[3] = FW_PARAM_PFVF(RQ_END); 3989 params[4] = FW_PARAM_PFVF(PBL_START); 3990 params[5] = FW_PARAM_PFVF(PBL_END); 3991 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3992 params, val); 3993 if (ret < 0) 3994 goto bye; 3995 adap->vres.stag.start = val[0]; 3996 adap->vres.stag.size = val[1] - val[0] + 1; 3997 adap->vres.rq.start = val[2]; 3998 adap->vres.rq.size = val[3] - val[2] + 1; 3999 adap->vres.pbl.start = val[4]; 4000 adap->vres.pbl.size = val[5] - val[4] + 1; 4001 4002 params[0] = FW_PARAM_PFVF(SQRQ_START); 4003 params[1] = FW_PARAM_PFVF(SQRQ_END); 4004 params[2] = FW_PARAM_PFVF(CQ_START); 4005 params[3] = FW_PARAM_PFVF(CQ_END); 4006 params[4] = FW_PARAM_PFVF(OCQ_START); 4007 params[5] = FW_PARAM_PFVF(OCQ_END); 4008 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 4009 val); 4010 if (ret < 0) 4011 goto bye; 4012 adap->vres.qp.start = val[0]; 4013 adap->vres.qp.size = val[1] - val[0] + 1; 4014 adap->vres.cq.start = val[2]; 4015 adap->vres.cq.size = val[3] - val[2] + 1; 4016 adap->vres.ocq.start = val[4]; 4017 adap->vres.ocq.size = val[5] - val[4] + 1; 4018 4019 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4020 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4021 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4022 val); 4023 if (ret < 0) { 4024 adap->params.max_ordird_qp = 8; 4025 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4026 ret = 0; 4027 } else { 4028 adap->params.max_ordird_qp = val[0]; 4029 adap->params.max_ird_adapter = val[1]; 4030 } 4031 dev_info(adap->pdev_dev, 4032 "max_ordird_qp %d max_ird_adapter %d\n", 4033 adap->params.max_ordird_qp, 4034 adap->params.max_ird_adapter); 4035 } 4036 if (caps_cmd.iscsicaps) { 4037 params[0] = FW_PARAM_PFVF(ISCSI_START); 4038 params[1] = FW_PARAM_PFVF(ISCSI_END); 4039 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4040 params, val); 4041 if (ret < 0) 4042 goto bye; 4043 adap->vres.iscsi.start = val[0]; 4044 adap->vres.iscsi.size = val[1] - val[0] + 1; 4045 } 4046 #undef FW_PARAM_PFVF 4047 #undef FW_PARAM_DEV 4048 4049 /* The MTU/MSS Table is initialized by now, so load their values. If 4050 * we're initializing the adapter, then we'll make any modifications 4051 * we want to the MTU/MSS Table and also initialize the congestion 4052 * parameters. 4053 */ 4054 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4055 if (state != DEV_STATE_INIT) { 4056 int i; 4057 4058 /* The default MTU Table contains values 1492 and 1500. 4059 * However, for TCP, it's better to have two values which are 4060 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4061 * This allows us to have a TCP Data Payload which is a 4062 * multiple of 8 regardless of what combination of TCP Options 4063 * are in use (always a multiple of 4 bytes) which is 4064 * important for performance reasons. For instance, if no 4065 * options are in use, then we have a 20-byte IP header and a 4066 * 20-byte TCP header. In this case, a 1500-byte MSS would 4067 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4068 * which is not a multiple of 8. So using an MSS of 1488 in 4069 * this case results in a TCP Data Payload of 1448 bytes which 4070 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4071 * Stamps have been negotiated, then an MTU of 1500 bytes 4072 * results in a TCP Data Payload of 1448 bytes which, as 4073 * above, is a multiple of 8 bytes ... 4074 */ 4075 for (i = 0; i < NMTUS; i++) 4076 if (adap->params.mtus[i] == 1492) { 4077 adap->params.mtus[i] = 1488; 4078 break; 4079 } 4080 4081 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4082 adap->params.b_wnd); 4083 } 4084 t4_init_sge_params(adap); 4085 adap->flags |= FW_OK; 4086 t4_init_tp_params(adap); 4087 return 0; 4088 4089 /* 4090 * Something bad happened. If a command timed out or failed with EIO 4091 * FW does not operate within its spec or something catastrophic 4092 * happened to HW/FW, stop issuing commands. 4093 */ 4094 bye: 4095 kfree(adap->sge.egr_map); 4096 kfree(adap->sge.ingr_map); 4097 kfree(adap->sge.starving_fl); 4098 kfree(adap->sge.txq_maperr); 4099 #ifdef CONFIG_DEBUG_FS 4100 kfree(adap->sge.blocked_fl); 4101 #endif 4102 if (ret != -ETIMEDOUT && ret != -EIO) 4103 t4_fw_bye(adap, adap->mbox); 4104 return ret; 4105 } 4106 4107 /* EEH callbacks */ 4108 4109 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4110 pci_channel_state_t state) 4111 { 4112 int i; 4113 struct adapter *adap = pci_get_drvdata(pdev); 4114 4115 if (!adap) 4116 goto out; 4117 4118 rtnl_lock(); 4119 adap->flags &= ~FW_OK; 4120 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4121 spin_lock(&adap->stats_lock); 4122 for_each_port(adap, i) { 4123 struct net_device *dev = adap->port[i]; 4124 4125 netif_device_detach(dev); 4126 netif_carrier_off(dev); 4127 } 4128 spin_unlock(&adap->stats_lock); 4129 disable_interrupts(adap); 4130 if (adap->flags & FULL_INIT_DONE) 4131 cxgb_down(adap); 4132 rtnl_unlock(); 4133 if ((adap->flags & DEV_ENABLED)) { 4134 pci_disable_device(pdev); 4135 adap->flags &= ~DEV_ENABLED; 4136 } 4137 out: return state == pci_channel_io_perm_failure ? 4138 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4139 } 4140 4141 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4142 { 4143 int i, ret; 4144 struct fw_caps_config_cmd c; 4145 struct adapter *adap = pci_get_drvdata(pdev); 4146 4147 if (!adap) { 4148 pci_restore_state(pdev); 4149 pci_save_state(pdev); 4150 return PCI_ERS_RESULT_RECOVERED; 4151 } 4152 4153 if (!(adap->flags & DEV_ENABLED)) { 4154 if (pci_enable_device(pdev)) { 4155 dev_err(&pdev->dev, "Cannot reenable PCI " 4156 "device after reset\n"); 4157 return PCI_ERS_RESULT_DISCONNECT; 4158 } 4159 adap->flags |= DEV_ENABLED; 4160 } 4161 4162 pci_set_master(pdev); 4163 pci_restore_state(pdev); 4164 pci_save_state(pdev); 4165 pci_cleanup_aer_uncorrect_error_status(pdev); 4166 4167 if (t4_wait_dev_ready(adap->regs) < 0) 4168 return PCI_ERS_RESULT_DISCONNECT; 4169 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 4170 return PCI_ERS_RESULT_DISCONNECT; 4171 adap->flags |= FW_OK; 4172 if (adap_init1(adap, &c)) 4173 return PCI_ERS_RESULT_DISCONNECT; 4174 4175 for_each_port(adap, i) { 4176 struct port_info *p = adap2pinfo(adap, i); 4177 4178 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, 4179 NULL, NULL); 4180 if (ret < 0) 4181 return PCI_ERS_RESULT_DISCONNECT; 4182 p->viid = ret; 4183 p->xact_addr_filt = -1; 4184 } 4185 4186 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4187 adap->params.b_wnd); 4188 setup_memwin(adap); 4189 if (cxgb_up(adap)) 4190 return PCI_ERS_RESULT_DISCONNECT; 4191 return PCI_ERS_RESULT_RECOVERED; 4192 } 4193 4194 static void eeh_resume(struct pci_dev *pdev) 4195 { 4196 int i; 4197 struct adapter *adap = pci_get_drvdata(pdev); 4198 4199 if (!adap) 4200 return; 4201 4202 rtnl_lock(); 4203 for_each_port(adap, i) { 4204 struct net_device *dev = adap->port[i]; 4205 4206 if (netif_running(dev)) { 4207 link_start(dev); 4208 cxgb_set_rxmode(dev); 4209 } 4210 netif_device_attach(dev); 4211 } 4212 rtnl_unlock(); 4213 } 4214 4215 static const struct pci_error_handlers cxgb4_eeh = { 4216 .error_detected = eeh_err_detected, 4217 .slot_reset = eeh_slot_reset, 4218 .resume = eeh_resume, 4219 }; 4220 4221 static inline bool is_x_10g_port(const struct link_config *lc) 4222 { 4223 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || 4224 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0; 4225 } 4226 4227 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 4228 unsigned int us, unsigned int cnt, 4229 unsigned int size, unsigned int iqe_size) 4230 { 4231 q->adap = adap; 4232 cxgb4_set_rspq_intr_params(q, us, cnt); 4233 q->iqe_len = iqe_size; 4234 q->size = size; 4235 } 4236 4237 /* 4238 * Perform default configuration of DMA queues depending on the number and type 4239 * of ports we found and the number of available CPUs. Most settings can be 4240 * modified by the admin prior to actual use. 4241 */ 4242 static void cfg_queues(struct adapter *adap) 4243 { 4244 struct sge *s = &adap->sge; 4245 int i, n10g = 0, qidx = 0; 4246 #ifndef CONFIG_CHELSIO_T4_DCB 4247 int q10g = 0; 4248 #endif 4249 int ciq_size; 4250 4251 for_each_port(adap, i) 4252 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 4253 #ifdef CONFIG_CHELSIO_T4_DCB 4254 /* For Data Center Bridging support we need to be able to support up 4255 * to 8 Traffic Priorities; each of which will be assigned to its 4256 * own TX Queue in order to prevent Head-Of-Line Blocking. 4257 */ 4258 if (adap->params.nports * 8 > MAX_ETH_QSETS) { 4259 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", 4260 MAX_ETH_QSETS, adap->params.nports * 8); 4261 BUG_ON(1); 4262 } 4263 4264 for_each_port(adap, i) { 4265 struct port_info *pi = adap2pinfo(adap, i); 4266 4267 pi->first_qset = qidx; 4268 pi->nqsets = 8; 4269 qidx += pi->nqsets; 4270 } 4271 #else /* !CONFIG_CHELSIO_T4_DCB */ 4272 /* 4273 * We default to 1 queue per non-10G port and up to # of cores queues 4274 * per 10G port. 4275 */ 4276 if (n10g) 4277 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; 4278 if (q10g > netif_get_num_default_rss_queues()) 4279 q10g = netif_get_num_default_rss_queues(); 4280 4281 for_each_port(adap, i) { 4282 struct port_info *pi = adap2pinfo(adap, i); 4283 4284 pi->first_qset = qidx; 4285 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 4286 qidx += pi->nqsets; 4287 } 4288 #endif /* !CONFIG_CHELSIO_T4_DCB */ 4289 4290 s->ethqsets = qidx; 4291 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 4292 4293 if (is_offload(adap)) { 4294 /* 4295 * For offload we use 1 queue/channel if all ports are up to 1G, 4296 * otherwise we divide all available queues amongst the channels 4297 * capped by the number of available cores. 4298 */ 4299 if (n10g) { 4300 i = min_t(int, ARRAY_SIZE(s->ofldrxq), 4301 num_online_cpus()); 4302 s->ofldqsets = roundup(i, adap->params.nports); 4303 } else 4304 s->ofldqsets = adap->params.nports; 4305 /* For RDMA one Rx queue per channel suffices */ 4306 s->rdmaqs = adap->params.nports; 4307 /* Try and allow at least 1 CIQ per cpu rounding down 4308 * to the number of ports, with a minimum of 1 per port. 4309 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port. 4310 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port. 4311 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port. 4312 */ 4313 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus()); 4314 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) * 4315 adap->params.nports; 4316 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports); 4317 } 4318 4319 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 4320 struct sge_eth_rxq *r = &s->ethrxq[i]; 4321 4322 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 4323 r->fl.size = 72; 4324 } 4325 4326 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 4327 s->ethtxq[i].q.size = 1024; 4328 4329 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 4330 s->ctrlq[i].q.size = 512; 4331 4332 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) 4333 s->ofldtxq[i].q.size = 1024; 4334 4335 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) { 4336 struct sge_ofld_rxq *r = &s->ofldrxq[i]; 4337 4338 init_rspq(adap, &r->rspq, 5, 1, 1024, 64); 4339 r->rspq.uld = CXGB4_ULD_ISCSI; 4340 r->fl.size = 72; 4341 } 4342 4343 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) { 4344 struct sge_ofld_rxq *r = &s->rdmarxq[i]; 4345 4346 init_rspq(adap, &r->rspq, 5, 1, 511, 64); 4347 r->rspq.uld = CXGB4_ULD_RDMA; 4348 r->fl.size = 72; 4349 } 4350 4351 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids; 4352 if (ciq_size > SGE_MAX_IQ_SIZE) { 4353 CH_WARN(adap, "CIQ size too small for available IQs\n"); 4354 ciq_size = SGE_MAX_IQ_SIZE; 4355 } 4356 4357 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) { 4358 struct sge_ofld_rxq *r = &s->rdmaciq[i]; 4359 4360 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64); 4361 r->rspq.uld = CXGB4_ULD_RDMA; 4362 } 4363 4364 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 4365 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64); 4366 } 4367 4368 /* 4369 * Reduce the number of Ethernet queues across all ports to at most n. 4370 * n provides at least one queue per port. 4371 */ 4372 static void reduce_ethqs(struct adapter *adap, int n) 4373 { 4374 int i; 4375 struct port_info *pi; 4376 4377 while (n < adap->sge.ethqsets) 4378 for_each_port(adap, i) { 4379 pi = adap2pinfo(adap, i); 4380 if (pi->nqsets > 1) { 4381 pi->nqsets--; 4382 adap->sge.ethqsets--; 4383 if (adap->sge.ethqsets <= n) 4384 break; 4385 } 4386 } 4387 4388 n = 0; 4389 for_each_port(adap, i) { 4390 pi = adap2pinfo(adap, i); 4391 pi->first_qset = n; 4392 n += pi->nqsets; 4393 } 4394 } 4395 4396 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 4397 #define EXTRA_VECS 2 4398 4399 static int enable_msix(struct adapter *adap) 4400 { 4401 int ofld_need = 0; 4402 int i, want, need, allocated; 4403 struct sge *s = &adap->sge; 4404 unsigned int nchan = adap->params.nports; 4405 struct msix_entry *entries; 4406 4407 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1), 4408 GFP_KERNEL); 4409 if (!entries) 4410 return -ENOMEM; 4411 4412 for (i = 0; i < MAX_INGQ + 1; ++i) 4413 entries[i].entry = i; 4414 4415 want = s->max_ethqsets + EXTRA_VECS; 4416 if (is_offload(adap)) { 4417 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets; 4418 /* need nchan for each possible ULD */ 4419 ofld_need = 3 * nchan; 4420 } 4421 #ifdef CONFIG_CHELSIO_T4_DCB 4422 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 4423 * each port. 4424 */ 4425 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need; 4426 #else 4427 need = adap->params.nports + EXTRA_VECS + ofld_need; 4428 #endif 4429 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 4430 if (allocated < 0) { 4431 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 4432 " not using MSI-X\n"); 4433 kfree(entries); 4434 return allocated; 4435 } 4436 4437 /* Distribute available vectors to the various queue groups. 4438 * Every group gets its minimum requirement and NIC gets top 4439 * priority for leftovers. 4440 */ 4441 i = allocated - EXTRA_VECS - ofld_need; 4442 if (i < s->max_ethqsets) { 4443 s->max_ethqsets = i; 4444 if (i < s->ethqsets) 4445 reduce_ethqs(adap, i); 4446 } 4447 if (is_offload(adap)) { 4448 if (allocated < want) { 4449 s->rdmaqs = nchan; 4450 s->rdmaciqs = nchan; 4451 } 4452 4453 /* leftovers go to OFLD */ 4454 i = allocated - EXTRA_VECS - s->max_ethqsets - 4455 s->rdmaqs - s->rdmaciqs; 4456 s->ofldqsets = (i / nchan) * nchan; /* round down */ 4457 } 4458 for (i = 0; i < allocated; ++i) 4459 adap->msix_info[i].vec = entries[i].vector; 4460 4461 kfree(entries); 4462 return 0; 4463 } 4464 4465 #undef EXTRA_VECS 4466 4467 static int init_rss(struct adapter *adap) 4468 { 4469 unsigned int i; 4470 int err; 4471 4472 err = t4_init_rss_mode(adap, adap->mbox); 4473 if (err) 4474 return err; 4475 4476 for_each_port(adap, i) { 4477 struct port_info *pi = adap2pinfo(adap, i); 4478 4479 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 4480 if (!pi->rss) 4481 return -ENOMEM; 4482 } 4483 return 0; 4484 } 4485 4486 static void print_port_info(const struct net_device *dev) 4487 { 4488 char buf[80]; 4489 char *bufp = buf; 4490 const char *spd = ""; 4491 const struct port_info *pi = netdev_priv(dev); 4492 const struct adapter *adap = pi->adapter; 4493 4494 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) 4495 spd = " 2.5 GT/s"; 4496 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) 4497 spd = " 5 GT/s"; 4498 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) 4499 spd = " 8 GT/s"; 4500 4501 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) 4502 bufp += sprintf(bufp, "100/"); 4503 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 4504 bufp += sprintf(bufp, "1000/"); 4505 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 4506 bufp += sprintf(bufp, "10G/"); 4507 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 4508 bufp += sprintf(bufp, "40G/"); 4509 if (bufp != buf) 4510 --bufp; 4511 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 4512 4513 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n", 4514 adap->params.vpd.id, 4515 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 4516 is_offload(adap) ? "R" : "", adap->params.pci.width, spd, 4517 (adap->flags & USING_MSIX) ? " MSI-X" : 4518 (adap->flags & USING_MSI) ? " MSI" : ""); 4519 netdev_info(dev, "S/N: %s, P/N: %s\n", 4520 adap->params.vpd.sn, adap->params.vpd.pn); 4521 } 4522 4523 static void enable_pcie_relaxed_ordering(struct pci_dev *dev) 4524 { 4525 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN); 4526 } 4527 4528 /* 4529 * Free the following resources: 4530 * - memory used for tables 4531 * - MSI/MSI-X 4532 * - net devices 4533 * - resources FW is holding for us 4534 */ 4535 static void free_some_resources(struct adapter *adapter) 4536 { 4537 unsigned int i; 4538 4539 t4_free_mem(adapter->l2t); 4540 t4_free_mem(adapter->tids.tid_tab); 4541 kfree(adapter->sge.egr_map); 4542 kfree(adapter->sge.ingr_map); 4543 kfree(adapter->sge.starving_fl); 4544 kfree(adapter->sge.txq_maperr); 4545 #ifdef CONFIG_DEBUG_FS 4546 kfree(adapter->sge.blocked_fl); 4547 #endif 4548 disable_msi(adapter); 4549 4550 for_each_port(adapter, i) 4551 if (adapter->port[i]) { 4552 struct port_info *pi = adap2pinfo(adapter, i); 4553 4554 if (pi->viid != 0) 4555 t4_free_vi(adapter, adapter->mbox, adapter->pf, 4556 0, pi->viid); 4557 kfree(adap2pinfo(adapter, i)->rss); 4558 free_netdev(adapter->port[i]); 4559 } 4560 if (adapter->flags & FW_OK) 4561 t4_fw_bye(adapter, adapter->pf); 4562 } 4563 4564 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 4565 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 4566 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 4567 #define SEGMENT_SIZE 128 4568 4569 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) 4570 { 4571 u16 device_id; 4572 4573 /* Retrieve adapter's device ID */ 4574 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 4575 4576 switch (device_id >> 12) { 4577 case CHELSIO_T4: 4578 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 4579 case CHELSIO_T5: 4580 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 4581 case CHELSIO_T6: 4582 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 4583 default: 4584 dev_err(&pdev->dev, "Device %d is not supported\n", 4585 device_id); 4586 } 4587 return -EINVAL; 4588 } 4589 4590 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4591 { 4592 int func, i, err, s_qpp, qpp, num_seg; 4593 struct port_info *pi; 4594 bool highdma = false; 4595 struct adapter *adapter = NULL; 4596 void __iomem *regs; 4597 u32 whoami, pl_rev; 4598 enum chip_type chip; 4599 4600 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 4601 4602 err = pci_request_regions(pdev, KBUILD_MODNAME); 4603 if (err) { 4604 /* Just info, some other driver may have claimed the device. */ 4605 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 4606 return err; 4607 } 4608 4609 err = pci_enable_device(pdev); 4610 if (err) { 4611 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4612 goto out_release_regions; 4613 } 4614 4615 regs = pci_ioremap_bar(pdev, 0); 4616 if (!regs) { 4617 dev_err(&pdev->dev, "cannot map device registers\n"); 4618 err = -ENOMEM; 4619 goto out_disable_device; 4620 } 4621 4622 err = t4_wait_dev_ready(regs); 4623 if (err < 0) 4624 goto out_unmap_bar0; 4625 4626 /* We control everything through one PF */ 4627 whoami = readl(regs + PL_WHOAMI_A); 4628 pl_rev = REV_G(readl(regs + PL_REV_A)); 4629 chip = get_chip_type(pdev, pl_rev); 4630 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 4631 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 4632 if (func != ent->driver_data) { 4633 iounmap(regs); 4634 pci_disable_device(pdev); 4635 pci_save_state(pdev); /* to restore SR-IOV later */ 4636 goto sriov; 4637 } 4638 4639 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4640 highdma = true; 4641 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4642 if (err) { 4643 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 4644 "coherent allocations\n"); 4645 goto out_unmap_bar0; 4646 } 4647 } else { 4648 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4649 if (err) { 4650 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4651 goto out_unmap_bar0; 4652 } 4653 } 4654 4655 pci_enable_pcie_error_reporting(pdev); 4656 enable_pcie_relaxed_ordering(pdev); 4657 pci_set_master(pdev); 4658 pci_save_state(pdev); 4659 4660 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 4661 if (!adapter) { 4662 err = -ENOMEM; 4663 goto out_unmap_bar0; 4664 } 4665 4666 adapter->workq = create_singlethread_workqueue("cxgb4"); 4667 if (!adapter->workq) { 4668 err = -ENOMEM; 4669 goto out_free_adapter; 4670 } 4671 4672 /* PCI device has been enabled */ 4673 adapter->flags |= DEV_ENABLED; 4674 4675 adapter->regs = regs; 4676 adapter->pdev = pdev; 4677 adapter->pdev_dev = &pdev->dev; 4678 adapter->mbox = func; 4679 adapter->pf = func; 4680 adapter->msg_enable = dflt_msg_enable; 4681 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 4682 4683 spin_lock_init(&adapter->stats_lock); 4684 spin_lock_init(&adapter->tid_release_lock); 4685 spin_lock_init(&adapter->win0_lock); 4686 4687 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 4688 INIT_WORK(&adapter->db_full_task, process_db_full); 4689 INIT_WORK(&adapter->db_drop_task, process_db_drop); 4690 4691 err = t4_prep_adapter(adapter); 4692 if (err) 4693 goto out_free_adapter; 4694 4695 4696 if (!is_t4(adapter->params.chip)) { 4697 s_qpp = (QUEUESPERPAGEPF0_S + 4698 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 4699 adapter->pf); 4700 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 4701 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 4702 num_seg = PAGE_SIZE / SEGMENT_SIZE; 4703 4704 /* Each segment size is 128B. Write coalescing is enabled only 4705 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 4706 * queue is less no of segments that can be accommodated in 4707 * a page size. 4708 */ 4709 if (qpp > num_seg) { 4710 dev_err(&pdev->dev, 4711 "Incorrect number of egress queues per page\n"); 4712 err = -EINVAL; 4713 goto out_free_adapter; 4714 } 4715 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 4716 pci_resource_len(pdev, 2)); 4717 if (!adapter->bar2) { 4718 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 4719 err = -ENOMEM; 4720 goto out_free_adapter; 4721 } 4722 } 4723 4724 setup_memwin(adapter); 4725 err = adap_init0(adapter); 4726 #ifdef CONFIG_DEBUG_FS 4727 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 4728 #endif 4729 setup_memwin_rdma(adapter); 4730 if (err) 4731 goto out_unmap_bar; 4732 4733 /* configure SGE_STAT_CFG_A to read WC stats */ 4734 if (!is_t4(adapter->params.chip)) 4735 t4_write_reg(adapter, SGE_STAT_CFG_A, 4736 STATSOURCE_T5_V(7) | STATMODE_V(0)); 4737 4738 for_each_port(adapter, i) { 4739 struct net_device *netdev; 4740 4741 netdev = alloc_etherdev_mq(sizeof(struct port_info), 4742 MAX_ETH_QSETS); 4743 if (!netdev) { 4744 err = -ENOMEM; 4745 goto out_free_dev; 4746 } 4747 4748 SET_NETDEV_DEV(netdev, &pdev->dev); 4749 4750 adapter->port[i] = netdev; 4751 pi = netdev_priv(netdev); 4752 pi->adapter = adapter; 4753 pi->xact_addr_filt = -1; 4754 pi->port_id = i; 4755 netdev->irq = pdev->irq; 4756 4757 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 4758 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4759 NETIF_F_RXCSUM | NETIF_F_RXHASH | 4760 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX; 4761 if (highdma) 4762 netdev->hw_features |= NETIF_F_HIGHDMA; 4763 netdev->features |= netdev->hw_features; 4764 netdev->vlan_features = netdev->features & VLAN_FEAT; 4765 4766 netdev->priv_flags |= IFF_UNICAST_FLT; 4767 4768 netdev->netdev_ops = &cxgb4_netdev_ops; 4769 #ifdef CONFIG_CHELSIO_T4_DCB 4770 netdev->dcbnl_ops = &cxgb4_dcb_ops; 4771 cxgb4_dcb_state_init(netdev); 4772 #endif 4773 cxgb4_set_ethtool_ops(netdev); 4774 } 4775 4776 pci_set_drvdata(pdev, adapter); 4777 4778 if (adapter->flags & FW_OK) { 4779 err = t4_port_init(adapter, func, func, 0); 4780 if (err) 4781 goto out_free_dev; 4782 } else if (adapter->params.nports == 1) { 4783 /* If we don't have a connection to the firmware -- possibly 4784 * because of an error -- grab the raw VPD parameters so we 4785 * can set the proper MAC Address on the debug network 4786 * interface that we've created. 4787 */ 4788 u8 hw_addr[ETH_ALEN]; 4789 u8 *na = adapter->params.vpd.na; 4790 4791 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 4792 if (!err) { 4793 for (i = 0; i < ETH_ALEN; i++) 4794 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 4795 hex2val(na[2 * i + 1])); 4796 t4_set_hw_addr(adapter, 0, hw_addr); 4797 } 4798 } 4799 4800 /* Configure queues and allocate tables now, they can be needed as 4801 * soon as the first register_netdev completes. 4802 */ 4803 cfg_queues(adapter); 4804 4805 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 4806 if (!adapter->l2t) { 4807 /* We tolerate a lack of L2T, giving up some functionality */ 4808 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 4809 adapter->params.offload = 0; 4810 } 4811 4812 #if IS_ENABLED(CONFIG_IPV6) 4813 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 4814 adapter->clipt_end); 4815 if (!adapter->clipt) { 4816 /* We tolerate a lack of clip_table, giving up 4817 * some functionality 4818 */ 4819 dev_warn(&pdev->dev, 4820 "could not allocate Clip table, continuing\n"); 4821 adapter->params.offload = 0; 4822 } 4823 #endif 4824 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) { 4825 dev_warn(&pdev->dev, "could not allocate TID table, " 4826 "continuing\n"); 4827 adapter->params.offload = 0; 4828 } 4829 4830 if (is_offload(adapter)) { 4831 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 4832 u32 hash_base, hash_reg; 4833 4834 if (chip <= CHELSIO_T5) { 4835 hash_reg = LE_DB_TID_HASHBASE_A; 4836 hash_base = t4_read_reg(adapter, hash_reg); 4837 adapter->tids.hash_base = hash_base / 4; 4838 } else { 4839 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 4840 hash_base = t4_read_reg(adapter, hash_reg); 4841 adapter->tids.hash_base = hash_base; 4842 } 4843 } 4844 } 4845 4846 /* See what interrupts we'll be using */ 4847 if (msi > 1 && enable_msix(adapter) == 0) 4848 adapter->flags |= USING_MSIX; 4849 else if (msi > 0 && pci_enable_msi(pdev) == 0) 4850 adapter->flags |= USING_MSI; 4851 4852 err = init_rss(adapter); 4853 if (err) 4854 goto out_free_dev; 4855 4856 /* 4857 * The card is now ready to go. If any errors occur during device 4858 * registration we do not fail the whole card but rather proceed only 4859 * with the ports we manage to register successfully. However we must 4860 * register at least one net device. 4861 */ 4862 for_each_port(adapter, i) { 4863 pi = adap2pinfo(adapter, i); 4864 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 4865 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 4866 4867 err = register_netdev(adapter->port[i]); 4868 if (err) 4869 break; 4870 adapter->chan_map[pi->tx_chan] = i; 4871 print_port_info(adapter->port[i]); 4872 } 4873 if (i == 0) { 4874 dev_err(&pdev->dev, "could not register any net devices\n"); 4875 goto out_free_dev; 4876 } 4877 if (err) { 4878 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 4879 err = 0; 4880 } 4881 4882 if (cxgb4_debugfs_root) { 4883 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 4884 cxgb4_debugfs_root); 4885 setup_debugfs(adapter); 4886 } 4887 4888 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 4889 pdev->needs_freset = 1; 4890 4891 if (is_offload(adapter)) 4892 attach_ulds(adapter); 4893 4894 sriov: 4895 #ifdef CONFIG_PCI_IOV 4896 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0) 4897 if (pci_enable_sriov(pdev, num_vf[func]) == 0) 4898 dev_info(&pdev->dev, 4899 "instantiated %u virtual functions\n", 4900 num_vf[func]); 4901 #endif 4902 return 0; 4903 4904 out_free_dev: 4905 free_some_resources(adapter); 4906 out_unmap_bar: 4907 if (!is_t4(adapter->params.chip)) 4908 iounmap(adapter->bar2); 4909 out_free_adapter: 4910 if (adapter->workq) 4911 destroy_workqueue(adapter->workq); 4912 4913 kfree(adapter); 4914 out_unmap_bar0: 4915 iounmap(regs); 4916 out_disable_device: 4917 pci_disable_pcie_error_reporting(pdev); 4918 pci_disable_device(pdev); 4919 out_release_regions: 4920 pci_release_regions(pdev); 4921 return err; 4922 } 4923 4924 static void remove_one(struct pci_dev *pdev) 4925 { 4926 struct adapter *adapter = pci_get_drvdata(pdev); 4927 4928 #ifdef CONFIG_PCI_IOV 4929 pci_disable_sriov(pdev); 4930 4931 #endif 4932 4933 if (adapter) { 4934 int i; 4935 4936 /* Tear down per-adapter Work Queue first since it can contain 4937 * references to our adapter data structure. 4938 */ 4939 destroy_workqueue(adapter->workq); 4940 4941 if (is_offload(adapter)) 4942 detach_ulds(adapter); 4943 4944 disable_interrupts(adapter); 4945 4946 for_each_port(adapter, i) 4947 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 4948 unregister_netdev(adapter->port[i]); 4949 4950 debugfs_remove_recursive(adapter->debugfs_root); 4951 4952 /* If we allocated filters, free up state associated with any 4953 * valid filters ... 4954 */ 4955 if (adapter->tids.ftid_tab) { 4956 struct filter_entry *f = &adapter->tids.ftid_tab[0]; 4957 for (i = 0; i < (adapter->tids.nftids + 4958 adapter->tids.nsftids); i++, f++) 4959 if (f->valid) 4960 clear_filter(adapter, f); 4961 } 4962 4963 if (adapter->flags & FULL_INIT_DONE) 4964 cxgb_down(adapter); 4965 4966 free_some_resources(adapter); 4967 #if IS_ENABLED(CONFIG_IPV6) 4968 t4_cleanup_clip_tbl(adapter); 4969 #endif 4970 iounmap(adapter->regs); 4971 if (!is_t4(adapter->params.chip)) 4972 iounmap(adapter->bar2); 4973 pci_disable_pcie_error_reporting(pdev); 4974 if ((adapter->flags & DEV_ENABLED)) { 4975 pci_disable_device(pdev); 4976 adapter->flags &= ~DEV_ENABLED; 4977 } 4978 pci_release_regions(pdev); 4979 synchronize_rcu(); 4980 kfree(adapter); 4981 } else 4982 pci_release_regions(pdev); 4983 } 4984 4985 static struct pci_driver cxgb4_driver = { 4986 .name = KBUILD_MODNAME, 4987 .id_table = cxgb4_pci_tbl, 4988 .probe = init_one, 4989 .remove = remove_one, 4990 .shutdown = remove_one, 4991 .err_handler = &cxgb4_eeh, 4992 }; 4993 4994 static int __init cxgb4_init_module(void) 4995 { 4996 int ret; 4997 4998 /* Debugfs support is optional, just warn if this fails */ 4999 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 5000 if (!cxgb4_debugfs_root) 5001 pr_warn("could not create debugfs entry, continuing\n"); 5002 5003 ret = pci_register_driver(&cxgb4_driver); 5004 if (ret < 0) 5005 debugfs_remove(cxgb4_debugfs_root); 5006 5007 #if IS_ENABLED(CONFIG_IPV6) 5008 if (!inet6addr_registered) { 5009 register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5010 inet6addr_registered = true; 5011 } 5012 #endif 5013 5014 return ret; 5015 } 5016 5017 static void __exit cxgb4_cleanup_module(void) 5018 { 5019 #if IS_ENABLED(CONFIG_IPV6) 5020 if (inet6addr_registered) { 5021 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5022 inet6addr_registered = false; 5023 } 5024 #endif 5025 pci_unregister_driver(&cxgb4_driver); 5026 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 5027 } 5028 5029 module_init(cxgb4_init_module); 5030 module_exit(cxgb4_cleanup_module); 5031