1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <net/addrconf.h> 66 #include <linux/uaccess.h> 67 #include <linux/crash_dump.h> 68 69 #include "cxgb4.h" 70 #include "cxgb4_filter.h" 71 #include "t4_regs.h" 72 #include "t4_values.h" 73 #include "t4_msg.h" 74 #include "t4fw_api.h" 75 #include "t4fw_version.h" 76 #include "cxgb4_dcb.h" 77 #include "cxgb4_debugfs.h" 78 #include "clip_tbl.h" 79 #include "l2t.h" 80 #include "smt.h" 81 #include "sched.h" 82 #include "cxgb4_tc_u32.h" 83 #include "cxgb4_tc_flower.h" 84 #include "cxgb4_ptp.h" 85 #include "cxgb4_cudbg.h" 86 87 char cxgb4_driver_name[] = KBUILD_MODNAME; 88 89 #ifdef DRV_VERSION 90 #undef DRV_VERSION 91 #endif 92 #define DRV_VERSION "2.0.0-ko" 93 const char cxgb4_driver_version[] = DRV_VERSION; 94 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 95 96 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 97 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 98 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 99 100 /* Macros needed to support the PCI Device ID Table ... 101 */ 102 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 103 static const struct pci_device_id cxgb4_pci_tbl[] = { 104 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 105 106 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 107 * called for both. 108 */ 109 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 110 111 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 112 {PCI_VDEVICE(CHELSIO, (devid)), 4} 113 114 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 115 { 0, } \ 116 } 117 118 #include "t4_pci_id_tbl.h" 119 120 #define FW4_FNAME "cxgb4/t4fw.bin" 121 #define FW5_FNAME "cxgb4/t5fw.bin" 122 #define FW6_FNAME "cxgb4/t6fw.bin" 123 #define FW4_CFNAME "cxgb4/t4-config.txt" 124 #define FW5_CFNAME "cxgb4/t5-config.txt" 125 #define FW6_CFNAME "cxgb4/t6-config.txt" 126 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 127 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 128 #define PHY_AQ1202_DEVICEID 0x4409 129 #define PHY_BCM84834_DEVICEID 0x4486 130 131 MODULE_DESCRIPTION(DRV_DESC); 132 MODULE_AUTHOR("Chelsio Communications"); 133 MODULE_LICENSE("Dual BSD/GPL"); 134 MODULE_VERSION(DRV_VERSION); 135 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 136 MODULE_FIRMWARE(FW4_FNAME); 137 MODULE_FIRMWARE(FW5_FNAME); 138 MODULE_FIRMWARE(FW6_FNAME); 139 140 /* 141 * The driver uses the best interrupt scheme available on a platform in the 142 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 143 * of these schemes the driver may consider as follows: 144 * 145 * msi = 2: choose from among all three options 146 * msi = 1: only consider MSI and INTx interrupts 147 * msi = 0: force INTx interrupts 148 */ 149 static int msi = 2; 150 151 module_param(msi, int, 0644); 152 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 153 154 /* 155 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 156 * offset by 2 bytes in order to have the IP headers line up on 4-byte 157 * boundaries. This is a requirement for many architectures which will throw 158 * a machine check fault if an attempt is made to access one of the 4-byte IP 159 * header fields on a non-4-byte boundary. And it's a major performance issue 160 * even on some architectures which allow it like some implementations of the 161 * x86 ISA. However, some architectures don't mind this and for some very 162 * edge-case performance sensitive applications (like forwarding large volumes 163 * of small packets), setting this DMA offset to 0 will decrease the number of 164 * PCI-E Bus transfers enough to measurably affect performance. 165 */ 166 static int rx_dma_offset = 2; 167 168 /* TX Queue select used to determine what algorithm to use for selecting TX 169 * queue. Select between the kernel provided function (select_queue=0) or user 170 * cxgb_select_queue function (select_queue=1) 171 * 172 * Default: select_queue=0 173 */ 174 static int select_queue; 175 module_param(select_queue, int, 0644); 176 MODULE_PARM_DESC(select_queue, 177 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 178 179 static struct dentry *cxgb4_debugfs_root; 180 181 LIST_HEAD(adapter_list); 182 DEFINE_MUTEX(uld_mutex); 183 184 static void link_report(struct net_device *dev) 185 { 186 if (!netif_carrier_ok(dev)) 187 netdev_info(dev, "link down\n"); 188 else { 189 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 190 191 const char *s; 192 const struct port_info *p = netdev_priv(dev); 193 194 switch (p->link_cfg.speed) { 195 case 100: 196 s = "100Mbps"; 197 break; 198 case 1000: 199 s = "1Gbps"; 200 break; 201 case 10000: 202 s = "10Gbps"; 203 break; 204 case 25000: 205 s = "25Gbps"; 206 break; 207 case 40000: 208 s = "40Gbps"; 209 break; 210 case 100000: 211 s = "100Gbps"; 212 break; 213 default: 214 pr_info("%s: unsupported speed: %d\n", 215 dev->name, p->link_cfg.speed); 216 return; 217 } 218 219 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 220 fc[p->link_cfg.fc]); 221 } 222 } 223 224 #ifdef CONFIG_CHELSIO_T4_DCB 225 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 226 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 227 { 228 struct port_info *pi = netdev_priv(dev); 229 struct adapter *adap = pi->adapter; 230 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 231 int i; 232 233 /* We use a simple mapping of Port TX Queue Index to DCB 234 * Priority when we're enabling DCB. 235 */ 236 for (i = 0; i < pi->nqsets; i++, txq++) { 237 u32 name, value; 238 int err; 239 240 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 241 FW_PARAMS_PARAM_X_V( 242 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 243 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 244 value = enable ? i : 0xffffffff; 245 246 /* Since we can be called while atomic (from "interrupt 247 * level") we need to issue the Set Parameters Commannd 248 * without sleeping (timeout < 0). 249 */ 250 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 251 &name, &value, 252 -FW_CMD_MAX_TIMEOUT); 253 254 if (err) 255 dev_err(adap->pdev_dev, 256 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 257 enable ? "set" : "unset", pi->port_id, i, -err); 258 else 259 txq->dcb_prio = value; 260 } 261 } 262 263 static int cxgb4_dcb_enabled(const struct net_device *dev) 264 { 265 struct port_info *pi = netdev_priv(dev); 266 267 if (!pi->dcb.enabled) 268 return 0; 269 270 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 271 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 272 } 273 #endif /* CONFIG_CHELSIO_T4_DCB */ 274 275 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 276 { 277 struct net_device *dev = adapter->port[port_id]; 278 279 /* Skip changes from disabled ports. */ 280 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 281 if (link_stat) 282 netif_carrier_on(dev); 283 else { 284 #ifdef CONFIG_CHELSIO_T4_DCB 285 if (cxgb4_dcb_enabled(dev)) { 286 cxgb4_dcb_reset(dev); 287 dcb_tx_queue_prio_enable(dev, false); 288 } 289 #endif /* CONFIG_CHELSIO_T4_DCB */ 290 netif_carrier_off(dev); 291 } 292 293 link_report(dev); 294 } 295 } 296 297 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 298 { 299 static const char *mod_str[] = { 300 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 301 }; 302 303 const struct net_device *dev = adap->port[port_id]; 304 const struct port_info *pi = netdev_priv(dev); 305 306 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 307 netdev_info(dev, "port module unplugged\n"); 308 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 309 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 310 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 311 netdev_info(dev, "%s: unsupported port module inserted\n", 312 dev->name); 313 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 314 netdev_info(dev, "%s: unknown port module inserted\n", 315 dev->name); 316 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 317 netdev_info(dev, "%s: transceiver module error\n", dev->name); 318 else 319 netdev_info(dev, "%s: unknown module type %d inserted\n", 320 dev->name, pi->mod_type); 321 } 322 323 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 324 module_param(dbfifo_int_thresh, int, 0644); 325 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 326 327 /* 328 * usecs to sleep while draining the dbfifo 329 */ 330 static int dbfifo_drain_delay = 1000; 331 module_param(dbfifo_drain_delay, int, 0644); 332 MODULE_PARM_DESC(dbfifo_drain_delay, 333 "usecs to sleep while draining the dbfifo"); 334 335 static inline int cxgb4_set_addr_hash(struct port_info *pi) 336 { 337 struct adapter *adap = pi->adapter; 338 u64 vec = 0; 339 bool ucast = false; 340 struct hash_mac_addr *entry; 341 342 /* Calculate the hash vector for the updated list and program it */ 343 list_for_each_entry(entry, &adap->mac_hlist, list) { 344 ucast |= is_unicast_ether_addr(entry->addr); 345 vec |= (1ULL << hash_mac_addr(entry->addr)); 346 } 347 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 348 vec, false); 349 } 350 351 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 352 { 353 struct port_info *pi = netdev_priv(netdev); 354 struct adapter *adap = pi->adapter; 355 int ret; 356 u64 mhash = 0; 357 u64 uhash = 0; 358 bool free = false; 359 bool ucast = is_unicast_ether_addr(mac_addr); 360 const u8 *maclist[1] = {mac_addr}; 361 struct hash_mac_addr *new_entry; 362 363 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, 364 NULL, ucast ? &uhash : &mhash, false); 365 if (ret < 0) 366 goto out; 367 /* if hash != 0, then add the addr to hash addr list 368 * so on the end we will calculate the hash for the 369 * list and program it 370 */ 371 if (uhash || mhash) { 372 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 373 if (!new_entry) 374 return -ENOMEM; 375 ether_addr_copy(new_entry->addr, mac_addr); 376 list_add_tail(&new_entry->list, &adap->mac_hlist); 377 ret = cxgb4_set_addr_hash(pi); 378 } 379 out: 380 return ret < 0 ? ret : 0; 381 } 382 383 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 384 { 385 struct port_info *pi = netdev_priv(netdev); 386 struct adapter *adap = pi->adapter; 387 int ret; 388 const u8 *maclist[1] = {mac_addr}; 389 struct hash_mac_addr *entry, *tmp; 390 391 /* If the MAC address to be removed is in the hash addr 392 * list, delete it from the list and update hash vector 393 */ 394 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 395 if (ether_addr_equal(entry->addr, mac_addr)) { 396 list_del(&entry->list); 397 kfree(entry); 398 return cxgb4_set_addr_hash(pi); 399 } 400 } 401 402 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); 403 return ret < 0 ? -EINVAL : 0; 404 } 405 406 /* 407 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 408 * If @mtu is -1 it is left unchanged. 409 */ 410 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 411 { 412 struct port_info *pi = netdev_priv(dev); 413 struct adapter *adapter = pi->adapter; 414 415 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 416 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 417 418 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, 419 (dev->flags & IFF_PROMISC) ? 1 : 0, 420 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 421 sleep_ok); 422 } 423 424 /** 425 * link_start - enable a port 426 * @dev: the port to enable 427 * 428 * Performs the MAC and PHY actions needed to enable a port. 429 */ 430 static int link_start(struct net_device *dev) 431 { 432 int ret; 433 struct port_info *pi = netdev_priv(dev); 434 unsigned int mb = pi->adapter->pf; 435 436 /* 437 * We do not set address filters and promiscuity here, the stack does 438 * that step explicitly. 439 */ 440 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 441 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 442 if (ret == 0) { 443 ret = t4_change_mac(pi->adapter, mb, pi->viid, 444 pi->xact_addr_filt, dev->dev_addr, true, 445 true); 446 if (ret >= 0) { 447 pi->xact_addr_filt = ret; 448 ret = 0; 449 } 450 } 451 if (ret == 0) 452 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 453 &pi->link_cfg); 454 if (ret == 0) { 455 local_bh_disable(); 456 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true, 457 true, CXGB4_DCB_ENABLED); 458 local_bh_enable(); 459 } 460 461 return ret; 462 } 463 464 #ifdef CONFIG_CHELSIO_T4_DCB 465 /* Handle a Data Center Bridging update message from the firmware. */ 466 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 467 { 468 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 469 struct net_device *dev = adap->port[adap->chan_map[port]]; 470 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 471 int new_dcb_enabled; 472 473 cxgb4_dcb_handle_fw_update(adap, pcmd); 474 new_dcb_enabled = cxgb4_dcb_enabled(dev); 475 476 /* If the DCB has become enabled or disabled on the port then we're 477 * going to need to set up/tear down DCB Priority parameters for the 478 * TX Queues associated with the port. 479 */ 480 if (new_dcb_enabled != old_dcb_enabled) 481 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 482 } 483 #endif /* CONFIG_CHELSIO_T4_DCB */ 484 485 /* Response queue handler for the FW event queue. 486 */ 487 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 488 const struct pkt_gl *gl) 489 { 490 u8 opcode = ((const struct rss_header *)rsp)->opcode; 491 492 rsp++; /* skip RSS header */ 493 494 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 495 */ 496 if (unlikely(opcode == CPL_FW4_MSG && 497 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 498 rsp++; 499 opcode = ((const struct rss_header *)rsp)->opcode; 500 rsp++; 501 if (opcode != CPL_SGE_EGR_UPDATE) { 502 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 503 , opcode); 504 goto out; 505 } 506 } 507 508 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 509 const struct cpl_sge_egr_update *p = (void *)rsp; 510 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 511 struct sge_txq *txq; 512 513 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 514 txq->restarts++; 515 if (txq->q_type == CXGB4_TXQ_ETH) { 516 struct sge_eth_txq *eq; 517 518 eq = container_of(txq, struct sge_eth_txq, q); 519 netif_tx_wake_queue(eq->txq); 520 } else { 521 struct sge_uld_txq *oq; 522 523 oq = container_of(txq, struct sge_uld_txq, q); 524 tasklet_schedule(&oq->qresume_tsk); 525 } 526 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 527 const struct cpl_fw6_msg *p = (void *)rsp; 528 529 #ifdef CONFIG_CHELSIO_T4_DCB 530 const struct fw_port_cmd *pcmd = (const void *)p->data; 531 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 532 unsigned int action = 533 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 534 535 if (cmd == FW_PORT_CMD && 536 (action == FW_PORT_ACTION_GET_PORT_INFO || 537 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 538 int port = FW_PORT_CMD_PORTID_G( 539 be32_to_cpu(pcmd->op_to_portid)); 540 struct net_device *dev; 541 int dcbxdis, state_input; 542 543 dev = q->adap->port[q->adap->chan_map[port]]; 544 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 545 ? !!(pcmd->u.info.dcbxdis_pkd & 546 FW_PORT_CMD_DCBXDIS_F) 547 : !!(pcmd->u.info32.lstatus32_to_cbllen32 & 548 FW_PORT_CMD_DCBXDIS32_F)); 549 state_input = (dcbxdis 550 ? CXGB4_DCB_INPUT_FW_DISABLED 551 : CXGB4_DCB_INPUT_FW_ENABLED); 552 553 cxgb4_dcb_state_fsm(dev, state_input); 554 } 555 556 if (cmd == FW_PORT_CMD && 557 action == FW_PORT_ACTION_L2_DCB_CFG) 558 dcb_rpl(q->adap, pcmd); 559 else 560 #endif 561 if (p->type == 0) 562 t4_handle_fw_rpl(q->adap, p->data); 563 } else if (opcode == CPL_L2T_WRITE_RPL) { 564 const struct cpl_l2t_write_rpl *p = (void *)rsp; 565 566 do_l2t_write_rpl(q->adap, p); 567 } else if (opcode == CPL_SMT_WRITE_RPL) { 568 const struct cpl_smt_write_rpl *p = (void *)rsp; 569 570 do_smt_write_rpl(q->adap, p); 571 } else if (opcode == CPL_SET_TCB_RPL) { 572 const struct cpl_set_tcb_rpl *p = (void *)rsp; 573 574 filter_rpl(q->adap, p); 575 } else 576 dev_err(q->adap->pdev_dev, 577 "unexpected CPL %#x on FW event queue\n", opcode); 578 out: 579 return 0; 580 } 581 582 static void disable_msi(struct adapter *adapter) 583 { 584 if (adapter->flags & USING_MSIX) { 585 pci_disable_msix(adapter->pdev); 586 adapter->flags &= ~USING_MSIX; 587 } else if (adapter->flags & USING_MSI) { 588 pci_disable_msi(adapter->pdev); 589 adapter->flags &= ~USING_MSI; 590 } 591 } 592 593 /* 594 * Interrupt handler for non-data events used with MSI-X. 595 */ 596 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 597 { 598 struct adapter *adap = cookie; 599 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 600 601 if (v & PFSW_F) { 602 adap->swintr = 1; 603 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 604 } 605 if (adap->flags & MASTER_PF) 606 t4_slow_intr_handler(adap); 607 return IRQ_HANDLED; 608 } 609 610 /* 611 * Name the MSI-X interrupts. 612 */ 613 static void name_msix_vecs(struct adapter *adap) 614 { 615 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 616 617 /* non-data interrupts */ 618 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 619 620 /* FW events */ 621 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 622 adap->port[0]->name); 623 624 /* Ethernet queues */ 625 for_each_port(adap, j) { 626 struct net_device *d = adap->port[j]; 627 const struct port_info *pi = netdev_priv(d); 628 629 for (i = 0; i < pi->nqsets; i++, msi_idx++) 630 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 631 d->name, i); 632 } 633 } 634 635 static int request_msix_queue_irqs(struct adapter *adap) 636 { 637 struct sge *s = &adap->sge; 638 int err, ethqidx; 639 int msi_index = 2; 640 641 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 642 adap->msix_info[1].desc, &s->fw_evtq); 643 if (err) 644 return err; 645 646 for_each_ethrxq(s, ethqidx) { 647 err = request_irq(adap->msix_info[msi_index].vec, 648 t4_sge_intr_msix, 0, 649 adap->msix_info[msi_index].desc, 650 &s->ethrxq[ethqidx].rspq); 651 if (err) 652 goto unwind; 653 msi_index++; 654 } 655 return 0; 656 657 unwind: 658 while (--ethqidx >= 0) 659 free_irq(adap->msix_info[--msi_index].vec, 660 &s->ethrxq[ethqidx].rspq); 661 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 662 return err; 663 } 664 665 static void free_msix_queue_irqs(struct adapter *adap) 666 { 667 int i, msi_index = 2; 668 struct sge *s = &adap->sge; 669 670 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 671 for_each_ethrxq(s, i) 672 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq); 673 } 674 675 /** 676 * cxgb4_write_rss - write the RSS table for a given port 677 * @pi: the port 678 * @queues: array of queue indices for RSS 679 * 680 * Sets up the portion of the HW RSS table for the port's VI to distribute 681 * packets to the Rx queues in @queues. 682 * Should never be called before setting up sge eth rx queues 683 */ 684 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 685 { 686 u16 *rss; 687 int i, err; 688 struct adapter *adapter = pi->adapter; 689 const struct sge_eth_rxq *rxq; 690 691 rxq = &adapter->sge.ethrxq[pi->first_qset]; 692 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL); 693 if (!rss) 694 return -ENOMEM; 695 696 /* map the queue indices to queue ids */ 697 for (i = 0; i < pi->rss_size; i++, queues++) 698 rss[i] = rxq[*queues].rspq.abs_id; 699 700 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 701 pi->rss_size, rss, pi->rss_size); 702 /* If Tunnel All Lookup isn't specified in the global RSS 703 * Configuration, then we need to specify a default Ingress 704 * Queue for any ingress packets which aren't hashed. We'll 705 * use our first ingress queue ... 706 */ 707 if (!err) 708 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 709 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 710 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 711 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 712 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 713 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 714 rss[0]); 715 kfree(rss); 716 return err; 717 } 718 719 /** 720 * setup_rss - configure RSS 721 * @adap: the adapter 722 * 723 * Sets up RSS for each port. 724 */ 725 static int setup_rss(struct adapter *adap) 726 { 727 int i, j, err; 728 729 for_each_port(adap, i) { 730 const struct port_info *pi = adap2pinfo(adap, i); 731 732 /* Fill default values with equal distribution */ 733 for (j = 0; j < pi->rss_size; j++) 734 pi->rss[j] = j % pi->nqsets; 735 736 err = cxgb4_write_rss(pi, pi->rss); 737 if (err) 738 return err; 739 } 740 return 0; 741 } 742 743 /* 744 * Return the channel of the ingress queue with the given qid. 745 */ 746 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 747 { 748 qid -= p->ingr_start; 749 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 750 } 751 752 /* 753 * Wait until all NAPI handlers are descheduled. 754 */ 755 static void quiesce_rx(struct adapter *adap) 756 { 757 int i; 758 759 for (i = 0; i < adap->sge.ingr_sz; i++) { 760 struct sge_rspq *q = adap->sge.ingr_map[i]; 761 762 if (q && q->handler) 763 napi_disable(&q->napi); 764 } 765 } 766 767 /* Disable interrupt and napi handler */ 768 static void disable_interrupts(struct adapter *adap) 769 { 770 if (adap->flags & FULL_INIT_DONE) { 771 t4_intr_disable(adap); 772 if (adap->flags & USING_MSIX) { 773 free_msix_queue_irqs(adap); 774 free_irq(adap->msix_info[0].vec, adap); 775 } else { 776 free_irq(adap->pdev->irq, adap); 777 } 778 quiesce_rx(adap); 779 } 780 } 781 782 /* 783 * Enable NAPI scheduling and interrupt generation for all Rx queues. 784 */ 785 static void enable_rx(struct adapter *adap) 786 { 787 int i; 788 789 for (i = 0; i < adap->sge.ingr_sz; i++) { 790 struct sge_rspq *q = adap->sge.ingr_map[i]; 791 792 if (!q) 793 continue; 794 if (q->handler) 795 napi_enable(&q->napi); 796 797 /* 0-increment GTS to start the timer and enable interrupts */ 798 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 799 SEINTARM_V(q->intr_params) | 800 INGRESSQID_V(q->cntxt_id)); 801 } 802 } 803 804 805 static int setup_fw_sge_queues(struct adapter *adap) 806 { 807 struct sge *s = &adap->sge; 808 int err = 0; 809 810 bitmap_zero(s->starving_fl, s->egr_sz); 811 bitmap_zero(s->txq_maperr, s->egr_sz); 812 813 if (adap->flags & USING_MSIX) 814 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ 815 else { 816 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 817 NULL, NULL, NULL, -1); 818 if (err) 819 return err; 820 adap->msi_idx = -((int)s->intrq.abs_id + 1); 821 } 822 823 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 824 adap->msi_idx, NULL, fwevtq_handler, NULL, -1); 825 if (err) 826 t4_free_sge_resources(adap); 827 return err; 828 } 829 830 /** 831 * setup_sge_queues - configure SGE Tx/Rx/response queues 832 * @adap: the adapter 833 * 834 * Determines how many sets of SGE queues to use and initializes them. 835 * We support multiple queue sets per port if we have MSI-X, otherwise 836 * just one queue set per port. 837 */ 838 static int setup_sge_queues(struct adapter *adap) 839 { 840 int err, i, j; 841 struct sge *s = &adap->sge; 842 struct sge_uld_rxq_info *rxq_info = NULL; 843 unsigned int cmplqid = 0; 844 845 if (is_uld(adap)) 846 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 847 848 for_each_port(adap, i) { 849 struct net_device *dev = adap->port[i]; 850 struct port_info *pi = netdev_priv(dev); 851 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 852 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 853 854 for (j = 0; j < pi->nqsets; j++, q++) { 855 if (adap->msi_idx > 0) 856 adap->msi_idx++; 857 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 858 adap->msi_idx, &q->fl, 859 t4_ethrx_handler, 860 NULL, 861 t4_get_tp_ch_map(adap, 862 pi->tx_chan)); 863 if (err) 864 goto freeout; 865 q->rspq.idx = j; 866 memset(&q->stats, 0, sizeof(q->stats)); 867 } 868 for (j = 0; j < pi->nqsets; j++, t++) { 869 err = t4_sge_alloc_eth_txq(adap, t, dev, 870 netdev_get_tx_queue(dev, j), 871 s->fw_evtq.cntxt_id); 872 if (err) 873 goto freeout; 874 } 875 } 876 877 for_each_port(adap, i) { 878 /* Note that cmplqid below is 0 if we don't 879 * have RDMA queues, and that's the right value. 880 */ 881 if (rxq_info) 882 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 883 884 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 885 s->fw_evtq.cntxt_id, cmplqid); 886 if (err) 887 goto freeout; 888 } 889 890 if (!is_t4(adap->params.chip)) { 891 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 892 netdev_get_tx_queue(adap->port[0], 0) 893 , s->fw_evtq.cntxt_id); 894 if (err) 895 goto freeout; 896 } 897 898 t4_write_reg(adap, is_t4(adap->params.chip) ? 899 MPS_TRC_RSS_CONTROL_A : 900 MPS_T5_TRC_RSS_CONTROL_A, 901 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 902 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 903 return 0; 904 freeout: 905 t4_free_sge_resources(adap); 906 return err; 907 } 908 909 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 910 void *accel_priv, select_queue_fallback_t fallback) 911 { 912 int txq; 913 914 #ifdef CONFIG_CHELSIO_T4_DCB 915 /* If a Data Center Bridging has been successfully negotiated on this 916 * link then we'll use the skb's priority to map it to a TX Queue. 917 * The skb's priority is determined via the VLAN Tag Priority Code 918 * Point field. 919 */ 920 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 921 u16 vlan_tci; 922 int err; 923 924 err = vlan_get_tag(skb, &vlan_tci); 925 if (unlikely(err)) { 926 if (net_ratelimit()) 927 netdev_warn(dev, 928 "TX Packet without VLAN Tag on DCB Link\n"); 929 txq = 0; 930 } else { 931 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 932 #ifdef CONFIG_CHELSIO_T4_FCOE 933 if (skb->protocol == htons(ETH_P_FCOE)) 934 txq = skb->priority & 0x7; 935 #endif /* CONFIG_CHELSIO_T4_FCOE */ 936 } 937 return txq; 938 } 939 #endif /* CONFIG_CHELSIO_T4_DCB */ 940 941 if (select_queue) { 942 txq = (skb_rx_queue_recorded(skb) 943 ? skb_get_rx_queue(skb) 944 : smp_processor_id()); 945 946 while (unlikely(txq >= dev->real_num_tx_queues)) 947 txq -= dev->real_num_tx_queues; 948 949 return txq; 950 } 951 952 return fallback(dev, skb) % dev->real_num_tx_queues; 953 } 954 955 static int closest_timer(const struct sge *s, int time) 956 { 957 int i, delta, match = 0, min_delta = INT_MAX; 958 959 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 960 delta = time - s->timer_val[i]; 961 if (delta < 0) 962 delta = -delta; 963 if (delta < min_delta) { 964 min_delta = delta; 965 match = i; 966 } 967 } 968 return match; 969 } 970 971 static int closest_thres(const struct sge *s, int thres) 972 { 973 int i, delta, match = 0, min_delta = INT_MAX; 974 975 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 976 delta = thres - s->counter_val[i]; 977 if (delta < 0) 978 delta = -delta; 979 if (delta < min_delta) { 980 min_delta = delta; 981 match = i; 982 } 983 } 984 return match; 985 } 986 987 /** 988 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 989 * @q: the Rx queue 990 * @us: the hold-off time in us, or 0 to disable timer 991 * @cnt: the hold-off packet count, or 0 to disable counter 992 * 993 * Sets an Rx queue's interrupt hold-off time and packet count. At least 994 * one of the two needs to be enabled for the queue to generate interrupts. 995 */ 996 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 997 unsigned int us, unsigned int cnt) 998 { 999 struct adapter *adap = q->adap; 1000 1001 if ((us | cnt) == 0) 1002 cnt = 1; 1003 1004 if (cnt) { 1005 int err; 1006 u32 v, new_idx; 1007 1008 new_idx = closest_thres(&adap->sge, cnt); 1009 if (q->desc && q->pktcnt_idx != new_idx) { 1010 /* the queue has already been created, update it */ 1011 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1012 FW_PARAMS_PARAM_X_V( 1013 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1014 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1015 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1016 &v, &new_idx); 1017 if (err) 1018 return err; 1019 } 1020 q->pktcnt_idx = new_idx; 1021 } 1022 1023 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1024 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1025 return 0; 1026 } 1027 1028 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1029 { 1030 const struct port_info *pi = netdev_priv(dev); 1031 netdev_features_t changed = dev->features ^ features; 1032 int err; 1033 1034 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1035 return 0; 1036 1037 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1038 -1, -1, -1, 1039 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1040 if (unlikely(err)) 1041 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1042 return err; 1043 } 1044 1045 static int setup_debugfs(struct adapter *adap) 1046 { 1047 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1048 return -1; 1049 1050 #ifdef CONFIG_DEBUG_FS 1051 t4_setup_debugfs(adap); 1052 #endif 1053 return 0; 1054 } 1055 1056 /* 1057 * upper-layer driver support 1058 */ 1059 1060 /* 1061 * Allocate an active-open TID and set it to the supplied value. 1062 */ 1063 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1064 { 1065 int atid = -1; 1066 1067 spin_lock_bh(&t->atid_lock); 1068 if (t->afree) { 1069 union aopen_entry *p = t->afree; 1070 1071 atid = (p - t->atid_tab) + t->atid_base; 1072 t->afree = p->next; 1073 p->data = data; 1074 t->atids_in_use++; 1075 } 1076 spin_unlock_bh(&t->atid_lock); 1077 return atid; 1078 } 1079 EXPORT_SYMBOL(cxgb4_alloc_atid); 1080 1081 /* 1082 * Release an active-open TID. 1083 */ 1084 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1085 { 1086 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1087 1088 spin_lock_bh(&t->atid_lock); 1089 p->next = t->afree; 1090 t->afree = p; 1091 t->atids_in_use--; 1092 spin_unlock_bh(&t->atid_lock); 1093 } 1094 EXPORT_SYMBOL(cxgb4_free_atid); 1095 1096 /* 1097 * Allocate a server TID and set it to the supplied value. 1098 */ 1099 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1100 { 1101 int stid; 1102 1103 spin_lock_bh(&t->stid_lock); 1104 if (family == PF_INET) { 1105 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1106 if (stid < t->nstids) 1107 __set_bit(stid, t->stid_bmap); 1108 else 1109 stid = -1; 1110 } else { 1111 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1112 if (stid < 0) 1113 stid = -1; 1114 } 1115 if (stid >= 0) { 1116 t->stid_tab[stid].data = data; 1117 stid += t->stid_base; 1118 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1119 * This is equivalent to 4 TIDs. With CLIP enabled it 1120 * needs 2 TIDs. 1121 */ 1122 if (family == PF_INET6) { 1123 t->stids_in_use += 2; 1124 t->v6_stids_in_use += 2; 1125 } else { 1126 t->stids_in_use++; 1127 } 1128 } 1129 spin_unlock_bh(&t->stid_lock); 1130 return stid; 1131 } 1132 EXPORT_SYMBOL(cxgb4_alloc_stid); 1133 1134 /* Allocate a server filter TID and set it to the supplied value. 1135 */ 1136 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1137 { 1138 int stid; 1139 1140 spin_lock_bh(&t->stid_lock); 1141 if (family == PF_INET) { 1142 stid = find_next_zero_bit(t->stid_bmap, 1143 t->nstids + t->nsftids, t->nstids); 1144 if (stid < (t->nstids + t->nsftids)) 1145 __set_bit(stid, t->stid_bmap); 1146 else 1147 stid = -1; 1148 } else { 1149 stid = -1; 1150 } 1151 if (stid >= 0) { 1152 t->stid_tab[stid].data = data; 1153 stid -= t->nstids; 1154 stid += t->sftid_base; 1155 t->sftids_in_use++; 1156 } 1157 spin_unlock_bh(&t->stid_lock); 1158 return stid; 1159 } 1160 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1161 1162 /* Release a server TID. 1163 */ 1164 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1165 { 1166 /* Is it a server filter TID? */ 1167 if (t->nsftids && (stid >= t->sftid_base)) { 1168 stid -= t->sftid_base; 1169 stid += t->nstids; 1170 } else { 1171 stid -= t->stid_base; 1172 } 1173 1174 spin_lock_bh(&t->stid_lock); 1175 if (family == PF_INET) 1176 __clear_bit(stid, t->stid_bmap); 1177 else 1178 bitmap_release_region(t->stid_bmap, stid, 1); 1179 t->stid_tab[stid].data = NULL; 1180 if (stid < t->nstids) { 1181 if (family == PF_INET6) { 1182 t->stids_in_use -= 2; 1183 t->v6_stids_in_use -= 2; 1184 } else { 1185 t->stids_in_use--; 1186 } 1187 } else { 1188 t->sftids_in_use--; 1189 } 1190 1191 spin_unlock_bh(&t->stid_lock); 1192 } 1193 EXPORT_SYMBOL(cxgb4_free_stid); 1194 1195 /* 1196 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1197 */ 1198 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1199 unsigned int tid) 1200 { 1201 struct cpl_tid_release *req; 1202 1203 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1204 req = __skb_put(skb, sizeof(*req)); 1205 INIT_TP_WR(req, tid); 1206 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1207 } 1208 1209 /* 1210 * Queue a TID release request and if necessary schedule a work queue to 1211 * process it. 1212 */ 1213 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1214 unsigned int tid) 1215 { 1216 void **p = &t->tid_tab[tid]; 1217 struct adapter *adap = container_of(t, struct adapter, tids); 1218 1219 spin_lock_bh(&adap->tid_release_lock); 1220 *p = adap->tid_release_head; 1221 /* Low 2 bits encode the Tx channel number */ 1222 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1223 if (!adap->tid_release_task_busy) { 1224 adap->tid_release_task_busy = true; 1225 queue_work(adap->workq, &adap->tid_release_task); 1226 } 1227 spin_unlock_bh(&adap->tid_release_lock); 1228 } 1229 1230 /* 1231 * Process the list of pending TID release requests. 1232 */ 1233 static void process_tid_release_list(struct work_struct *work) 1234 { 1235 struct sk_buff *skb; 1236 struct adapter *adap; 1237 1238 adap = container_of(work, struct adapter, tid_release_task); 1239 1240 spin_lock_bh(&adap->tid_release_lock); 1241 while (adap->tid_release_head) { 1242 void **p = adap->tid_release_head; 1243 unsigned int chan = (uintptr_t)p & 3; 1244 p = (void *)p - chan; 1245 1246 adap->tid_release_head = *p; 1247 *p = NULL; 1248 spin_unlock_bh(&adap->tid_release_lock); 1249 1250 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1251 GFP_KERNEL))) 1252 schedule_timeout_uninterruptible(1); 1253 1254 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1255 t4_ofld_send(adap, skb); 1256 spin_lock_bh(&adap->tid_release_lock); 1257 } 1258 adap->tid_release_task_busy = false; 1259 spin_unlock_bh(&adap->tid_release_lock); 1260 } 1261 1262 /* 1263 * Release a TID and inform HW. If we are unable to allocate the release 1264 * message we defer to a work queue. 1265 */ 1266 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1267 unsigned short family) 1268 { 1269 struct sk_buff *skb; 1270 struct adapter *adap = container_of(t, struct adapter, tids); 1271 1272 WARN_ON(tid >= t->ntids); 1273 1274 if (t->tid_tab[tid]) { 1275 t->tid_tab[tid] = NULL; 1276 atomic_dec(&t->conns_in_use); 1277 if (t->hash_base && (tid >= t->hash_base)) { 1278 if (family == AF_INET6) 1279 atomic_sub(2, &t->hash_tids_in_use); 1280 else 1281 atomic_dec(&t->hash_tids_in_use); 1282 } else { 1283 if (family == AF_INET6) 1284 atomic_sub(2, &t->tids_in_use); 1285 else 1286 atomic_dec(&t->tids_in_use); 1287 } 1288 } 1289 1290 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1291 if (likely(skb)) { 1292 mk_tid_release(skb, chan, tid); 1293 t4_ofld_send(adap, skb); 1294 } else 1295 cxgb4_queue_tid_release(t, chan, tid); 1296 } 1297 EXPORT_SYMBOL(cxgb4_remove_tid); 1298 1299 /* 1300 * Allocate and initialize the TID tables. Returns 0 on success. 1301 */ 1302 static int tid_init(struct tid_info *t) 1303 { 1304 struct adapter *adap = container_of(t, struct adapter, tids); 1305 unsigned int max_ftids = t->nftids + t->nsftids; 1306 unsigned int natids = t->natids; 1307 unsigned int stid_bmap_size; 1308 unsigned int ftid_bmap_size; 1309 size_t size; 1310 1311 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1312 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1313 size = t->ntids * sizeof(*t->tid_tab) + 1314 natids * sizeof(*t->atid_tab) + 1315 t->nstids * sizeof(*t->stid_tab) + 1316 t->nsftids * sizeof(*t->stid_tab) + 1317 stid_bmap_size * sizeof(long) + 1318 max_ftids * sizeof(*t->ftid_tab) + 1319 ftid_bmap_size * sizeof(long); 1320 1321 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1322 if (!t->tid_tab) 1323 return -ENOMEM; 1324 1325 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1326 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1327 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1328 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1329 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1330 spin_lock_init(&t->stid_lock); 1331 spin_lock_init(&t->atid_lock); 1332 spin_lock_init(&t->ftid_lock); 1333 1334 t->stids_in_use = 0; 1335 t->v6_stids_in_use = 0; 1336 t->sftids_in_use = 0; 1337 t->afree = NULL; 1338 t->atids_in_use = 0; 1339 atomic_set(&t->tids_in_use, 0); 1340 atomic_set(&t->conns_in_use, 0); 1341 atomic_set(&t->hash_tids_in_use, 0); 1342 1343 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1344 if (natids) { 1345 while (--natids) 1346 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1347 t->afree = t->atid_tab; 1348 } 1349 1350 if (is_offload(adap)) { 1351 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1352 /* Reserve stid 0 for T4/T5 adapters */ 1353 if (!t->stid_base && 1354 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1355 __set_bit(0, t->stid_bmap); 1356 } 1357 1358 bitmap_zero(t->ftid_bmap, t->nftids); 1359 return 0; 1360 } 1361 1362 /** 1363 * cxgb4_create_server - create an IP server 1364 * @dev: the device 1365 * @stid: the server TID 1366 * @sip: local IP address to bind server to 1367 * @sport: the server's TCP port 1368 * @queue: queue to direct messages from this server to 1369 * 1370 * Create an IP server for the given port and address. 1371 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1372 */ 1373 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1374 __be32 sip, __be16 sport, __be16 vlan, 1375 unsigned int queue) 1376 { 1377 unsigned int chan; 1378 struct sk_buff *skb; 1379 struct adapter *adap; 1380 struct cpl_pass_open_req *req; 1381 int ret; 1382 1383 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1384 if (!skb) 1385 return -ENOMEM; 1386 1387 adap = netdev2adap(dev); 1388 req = __skb_put(skb, sizeof(*req)); 1389 INIT_TP_WR(req, 0); 1390 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1391 req->local_port = sport; 1392 req->peer_port = htons(0); 1393 req->local_ip = sip; 1394 req->peer_ip = htonl(0); 1395 chan = rxq_to_chan(&adap->sge, queue); 1396 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1397 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1398 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1399 ret = t4_mgmt_tx(adap, skb); 1400 return net_xmit_eval(ret); 1401 } 1402 EXPORT_SYMBOL(cxgb4_create_server); 1403 1404 /* cxgb4_create_server6 - create an IPv6 server 1405 * @dev: the device 1406 * @stid: the server TID 1407 * @sip: local IPv6 address to bind server to 1408 * @sport: the server's TCP port 1409 * @queue: queue to direct messages from this server to 1410 * 1411 * Create an IPv6 server for the given port and address. 1412 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1413 */ 1414 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1415 const struct in6_addr *sip, __be16 sport, 1416 unsigned int queue) 1417 { 1418 unsigned int chan; 1419 struct sk_buff *skb; 1420 struct adapter *adap; 1421 struct cpl_pass_open_req6 *req; 1422 int ret; 1423 1424 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1425 if (!skb) 1426 return -ENOMEM; 1427 1428 adap = netdev2adap(dev); 1429 req = __skb_put(skb, sizeof(*req)); 1430 INIT_TP_WR(req, 0); 1431 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1432 req->local_port = sport; 1433 req->peer_port = htons(0); 1434 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1435 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1436 req->peer_ip_hi = cpu_to_be64(0); 1437 req->peer_ip_lo = cpu_to_be64(0); 1438 chan = rxq_to_chan(&adap->sge, queue); 1439 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1440 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1441 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1442 ret = t4_mgmt_tx(adap, skb); 1443 return net_xmit_eval(ret); 1444 } 1445 EXPORT_SYMBOL(cxgb4_create_server6); 1446 1447 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1448 unsigned int queue, bool ipv6) 1449 { 1450 struct sk_buff *skb; 1451 struct adapter *adap; 1452 struct cpl_close_listsvr_req *req; 1453 int ret; 1454 1455 adap = netdev2adap(dev); 1456 1457 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1458 if (!skb) 1459 return -ENOMEM; 1460 1461 req = __skb_put(skb, sizeof(*req)); 1462 INIT_TP_WR(req, 0); 1463 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1464 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1465 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1466 ret = t4_mgmt_tx(adap, skb); 1467 return net_xmit_eval(ret); 1468 } 1469 EXPORT_SYMBOL(cxgb4_remove_server); 1470 1471 /** 1472 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1473 * @mtus: the HW MTU table 1474 * @mtu: the target MTU 1475 * @idx: index of selected entry in the MTU table 1476 * 1477 * Returns the index and the value in the HW MTU table that is closest to 1478 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1479 * table, in which case that smallest available value is selected. 1480 */ 1481 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1482 unsigned int *idx) 1483 { 1484 unsigned int i = 0; 1485 1486 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1487 ++i; 1488 if (idx) 1489 *idx = i; 1490 return mtus[i]; 1491 } 1492 EXPORT_SYMBOL(cxgb4_best_mtu); 1493 1494 /** 1495 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1496 * @mtus: the HW MTU table 1497 * @header_size: Header Size 1498 * @data_size_max: maximum Data Segment Size 1499 * @data_size_align: desired Data Segment Size Alignment (2^N) 1500 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1501 * 1502 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1503 * MTU Table based solely on a Maximum MTU parameter, we break that 1504 * parameter up into a Header Size and Maximum Data Segment Size, and 1505 * provide a desired Data Segment Size Alignment. If we find an MTU in 1506 * the Hardware MTU Table which will result in a Data Segment Size with 1507 * the requested alignment _and_ that MTU isn't "too far" from the 1508 * closest MTU, then we'll return that rather than the closest MTU. 1509 */ 1510 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1511 unsigned short header_size, 1512 unsigned short data_size_max, 1513 unsigned short data_size_align, 1514 unsigned int *mtu_idxp) 1515 { 1516 unsigned short max_mtu = header_size + data_size_max; 1517 unsigned short data_size_align_mask = data_size_align - 1; 1518 int mtu_idx, aligned_mtu_idx; 1519 1520 /* Scan the MTU Table till we find an MTU which is larger than our 1521 * Maximum MTU or we reach the end of the table. Along the way, 1522 * record the last MTU found, if any, which will result in a Data 1523 * Segment Length matching the requested alignment. 1524 */ 1525 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1526 unsigned short data_size = mtus[mtu_idx] - header_size; 1527 1528 /* If this MTU minus the Header Size would result in a 1529 * Data Segment Size of the desired alignment, remember it. 1530 */ 1531 if ((data_size & data_size_align_mask) == 0) 1532 aligned_mtu_idx = mtu_idx; 1533 1534 /* If we're not at the end of the Hardware MTU Table and the 1535 * next element is larger than our Maximum MTU, drop out of 1536 * the loop. 1537 */ 1538 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1539 break; 1540 } 1541 1542 /* If we fell out of the loop because we ran to the end of the table, 1543 * then we just have to use the last [largest] entry. 1544 */ 1545 if (mtu_idx == NMTUS) 1546 mtu_idx--; 1547 1548 /* If we found an MTU which resulted in the requested Data Segment 1549 * Length alignment and that's "not far" from the largest MTU which is 1550 * less than or equal to the maximum MTU, then use that. 1551 */ 1552 if (aligned_mtu_idx >= 0 && 1553 mtu_idx - aligned_mtu_idx <= 1) 1554 mtu_idx = aligned_mtu_idx; 1555 1556 /* If the caller has passed in an MTU Index pointer, pass the 1557 * MTU Index back. Return the MTU value. 1558 */ 1559 if (mtu_idxp) 1560 *mtu_idxp = mtu_idx; 1561 return mtus[mtu_idx]; 1562 } 1563 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1564 1565 /** 1566 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI 1567 * @chip: chip type 1568 * @viid: VI id of the given port 1569 * 1570 * Return the SMT index for this VI. 1571 */ 1572 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid) 1573 { 1574 /* In T4/T5, SMT contains 256 SMAC entries organized in 1575 * 128 rows of 2 entries each. 1576 * In T6, SMT contains 256 SMAC entries in 256 rows. 1577 * TODO: The below code needs to be updated when we add support 1578 * for 256 VFs. 1579 */ 1580 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5) 1581 return ((viid & 0x7f) << 1); 1582 else 1583 return (viid & 0x7f); 1584 } 1585 EXPORT_SYMBOL(cxgb4_tp_smt_idx); 1586 1587 /** 1588 * cxgb4_port_chan - get the HW channel of a port 1589 * @dev: the net device for the port 1590 * 1591 * Return the HW Tx channel of the given port. 1592 */ 1593 unsigned int cxgb4_port_chan(const struct net_device *dev) 1594 { 1595 return netdev2pinfo(dev)->tx_chan; 1596 } 1597 EXPORT_SYMBOL(cxgb4_port_chan); 1598 1599 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1600 { 1601 struct adapter *adap = netdev2adap(dev); 1602 u32 v1, v2, lp_count, hp_count; 1603 1604 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1605 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1606 if (is_t4(adap->params.chip)) { 1607 lp_count = LP_COUNT_G(v1); 1608 hp_count = HP_COUNT_G(v1); 1609 } else { 1610 lp_count = LP_COUNT_T5_G(v1); 1611 hp_count = HP_COUNT_T5_G(v2); 1612 } 1613 return lpfifo ? lp_count : hp_count; 1614 } 1615 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1616 1617 /** 1618 * cxgb4_port_viid - get the VI id of a port 1619 * @dev: the net device for the port 1620 * 1621 * Return the VI id of the given port. 1622 */ 1623 unsigned int cxgb4_port_viid(const struct net_device *dev) 1624 { 1625 return netdev2pinfo(dev)->viid; 1626 } 1627 EXPORT_SYMBOL(cxgb4_port_viid); 1628 1629 /** 1630 * cxgb4_port_idx - get the index of a port 1631 * @dev: the net device for the port 1632 * 1633 * Return the index of the given port. 1634 */ 1635 unsigned int cxgb4_port_idx(const struct net_device *dev) 1636 { 1637 return netdev2pinfo(dev)->port_id; 1638 } 1639 EXPORT_SYMBOL(cxgb4_port_idx); 1640 1641 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1642 struct tp_tcp_stats *v6) 1643 { 1644 struct adapter *adap = pci_get_drvdata(pdev); 1645 1646 spin_lock(&adap->stats_lock); 1647 t4_tp_get_tcp_stats(adap, v4, v6, false); 1648 spin_unlock(&adap->stats_lock); 1649 } 1650 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1651 1652 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1653 const unsigned int *pgsz_order) 1654 { 1655 struct adapter *adap = netdev2adap(dev); 1656 1657 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1658 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1659 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 1660 HPZ3_V(pgsz_order[3])); 1661 } 1662 EXPORT_SYMBOL(cxgb4_iscsi_init); 1663 1664 int cxgb4_flush_eq_cache(struct net_device *dev) 1665 { 1666 struct adapter *adap = netdev2adap(dev); 1667 1668 return t4_sge_ctxt_flush(adap, adap->mbox); 1669 } 1670 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 1671 1672 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 1673 { 1674 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 1675 __be64 indices; 1676 int ret; 1677 1678 spin_lock(&adap->win0_lock); 1679 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 1680 sizeof(indices), (__be32 *)&indices, 1681 T4_MEMORY_READ); 1682 spin_unlock(&adap->win0_lock); 1683 if (!ret) { 1684 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 1685 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 1686 } 1687 return ret; 1688 } 1689 1690 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 1691 u16 size) 1692 { 1693 struct adapter *adap = netdev2adap(dev); 1694 u16 hw_pidx, hw_cidx; 1695 int ret; 1696 1697 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 1698 if (ret) 1699 goto out; 1700 1701 if (pidx != hw_pidx) { 1702 u16 delta; 1703 u32 val; 1704 1705 if (pidx >= hw_pidx) 1706 delta = pidx - hw_pidx; 1707 else 1708 delta = size - hw_pidx + pidx; 1709 1710 if (is_t4(adap->params.chip)) 1711 val = PIDX_V(delta); 1712 else 1713 val = PIDX_T5_V(delta); 1714 wmb(); 1715 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1716 QID_V(qid) | val); 1717 } 1718 out: 1719 return ret; 1720 } 1721 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 1722 1723 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 1724 { 1725 struct adapter *adap; 1726 u32 offset, memtype, memaddr; 1727 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 1728 u32 edc0_end, edc1_end, mc0_end, mc1_end; 1729 int ret; 1730 1731 adap = netdev2adap(dev); 1732 1733 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 1734 1735 /* Figure out where the offset lands in the Memory Type/Address scheme. 1736 * This code assumes that the memory is laid out starting at offset 0 1737 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 1738 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 1739 * MC0, and some have both MC0 and MC1. 1740 */ 1741 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 1742 edc0_size = EDRAM0_SIZE_G(size) << 20; 1743 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 1744 edc1_size = EDRAM1_SIZE_G(size) << 20; 1745 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 1746 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 1747 1748 edc0_end = edc0_size; 1749 edc1_end = edc0_end + edc1_size; 1750 mc0_end = edc1_end + mc0_size; 1751 1752 if (offset < edc0_end) { 1753 memtype = MEM_EDC0; 1754 memaddr = offset; 1755 } else if (offset < edc1_end) { 1756 memtype = MEM_EDC1; 1757 memaddr = offset - edc0_end; 1758 } else { 1759 if (offset < mc0_end) { 1760 memtype = MEM_MC0; 1761 memaddr = offset - edc1_end; 1762 } else if (is_t5(adap->params.chip)) { 1763 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1764 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 1765 mc1_end = mc0_end + mc1_size; 1766 if (offset < mc1_end) { 1767 memtype = MEM_MC1; 1768 memaddr = offset - mc0_end; 1769 } else { 1770 /* offset beyond the end of any memory */ 1771 goto err; 1772 } 1773 } else { 1774 /* T4/T6 only has a single memory channel */ 1775 goto err; 1776 } 1777 } 1778 1779 spin_lock(&adap->win0_lock); 1780 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 1781 spin_unlock(&adap->win0_lock); 1782 return ret; 1783 1784 err: 1785 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 1786 stag, offset); 1787 return -EINVAL; 1788 } 1789 EXPORT_SYMBOL(cxgb4_read_tpte); 1790 1791 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 1792 { 1793 u32 hi, lo; 1794 struct adapter *adap; 1795 1796 adap = netdev2adap(dev); 1797 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 1798 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 1799 1800 return ((u64)hi << 32) | (u64)lo; 1801 } 1802 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 1803 1804 int cxgb4_bar2_sge_qregs(struct net_device *dev, 1805 unsigned int qid, 1806 enum cxgb4_bar2_qtype qtype, 1807 int user, 1808 u64 *pbar2_qoffset, 1809 unsigned int *pbar2_qid) 1810 { 1811 return t4_bar2_sge_qregs(netdev2adap(dev), 1812 qid, 1813 (qtype == CXGB4_BAR2_QTYPE_EGRESS 1814 ? T4_BAR2_QTYPE_EGRESS 1815 : T4_BAR2_QTYPE_INGRESS), 1816 user, 1817 pbar2_qoffset, 1818 pbar2_qid); 1819 } 1820 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 1821 1822 static struct pci_driver cxgb4_driver; 1823 1824 static void check_neigh_update(struct neighbour *neigh) 1825 { 1826 const struct device *parent; 1827 const struct net_device *netdev = neigh->dev; 1828 1829 if (is_vlan_dev(netdev)) 1830 netdev = vlan_dev_real_dev(netdev); 1831 parent = netdev->dev.parent; 1832 if (parent && parent->driver == &cxgb4_driver.driver) 1833 t4_l2t_update(dev_get_drvdata(parent), neigh); 1834 } 1835 1836 static int netevent_cb(struct notifier_block *nb, unsigned long event, 1837 void *data) 1838 { 1839 switch (event) { 1840 case NETEVENT_NEIGH_UPDATE: 1841 check_neigh_update(data); 1842 break; 1843 case NETEVENT_REDIRECT: 1844 default: 1845 break; 1846 } 1847 return 0; 1848 } 1849 1850 static bool netevent_registered; 1851 static struct notifier_block cxgb4_netevent_nb = { 1852 .notifier_call = netevent_cb 1853 }; 1854 1855 static void drain_db_fifo(struct adapter *adap, int usecs) 1856 { 1857 u32 v1, v2, lp_count, hp_count; 1858 1859 do { 1860 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1861 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1862 if (is_t4(adap->params.chip)) { 1863 lp_count = LP_COUNT_G(v1); 1864 hp_count = HP_COUNT_G(v1); 1865 } else { 1866 lp_count = LP_COUNT_T5_G(v1); 1867 hp_count = HP_COUNT_T5_G(v2); 1868 } 1869 1870 if (lp_count == 0 && hp_count == 0) 1871 break; 1872 set_current_state(TASK_UNINTERRUPTIBLE); 1873 schedule_timeout(usecs_to_jiffies(usecs)); 1874 } while (1); 1875 } 1876 1877 static void disable_txq_db(struct sge_txq *q) 1878 { 1879 unsigned long flags; 1880 1881 spin_lock_irqsave(&q->db_lock, flags); 1882 q->db_disabled = 1; 1883 spin_unlock_irqrestore(&q->db_lock, flags); 1884 } 1885 1886 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 1887 { 1888 spin_lock_irq(&q->db_lock); 1889 if (q->db_pidx_inc) { 1890 /* Make sure that all writes to the TX descriptors 1891 * are committed before we tell HW about them. 1892 */ 1893 wmb(); 1894 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1895 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 1896 q->db_pidx_inc = 0; 1897 } 1898 q->db_disabled = 0; 1899 spin_unlock_irq(&q->db_lock); 1900 } 1901 1902 static void disable_dbs(struct adapter *adap) 1903 { 1904 int i; 1905 1906 for_each_ethrxq(&adap->sge, i) 1907 disable_txq_db(&adap->sge.ethtxq[i].q); 1908 if (is_offload(adap)) { 1909 struct sge_uld_txq_info *txq_info = 1910 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1911 1912 if (txq_info) { 1913 for_each_ofldtxq(&adap->sge, i) { 1914 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1915 1916 disable_txq_db(&txq->q); 1917 } 1918 } 1919 } 1920 for_each_port(adap, i) 1921 disable_txq_db(&adap->sge.ctrlq[i].q); 1922 } 1923 1924 static void enable_dbs(struct adapter *adap) 1925 { 1926 int i; 1927 1928 for_each_ethrxq(&adap->sge, i) 1929 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 1930 if (is_offload(adap)) { 1931 struct sge_uld_txq_info *txq_info = 1932 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 1933 1934 if (txq_info) { 1935 for_each_ofldtxq(&adap->sge, i) { 1936 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 1937 1938 enable_txq_db(adap, &txq->q); 1939 } 1940 } 1941 } 1942 for_each_port(adap, i) 1943 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 1944 } 1945 1946 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 1947 { 1948 enum cxgb4_uld type = CXGB4_ULD_RDMA; 1949 1950 if (adap->uld && adap->uld[type].handle) 1951 adap->uld[type].control(adap->uld[type].handle, cmd); 1952 } 1953 1954 static void process_db_full(struct work_struct *work) 1955 { 1956 struct adapter *adap; 1957 1958 adap = container_of(work, struct adapter, db_full_task); 1959 1960 drain_db_fifo(adap, dbfifo_drain_delay); 1961 enable_dbs(adap); 1962 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 1963 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1964 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1965 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 1966 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 1967 else 1968 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 1969 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 1970 } 1971 1972 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 1973 { 1974 u16 hw_pidx, hw_cidx; 1975 int ret; 1976 1977 spin_lock_irq(&q->db_lock); 1978 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 1979 if (ret) 1980 goto out; 1981 if (q->db_pidx != hw_pidx) { 1982 u16 delta; 1983 u32 val; 1984 1985 if (q->db_pidx >= hw_pidx) 1986 delta = q->db_pidx - hw_pidx; 1987 else 1988 delta = q->size - hw_pidx + q->db_pidx; 1989 1990 if (is_t4(adap->params.chip)) 1991 val = PIDX_V(delta); 1992 else 1993 val = PIDX_T5_V(delta); 1994 wmb(); 1995 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1996 QID_V(q->cntxt_id) | val); 1997 } 1998 out: 1999 q->db_disabled = 0; 2000 q->db_pidx_inc = 0; 2001 spin_unlock_irq(&q->db_lock); 2002 if (ret) 2003 CH_WARN(adap, "DB drop recovery failed.\n"); 2004 } 2005 2006 static void recover_all_queues(struct adapter *adap) 2007 { 2008 int i; 2009 2010 for_each_ethrxq(&adap->sge, i) 2011 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2012 if (is_offload(adap)) { 2013 struct sge_uld_txq_info *txq_info = 2014 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2015 if (txq_info) { 2016 for_each_ofldtxq(&adap->sge, i) { 2017 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2018 2019 sync_txq_pidx(adap, &txq->q); 2020 } 2021 } 2022 } 2023 for_each_port(adap, i) 2024 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2025 } 2026 2027 static void process_db_drop(struct work_struct *work) 2028 { 2029 struct adapter *adap; 2030 2031 adap = container_of(work, struct adapter, db_drop_task); 2032 2033 if (is_t4(adap->params.chip)) { 2034 drain_db_fifo(adap, dbfifo_drain_delay); 2035 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2036 drain_db_fifo(adap, dbfifo_drain_delay); 2037 recover_all_queues(adap); 2038 drain_db_fifo(adap, dbfifo_drain_delay); 2039 enable_dbs(adap); 2040 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2041 } else if (is_t5(adap->params.chip)) { 2042 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2043 u16 qid = (dropped_db >> 15) & 0x1ffff; 2044 u16 pidx_inc = dropped_db & 0x1fff; 2045 u64 bar2_qoffset; 2046 unsigned int bar2_qid; 2047 int ret; 2048 2049 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2050 0, &bar2_qoffset, &bar2_qid); 2051 if (ret) 2052 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2053 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2054 else 2055 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2056 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2057 2058 /* Re-enable BAR2 WC */ 2059 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2060 } 2061 2062 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2063 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2064 } 2065 2066 void t4_db_full(struct adapter *adap) 2067 { 2068 if (is_t4(adap->params.chip)) { 2069 disable_dbs(adap); 2070 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2071 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2072 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2073 queue_work(adap->workq, &adap->db_full_task); 2074 } 2075 } 2076 2077 void t4_db_dropped(struct adapter *adap) 2078 { 2079 if (is_t4(adap->params.chip)) { 2080 disable_dbs(adap); 2081 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2082 } 2083 queue_work(adap->workq, &adap->db_drop_task); 2084 } 2085 2086 void t4_register_netevent_notifier(void) 2087 { 2088 if (!netevent_registered) { 2089 register_netevent_notifier(&cxgb4_netevent_nb); 2090 netevent_registered = true; 2091 } 2092 } 2093 2094 static void detach_ulds(struct adapter *adap) 2095 { 2096 unsigned int i; 2097 2098 mutex_lock(&uld_mutex); 2099 list_del(&adap->list_node); 2100 2101 for (i = 0; i < CXGB4_ULD_MAX; i++) 2102 if (adap->uld && adap->uld[i].handle) 2103 adap->uld[i].state_change(adap->uld[i].handle, 2104 CXGB4_STATE_DETACH); 2105 2106 if (netevent_registered && list_empty(&adapter_list)) { 2107 unregister_netevent_notifier(&cxgb4_netevent_nb); 2108 netevent_registered = false; 2109 } 2110 mutex_unlock(&uld_mutex); 2111 } 2112 2113 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2114 { 2115 unsigned int i; 2116 2117 mutex_lock(&uld_mutex); 2118 for (i = 0; i < CXGB4_ULD_MAX; i++) 2119 if (adap->uld && adap->uld[i].handle) 2120 adap->uld[i].state_change(adap->uld[i].handle, 2121 new_state); 2122 mutex_unlock(&uld_mutex); 2123 } 2124 2125 #if IS_ENABLED(CONFIG_IPV6) 2126 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2127 unsigned long event, void *data) 2128 { 2129 struct inet6_ifaddr *ifa = data; 2130 struct net_device *event_dev = ifa->idev->dev; 2131 const struct device *parent = NULL; 2132 #if IS_ENABLED(CONFIG_BONDING) 2133 struct adapter *adap; 2134 #endif 2135 if (is_vlan_dev(event_dev)) 2136 event_dev = vlan_dev_real_dev(event_dev); 2137 #if IS_ENABLED(CONFIG_BONDING) 2138 if (event_dev->flags & IFF_MASTER) { 2139 list_for_each_entry(adap, &adapter_list, list_node) { 2140 switch (event) { 2141 case NETDEV_UP: 2142 cxgb4_clip_get(adap->port[0], 2143 (const u32 *)ifa, 1); 2144 break; 2145 case NETDEV_DOWN: 2146 cxgb4_clip_release(adap->port[0], 2147 (const u32 *)ifa, 1); 2148 break; 2149 default: 2150 break; 2151 } 2152 } 2153 return NOTIFY_OK; 2154 } 2155 #endif 2156 2157 if (event_dev) 2158 parent = event_dev->dev.parent; 2159 2160 if (parent && parent->driver == &cxgb4_driver.driver) { 2161 switch (event) { 2162 case NETDEV_UP: 2163 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2164 break; 2165 case NETDEV_DOWN: 2166 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2167 break; 2168 default: 2169 break; 2170 } 2171 } 2172 return NOTIFY_OK; 2173 } 2174 2175 static bool inet6addr_registered; 2176 static struct notifier_block cxgb4_inet6addr_notifier = { 2177 .notifier_call = cxgb4_inet6addr_handler 2178 }; 2179 2180 static void update_clip(const struct adapter *adap) 2181 { 2182 int i; 2183 struct net_device *dev; 2184 int ret; 2185 2186 rcu_read_lock(); 2187 2188 for (i = 0; i < MAX_NPORTS; i++) { 2189 dev = adap->port[i]; 2190 ret = 0; 2191 2192 if (dev) 2193 ret = cxgb4_update_root_dev_clip(dev); 2194 2195 if (ret < 0) 2196 break; 2197 } 2198 rcu_read_unlock(); 2199 } 2200 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2201 2202 /** 2203 * cxgb_up - enable the adapter 2204 * @adap: adapter being enabled 2205 * 2206 * Called when the first port is enabled, this function performs the 2207 * actions necessary to make an adapter operational, such as completing 2208 * the initialization of HW modules, and enabling interrupts. 2209 * 2210 * Must be called with the rtnl lock held. 2211 */ 2212 static int cxgb_up(struct adapter *adap) 2213 { 2214 int err; 2215 2216 mutex_lock(&uld_mutex); 2217 err = setup_sge_queues(adap); 2218 if (err) 2219 goto rel_lock; 2220 err = setup_rss(adap); 2221 if (err) 2222 goto freeq; 2223 2224 if (adap->flags & USING_MSIX) { 2225 name_msix_vecs(adap); 2226 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2227 adap->msix_info[0].desc, adap); 2228 if (err) 2229 goto irq_err; 2230 err = request_msix_queue_irqs(adap); 2231 if (err) { 2232 free_irq(adap->msix_info[0].vec, adap); 2233 goto irq_err; 2234 } 2235 } else { 2236 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2237 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED, 2238 adap->port[0]->name, adap); 2239 if (err) 2240 goto irq_err; 2241 } 2242 2243 enable_rx(adap); 2244 t4_sge_start(adap); 2245 t4_intr_enable(adap); 2246 adap->flags |= FULL_INIT_DONE; 2247 mutex_unlock(&uld_mutex); 2248 2249 notify_ulds(adap, CXGB4_STATE_UP); 2250 #if IS_ENABLED(CONFIG_IPV6) 2251 update_clip(adap); 2252 #endif 2253 /* Initialize hash mac addr list*/ 2254 INIT_LIST_HEAD(&adap->mac_hlist); 2255 return err; 2256 2257 irq_err: 2258 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2259 freeq: 2260 t4_free_sge_resources(adap); 2261 rel_lock: 2262 mutex_unlock(&uld_mutex); 2263 return err; 2264 } 2265 2266 static void cxgb_down(struct adapter *adapter) 2267 { 2268 cancel_work_sync(&adapter->tid_release_task); 2269 cancel_work_sync(&adapter->db_full_task); 2270 cancel_work_sync(&adapter->db_drop_task); 2271 adapter->tid_release_task_busy = false; 2272 adapter->tid_release_head = NULL; 2273 2274 t4_sge_stop(adapter); 2275 t4_free_sge_resources(adapter); 2276 adapter->flags &= ~FULL_INIT_DONE; 2277 } 2278 2279 /* 2280 * net_device operations 2281 */ 2282 static int cxgb_open(struct net_device *dev) 2283 { 2284 int err; 2285 struct port_info *pi = netdev_priv(dev); 2286 struct adapter *adapter = pi->adapter; 2287 2288 netif_carrier_off(dev); 2289 2290 if (!(adapter->flags & FULL_INIT_DONE)) { 2291 err = cxgb_up(adapter); 2292 if (err < 0) 2293 return err; 2294 } 2295 2296 /* It's possible that the basic port information could have 2297 * changed since we first read it. 2298 */ 2299 err = t4_update_port_info(pi); 2300 if (err < 0) 2301 return err; 2302 2303 err = link_start(dev); 2304 if (!err) 2305 netif_tx_start_all_queues(dev); 2306 return err; 2307 } 2308 2309 static int cxgb_close(struct net_device *dev) 2310 { 2311 struct port_info *pi = netdev_priv(dev); 2312 struct adapter *adapter = pi->adapter; 2313 int ret; 2314 2315 netif_tx_stop_all_queues(dev); 2316 netif_carrier_off(dev); 2317 ret = t4_enable_vi(adapter, adapter->pf, pi->viid, false, false); 2318 #ifdef CONFIG_CHELSIO_T4_DCB 2319 cxgb4_dcb_reset(dev); 2320 dcb_tx_queue_prio_enable(dev, false); 2321 #endif 2322 return ret; 2323 } 2324 2325 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2326 __be32 sip, __be16 sport, __be16 vlan, 2327 unsigned int queue, unsigned char port, unsigned char mask) 2328 { 2329 int ret; 2330 struct filter_entry *f; 2331 struct adapter *adap; 2332 int i; 2333 u8 *val; 2334 2335 adap = netdev2adap(dev); 2336 2337 /* Adjust stid to correct filter index */ 2338 stid -= adap->tids.sftid_base; 2339 stid += adap->tids.nftids; 2340 2341 /* Check to make sure the filter requested is writable ... 2342 */ 2343 f = &adap->tids.ftid_tab[stid]; 2344 ret = writable_filter(f); 2345 if (ret) 2346 return ret; 2347 2348 /* Clear out any old resources being used by the filter before 2349 * we start constructing the new filter. 2350 */ 2351 if (f->valid) 2352 clear_filter(adap, f); 2353 2354 /* Clear out filter specifications */ 2355 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2356 f->fs.val.lport = cpu_to_be16(sport); 2357 f->fs.mask.lport = ~0; 2358 val = (u8 *)&sip; 2359 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2360 for (i = 0; i < 4; i++) { 2361 f->fs.val.lip[i] = val[i]; 2362 f->fs.mask.lip[i] = ~0; 2363 } 2364 if (adap->params.tp.vlan_pri_map & PORT_F) { 2365 f->fs.val.iport = port; 2366 f->fs.mask.iport = mask; 2367 } 2368 } 2369 2370 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2371 f->fs.val.proto = IPPROTO_TCP; 2372 f->fs.mask.proto = ~0; 2373 } 2374 2375 f->fs.dirsteer = 1; 2376 f->fs.iq = queue; 2377 /* Mark filter as locked */ 2378 f->locked = 1; 2379 f->fs.rpttid = 1; 2380 2381 /* Save the actual tid. We need this to get the corresponding 2382 * filter entry structure in filter_rpl. 2383 */ 2384 f->tid = stid + adap->tids.ftid_base; 2385 ret = set_filter_wr(adap, stid); 2386 if (ret) { 2387 clear_filter(adap, f); 2388 return ret; 2389 } 2390 2391 return 0; 2392 } 2393 EXPORT_SYMBOL(cxgb4_create_server_filter); 2394 2395 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2396 unsigned int queue, bool ipv6) 2397 { 2398 struct filter_entry *f; 2399 struct adapter *adap; 2400 2401 adap = netdev2adap(dev); 2402 2403 /* Adjust stid to correct filter index */ 2404 stid -= adap->tids.sftid_base; 2405 stid += adap->tids.nftids; 2406 2407 f = &adap->tids.ftid_tab[stid]; 2408 /* Unlock the filter */ 2409 f->locked = 0; 2410 2411 return delete_filter(adap, stid); 2412 } 2413 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2414 2415 static void cxgb_get_stats(struct net_device *dev, 2416 struct rtnl_link_stats64 *ns) 2417 { 2418 struct port_stats stats; 2419 struct port_info *p = netdev_priv(dev); 2420 struct adapter *adapter = p->adapter; 2421 2422 /* Block retrieving statistics during EEH error 2423 * recovery. Otherwise, the recovery might fail 2424 * and the PCI device will be removed permanently 2425 */ 2426 spin_lock(&adapter->stats_lock); 2427 if (!netif_device_present(dev)) { 2428 spin_unlock(&adapter->stats_lock); 2429 return; 2430 } 2431 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2432 &p->stats_base); 2433 spin_unlock(&adapter->stats_lock); 2434 2435 ns->tx_bytes = stats.tx_octets; 2436 ns->tx_packets = stats.tx_frames; 2437 ns->rx_bytes = stats.rx_octets; 2438 ns->rx_packets = stats.rx_frames; 2439 ns->multicast = stats.rx_mcast_frames; 2440 2441 /* detailed rx_errors */ 2442 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2443 stats.rx_runt; 2444 ns->rx_over_errors = 0; 2445 ns->rx_crc_errors = stats.rx_fcs_err; 2446 ns->rx_frame_errors = stats.rx_symbol_err; 2447 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 2448 stats.rx_ovflow2 + stats.rx_ovflow3 + 2449 stats.rx_trunc0 + stats.rx_trunc1 + 2450 stats.rx_trunc2 + stats.rx_trunc3; 2451 ns->rx_missed_errors = 0; 2452 2453 /* detailed tx_errors */ 2454 ns->tx_aborted_errors = 0; 2455 ns->tx_carrier_errors = 0; 2456 ns->tx_fifo_errors = 0; 2457 ns->tx_heartbeat_errors = 0; 2458 ns->tx_window_errors = 0; 2459 2460 ns->tx_errors = stats.tx_error_frames; 2461 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2462 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2463 } 2464 2465 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2466 { 2467 unsigned int mbox; 2468 int ret = 0, prtad, devad; 2469 struct port_info *pi = netdev_priv(dev); 2470 struct adapter *adapter = pi->adapter; 2471 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2472 2473 switch (cmd) { 2474 case SIOCGMIIPHY: 2475 if (pi->mdio_addr < 0) 2476 return -EOPNOTSUPP; 2477 data->phy_id = pi->mdio_addr; 2478 break; 2479 case SIOCGMIIREG: 2480 case SIOCSMIIREG: 2481 if (mdio_phy_id_is_c45(data->phy_id)) { 2482 prtad = mdio_phy_id_prtad(data->phy_id); 2483 devad = mdio_phy_id_devad(data->phy_id); 2484 } else if (data->phy_id < 32) { 2485 prtad = data->phy_id; 2486 devad = 0; 2487 data->reg_num &= 0x1f; 2488 } else 2489 return -EINVAL; 2490 2491 mbox = pi->adapter->pf; 2492 if (cmd == SIOCGMIIREG) 2493 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2494 data->reg_num, &data->val_out); 2495 else 2496 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2497 data->reg_num, data->val_in); 2498 break; 2499 case SIOCGHWTSTAMP: 2500 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2501 sizeof(pi->tstamp_config)) ? 2502 -EFAULT : 0; 2503 case SIOCSHWTSTAMP: 2504 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 2505 sizeof(pi->tstamp_config))) 2506 return -EFAULT; 2507 2508 if (!is_t4(adapter->params.chip)) { 2509 switch (pi->tstamp_config.tx_type) { 2510 case HWTSTAMP_TX_OFF: 2511 case HWTSTAMP_TX_ON: 2512 break; 2513 default: 2514 return -ERANGE; 2515 } 2516 2517 switch (pi->tstamp_config.rx_filter) { 2518 case HWTSTAMP_FILTER_NONE: 2519 pi->rxtstamp = false; 2520 break; 2521 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2522 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2523 cxgb4_ptprx_timestamping(pi, pi->port_id, 2524 PTP_TS_L4); 2525 break; 2526 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2527 cxgb4_ptprx_timestamping(pi, pi->port_id, 2528 PTP_TS_L2_L4); 2529 break; 2530 case HWTSTAMP_FILTER_ALL: 2531 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2532 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2533 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2534 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2535 pi->rxtstamp = true; 2536 break; 2537 default: 2538 pi->tstamp_config.rx_filter = 2539 HWTSTAMP_FILTER_NONE; 2540 return -ERANGE; 2541 } 2542 2543 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 2544 (pi->tstamp_config.rx_filter == 2545 HWTSTAMP_FILTER_NONE)) { 2546 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 2547 pi->ptp_enable = false; 2548 } 2549 2550 if (pi->tstamp_config.rx_filter != 2551 HWTSTAMP_FILTER_NONE) { 2552 if (cxgb4_ptp_redirect_rx_packet(adapter, 2553 pi) >= 0) 2554 pi->ptp_enable = true; 2555 } 2556 } else { 2557 /* For T4 Adapters */ 2558 switch (pi->tstamp_config.rx_filter) { 2559 case HWTSTAMP_FILTER_NONE: 2560 pi->rxtstamp = false; 2561 break; 2562 case HWTSTAMP_FILTER_ALL: 2563 pi->rxtstamp = true; 2564 break; 2565 default: 2566 pi->tstamp_config.rx_filter = 2567 HWTSTAMP_FILTER_NONE; 2568 return -ERANGE; 2569 } 2570 } 2571 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2572 sizeof(pi->tstamp_config)) ? 2573 -EFAULT : 0; 2574 default: 2575 return -EOPNOTSUPP; 2576 } 2577 return ret; 2578 } 2579 2580 static void cxgb_set_rxmode(struct net_device *dev) 2581 { 2582 /* unfortunately we can't return errors to the stack */ 2583 set_rxmode(dev, -1, false); 2584 } 2585 2586 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2587 { 2588 int ret; 2589 struct port_info *pi = netdev_priv(dev); 2590 2591 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2592 -1, -1, -1, true); 2593 if (!ret) 2594 dev->mtu = new_mtu; 2595 return ret; 2596 } 2597 2598 #ifdef CONFIG_PCI_IOV 2599 static int dummy_open(struct net_device *dev) 2600 { 2601 /* Turn carrier off since we don't have to transmit anything on this 2602 * interface. 2603 */ 2604 netif_carrier_off(dev); 2605 return 0; 2606 } 2607 2608 /* Fill MAC address that will be assigned by the FW */ 2609 static void fill_vf_station_mac_addr(struct adapter *adap) 2610 { 2611 unsigned int i; 2612 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 2613 int err; 2614 u8 *na; 2615 u16 a, b; 2616 2617 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 2618 if (!err) { 2619 na = adap->params.vpd.na; 2620 for (i = 0; i < ETH_ALEN; i++) 2621 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 2622 hex2val(na[2 * i + 1])); 2623 a = (hw_addr[0] << 8) | hw_addr[1]; 2624 b = (hw_addr[1] << 8) | hw_addr[2]; 2625 a ^= b; 2626 a |= 0x0200; /* locally assigned Ethernet MAC address */ 2627 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 2628 macaddr[0] = a >> 8; 2629 macaddr[1] = a & 0xff; 2630 2631 for (i = 2; i < 5; i++) 2632 macaddr[i] = hw_addr[i + 1]; 2633 2634 for (i = 0; i < adap->num_vfs; i++) { 2635 macaddr[5] = adap->pf * 16 + i; 2636 ether_addr_copy(adap->vfinfo[i].vf_mac_addr, macaddr); 2637 } 2638 } 2639 } 2640 2641 static int cxgb_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 2642 { 2643 struct port_info *pi = netdev_priv(dev); 2644 struct adapter *adap = pi->adapter; 2645 int ret; 2646 2647 /* verify MAC addr is valid */ 2648 if (!is_valid_ether_addr(mac)) { 2649 dev_err(pi->adapter->pdev_dev, 2650 "Invalid Ethernet address %pM for VF %d\n", 2651 mac, vf); 2652 return -EINVAL; 2653 } 2654 2655 dev_info(pi->adapter->pdev_dev, 2656 "Setting MAC %pM on VF %d\n", mac, vf); 2657 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 2658 if (!ret) 2659 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 2660 return ret; 2661 } 2662 2663 static int cxgb_get_vf_config(struct net_device *dev, 2664 int vf, struct ifla_vf_info *ivi) 2665 { 2666 struct port_info *pi = netdev_priv(dev); 2667 struct adapter *adap = pi->adapter; 2668 2669 if (vf >= adap->num_vfs) 2670 return -EINVAL; 2671 ivi->vf = vf; 2672 ivi->max_tx_rate = adap->vfinfo[vf].tx_rate; 2673 ivi->min_tx_rate = 0; 2674 ether_addr_copy(ivi->mac, adap->vfinfo[vf].vf_mac_addr); 2675 return 0; 2676 } 2677 2678 static int cxgb_get_phys_port_id(struct net_device *dev, 2679 struct netdev_phys_item_id *ppid) 2680 { 2681 struct port_info *pi = netdev_priv(dev); 2682 unsigned int phy_port_id; 2683 2684 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 2685 ppid->id_len = sizeof(phy_port_id); 2686 memcpy(ppid->id, &phy_port_id, ppid->id_len); 2687 return 0; 2688 } 2689 2690 static int cxgb_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate, 2691 int max_tx_rate) 2692 { 2693 struct port_info *pi = netdev_priv(dev); 2694 struct adapter *adap = pi->adapter; 2695 unsigned int link_ok, speed, mtu; 2696 u32 fw_pfvf, fw_class; 2697 int class_id = vf; 2698 int ret; 2699 u16 pktsize; 2700 2701 if (vf >= adap->num_vfs) 2702 return -EINVAL; 2703 2704 if (min_tx_rate) { 2705 dev_err(adap->pdev_dev, 2706 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 2707 min_tx_rate, vf); 2708 return -EINVAL; 2709 } 2710 2711 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 2712 if (ret != FW_SUCCESS) { 2713 dev_err(adap->pdev_dev, 2714 "Failed to get link information for VF %d\n", vf); 2715 return -EINVAL; 2716 } 2717 2718 if (!link_ok) { 2719 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 2720 return -EINVAL; 2721 } 2722 2723 if (max_tx_rate > speed) { 2724 dev_err(adap->pdev_dev, 2725 "Max tx rate %d for VF %d can't be > link-speed %u", 2726 max_tx_rate, vf, speed); 2727 return -EINVAL; 2728 } 2729 2730 pktsize = mtu; 2731 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 2732 pktsize = pktsize - sizeof(struct ethhdr) - 4; 2733 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 2734 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 2735 /* configure Traffic Class for rate-limiting */ 2736 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 2737 SCHED_CLASS_LEVEL_CL_RL, 2738 SCHED_CLASS_MODE_CLASS, 2739 SCHED_CLASS_RATEUNIT_BITS, 2740 SCHED_CLASS_RATEMODE_ABS, 2741 pi->tx_chan, class_id, 0, 2742 max_tx_rate * 1000, 0, pktsize); 2743 if (ret) { 2744 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 2745 ret); 2746 return -EINVAL; 2747 } 2748 dev_info(adap->pdev_dev, 2749 "Class %d with MSS %u configured with rate %u\n", 2750 class_id, pktsize, max_tx_rate); 2751 2752 /* bind VF to configured Traffic Class */ 2753 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2754 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2755 fw_class = class_id; 2756 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 2757 &fw_class); 2758 if (ret) { 2759 dev_err(adap->pdev_dev, 2760 "Err %d in binding VF %d to Traffic Class %d\n", 2761 ret, vf, class_id); 2762 return -EINVAL; 2763 } 2764 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 2765 adap->pf, vf, class_id); 2766 adap->vfinfo[vf].tx_rate = max_tx_rate; 2767 return 0; 2768 } 2769 2770 #endif 2771 2772 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 2773 { 2774 int ret; 2775 struct sockaddr *addr = p; 2776 struct port_info *pi = netdev_priv(dev); 2777 2778 if (!is_valid_ether_addr(addr->sa_data)) 2779 return -EADDRNOTAVAIL; 2780 2781 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid, 2782 pi->xact_addr_filt, addr->sa_data, true, true); 2783 if (ret < 0) 2784 return ret; 2785 2786 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 2787 pi->xact_addr_filt = ret; 2788 return 0; 2789 } 2790 2791 #ifdef CONFIG_NET_POLL_CONTROLLER 2792 static void cxgb_netpoll(struct net_device *dev) 2793 { 2794 struct port_info *pi = netdev_priv(dev); 2795 struct adapter *adap = pi->adapter; 2796 2797 if (adap->flags & USING_MSIX) { 2798 int i; 2799 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 2800 2801 for (i = pi->nqsets; i; i--, rx++) 2802 t4_sge_intr_msix(0, &rx->rspq); 2803 } else 2804 t4_intr_handler(adap)(0, adap); 2805 } 2806 #endif 2807 2808 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 2809 { 2810 struct port_info *pi = netdev_priv(dev); 2811 struct adapter *adap = pi->adapter; 2812 struct sched_class *e; 2813 struct ch_sched_params p; 2814 struct ch_sched_queue qe; 2815 u32 req_rate; 2816 int err = 0; 2817 2818 if (!can_sched(dev)) 2819 return -ENOTSUPP; 2820 2821 if (index < 0 || index > pi->nqsets - 1) 2822 return -EINVAL; 2823 2824 if (!(adap->flags & FULL_INIT_DONE)) { 2825 dev_err(adap->pdev_dev, 2826 "Failed to rate limit on queue %d. Link Down?\n", 2827 index); 2828 return -EINVAL; 2829 } 2830 2831 /* Convert from Mbps to Kbps */ 2832 req_rate = rate << 10; 2833 2834 /* Max rate is 10 Gbps */ 2835 if (req_rate >= SCHED_MAX_RATE_KBPS) { 2836 dev_err(adap->pdev_dev, 2837 "Invalid rate %u Mbps, Max rate is %u Gbps\n", 2838 rate, SCHED_MAX_RATE_KBPS); 2839 return -ERANGE; 2840 } 2841 2842 /* First unbind the queue from any existing class */ 2843 memset(&qe, 0, sizeof(qe)); 2844 qe.queue = index; 2845 qe.class = SCHED_CLS_NONE; 2846 2847 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 2848 if (err) { 2849 dev_err(adap->pdev_dev, 2850 "Unbinding Queue %d on port %d fail. Err: %d\n", 2851 index, pi->port_id, err); 2852 return err; 2853 } 2854 2855 /* Queue already unbound */ 2856 if (!req_rate) 2857 return 0; 2858 2859 /* Fetch any available unused or matching scheduling class */ 2860 memset(&p, 0, sizeof(p)); 2861 p.type = SCHED_CLASS_TYPE_PACKET; 2862 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 2863 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 2864 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 2865 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 2866 p.u.params.channel = pi->tx_chan; 2867 p.u.params.class = SCHED_CLS_NONE; 2868 p.u.params.minrate = 0; 2869 p.u.params.maxrate = req_rate; 2870 p.u.params.weight = 0; 2871 p.u.params.pktsize = dev->mtu; 2872 2873 e = cxgb4_sched_class_alloc(dev, &p); 2874 if (!e) 2875 return -ENOMEM; 2876 2877 /* Bind the queue to a scheduling class */ 2878 memset(&qe, 0, sizeof(qe)); 2879 qe.queue = index; 2880 qe.class = e->idx; 2881 2882 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 2883 if (err) 2884 dev_err(adap->pdev_dev, 2885 "Queue rate limiting failed. Err: %d\n", err); 2886 return err; 2887 } 2888 2889 static int cxgb_setup_tc_flower(struct net_device *dev, 2890 struct tc_cls_flower_offload *cls_flower) 2891 { 2892 if (cls_flower->common.chain_index) 2893 return -EOPNOTSUPP; 2894 2895 switch (cls_flower->command) { 2896 case TC_CLSFLOWER_REPLACE: 2897 return cxgb4_tc_flower_replace(dev, cls_flower); 2898 case TC_CLSFLOWER_DESTROY: 2899 return cxgb4_tc_flower_destroy(dev, cls_flower); 2900 case TC_CLSFLOWER_STATS: 2901 return cxgb4_tc_flower_stats(dev, cls_flower); 2902 default: 2903 return -EOPNOTSUPP; 2904 } 2905 } 2906 2907 static int cxgb_setup_tc_cls_u32(struct net_device *dev, 2908 struct tc_cls_u32_offload *cls_u32) 2909 { 2910 if (cls_u32->common.chain_index) 2911 return -EOPNOTSUPP; 2912 2913 switch (cls_u32->command) { 2914 case TC_CLSU32_NEW_KNODE: 2915 case TC_CLSU32_REPLACE_KNODE: 2916 return cxgb4_config_knode(dev, cls_u32); 2917 case TC_CLSU32_DELETE_KNODE: 2918 return cxgb4_delete_knode(dev, cls_u32); 2919 default: 2920 return -EOPNOTSUPP; 2921 } 2922 } 2923 2924 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 2925 void *cb_priv) 2926 { 2927 struct net_device *dev = cb_priv; 2928 struct port_info *pi = netdev2pinfo(dev); 2929 struct adapter *adap = netdev2adap(dev); 2930 2931 if (!(adap->flags & FULL_INIT_DONE)) { 2932 dev_err(adap->pdev_dev, 2933 "Failed to setup tc on port %d. Link Down?\n", 2934 pi->port_id); 2935 return -EINVAL; 2936 } 2937 2938 switch (type) { 2939 case TC_SETUP_CLSU32: 2940 return cxgb_setup_tc_cls_u32(dev, type_data); 2941 case TC_SETUP_CLSFLOWER: 2942 return cxgb_setup_tc_flower(dev, type_data); 2943 default: 2944 return -EOPNOTSUPP; 2945 } 2946 } 2947 2948 static int cxgb_setup_tc_block(struct net_device *dev, 2949 struct tc_block_offload *f) 2950 { 2951 struct port_info *pi = netdev2pinfo(dev); 2952 2953 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 2954 return -EOPNOTSUPP; 2955 2956 switch (f->command) { 2957 case TC_BLOCK_BIND: 2958 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb, 2959 pi, dev); 2960 case TC_BLOCK_UNBIND: 2961 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi); 2962 return 0; 2963 default: 2964 return -EOPNOTSUPP; 2965 } 2966 } 2967 2968 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 2969 void *type_data) 2970 { 2971 switch (type) { 2972 case TC_SETUP_BLOCK: 2973 return cxgb_setup_tc_block(dev, type_data); 2974 default: 2975 return -EOPNOTSUPP; 2976 } 2977 } 2978 2979 static netdev_features_t cxgb_fix_features(struct net_device *dev, 2980 netdev_features_t features) 2981 { 2982 /* Disable GRO, if RX_CSUM is disabled */ 2983 if (!(features & NETIF_F_RXCSUM)) 2984 features &= ~NETIF_F_GRO; 2985 2986 return features; 2987 } 2988 2989 static const struct net_device_ops cxgb4_netdev_ops = { 2990 .ndo_open = cxgb_open, 2991 .ndo_stop = cxgb_close, 2992 .ndo_start_xmit = t4_eth_xmit, 2993 .ndo_select_queue = cxgb_select_queue, 2994 .ndo_get_stats64 = cxgb_get_stats, 2995 .ndo_set_rx_mode = cxgb_set_rxmode, 2996 .ndo_set_mac_address = cxgb_set_mac_addr, 2997 .ndo_set_features = cxgb_set_features, 2998 .ndo_validate_addr = eth_validate_addr, 2999 .ndo_do_ioctl = cxgb_ioctl, 3000 .ndo_change_mtu = cxgb_change_mtu, 3001 #ifdef CONFIG_NET_POLL_CONTROLLER 3002 .ndo_poll_controller = cxgb_netpoll, 3003 #endif 3004 #ifdef CONFIG_CHELSIO_T4_FCOE 3005 .ndo_fcoe_enable = cxgb_fcoe_enable, 3006 .ndo_fcoe_disable = cxgb_fcoe_disable, 3007 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3008 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 3009 .ndo_setup_tc = cxgb_setup_tc, 3010 .ndo_fix_features = cxgb_fix_features, 3011 }; 3012 3013 #ifdef CONFIG_PCI_IOV 3014 static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 3015 .ndo_open = dummy_open, 3016 .ndo_set_vf_mac = cxgb_set_vf_mac, 3017 .ndo_get_vf_config = cxgb_get_vf_config, 3018 .ndo_set_vf_rate = cxgb_set_vf_rate, 3019 .ndo_get_phys_port_id = cxgb_get_phys_port_id, 3020 }; 3021 #endif 3022 3023 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 3024 { 3025 struct adapter *adapter = netdev2adap(dev); 3026 3027 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 3028 strlcpy(info->version, cxgb4_driver_version, 3029 sizeof(info->version)); 3030 strlcpy(info->bus_info, pci_name(adapter->pdev), 3031 sizeof(info->bus_info)); 3032 } 3033 3034 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 3035 .get_drvinfo = get_drvinfo, 3036 }; 3037 3038 void t4_fatal_err(struct adapter *adap) 3039 { 3040 int port; 3041 3042 if (pci_channel_offline(adap->pdev)) 3043 return; 3044 3045 /* Disable the SGE since ULDs are going to free resources that 3046 * could be exposed to the adapter. RDMA MWs for example... 3047 */ 3048 t4_shutdown_adapter(adap); 3049 for_each_port(adap, port) { 3050 struct net_device *dev = adap->port[port]; 3051 3052 /* If we get here in very early initialization the network 3053 * devices may not have been set up yet. 3054 */ 3055 if (!dev) 3056 continue; 3057 3058 netif_tx_stop_all_queues(dev); 3059 netif_carrier_off(dev); 3060 } 3061 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3062 } 3063 3064 static void setup_memwin(struct adapter *adap) 3065 { 3066 u32 nic_win_base = t4_get_util_window(adap); 3067 3068 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3069 } 3070 3071 static void setup_memwin_rdma(struct adapter *adap) 3072 { 3073 if (adap->vres.ocq.size) { 3074 u32 start; 3075 unsigned int sz_kb; 3076 3077 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3078 start &= PCI_BASE_ADDRESS_MEM_MASK; 3079 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3080 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3081 t4_write_reg(adap, 3082 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3083 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3084 t4_write_reg(adap, 3085 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3086 adap->vres.ocq.start); 3087 t4_read_reg(adap, 3088 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3089 } 3090 } 3091 3092 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3093 { 3094 u32 v; 3095 int ret; 3096 3097 /* get device capabilities */ 3098 memset(c, 0, sizeof(*c)); 3099 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3100 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3101 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3102 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3103 if (ret < 0) 3104 return ret; 3105 3106 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3107 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3108 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3109 if (ret < 0) 3110 return ret; 3111 3112 ret = t4_config_glbl_rss(adap, adap->pf, 3113 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3114 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3115 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3116 if (ret < 0) 3117 return ret; 3118 3119 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3120 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3121 FW_CMD_CAP_PF); 3122 if (ret < 0) 3123 return ret; 3124 3125 t4_sge_init(adap); 3126 3127 /* tweak some settings */ 3128 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3129 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3130 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3131 v = t4_read_reg(adap, TP_PIO_DATA_A); 3132 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3133 3134 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3135 adap->params.tp.tx_modq_map = 0xE4; 3136 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3137 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3138 3139 /* associate each Tx modulation queue with consecutive Tx channels */ 3140 v = 0x84218421; 3141 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3142 &v, 1, TP_TX_SCHED_HDR_A); 3143 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3144 &v, 1, TP_TX_SCHED_FIFO_A); 3145 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3146 &v, 1, TP_TX_SCHED_PCMD_A); 3147 3148 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3149 if (is_offload(adap)) { 3150 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3151 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3152 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3153 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3154 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3155 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3156 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3157 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3158 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3159 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3160 } 3161 3162 /* get basic stuff going */ 3163 return t4_early_init(adap, adap->pf); 3164 } 3165 3166 /* 3167 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3168 */ 3169 #define MAX_ATIDS 8192U 3170 3171 /* 3172 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3173 * 3174 * If the firmware we're dealing with has Configuration File support, then 3175 * we use that to perform all configuration 3176 */ 3177 3178 /* 3179 * Tweak configuration based on module parameters, etc. Most of these have 3180 * defaults assigned to them by Firmware Configuration Files (if we're using 3181 * them) but need to be explicitly set if we're using hard-coded 3182 * initialization. But even in the case of using Firmware Configuration 3183 * Files, we'd like to expose the ability to change these via module 3184 * parameters so these are essentially common tweaks/settings for 3185 * Configuration Files and hard-coded initialization ... 3186 */ 3187 static int adap_init0_tweaks(struct adapter *adapter) 3188 { 3189 /* 3190 * Fix up various Host-Dependent Parameters like Page Size, Cache 3191 * Line Size, etc. The firmware default is for a 4KB Page Size and 3192 * 64B Cache Line Size ... 3193 */ 3194 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3195 3196 /* 3197 * Process module parameters which affect early initialization. 3198 */ 3199 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3200 dev_err(&adapter->pdev->dev, 3201 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3202 rx_dma_offset); 3203 rx_dma_offset = 2; 3204 } 3205 t4_set_reg_field(adapter, SGE_CONTROL_A, 3206 PKTSHIFT_V(PKTSHIFT_M), 3207 PKTSHIFT_V(rx_dma_offset)); 3208 3209 /* 3210 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3211 * adds the pseudo header itself. 3212 */ 3213 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3214 CSUM_HAS_PSEUDO_HDR_F, 0); 3215 3216 return 0; 3217 } 3218 3219 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3220 * unto themselves and they contain their own firmware to perform their 3221 * tasks ... 3222 */ 3223 static int phy_aq1202_version(const u8 *phy_fw_data, 3224 size_t phy_fw_size) 3225 { 3226 int offset; 3227 3228 /* At offset 0x8 you're looking for the primary image's 3229 * starting offset which is 3 Bytes wide 3230 * 3231 * At offset 0xa of the primary image, you look for the offset 3232 * of the DRAM segment which is 3 Bytes wide. 3233 * 3234 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3235 * wide 3236 */ 3237 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3238 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3239 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3240 3241 offset = le24(phy_fw_data + 0x8) << 12; 3242 offset = le24(phy_fw_data + offset + 0xa); 3243 return be16(phy_fw_data + offset + 0x27e); 3244 3245 #undef be16 3246 #undef le16 3247 #undef le24 3248 } 3249 3250 static struct info_10gbt_phy_fw { 3251 unsigned int phy_fw_id; /* PCI Device ID */ 3252 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3253 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3254 int phy_flash; /* Has FLASH for PHY Firmware */ 3255 } phy_info_array[] = { 3256 { 3257 PHY_AQ1202_DEVICEID, 3258 PHY_AQ1202_FIRMWARE, 3259 phy_aq1202_version, 3260 1, 3261 }, 3262 { 3263 PHY_BCM84834_DEVICEID, 3264 PHY_BCM84834_FIRMWARE, 3265 NULL, 3266 0, 3267 }, 3268 { 0, NULL, NULL }, 3269 }; 3270 3271 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3272 { 3273 int i; 3274 3275 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3276 if (phy_info_array[i].phy_fw_id == devid) 3277 return &phy_info_array[i]; 3278 } 3279 return NULL; 3280 } 3281 3282 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3283 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3284 * we return a negative error number. If we transfer new firmware we return 1 3285 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3286 */ 3287 static int adap_init0_phy(struct adapter *adap) 3288 { 3289 const struct firmware *phyf; 3290 int ret; 3291 struct info_10gbt_phy_fw *phy_info; 3292 3293 /* Use the device ID to determine which PHY file to flash. 3294 */ 3295 phy_info = find_phy_info(adap->pdev->device); 3296 if (!phy_info) { 3297 dev_warn(adap->pdev_dev, 3298 "No PHY Firmware file found for this PHY\n"); 3299 return -EOPNOTSUPP; 3300 } 3301 3302 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3303 * use that. The adapter firmware provides us with a memory buffer 3304 * where we can load a PHY firmware file from the host if we want to 3305 * override the PHY firmware File in flash. 3306 */ 3307 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3308 adap->pdev_dev); 3309 if (ret < 0) { 3310 /* For adapters without FLASH attached to PHY for their 3311 * firmware, it's obviously a fatal error if we can't get the 3312 * firmware to the adapter. For adapters with PHY firmware 3313 * FLASH storage, it's worth a warning if we can't find the 3314 * PHY Firmware but we'll neuter the error ... 3315 */ 3316 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3317 "/lib/firmware/%s, error %d\n", 3318 phy_info->phy_fw_file, -ret); 3319 if (phy_info->phy_flash) { 3320 int cur_phy_fw_ver = 0; 3321 3322 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3323 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3324 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3325 ret = 0; 3326 } 3327 3328 return ret; 3329 } 3330 3331 /* Load PHY Firmware onto adapter. 3332 */ 3333 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3334 phy_info->phy_fw_version, 3335 (u8 *)phyf->data, phyf->size); 3336 if (ret < 0) 3337 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3338 -ret); 3339 else if (ret > 0) { 3340 int new_phy_fw_ver = 0; 3341 3342 if (phy_info->phy_fw_version) 3343 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3344 phyf->size); 3345 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3346 "Firmware /lib/firmware/%s, version %#x\n", 3347 phy_info->phy_fw_file, new_phy_fw_ver); 3348 } 3349 3350 release_firmware(phyf); 3351 3352 return ret; 3353 } 3354 3355 /* 3356 * Attempt to initialize the adapter via a Firmware Configuration File. 3357 */ 3358 static int adap_init0_config(struct adapter *adapter, int reset) 3359 { 3360 struct fw_caps_config_cmd caps_cmd; 3361 const struct firmware *cf; 3362 unsigned long mtype = 0, maddr = 0; 3363 u32 finiver, finicsum, cfcsum; 3364 int ret; 3365 int config_issued = 0; 3366 char *fw_config_file, fw_config_file_path[256]; 3367 char *config_name = NULL; 3368 3369 /* 3370 * Reset device if necessary. 3371 */ 3372 if (reset) { 3373 ret = t4_fw_reset(adapter, adapter->mbox, 3374 PIORSTMODE_F | PIORST_F); 3375 if (ret < 0) 3376 goto bye; 3377 } 3378 3379 /* If this is a 10Gb/s-BT adapter make sure the chip-external 3380 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 3381 * to be performed after any global adapter RESET above since some 3382 * PHYs only have local RAM copies of the PHY firmware. 3383 */ 3384 if (is_10gbt_device(adapter->pdev->device)) { 3385 ret = adap_init0_phy(adapter); 3386 if (ret < 0) 3387 goto bye; 3388 } 3389 /* 3390 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 3391 * then use that. Otherwise, use the configuration file stored 3392 * in the adapter flash ... 3393 */ 3394 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 3395 case CHELSIO_T4: 3396 fw_config_file = FW4_CFNAME; 3397 break; 3398 case CHELSIO_T5: 3399 fw_config_file = FW5_CFNAME; 3400 break; 3401 case CHELSIO_T6: 3402 fw_config_file = FW6_CFNAME; 3403 break; 3404 default: 3405 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 3406 adapter->pdev->device); 3407 ret = -EINVAL; 3408 goto bye; 3409 } 3410 3411 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 3412 if (ret < 0) { 3413 config_name = "On FLASH"; 3414 mtype = FW_MEMTYPE_CF_FLASH; 3415 maddr = t4_flash_cfg_addr(adapter); 3416 } else { 3417 u32 params[7], val[7]; 3418 3419 sprintf(fw_config_file_path, 3420 "/lib/firmware/%s", fw_config_file); 3421 config_name = fw_config_file_path; 3422 3423 if (cf->size >= FLASH_CFG_MAX_SIZE) 3424 ret = -ENOMEM; 3425 else { 3426 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3427 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3428 ret = t4_query_params(adapter, adapter->mbox, 3429 adapter->pf, 0, 1, params, val); 3430 if (ret == 0) { 3431 /* 3432 * For t4_memory_rw() below addresses and 3433 * sizes have to be in terms of multiples of 4 3434 * bytes. So, if the Configuration File isn't 3435 * a multiple of 4 bytes in length we'll have 3436 * to write that out separately since we can't 3437 * guarantee that the bytes following the 3438 * residual byte in the buffer returned by 3439 * request_firmware() are zeroed out ... 3440 */ 3441 size_t resid = cf->size & 0x3; 3442 size_t size = cf->size & ~0x3; 3443 __be32 *data = (__be32 *)cf->data; 3444 3445 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 3446 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 3447 3448 spin_lock(&adapter->win0_lock); 3449 ret = t4_memory_rw(adapter, 0, mtype, maddr, 3450 size, data, T4_MEMORY_WRITE); 3451 if (ret == 0 && resid != 0) { 3452 union { 3453 __be32 word; 3454 char buf[4]; 3455 } last; 3456 int i; 3457 3458 last.word = data[size >> 2]; 3459 for (i = resid; i < 4; i++) 3460 last.buf[i] = 0; 3461 ret = t4_memory_rw(adapter, 0, mtype, 3462 maddr + size, 3463 4, &last.word, 3464 T4_MEMORY_WRITE); 3465 } 3466 spin_unlock(&adapter->win0_lock); 3467 } 3468 } 3469 3470 release_firmware(cf); 3471 if (ret) 3472 goto bye; 3473 } 3474 3475 /* 3476 * Issue a Capability Configuration command to the firmware to get it 3477 * to parse the Configuration File. We don't use t4_fw_config_file() 3478 * because we want the ability to modify various features after we've 3479 * processed the configuration file ... 3480 */ 3481 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3482 caps_cmd.op_to_write = 3483 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3484 FW_CMD_REQUEST_F | 3485 FW_CMD_READ_F); 3486 caps_cmd.cfvalid_to_len16 = 3487 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 3488 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 3489 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 3490 FW_LEN16(caps_cmd)); 3491 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3492 &caps_cmd); 3493 3494 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 3495 * Configuration File in FLASH), our last gasp effort is to use the 3496 * Firmware Configuration File which is embedded in the firmware. A 3497 * very few early versions of the firmware didn't have one embedded 3498 * but we can ignore those. 3499 */ 3500 if (ret == -ENOENT) { 3501 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3502 caps_cmd.op_to_write = 3503 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3504 FW_CMD_REQUEST_F | 3505 FW_CMD_READ_F); 3506 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3507 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 3508 sizeof(caps_cmd), &caps_cmd); 3509 config_name = "Firmware Default"; 3510 } 3511 3512 config_issued = 1; 3513 if (ret < 0) 3514 goto bye; 3515 3516 finiver = ntohl(caps_cmd.finiver); 3517 finicsum = ntohl(caps_cmd.finicsum); 3518 cfcsum = ntohl(caps_cmd.cfcsum); 3519 if (finicsum != cfcsum) 3520 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 3521 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 3522 finicsum, cfcsum); 3523 3524 /* 3525 * And now tell the firmware to use the configuration we just loaded. 3526 */ 3527 caps_cmd.op_to_write = 3528 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3529 FW_CMD_REQUEST_F | 3530 FW_CMD_WRITE_F); 3531 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3532 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 3533 NULL); 3534 if (ret < 0) 3535 goto bye; 3536 3537 /* 3538 * Tweak configuration based on system architecture, module 3539 * parameters, etc. 3540 */ 3541 ret = adap_init0_tweaks(adapter); 3542 if (ret < 0) 3543 goto bye; 3544 3545 /* 3546 * And finally tell the firmware to initialize itself using the 3547 * parameters from the Configuration File. 3548 */ 3549 ret = t4_fw_initialize(adapter, adapter->mbox); 3550 if (ret < 0) 3551 goto bye; 3552 3553 /* Emit Firmware Configuration File information and return 3554 * successfully. 3555 */ 3556 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 3557 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 3558 config_name, finiver, cfcsum); 3559 return 0; 3560 3561 /* 3562 * Something bad happened. Return the error ... (If the "error" 3563 * is that there's no Configuration File on the adapter we don't 3564 * want to issue a warning since this is fairly common.) 3565 */ 3566 bye: 3567 if (config_issued && ret != -ENOENT) 3568 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 3569 config_name, -ret); 3570 return ret; 3571 } 3572 3573 static struct fw_info fw_info_array[] = { 3574 { 3575 .chip = CHELSIO_T4, 3576 .fs_name = FW4_CFNAME, 3577 .fw_mod_name = FW4_FNAME, 3578 .fw_hdr = { 3579 .chip = FW_HDR_CHIP_T4, 3580 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 3581 .intfver_nic = FW_INTFVER(T4, NIC), 3582 .intfver_vnic = FW_INTFVER(T4, VNIC), 3583 .intfver_ri = FW_INTFVER(T4, RI), 3584 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 3585 .intfver_fcoe = FW_INTFVER(T4, FCOE), 3586 }, 3587 }, { 3588 .chip = CHELSIO_T5, 3589 .fs_name = FW5_CFNAME, 3590 .fw_mod_name = FW5_FNAME, 3591 .fw_hdr = { 3592 .chip = FW_HDR_CHIP_T5, 3593 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 3594 .intfver_nic = FW_INTFVER(T5, NIC), 3595 .intfver_vnic = FW_INTFVER(T5, VNIC), 3596 .intfver_ri = FW_INTFVER(T5, RI), 3597 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 3598 .intfver_fcoe = FW_INTFVER(T5, FCOE), 3599 }, 3600 }, { 3601 .chip = CHELSIO_T6, 3602 .fs_name = FW6_CFNAME, 3603 .fw_mod_name = FW6_FNAME, 3604 .fw_hdr = { 3605 .chip = FW_HDR_CHIP_T6, 3606 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 3607 .intfver_nic = FW_INTFVER(T6, NIC), 3608 .intfver_vnic = FW_INTFVER(T6, VNIC), 3609 .intfver_ofld = FW_INTFVER(T6, OFLD), 3610 .intfver_ri = FW_INTFVER(T6, RI), 3611 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 3612 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 3613 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 3614 .intfver_fcoe = FW_INTFVER(T6, FCOE), 3615 }, 3616 } 3617 3618 }; 3619 3620 static struct fw_info *find_fw_info(int chip) 3621 { 3622 int i; 3623 3624 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 3625 if (fw_info_array[i].chip == chip) 3626 return &fw_info_array[i]; 3627 } 3628 return NULL; 3629 } 3630 3631 /* 3632 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3633 */ 3634 static int adap_init0(struct adapter *adap) 3635 { 3636 int ret; 3637 u32 v, port_vec; 3638 enum dev_state state; 3639 u32 params[7], val[7]; 3640 struct fw_caps_config_cmd caps_cmd; 3641 int reset = 1; 3642 3643 /* Grab Firmware Device Log parameters as early as possible so we have 3644 * access to it for debugging, etc. 3645 */ 3646 ret = t4_init_devlog_params(adap); 3647 if (ret < 0) 3648 return ret; 3649 3650 /* Contact FW, advertising Master capability */ 3651 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 3652 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 3653 if (ret < 0) { 3654 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 3655 ret); 3656 return ret; 3657 } 3658 if (ret == adap->mbox) 3659 adap->flags |= MASTER_PF; 3660 3661 /* 3662 * If we're the Master PF Driver and the device is uninitialized, 3663 * then let's consider upgrading the firmware ... (We always want 3664 * to check the firmware version number in order to A. get it for 3665 * later reporting and B. to warn if the currently loaded firmware 3666 * is excessively mismatched relative to the driver.) 3667 */ 3668 3669 t4_get_version_info(adap); 3670 ret = t4_check_fw_version(adap); 3671 /* If firmware is too old (not supported by driver) force an update. */ 3672 if (ret) 3673 state = DEV_STATE_UNINIT; 3674 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) { 3675 struct fw_info *fw_info; 3676 struct fw_hdr *card_fw; 3677 const struct firmware *fw; 3678 const u8 *fw_data = NULL; 3679 unsigned int fw_size = 0; 3680 3681 /* This is the firmware whose headers the driver was compiled 3682 * against 3683 */ 3684 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 3685 if (fw_info == NULL) { 3686 dev_err(adap->pdev_dev, 3687 "unable to get firmware info for chip %d.\n", 3688 CHELSIO_CHIP_VERSION(adap->params.chip)); 3689 return -EINVAL; 3690 } 3691 3692 /* allocate memory to read the header of the firmware on the 3693 * card 3694 */ 3695 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 3696 3697 /* Get FW from from /lib/firmware/ */ 3698 ret = request_firmware(&fw, fw_info->fw_mod_name, 3699 adap->pdev_dev); 3700 if (ret < 0) { 3701 dev_err(adap->pdev_dev, 3702 "unable to load firmware image %s, error %d\n", 3703 fw_info->fw_mod_name, ret); 3704 } else { 3705 fw_data = fw->data; 3706 fw_size = fw->size; 3707 } 3708 3709 /* upgrade FW logic */ 3710 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 3711 state, &reset); 3712 3713 /* Cleaning up */ 3714 release_firmware(fw); 3715 kvfree(card_fw); 3716 3717 if (ret < 0) 3718 goto bye; 3719 } 3720 3721 /* 3722 * Grab VPD parameters. This should be done after we establish a 3723 * connection to the firmware since some of the VPD parameters 3724 * (notably the Core Clock frequency) are retrieved via requests to 3725 * the firmware. On the other hand, we need these fairly early on 3726 * so we do this right after getting ahold of the firmware. 3727 */ 3728 ret = t4_get_vpd_params(adap, &adap->params.vpd); 3729 if (ret < 0) 3730 goto bye; 3731 3732 /* 3733 * Find out what ports are available to us. Note that we need to do 3734 * this before calling adap_init0_no_config() since it needs nports 3735 * and portvec ... 3736 */ 3737 v = 3738 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3739 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 3740 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 3741 if (ret < 0) 3742 goto bye; 3743 3744 adap->params.nports = hweight32(port_vec); 3745 adap->params.portvec = port_vec; 3746 3747 /* If the firmware is initialized already, emit a simply note to that 3748 * effect. Otherwise, it's time to try initializing the adapter. 3749 */ 3750 if (state == DEV_STATE_INIT) { 3751 dev_info(adap->pdev_dev, "Coming up as %s: "\ 3752 "Adapter already initialized\n", 3753 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 3754 } else { 3755 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 3756 "Initializing adapter\n"); 3757 3758 /* Find out whether we're dealing with a version of the 3759 * firmware which has configuration file support. 3760 */ 3761 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3762 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 3763 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 3764 params, val); 3765 3766 /* If the firmware doesn't support Configuration Files, 3767 * return an error. 3768 */ 3769 if (ret < 0) { 3770 dev_err(adap->pdev_dev, "firmware doesn't support " 3771 "Firmware Configuration Files\n"); 3772 goto bye; 3773 } 3774 3775 /* The firmware provides us with a memory buffer where we can 3776 * load a Configuration File from the host if we want to 3777 * override the Configuration File in flash. 3778 */ 3779 ret = adap_init0_config(adap, reset); 3780 if (ret == -ENOENT) { 3781 dev_err(adap->pdev_dev, "no Configuration File " 3782 "present on adapter.\n"); 3783 goto bye; 3784 } 3785 if (ret < 0) { 3786 dev_err(adap->pdev_dev, "could not initialize " 3787 "adapter, error %d\n", -ret); 3788 goto bye; 3789 } 3790 } 3791 3792 /* Give the SGE code a chance to pull in anything that it needs ... 3793 * Note that this must be called after we retrieve our VPD parameters 3794 * in order to know how to convert core ticks to seconds, etc. 3795 */ 3796 ret = t4_sge_init(adap); 3797 if (ret < 0) 3798 goto bye; 3799 3800 if (is_bypass_device(adap->pdev->device)) 3801 adap->params.bypass = 1; 3802 3803 /* 3804 * Grab some of our basic fundamental operating parameters. 3805 */ 3806 #define FW_PARAM_DEV(param) \ 3807 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 3808 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 3809 3810 #define FW_PARAM_PFVF(param) \ 3811 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 3812 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 3813 FW_PARAMS_PARAM_Y_V(0) | \ 3814 FW_PARAMS_PARAM_Z_V(0) 3815 3816 params[0] = FW_PARAM_PFVF(EQ_START); 3817 params[1] = FW_PARAM_PFVF(L2T_START); 3818 params[2] = FW_PARAM_PFVF(L2T_END); 3819 params[3] = FW_PARAM_PFVF(FILTER_START); 3820 params[4] = FW_PARAM_PFVF(FILTER_END); 3821 params[5] = FW_PARAM_PFVF(IQFLINT_START); 3822 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 3823 if (ret < 0) 3824 goto bye; 3825 adap->sge.egr_start = val[0]; 3826 adap->l2t_start = val[1]; 3827 adap->l2t_end = val[2]; 3828 adap->tids.ftid_base = val[3]; 3829 adap->tids.nftids = val[4] - val[3] + 1; 3830 adap->sge.ingr_start = val[5]; 3831 3832 /* qids (ingress/egress) returned from firmware can be anywhere 3833 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 3834 * Hence driver needs to allocate memory for this range to 3835 * store the queue info. Get the highest IQFLINT/EQ index returned 3836 * in FW_EQ_*_CMD.alloc command. 3837 */ 3838 params[0] = FW_PARAM_PFVF(EQ_END); 3839 params[1] = FW_PARAM_PFVF(IQFLINT_END); 3840 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3841 if (ret < 0) 3842 goto bye; 3843 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 3844 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 3845 3846 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 3847 sizeof(*adap->sge.egr_map), GFP_KERNEL); 3848 if (!adap->sge.egr_map) { 3849 ret = -ENOMEM; 3850 goto bye; 3851 } 3852 3853 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 3854 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 3855 if (!adap->sge.ingr_map) { 3856 ret = -ENOMEM; 3857 goto bye; 3858 } 3859 3860 /* Allocate the memory for the vaious egress queue bitmaps 3861 * ie starving_fl, txq_maperr and blocked_fl. 3862 */ 3863 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3864 sizeof(long), GFP_KERNEL); 3865 if (!adap->sge.starving_fl) { 3866 ret = -ENOMEM; 3867 goto bye; 3868 } 3869 3870 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3871 sizeof(long), GFP_KERNEL); 3872 if (!adap->sge.txq_maperr) { 3873 ret = -ENOMEM; 3874 goto bye; 3875 } 3876 3877 #ifdef CONFIG_DEBUG_FS 3878 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 3879 sizeof(long), GFP_KERNEL); 3880 if (!adap->sge.blocked_fl) { 3881 ret = -ENOMEM; 3882 goto bye; 3883 } 3884 #endif 3885 3886 params[0] = FW_PARAM_PFVF(CLIP_START); 3887 params[1] = FW_PARAM_PFVF(CLIP_END); 3888 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3889 if (ret < 0) 3890 goto bye; 3891 adap->clipt_start = val[0]; 3892 adap->clipt_end = val[1]; 3893 3894 /* We don't yet have a PARAMs calls to retrieve the number of Traffic 3895 * Classes supported by the hardware/firmware so we hard code it here 3896 * for now. 3897 */ 3898 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 3899 3900 /* query params related to active filter region */ 3901 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 3902 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 3903 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 3904 /* If Active filter size is set we enable establishing 3905 * offload connection through firmware work request 3906 */ 3907 if ((val[0] != val[1]) && (ret >= 0)) { 3908 adap->flags |= FW_OFLD_CONN; 3909 adap->tids.aftid_base = val[0]; 3910 adap->tids.aftid_end = val[1]; 3911 } 3912 3913 /* If we're running on newer firmware, let it know that we're 3914 * prepared to deal with encapsulated CPL messages. Older 3915 * firmware won't understand this and we'll just get 3916 * unencapsulated messages ... 3917 */ 3918 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 3919 val[0] = 1; 3920 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 3921 3922 /* 3923 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 3924 * capability. Earlier versions of the firmware didn't have the 3925 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 3926 * permission to use ULPTX MEMWRITE DSGL. 3927 */ 3928 if (is_t4(adap->params.chip)) { 3929 adap->params.ulptx_memwrite_dsgl = false; 3930 } else { 3931 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 3932 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3933 1, params, val); 3934 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 3935 } 3936 3937 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 3938 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 3939 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3940 1, params, val); 3941 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 3942 3943 /* See if FW supports FW_FILTER2 work request */ 3944 if (is_t4(adap->params.chip)) { 3945 adap->params.filter2_wr_support = 0; 3946 } else { 3947 params[0] = FW_PARAM_DEV(FILTER2_WR); 3948 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 3949 1, params, val); 3950 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 3951 } 3952 3953 /* 3954 * Get device capabilities so we can determine what resources we need 3955 * to manage. 3956 */ 3957 memset(&caps_cmd, 0, sizeof(caps_cmd)); 3958 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3959 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3960 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 3961 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 3962 &caps_cmd); 3963 if (ret < 0) 3964 goto bye; 3965 3966 if (caps_cmd.ofldcaps) { 3967 /* query offload-related parameters */ 3968 params[0] = FW_PARAM_DEV(NTID); 3969 params[1] = FW_PARAM_PFVF(SERVER_START); 3970 params[2] = FW_PARAM_PFVF(SERVER_END); 3971 params[3] = FW_PARAM_PFVF(TDDP_START); 3972 params[4] = FW_PARAM_PFVF(TDDP_END); 3973 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 3974 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 3975 params, val); 3976 if (ret < 0) 3977 goto bye; 3978 adap->tids.ntids = val[0]; 3979 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 3980 adap->tids.stid_base = val[1]; 3981 adap->tids.nstids = val[2] - val[1] + 1; 3982 /* 3983 * Setup server filter region. Divide the available filter 3984 * region into two parts. Regular filters get 1/3rd and server 3985 * filters get 2/3rd part. This is only enabled if workarond 3986 * path is enabled. 3987 * 1. For regular filters. 3988 * 2. Server filter: This are special filters which are used 3989 * to redirect SYN packets to offload queue. 3990 */ 3991 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) { 3992 adap->tids.sftid_base = adap->tids.ftid_base + 3993 DIV_ROUND_UP(adap->tids.nftids, 3); 3994 adap->tids.nsftids = adap->tids.nftids - 3995 DIV_ROUND_UP(adap->tids.nftids, 3); 3996 adap->tids.nftids = adap->tids.sftid_base - 3997 adap->tids.ftid_base; 3998 } 3999 adap->vres.ddp.start = val[3]; 4000 adap->vres.ddp.size = val[4] - val[3] + 1; 4001 adap->params.ofldq_wr_cred = val[5]; 4002 4003 adap->params.offload = 1; 4004 adap->num_ofld_uld += 1; 4005 } 4006 if (caps_cmd.rdmacaps) { 4007 params[0] = FW_PARAM_PFVF(STAG_START); 4008 params[1] = FW_PARAM_PFVF(STAG_END); 4009 params[2] = FW_PARAM_PFVF(RQ_START); 4010 params[3] = FW_PARAM_PFVF(RQ_END); 4011 params[4] = FW_PARAM_PFVF(PBL_START); 4012 params[5] = FW_PARAM_PFVF(PBL_END); 4013 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4014 params, val); 4015 if (ret < 0) 4016 goto bye; 4017 adap->vres.stag.start = val[0]; 4018 adap->vres.stag.size = val[1] - val[0] + 1; 4019 adap->vres.rq.start = val[2]; 4020 adap->vres.rq.size = val[3] - val[2] + 1; 4021 adap->vres.pbl.start = val[4]; 4022 adap->vres.pbl.size = val[5] - val[4] + 1; 4023 4024 params[0] = FW_PARAM_PFVF(SQRQ_START); 4025 params[1] = FW_PARAM_PFVF(SQRQ_END); 4026 params[2] = FW_PARAM_PFVF(CQ_START); 4027 params[3] = FW_PARAM_PFVF(CQ_END); 4028 params[4] = FW_PARAM_PFVF(OCQ_START); 4029 params[5] = FW_PARAM_PFVF(OCQ_END); 4030 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 4031 val); 4032 if (ret < 0) 4033 goto bye; 4034 adap->vres.qp.start = val[0]; 4035 adap->vres.qp.size = val[1] - val[0] + 1; 4036 adap->vres.cq.start = val[2]; 4037 adap->vres.cq.size = val[3] - val[2] + 1; 4038 adap->vres.ocq.start = val[4]; 4039 adap->vres.ocq.size = val[5] - val[4] + 1; 4040 4041 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4042 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4043 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4044 val); 4045 if (ret < 0) { 4046 adap->params.max_ordird_qp = 8; 4047 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4048 ret = 0; 4049 } else { 4050 adap->params.max_ordird_qp = val[0]; 4051 adap->params.max_ird_adapter = val[1]; 4052 } 4053 dev_info(adap->pdev_dev, 4054 "max_ordird_qp %d max_ird_adapter %d\n", 4055 adap->params.max_ordird_qp, 4056 adap->params.max_ird_adapter); 4057 adap->num_ofld_uld += 2; 4058 } 4059 if (caps_cmd.iscsicaps) { 4060 params[0] = FW_PARAM_PFVF(ISCSI_START); 4061 params[1] = FW_PARAM_PFVF(ISCSI_END); 4062 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4063 params, val); 4064 if (ret < 0) 4065 goto bye; 4066 adap->vres.iscsi.start = val[0]; 4067 adap->vres.iscsi.size = val[1] - val[0] + 1; 4068 /* LIO target and cxgb4i initiaitor */ 4069 adap->num_ofld_uld += 2; 4070 } 4071 if (caps_cmd.cryptocaps) { 4072 /* Should query params here...TODO */ 4073 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 4074 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4075 params, val); 4076 if (ret < 0) { 4077 if (ret != -EINVAL) 4078 goto bye; 4079 } else { 4080 adap->vres.ncrypto_fc = val[0]; 4081 } 4082 adap->params.crypto |= ULP_CRYPTO_LOOKASIDE; 4083 adap->num_uld += 1; 4084 } 4085 #undef FW_PARAM_PFVF 4086 #undef FW_PARAM_DEV 4087 4088 /* The MTU/MSS Table is initialized by now, so load their values. If 4089 * we're initializing the adapter, then we'll make any modifications 4090 * we want to the MTU/MSS Table and also initialize the congestion 4091 * parameters. 4092 */ 4093 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4094 if (state != DEV_STATE_INIT) { 4095 int i; 4096 4097 /* The default MTU Table contains values 1492 and 1500. 4098 * However, for TCP, it's better to have two values which are 4099 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4100 * This allows us to have a TCP Data Payload which is a 4101 * multiple of 8 regardless of what combination of TCP Options 4102 * are in use (always a multiple of 4 bytes) which is 4103 * important for performance reasons. For instance, if no 4104 * options are in use, then we have a 20-byte IP header and a 4105 * 20-byte TCP header. In this case, a 1500-byte MSS would 4106 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4107 * which is not a multiple of 8. So using an MSS of 1488 in 4108 * this case results in a TCP Data Payload of 1448 bytes which 4109 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4110 * Stamps have been negotiated, then an MTU of 1500 bytes 4111 * results in a TCP Data Payload of 1448 bytes which, as 4112 * above, is a multiple of 8 bytes ... 4113 */ 4114 for (i = 0; i < NMTUS; i++) 4115 if (adap->params.mtus[i] == 1492) { 4116 adap->params.mtus[i] = 1488; 4117 break; 4118 } 4119 4120 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4121 adap->params.b_wnd); 4122 } 4123 t4_init_sge_params(adap); 4124 adap->flags |= FW_OK; 4125 t4_init_tp_params(adap, true); 4126 return 0; 4127 4128 /* 4129 * Something bad happened. If a command timed out or failed with EIO 4130 * FW does not operate within its spec or something catastrophic 4131 * happened to HW/FW, stop issuing commands. 4132 */ 4133 bye: 4134 kfree(adap->sge.egr_map); 4135 kfree(adap->sge.ingr_map); 4136 kfree(adap->sge.starving_fl); 4137 kfree(adap->sge.txq_maperr); 4138 #ifdef CONFIG_DEBUG_FS 4139 kfree(adap->sge.blocked_fl); 4140 #endif 4141 if (ret != -ETIMEDOUT && ret != -EIO) 4142 t4_fw_bye(adap, adap->mbox); 4143 return ret; 4144 } 4145 4146 /* EEH callbacks */ 4147 4148 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4149 pci_channel_state_t state) 4150 { 4151 int i; 4152 struct adapter *adap = pci_get_drvdata(pdev); 4153 4154 if (!adap) 4155 goto out; 4156 4157 rtnl_lock(); 4158 adap->flags &= ~FW_OK; 4159 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4160 spin_lock(&adap->stats_lock); 4161 for_each_port(adap, i) { 4162 struct net_device *dev = adap->port[i]; 4163 if (dev) { 4164 netif_device_detach(dev); 4165 netif_carrier_off(dev); 4166 } 4167 } 4168 spin_unlock(&adap->stats_lock); 4169 disable_interrupts(adap); 4170 if (adap->flags & FULL_INIT_DONE) 4171 cxgb_down(adap); 4172 rtnl_unlock(); 4173 if ((adap->flags & DEV_ENABLED)) { 4174 pci_disable_device(pdev); 4175 adap->flags &= ~DEV_ENABLED; 4176 } 4177 out: return state == pci_channel_io_perm_failure ? 4178 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4179 } 4180 4181 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4182 { 4183 int i, ret; 4184 struct fw_caps_config_cmd c; 4185 struct adapter *adap = pci_get_drvdata(pdev); 4186 4187 if (!adap) { 4188 pci_restore_state(pdev); 4189 pci_save_state(pdev); 4190 return PCI_ERS_RESULT_RECOVERED; 4191 } 4192 4193 if (!(adap->flags & DEV_ENABLED)) { 4194 if (pci_enable_device(pdev)) { 4195 dev_err(&pdev->dev, "Cannot reenable PCI " 4196 "device after reset\n"); 4197 return PCI_ERS_RESULT_DISCONNECT; 4198 } 4199 adap->flags |= DEV_ENABLED; 4200 } 4201 4202 pci_set_master(pdev); 4203 pci_restore_state(pdev); 4204 pci_save_state(pdev); 4205 pci_cleanup_aer_uncorrect_error_status(pdev); 4206 4207 if (t4_wait_dev_ready(adap->regs) < 0) 4208 return PCI_ERS_RESULT_DISCONNECT; 4209 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 4210 return PCI_ERS_RESULT_DISCONNECT; 4211 adap->flags |= FW_OK; 4212 if (adap_init1(adap, &c)) 4213 return PCI_ERS_RESULT_DISCONNECT; 4214 4215 for_each_port(adap, i) { 4216 struct port_info *p = adap2pinfo(adap, i); 4217 4218 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1, 4219 NULL, NULL); 4220 if (ret < 0) 4221 return PCI_ERS_RESULT_DISCONNECT; 4222 p->viid = ret; 4223 p->xact_addr_filt = -1; 4224 } 4225 4226 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4227 adap->params.b_wnd); 4228 setup_memwin(adap); 4229 if (cxgb_up(adap)) 4230 return PCI_ERS_RESULT_DISCONNECT; 4231 return PCI_ERS_RESULT_RECOVERED; 4232 } 4233 4234 static void eeh_resume(struct pci_dev *pdev) 4235 { 4236 int i; 4237 struct adapter *adap = pci_get_drvdata(pdev); 4238 4239 if (!adap) 4240 return; 4241 4242 rtnl_lock(); 4243 for_each_port(adap, i) { 4244 struct net_device *dev = adap->port[i]; 4245 if (dev) { 4246 if (netif_running(dev)) { 4247 link_start(dev); 4248 cxgb_set_rxmode(dev); 4249 } 4250 netif_device_attach(dev); 4251 } 4252 } 4253 rtnl_unlock(); 4254 } 4255 4256 static const struct pci_error_handlers cxgb4_eeh = { 4257 .error_detected = eeh_err_detected, 4258 .slot_reset = eeh_slot_reset, 4259 .resume = eeh_resume, 4260 }; 4261 4262 /* Return true if the Link Configuration supports "High Speeds" (those greater 4263 * than 1Gb/s). 4264 */ 4265 static inline bool is_x_10g_port(const struct link_config *lc) 4266 { 4267 unsigned int speeds, high_speeds; 4268 4269 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 4270 high_speeds = speeds & 4271 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 4272 4273 return high_speeds != 0; 4274 } 4275 4276 /* 4277 * Perform default configuration of DMA queues depending on the number and type 4278 * of ports we found and the number of available CPUs. Most settings can be 4279 * modified by the admin prior to actual use. 4280 */ 4281 static void cfg_queues(struct adapter *adap) 4282 { 4283 struct sge *s = &adap->sge; 4284 int i = 0, n10g = 0, qidx = 0; 4285 #ifndef CONFIG_CHELSIO_T4_DCB 4286 int q10g = 0; 4287 #endif 4288 4289 /* Reduce memory usage in kdump environment, disable all offload. 4290 */ 4291 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 4292 adap->params.offload = 0; 4293 adap->params.crypto = 0; 4294 } 4295 4296 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 4297 #ifdef CONFIG_CHELSIO_T4_DCB 4298 /* For Data Center Bridging support we need to be able to support up 4299 * to 8 Traffic Priorities; each of which will be assigned to its 4300 * own TX Queue in order to prevent Head-Of-Line Blocking. 4301 */ 4302 if (adap->params.nports * 8 > MAX_ETH_QSETS) { 4303 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n", 4304 MAX_ETH_QSETS, adap->params.nports * 8); 4305 BUG_ON(1); 4306 } 4307 4308 for_each_port(adap, i) { 4309 struct port_info *pi = adap2pinfo(adap, i); 4310 4311 pi->first_qset = qidx; 4312 pi->nqsets = is_kdump_kernel() ? 1 : 8; 4313 qidx += pi->nqsets; 4314 } 4315 #else /* !CONFIG_CHELSIO_T4_DCB */ 4316 /* 4317 * We default to 1 queue per non-10G port and up to # of cores queues 4318 * per 10G port. 4319 */ 4320 if (n10g) 4321 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g; 4322 if (q10g > netif_get_num_default_rss_queues()) 4323 q10g = netif_get_num_default_rss_queues(); 4324 4325 if (is_kdump_kernel()) 4326 q10g = 1; 4327 4328 for_each_port(adap, i) { 4329 struct port_info *pi = adap2pinfo(adap, i); 4330 4331 pi->first_qset = qidx; 4332 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 4333 qidx += pi->nqsets; 4334 } 4335 #endif /* !CONFIG_CHELSIO_T4_DCB */ 4336 4337 s->ethqsets = qidx; 4338 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 4339 4340 if (is_uld(adap)) { 4341 /* 4342 * For offload we use 1 queue/channel if all ports are up to 1G, 4343 * otherwise we divide all available queues amongst the channels 4344 * capped by the number of available cores. 4345 */ 4346 if (n10g) { 4347 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); 4348 s->ofldqsets = roundup(i, adap->params.nports); 4349 } else { 4350 s->ofldqsets = adap->params.nports; 4351 } 4352 } 4353 4354 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 4355 struct sge_eth_rxq *r = &s->ethrxq[i]; 4356 4357 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 4358 r->fl.size = 72; 4359 } 4360 4361 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 4362 s->ethtxq[i].q.size = 1024; 4363 4364 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 4365 s->ctrlq[i].q.size = 512; 4366 4367 if (!is_t4(adap->params.chip)) 4368 s->ptptxq.q.size = 8; 4369 4370 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 4371 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 4372 } 4373 4374 /* 4375 * Reduce the number of Ethernet queues across all ports to at most n. 4376 * n provides at least one queue per port. 4377 */ 4378 static void reduce_ethqs(struct adapter *adap, int n) 4379 { 4380 int i; 4381 struct port_info *pi; 4382 4383 while (n < adap->sge.ethqsets) 4384 for_each_port(adap, i) { 4385 pi = adap2pinfo(adap, i); 4386 if (pi->nqsets > 1) { 4387 pi->nqsets--; 4388 adap->sge.ethqsets--; 4389 if (adap->sge.ethqsets <= n) 4390 break; 4391 } 4392 } 4393 4394 n = 0; 4395 for_each_port(adap, i) { 4396 pi = adap2pinfo(adap, i); 4397 pi->first_qset = n; 4398 n += pi->nqsets; 4399 } 4400 } 4401 4402 static int get_msix_info(struct adapter *adap) 4403 { 4404 struct uld_msix_info *msix_info; 4405 unsigned int max_ingq = 0; 4406 4407 if (is_offload(adap)) 4408 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; 4409 if (is_pci_uld(adap)) 4410 max_ingq += MAX_OFLD_QSETS * adap->num_uld; 4411 4412 if (!max_ingq) 4413 goto out; 4414 4415 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); 4416 if (!msix_info) 4417 return -ENOMEM; 4418 4419 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), 4420 sizeof(long), GFP_KERNEL); 4421 if (!adap->msix_bmap_ulds.msix_bmap) { 4422 kfree(msix_info); 4423 return -ENOMEM; 4424 } 4425 spin_lock_init(&adap->msix_bmap_ulds.lock); 4426 adap->msix_info_ulds = msix_info; 4427 out: 4428 return 0; 4429 } 4430 4431 static void free_msix_info(struct adapter *adap) 4432 { 4433 if (!(adap->num_uld && adap->num_ofld_uld)) 4434 return; 4435 4436 kfree(adap->msix_info_ulds); 4437 kfree(adap->msix_bmap_ulds.msix_bmap); 4438 } 4439 4440 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 4441 #define EXTRA_VECS 2 4442 4443 static int enable_msix(struct adapter *adap) 4444 { 4445 int ofld_need = 0, uld_need = 0; 4446 int i, j, want, need, allocated; 4447 struct sge *s = &adap->sge; 4448 unsigned int nchan = adap->params.nports; 4449 struct msix_entry *entries; 4450 int max_ingq = MAX_INGQ; 4451 4452 if (is_pci_uld(adap)) 4453 max_ingq += (MAX_OFLD_QSETS * adap->num_uld); 4454 if (is_offload(adap)) 4455 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); 4456 entries = kmalloc(sizeof(*entries) * (max_ingq + 1), 4457 GFP_KERNEL); 4458 if (!entries) 4459 return -ENOMEM; 4460 4461 /* map for msix */ 4462 if (get_msix_info(adap)) { 4463 adap->params.offload = 0; 4464 adap->params.crypto = 0; 4465 } 4466 4467 for (i = 0; i < max_ingq + 1; ++i) 4468 entries[i].entry = i; 4469 4470 want = s->max_ethqsets + EXTRA_VECS; 4471 if (is_offload(adap)) { 4472 want += adap->num_ofld_uld * s->ofldqsets; 4473 ofld_need = adap->num_ofld_uld * nchan; 4474 } 4475 if (is_pci_uld(adap)) { 4476 want += adap->num_uld * s->ofldqsets; 4477 uld_need = adap->num_uld * nchan; 4478 } 4479 #ifdef CONFIG_CHELSIO_T4_DCB 4480 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 4481 * each port. 4482 */ 4483 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 4484 #else 4485 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 4486 #endif 4487 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 4488 if (allocated < 0) { 4489 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 4490 " not using MSI-X\n"); 4491 kfree(entries); 4492 return allocated; 4493 } 4494 4495 /* Distribute available vectors to the various queue groups. 4496 * Every group gets its minimum requirement and NIC gets top 4497 * priority for leftovers. 4498 */ 4499 i = allocated - EXTRA_VECS - ofld_need - uld_need; 4500 if (i < s->max_ethqsets) { 4501 s->max_ethqsets = i; 4502 if (i < s->ethqsets) 4503 reduce_ethqs(adap, i); 4504 } 4505 if (is_uld(adap)) { 4506 if (allocated < want) 4507 s->nqs_per_uld = nchan; 4508 else 4509 s->nqs_per_uld = s->ofldqsets; 4510 } 4511 4512 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) 4513 adap->msix_info[i].vec = entries[i].vector; 4514 if (is_uld(adap)) { 4515 for (j = 0 ; i < allocated; ++i, j++) { 4516 adap->msix_info_ulds[j].vec = entries[i].vector; 4517 adap->msix_info_ulds[j].idx = i; 4518 } 4519 adap->msix_bmap_ulds.mapsize = j; 4520 } 4521 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " 4522 "nic %d per uld %d\n", 4523 allocated, s->max_ethqsets, s->nqs_per_uld); 4524 4525 kfree(entries); 4526 return 0; 4527 } 4528 4529 #undef EXTRA_VECS 4530 4531 static int init_rss(struct adapter *adap) 4532 { 4533 unsigned int i; 4534 int err; 4535 4536 err = t4_init_rss_mode(adap, adap->mbox); 4537 if (err) 4538 return err; 4539 4540 for_each_port(adap, i) { 4541 struct port_info *pi = adap2pinfo(adap, i); 4542 4543 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 4544 if (!pi->rss) 4545 return -ENOMEM; 4546 } 4547 return 0; 4548 } 4549 4550 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap, 4551 enum pci_bus_speed *speed, 4552 enum pcie_link_width *width) 4553 { 4554 u32 lnkcap1, lnkcap2; 4555 int err1, err2; 4556 4557 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ 4558 4559 *speed = PCI_SPEED_UNKNOWN; 4560 *width = PCIE_LNK_WIDTH_UNKNOWN; 4561 4562 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP, 4563 &lnkcap1); 4564 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2, 4565 &lnkcap2); 4566 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ 4567 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) 4568 *speed = PCIE_SPEED_8_0GT; 4569 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) 4570 *speed = PCIE_SPEED_5_0GT; 4571 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) 4572 *speed = PCIE_SPEED_2_5GT; 4573 } 4574 if (!err1) { 4575 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; 4576 if (!lnkcap2) { /* pre-r3.0 */ 4577 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) 4578 *speed = PCIE_SPEED_5_0GT; 4579 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) 4580 *speed = PCIE_SPEED_2_5GT; 4581 } 4582 } 4583 4584 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) 4585 return err1 ? err1 : err2 ? err2 : -EINVAL; 4586 return 0; 4587 } 4588 4589 static void cxgb4_check_pcie_caps(struct adapter *adap) 4590 { 4591 enum pcie_link_width width, width_cap; 4592 enum pci_bus_speed speed, speed_cap; 4593 4594 #define PCIE_SPEED_STR(speed) \ 4595 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ 4596 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ 4597 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ 4598 "Unknown") 4599 4600 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) { 4601 dev_warn(adap->pdev_dev, 4602 "Unable to determine PCIe device BW capabilities\n"); 4603 return; 4604 } 4605 4606 if (pcie_get_minimum_link(adap->pdev, &speed, &width) || 4607 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) { 4608 dev_warn(adap->pdev_dev, 4609 "Unable to determine PCI Express bandwidth.\n"); 4610 return; 4611 } 4612 4613 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n", 4614 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); 4615 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n", 4616 width, width_cap); 4617 if (speed < speed_cap || width < width_cap) 4618 dev_info(adap->pdev_dev, 4619 "A slot with more lanes and/or higher speed is " 4620 "suggested for optimal performance.\n"); 4621 } 4622 4623 /* Dump basic information about the adapter */ 4624 static void print_adapter_info(struct adapter *adapter) 4625 { 4626 /* Hardware/Firmware/etc. Version/Revision IDs */ 4627 t4_dump_version_info(adapter); 4628 4629 /* Software/Hardware configuration */ 4630 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 4631 is_offload(adapter) ? "R" : "", 4632 ((adapter->flags & USING_MSIX) ? "MSI-X" : 4633 (adapter->flags & USING_MSI) ? "MSI" : ""), 4634 is_offload(adapter) ? "Offload" : "non-Offload"); 4635 } 4636 4637 static void print_port_info(const struct net_device *dev) 4638 { 4639 char buf[80]; 4640 char *bufp = buf; 4641 const char *spd = ""; 4642 const struct port_info *pi = netdev_priv(dev); 4643 const struct adapter *adap = pi->adapter; 4644 4645 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB) 4646 spd = " 2.5 GT/s"; 4647 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB) 4648 spd = " 5 GT/s"; 4649 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB) 4650 spd = " 8 GT/s"; 4651 4652 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 4653 bufp += sprintf(bufp, "100M/"); 4654 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 4655 bufp += sprintf(bufp, "1G/"); 4656 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 4657 bufp += sprintf(bufp, "10G/"); 4658 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 4659 bufp += sprintf(bufp, "25G/"); 4660 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 4661 bufp += sprintf(bufp, "40G/"); 4662 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 4663 bufp += sprintf(bufp, "50G/"); 4664 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 4665 bufp += sprintf(bufp, "100G/"); 4666 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 4667 bufp += sprintf(bufp, "200G/"); 4668 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 4669 bufp += sprintf(bufp, "400G/"); 4670 if (bufp != buf) 4671 --bufp; 4672 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 4673 4674 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 4675 dev->name, adap->params.vpd.id, adap->name, buf); 4676 } 4677 4678 /* 4679 * Free the following resources: 4680 * - memory used for tables 4681 * - MSI/MSI-X 4682 * - net devices 4683 * - resources FW is holding for us 4684 */ 4685 static void free_some_resources(struct adapter *adapter) 4686 { 4687 unsigned int i; 4688 4689 kvfree(adapter->smt); 4690 kvfree(adapter->l2t); 4691 t4_cleanup_sched(adapter); 4692 kvfree(adapter->tids.tid_tab); 4693 cxgb4_cleanup_tc_flower(adapter); 4694 cxgb4_cleanup_tc_u32(adapter); 4695 kfree(adapter->sge.egr_map); 4696 kfree(adapter->sge.ingr_map); 4697 kfree(adapter->sge.starving_fl); 4698 kfree(adapter->sge.txq_maperr); 4699 #ifdef CONFIG_DEBUG_FS 4700 kfree(adapter->sge.blocked_fl); 4701 #endif 4702 disable_msi(adapter); 4703 4704 for_each_port(adapter, i) 4705 if (adapter->port[i]) { 4706 struct port_info *pi = adap2pinfo(adapter, i); 4707 4708 if (pi->viid != 0) 4709 t4_free_vi(adapter, adapter->mbox, adapter->pf, 4710 0, pi->viid); 4711 kfree(adap2pinfo(adapter, i)->rss); 4712 free_netdev(adapter->port[i]); 4713 } 4714 if (adapter->flags & FW_OK) 4715 t4_fw_bye(adapter, adapter->pf); 4716 } 4717 4718 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 4719 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 4720 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 4721 #define SEGMENT_SIZE 128 4722 4723 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev) 4724 { 4725 u16 device_id; 4726 4727 /* Retrieve adapter's device ID */ 4728 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 4729 4730 switch (device_id >> 12) { 4731 case CHELSIO_T4: 4732 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 4733 case CHELSIO_T5: 4734 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 4735 case CHELSIO_T6: 4736 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 4737 default: 4738 dev_err(&pdev->dev, "Device %d is not supported\n", 4739 device_id); 4740 } 4741 return -EINVAL; 4742 } 4743 4744 #ifdef CONFIG_PCI_IOV 4745 static void dummy_setup(struct net_device *dev) 4746 { 4747 dev->type = ARPHRD_NONE; 4748 dev->mtu = 0; 4749 dev->hard_header_len = 0; 4750 dev->addr_len = 0; 4751 dev->tx_queue_len = 0; 4752 dev->flags |= IFF_NOARP; 4753 dev->priv_flags |= IFF_NO_QUEUE; 4754 4755 /* Initialize the device structure. */ 4756 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 4757 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 4758 dev->needs_free_netdev = true; 4759 } 4760 4761 static int config_mgmt_dev(struct pci_dev *pdev) 4762 { 4763 struct adapter *adap = pci_get_drvdata(pdev); 4764 struct net_device *netdev; 4765 struct port_info *pi; 4766 char name[IFNAMSIZ]; 4767 int err; 4768 4769 snprintf(name, IFNAMSIZ, "mgmtpf%d%d", adap->adap_idx, adap->pf); 4770 netdev = alloc_netdev(sizeof(struct port_info), name, NET_NAME_UNKNOWN, 4771 dummy_setup); 4772 if (!netdev) 4773 return -ENOMEM; 4774 4775 pi = netdev_priv(netdev); 4776 pi->adapter = adap; 4777 pi->tx_chan = adap->pf % adap->params.nports; 4778 SET_NETDEV_DEV(netdev, &pdev->dev); 4779 4780 adap->port[0] = netdev; 4781 pi->port_id = 0; 4782 4783 err = register_netdev(adap->port[0]); 4784 if (err) { 4785 pr_info("Unable to register VF mgmt netdev %s\n", name); 4786 free_netdev(adap->port[0]); 4787 adap->port[0] = NULL; 4788 return err; 4789 } 4790 return 0; 4791 } 4792 4793 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 4794 { 4795 struct adapter *adap = pci_get_drvdata(pdev); 4796 int err = 0; 4797 int current_vfs = pci_num_vf(pdev); 4798 u32 pcie_fw; 4799 4800 pcie_fw = readl(adap->regs + PCIE_FW_A); 4801 /* Check if cxgb4 is the MASTER and fw is initialized */ 4802 if (!(pcie_fw & PCIE_FW_INIT_F) || 4803 !(pcie_fw & PCIE_FW_MASTER_VLD_F) || 4804 PCIE_FW_MASTER_G(pcie_fw) != 4) { 4805 dev_warn(&pdev->dev, 4806 "cxgb4 driver needs to be MASTER to support SRIOV\n"); 4807 return -EOPNOTSUPP; 4808 } 4809 4810 /* If any of the VF's is already assigned to Guest OS, then 4811 * SRIOV for the same cannot be modified 4812 */ 4813 if (current_vfs && pci_vfs_assigned(pdev)) { 4814 dev_err(&pdev->dev, 4815 "Cannot modify SR-IOV while VFs are assigned\n"); 4816 num_vfs = current_vfs; 4817 return num_vfs; 4818 } 4819 4820 /* Disable SRIOV when zero is passed. 4821 * One needs to disable SRIOV before modifying it, else 4822 * stack throws the below warning: 4823 * " 'n' VFs already enabled. Disable before enabling 'm' VFs." 4824 */ 4825 if (!num_vfs) { 4826 pci_disable_sriov(pdev); 4827 if (adap->port[0]) { 4828 unregister_netdev(adap->port[0]); 4829 adap->port[0] = NULL; 4830 } 4831 /* free VF resources */ 4832 kfree(adap->vfinfo); 4833 adap->vfinfo = NULL; 4834 adap->num_vfs = 0; 4835 return num_vfs; 4836 } 4837 4838 if (num_vfs != current_vfs) { 4839 err = pci_enable_sriov(pdev, num_vfs); 4840 if (err) 4841 return err; 4842 4843 adap->num_vfs = num_vfs; 4844 err = config_mgmt_dev(pdev); 4845 if (err) 4846 return err; 4847 } 4848 4849 adap->vfinfo = kcalloc(adap->num_vfs, 4850 sizeof(struct vf_info), GFP_KERNEL); 4851 if (adap->vfinfo) 4852 fill_vf_station_mac_addr(adap); 4853 return num_vfs; 4854 } 4855 #endif 4856 4857 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4858 { 4859 int func, i, err, s_qpp, qpp, num_seg; 4860 struct port_info *pi; 4861 bool highdma = false; 4862 struct adapter *adapter = NULL; 4863 struct net_device *netdev; 4864 void __iomem *regs; 4865 u32 whoami, pl_rev; 4866 enum chip_type chip; 4867 static int adap_idx = 1; 4868 #ifdef CONFIG_PCI_IOV 4869 u32 v, port_vec; 4870 #endif 4871 4872 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 4873 4874 err = pci_request_regions(pdev, KBUILD_MODNAME); 4875 if (err) { 4876 /* Just info, some other driver may have claimed the device. */ 4877 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 4878 return err; 4879 } 4880 4881 err = pci_enable_device(pdev); 4882 if (err) { 4883 dev_err(&pdev->dev, "cannot enable PCI device\n"); 4884 goto out_release_regions; 4885 } 4886 4887 regs = pci_ioremap_bar(pdev, 0); 4888 if (!regs) { 4889 dev_err(&pdev->dev, "cannot map device registers\n"); 4890 err = -ENOMEM; 4891 goto out_disable_device; 4892 } 4893 4894 err = t4_wait_dev_ready(regs); 4895 if (err < 0) 4896 goto out_unmap_bar0; 4897 4898 /* We control everything through one PF */ 4899 whoami = readl(regs + PL_WHOAMI_A); 4900 pl_rev = REV_G(readl(regs + PL_REV_A)); 4901 chip = get_chip_type(pdev, pl_rev); 4902 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ? 4903 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 4904 if (func != ent->driver_data) { 4905 #ifndef CONFIG_PCI_IOV 4906 iounmap(regs); 4907 #endif 4908 pci_disable_device(pdev); 4909 pci_save_state(pdev); /* to restore SR-IOV later */ 4910 goto sriov; 4911 } 4912 4913 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 4914 highdma = true; 4915 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 4916 if (err) { 4917 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 4918 "coherent allocations\n"); 4919 goto out_unmap_bar0; 4920 } 4921 } else { 4922 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 4923 if (err) { 4924 dev_err(&pdev->dev, "no usable DMA configuration\n"); 4925 goto out_unmap_bar0; 4926 } 4927 } 4928 4929 pci_enable_pcie_error_reporting(pdev); 4930 pci_set_master(pdev); 4931 pci_save_state(pdev); 4932 4933 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 4934 if (!adapter) { 4935 err = -ENOMEM; 4936 goto out_unmap_bar0; 4937 } 4938 adap_idx++; 4939 4940 adapter->workq = create_singlethread_workqueue("cxgb4"); 4941 if (!adapter->workq) { 4942 err = -ENOMEM; 4943 goto out_free_adapter; 4944 } 4945 4946 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 4947 (sizeof(struct mbox_cmd) * 4948 T4_OS_LOG_MBOX_CMDS), 4949 GFP_KERNEL); 4950 if (!adapter->mbox_log) { 4951 err = -ENOMEM; 4952 goto out_free_adapter; 4953 } 4954 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 4955 4956 /* PCI device has been enabled */ 4957 adapter->flags |= DEV_ENABLED; 4958 4959 adapter->regs = regs; 4960 adapter->pdev = pdev; 4961 adapter->pdev_dev = &pdev->dev; 4962 adapter->name = pci_name(pdev); 4963 adapter->mbox = func; 4964 adapter->pf = func; 4965 adapter->msg_enable = DFLT_MSG_ENABLE; 4966 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 4967 4968 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 4969 * Ingress Packet Data to Free List Buffers in order to allow for 4970 * chipset performance optimizations between the Root Complex and 4971 * Memory Controllers. (Messages to the associated Ingress Queue 4972 * notifying new Packet Placement in the Free Lists Buffers will be 4973 * send without the Relaxed Ordering Attribute thus guaranteeing that 4974 * all preceding PCIe Transaction Layer Packets will be processed 4975 * first.) But some Root Complexes have various issues with Upstream 4976 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 4977 * The PCIe devices which under the Root Complexes will be cleared the 4978 * Relaxed Ordering bit in the configuration space, So we check our 4979 * PCIe configuration space to see if it's flagged with advice against 4980 * using Relaxed Ordering. 4981 */ 4982 if (!pcie_relaxed_ordering_enabled(pdev)) 4983 adapter->flags |= ROOT_NO_RELAXED_ORDERING; 4984 4985 spin_lock_init(&adapter->stats_lock); 4986 spin_lock_init(&adapter->tid_release_lock); 4987 spin_lock_init(&adapter->win0_lock); 4988 spin_lock_init(&adapter->mbox_lock); 4989 4990 INIT_LIST_HEAD(&adapter->mlist.list); 4991 4992 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 4993 INIT_WORK(&adapter->db_full_task, process_db_full); 4994 INIT_WORK(&adapter->db_drop_task, process_db_drop); 4995 4996 err = t4_prep_adapter(adapter); 4997 if (err) 4998 goto out_free_adapter; 4999 5000 5001 if (!is_t4(adapter->params.chip)) { 5002 s_qpp = (QUEUESPERPAGEPF0_S + 5003 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 5004 adapter->pf); 5005 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 5006 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 5007 num_seg = PAGE_SIZE / SEGMENT_SIZE; 5008 5009 /* Each segment size is 128B. Write coalescing is enabled only 5010 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 5011 * queue is less no of segments that can be accommodated in 5012 * a page size. 5013 */ 5014 if (qpp > num_seg) { 5015 dev_err(&pdev->dev, 5016 "Incorrect number of egress queues per page\n"); 5017 err = -EINVAL; 5018 goto out_free_adapter; 5019 } 5020 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 5021 pci_resource_len(pdev, 2)); 5022 if (!adapter->bar2) { 5023 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 5024 err = -ENOMEM; 5025 goto out_free_adapter; 5026 } 5027 } 5028 5029 setup_memwin(adapter); 5030 err = adap_init0(adapter); 5031 #ifdef CONFIG_DEBUG_FS 5032 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 5033 #endif 5034 setup_memwin_rdma(adapter); 5035 if (err) 5036 goto out_unmap_bar; 5037 5038 /* configure SGE_STAT_CFG_A to read WC stats */ 5039 if (!is_t4(adapter->params.chip)) 5040 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 5041 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 5042 T6_STATMODE_V(0))); 5043 5044 for_each_port(adapter, i) { 5045 netdev = alloc_etherdev_mq(sizeof(struct port_info), 5046 MAX_ETH_QSETS); 5047 if (!netdev) { 5048 err = -ENOMEM; 5049 goto out_free_dev; 5050 } 5051 5052 SET_NETDEV_DEV(netdev, &pdev->dev); 5053 5054 adapter->port[i] = netdev; 5055 pi = netdev_priv(netdev); 5056 pi->adapter = adapter; 5057 pi->xact_addr_filt = -1; 5058 pi->port_id = i; 5059 netdev->irq = pdev->irq; 5060 5061 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 5062 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5063 NETIF_F_RXCSUM | NETIF_F_RXHASH | 5064 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 5065 NETIF_F_HW_TC; 5066 if (highdma) 5067 netdev->hw_features |= NETIF_F_HIGHDMA; 5068 netdev->features |= netdev->hw_features; 5069 netdev->vlan_features = netdev->features & VLAN_FEAT; 5070 5071 netdev->priv_flags |= IFF_UNICAST_FLT; 5072 5073 /* MTU range: 81 - 9600 */ 5074 netdev->min_mtu = 81; /* accommodate SACK */ 5075 netdev->max_mtu = MAX_MTU; 5076 5077 netdev->netdev_ops = &cxgb4_netdev_ops; 5078 #ifdef CONFIG_CHELSIO_T4_DCB 5079 netdev->dcbnl_ops = &cxgb4_dcb_ops; 5080 cxgb4_dcb_state_init(netdev); 5081 #endif 5082 cxgb4_set_ethtool_ops(netdev); 5083 } 5084 5085 cxgb4_init_ethtool_dump(adapter); 5086 5087 pci_set_drvdata(pdev, adapter); 5088 5089 if (adapter->flags & FW_OK) { 5090 err = t4_port_init(adapter, func, func, 0); 5091 if (err) 5092 goto out_free_dev; 5093 } else if (adapter->params.nports == 1) { 5094 /* If we don't have a connection to the firmware -- possibly 5095 * because of an error -- grab the raw VPD parameters so we 5096 * can set the proper MAC Address on the debug network 5097 * interface that we've created. 5098 */ 5099 u8 hw_addr[ETH_ALEN]; 5100 u8 *na = adapter->params.vpd.na; 5101 5102 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 5103 if (!err) { 5104 for (i = 0; i < ETH_ALEN; i++) 5105 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 5106 hex2val(na[2 * i + 1])); 5107 t4_set_hw_addr(adapter, 0, hw_addr); 5108 } 5109 } 5110 5111 /* Configure queues and allocate tables now, they can be needed as 5112 * soon as the first register_netdev completes. 5113 */ 5114 cfg_queues(adapter); 5115 5116 adapter->smt = t4_init_smt(); 5117 if (!adapter->smt) { 5118 /* We tolerate a lack of SMT, giving up some functionality */ 5119 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); 5120 } 5121 5122 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 5123 if (!adapter->l2t) { 5124 /* We tolerate a lack of L2T, giving up some functionality */ 5125 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 5126 adapter->params.offload = 0; 5127 } 5128 5129 #if IS_ENABLED(CONFIG_IPV6) 5130 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) && 5131 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 5132 /* CLIP functionality is not present in hardware, 5133 * hence disable all offload features 5134 */ 5135 dev_warn(&pdev->dev, 5136 "CLIP not enabled in hardware, continuing\n"); 5137 adapter->params.offload = 0; 5138 } else { 5139 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 5140 adapter->clipt_end); 5141 if (!adapter->clipt) { 5142 /* We tolerate a lack of clip_table, giving up 5143 * some functionality 5144 */ 5145 dev_warn(&pdev->dev, 5146 "could not allocate Clip table, continuing\n"); 5147 adapter->params.offload = 0; 5148 } 5149 } 5150 #endif 5151 5152 for_each_port(adapter, i) { 5153 pi = adap2pinfo(adapter, i); 5154 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 5155 if (!pi->sched_tbl) 5156 dev_warn(&pdev->dev, 5157 "could not activate scheduling on port %d\n", 5158 i); 5159 } 5160 5161 if (tid_init(&adapter->tids) < 0) { 5162 dev_warn(&pdev->dev, "could not allocate TID table, " 5163 "continuing\n"); 5164 adapter->params.offload = 0; 5165 } else { 5166 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 5167 if (!adapter->tc_u32) 5168 dev_warn(&pdev->dev, 5169 "could not offload tc u32, continuing\n"); 5170 5171 cxgb4_init_tc_flower(adapter); 5172 } 5173 5174 if (is_offload(adapter)) { 5175 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 5176 u32 hash_base, hash_reg; 5177 5178 if (chip <= CHELSIO_T5) { 5179 hash_reg = LE_DB_TID_HASHBASE_A; 5180 hash_base = t4_read_reg(adapter, hash_reg); 5181 adapter->tids.hash_base = hash_base / 4; 5182 } else { 5183 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 5184 hash_base = t4_read_reg(adapter, hash_reg); 5185 adapter->tids.hash_base = hash_base; 5186 } 5187 } 5188 } 5189 5190 /* See what interrupts we'll be using */ 5191 if (msi > 1 && enable_msix(adapter) == 0) 5192 adapter->flags |= USING_MSIX; 5193 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 5194 adapter->flags |= USING_MSI; 5195 if (msi > 1) 5196 free_msix_info(adapter); 5197 } 5198 5199 /* check for PCI Express bandwidth capabiltites */ 5200 cxgb4_check_pcie_caps(adapter); 5201 5202 err = init_rss(adapter); 5203 if (err) 5204 goto out_free_dev; 5205 5206 /* 5207 * The card is now ready to go. If any errors occur during device 5208 * registration we do not fail the whole card but rather proceed only 5209 * with the ports we manage to register successfully. However we must 5210 * register at least one net device. 5211 */ 5212 for_each_port(adapter, i) { 5213 pi = adap2pinfo(adapter, i); 5214 adapter->port[i]->dev_port = pi->lport; 5215 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 5216 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 5217 5218 netif_carrier_off(adapter->port[i]); 5219 5220 err = register_netdev(adapter->port[i]); 5221 if (err) 5222 break; 5223 adapter->chan_map[pi->tx_chan] = i; 5224 print_port_info(adapter->port[i]); 5225 } 5226 if (i == 0) { 5227 dev_err(&pdev->dev, "could not register any net devices\n"); 5228 goto out_free_dev; 5229 } 5230 if (err) { 5231 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 5232 err = 0; 5233 } 5234 5235 if (cxgb4_debugfs_root) { 5236 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 5237 cxgb4_debugfs_root); 5238 setup_debugfs(adapter); 5239 } 5240 5241 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 5242 pdev->needs_freset = 1; 5243 5244 if (is_uld(adapter)) { 5245 mutex_lock(&uld_mutex); 5246 list_add_tail(&adapter->list_node, &adapter_list); 5247 mutex_unlock(&uld_mutex); 5248 } 5249 5250 if (!is_t4(adapter->params.chip)) 5251 cxgb4_ptp_init(adapter); 5252 5253 print_adapter_info(adapter); 5254 setup_fw_sge_queues(adapter); 5255 return 0; 5256 5257 sriov: 5258 #ifdef CONFIG_PCI_IOV 5259 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 5260 if (!adapter) { 5261 err = -ENOMEM; 5262 goto free_pci_region; 5263 } 5264 5265 adapter->pdev = pdev; 5266 adapter->pdev_dev = &pdev->dev; 5267 adapter->name = pci_name(pdev); 5268 adapter->mbox = func; 5269 adapter->pf = func; 5270 adapter->regs = regs; 5271 adapter->adap_idx = adap_idx; 5272 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 5273 (sizeof(struct mbox_cmd) * 5274 T4_OS_LOG_MBOX_CMDS), 5275 GFP_KERNEL); 5276 if (!adapter->mbox_log) { 5277 err = -ENOMEM; 5278 goto free_adapter; 5279 } 5280 spin_lock_init(&adapter->mbox_lock); 5281 INIT_LIST_HEAD(&adapter->mlist.list); 5282 5283 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 5284 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 5285 err = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 1, 5286 &v, &port_vec); 5287 if (err < 0) { 5288 dev_err(adapter->pdev_dev, "Could not fetch port params\n"); 5289 goto free_mbox_log; 5290 } 5291 5292 adapter->params.nports = hweight32(port_vec); 5293 pci_set_drvdata(pdev, adapter); 5294 return 0; 5295 5296 free_mbox_log: 5297 kfree(adapter->mbox_log); 5298 free_adapter: 5299 kfree(adapter); 5300 free_pci_region: 5301 iounmap(regs); 5302 pci_disable_sriov(pdev); 5303 pci_release_regions(pdev); 5304 return err; 5305 #else 5306 return 0; 5307 #endif 5308 5309 out_free_dev: 5310 free_some_resources(adapter); 5311 if (adapter->flags & USING_MSIX) 5312 free_msix_info(adapter); 5313 if (adapter->num_uld || adapter->num_ofld_uld) 5314 t4_uld_mem_free(adapter); 5315 out_unmap_bar: 5316 if (!is_t4(adapter->params.chip)) 5317 iounmap(adapter->bar2); 5318 out_free_adapter: 5319 if (adapter->workq) 5320 destroy_workqueue(adapter->workq); 5321 5322 kfree(adapter->mbox_log); 5323 kfree(adapter); 5324 out_unmap_bar0: 5325 iounmap(regs); 5326 out_disable_device: 5327 pci_disable_pcie_error_reporting(pdev); 5328 pci_disable_device(pdev); 5329 out_release_regions: 5330 pci_release_regions(pdev); 5331 return err; 5332 } 5333 5334 static void remove_one(struct pci_dev *pdev) 5335 { 5336 struct adapter *adapter = pci_get_drvdata(pdev); 5337 5338 if (!adapter) { 5339 pci_release_regions(pdev); 5340 return; 5341 } 5342 5343 adapter->flags |= SHUTTING_DOWN; 5344 5345 if (adapter->pf == 4) { 5346 int i; 5347 5348 /* Tear down per-adapter Work Queue first since it can contain 5349 * references to our adapter data structure. 5350 */ 5351 destroy_workqueue(adapter->workq); 5352 5353 if (is_uld(adapter)) { 5354 detach_ulds(adapter); 5355 t4_uld_clean_up(adapter); 5356 } 5357 5358 disable_interrupts(adapter); 5359 5360 for_each_port(adapter, i) 5361 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5362 unregister_netdev(adapter->port[i]); 5363 5364 debugfs_remove_recursive(adapter->debugfs_root); 5365 5366 if (!is_t4(adapter->params.chip)) 5367 cxgb4_ptp_stop(adapter); 5368 5369 /* If we allocated filters, free up state associated with any 5370 * valid filters ... 5371 */ 5372 clear_all_filters(adapter); 5373 5374 if (adapter->flags & FULL_INIT_DONE) 5375 cxgb_down(adapter); 5376 5377 if (adapter->flags & USING_MSIX) 5378 free_msix_info(adapter); 5379 if (adapter->num_uld || adapter->num_ofld_uld) 5380 t4_uld_mem_free(adapter); 5381 free_some_resources(adapter); 5382 #if IS_ENABLED(CONFIG_IPV6) 5383 t4_cleanup_clip_tbl(adapter); 5384 #endif 5385 iounmap(adapter->regs); 5386 if (!is_t4(adapter->params.chip)) 5387 iounmap(adapter->bar2); 5388 pci_disable_pcie_error_reporting(pdev); 5389 if ((adapter->flags & DEV_ENABLED)) { 5390 pci_disable_device(pdev); 5391 adapter->flags &= ~DEV_ENABLED; 5392 } 5393 pci_release_regions(pdev); 5394 kfree(adapter->mbox_log); 5395 synchronize_rcu(); 5396 kfree(adapter); 5397 } 5398 #ifdef CONFIG_PCI_IOV 5399 else { 5400 if (adapter->port[0]) 5401 unregister_netdev(adapter->port[0]); 5402 iounmap(adapter->regs); 5403 kfree(adapter->vfinfo); 5404 kfree(adapter->mbox_log); 5405 kfree(adapter); 5406 pci_disable_sriov(pdev); 5407 pci_release_regions(pdev); 5408 } 5409 #endif 5410 } 5411 5412 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 5413 * delivery. This is essentially a stripped down version of the PCI remove() 5414 * function where we do the minimal amount of work necessary to shutdown any 5415 * further activity. 5416 */ 5417 static void shutdown_one(struct pci_dev *pdev) 5418 { 5419 struct adapter *adapter = pci_get_drvdata(pdev); 5420 5421 /* As with remove_one() above (see extended comment), we only want do 5422 * do cleanup on PCI Devices which went all the way through init_one() 5423 * ... 5424 */ 5425 if (!adapter) { 5426 pci_release_regions(pdev); 5427 return; 5428 } 5429 5430 adapter->flags |= SHUTTING_DOWN; 5431 5432 if (adapter->pf == 4) { 5433 int i; 5434 5435 for_each_port(adapter, i) 5436 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 5437 cxgb_close(adapter->port[i]); 5438 5439 if (is_uld(adapter)) { 5440 detach_ulds(adapter); 5441 t4_uld_clean_up(adapter); 5442 } 5443 5444 disable_interrupts(adapter); 5445 disable_msi(adapter); 5446 5447 t4_sge_stop(adapter); 5448 if (adapter->flags & FW_OK) 5449 t4_fw_bye(adapter, adapter->mbox); 5450 } 5451 #ifdef CONFIG_PCI_IOV 5452 else { 5453 if (adapter->port[0]) 5454 unregister_netdev(adapter->port[0]); 5455 iounmap(adapter->regs); 5456 kfree(adapter->vfinfo); 5457 kfree(adapter->mbox_log); 5458 kfree(adapter); 5459 pci_disable_sriov(pdev); 5460 pci_release_regions(pdev); 5461 } 5462 #endif 5463 } 5464 5465 static struct pci_driver cxgb4_driver = { 5466 .name = KBUILD_MODNAME, 5467 .id_table = cxgb4_pci_tbl, 5468 .probe = init_one, 5469 .remove = remove_one, 5470 .shutdown = shutdown_one, 5471 #ifdef CONFIG_PCI_IOV 5472 .sriov_configure = cxgb4_iov_configure, 5473 #endif 5474 .err_handler = &cxgb4_eeh, 5475 }; 5476 5477 static int __init cxgb4_init_module(void) 5478 { 5479 int ret; 5480 5481 /* Debugfs support is optional, just warn if this fails */ 5482 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 5483 if (!cxgb4_debugfs_root) 5484 pr_warn("could not create debugfs entry, continuing\n"); 5485 5486 ret = pci_register_driver(&cxgb4_driver); 5487 if (ret < 0) 5488 debugfs_remove(cxgb4_debugfs_root); 5489 5490 #if IS_ENABLED(CONFIG_IPV6) 5491 if (!inet6addr_registered) { 5492 register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5493 inet6addr_registered = true; 5494 } 5495 #endif 5496 5497 return ret; 5498 } 5499 5500 static void __exit cxgb4_cleanup_module(void) 5501 { 5502 #if IS_ENABLED(CONFIG_IPV6) 5503 if (inet6addr_registered) { 5504 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 5505 inet6addr_registered = false; 5506 } 5507 #endif 5508 pci_unregister_driver(&cxgb4_driver); 5509 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 5510 } 5511 5512 module_init(cxgb4_init_module); 5513 module_exit(cxgb4_cleanup_module); 5514