1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 36 37 #include <linux/bitmap.h> 38 #include <linux/crc32.h> 39 #include <linux/ctype.h> 40 #include <linux/debugfs.h> 41 #include <linux/err.h> 42 #include <linux/etherdevice.h> 43 #include <linux/firmware.h> 44 #include <linux/if.h> 45 #include <linux/if_vlan.h> 46 #include <linux/init.h> 47 #include <linux/log2.h> 48 #include <linux/mdio.h> 49 #include <linux/module.h> 50 #include <linux/moduleparam.h> 51 #include <linux/mutex.h> 52 #include <linux/netdevice.h> 53 #include <linux/pci.h> 54 #include <linux/aer.h> 55 #include <linux/rtnetlink.h> 56 #include <linux/sched.h> 57 #include <linux/seq_file.h> 58 #include <linux/sockios.h> 59 #include <linux/vmalloc.h> 60 #include <linux/workqueue.h> 61 #include <net/neighbour.h> 62 #include <net/netevent.h> 63 #include <net/addrconf.h> 64 #include <net/bonding.h> 65 #include <linux/uaccess.h> 66 #include <linux/crash_dump.h> 67 #include <net/udp_tunnel.h> 68 69 #include "cxgb4.h" 70 #include "cxgb4_filter.h" 71 #include "t4_regs.h" 72 #include "t4_values.h" 73 #include "t4_msg.h" 74 #include "t4fw_api.h" 75 #include "t4fw_version.h" 76 #include "cxgb4_dcb.h" 77 #include "srq.h" 78 #include "cxgb4_debugfs.h" 79 #include "clip_tbl.h" 80 #include "l2t.h" 81 #include "smt.h" 82 #include "sched.h" 83 #include "cxgb4_tc_u32.h" 84 #include "cxgb4_tc_flower.h" 85 #include "cxgb4_ptp.h" 86 #include "cxgb4_cudbg.h" 87 88 char cxgb4_driver_name[] = KBUILD_MODNAME; 89 90 #ifdef DRV_VERSION 91 #undef DRV_VERSION 92 #endif 93 #define DRV_VERSION "2.0.0-ko" 94 const char cxgb4_driver_version[] = DRV_VERSION; 95 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver" 96 97 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \ 98 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\ 99 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 100 101 /* Macros needed to support the PCI Device ID Table ... 102 */ 103 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 104 static const struct pci_device_id cxgb4_pci_tbl[] = { 105 #define CXGB4_UNIFIED_PF 0x4 106 107 #define CH_PCI_DEVICE_ID_FUNCTION CXGB4_UNIFIED_PF 108 109 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is 110 * called for both. 111 */ 112 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0 113 114 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 115 {PCI_VDEVICE(CHELSIO, (devid)), CXGB4_UNIFIED_PF} 116 117 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 118 { 0, } \ 119 } 120 121 #include "t4_pci_id_tbl.h" 122 123 #define FW4_FNAME "cxgb4/t4fw.bin" 124 #define FW5_FNAME "cxgb4/t5fw.bin" 125 #define FW6_FNAME "cxgb4/t6fw.bin" 126 #define FW4_CFNAME "cxgb4/t4-config.txt" 127 #define FW5_CFNAME "cxgb4/t5-config.txt" 128 #define FW6_CFNAME "cxgb4/t6-config.txt" 129 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld" 130 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin" 131 #define PHY_AQ1202_DEVICEID 0x4409 132 #define PHY_BCM84834_DEVICEID 0x4486 133 134 MODULE_DESCRIPTION(DRV_DESC); 135 MODULE_AUTHOR("Chelsio Communications"); 136 MODULE_LICENSE("Dual BSD/GPL"); 137 MODULE_VERSION(DRV_VERSION); 138 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl); 139 MODULE_FIRMWARE(FW4_FNAME); 140 MODULE_FIRMWARE(FW5_FNAME); 141 MODULE_FIRMWARE(FW6_FNAME); 142 143 /* 144 * The driver uses the best interrupt scheme available on a platform in the 145 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which 146 * of these schemes the driver may consider as follows: 147 * 148 * msi = 2: choose from among all three options 149 * msi = 1: only consider MSI and INTx interrupts 150 * msi = 0: force INTx interrupts 151 */ 152 static int msi = 2; 153 154 module_param(msi, int, 0644); 155 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)"); 156 157 /* 158 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers 159 * offset by 2 bytes in order to have the IP headers line up on 4-byte 160 * boundaries. This is a requirement for many architectures which will throw 161 * a machine check fault if an attempt is made to access one of the 4-byte IP 162 * header fields on a non-4-byte boundary. And it's a major performance issue 163 * even on some architectures which allow it like some implementations of the 164 * x86 ISA. However, some architectures don't mind this and for some very 165 * edge-case performance sensitive applications (like forwarding large volumes 166 * of small packets), setting this DMA offset to 0 will decrease the number of 167 * PCI-E Bus transfers enough to measurably affect performance. 168 */ 169 static int rx_dma_offset = 2; 170 171 /* TX Queue select used to determine what algorithm to use for selecting TX 172 * queue. Select between the kernel provided function (select_queue=0) or user 173 * cxgb_select_queue function (select_queue=1) 174 * 175 * Default: select_queue=0 176 */ 177 static int select_queue; 178 module_param(select_queue, int, 0644); 179 MODULE_PARM_DESC(select_queue, 180 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method."); 181 182 static struct dentry *cxgb4_debugfs_root; 183 184 LIST_HEAD(adapter_list); 185 DEFINE_MUTEX(uld_mutex); 186 187 static void link_report(struct net_device *dev) 188 { 189 if (!netif_carrier_ok(dev)) 190 netdev_info(dev, "link down\n"); 191 else { 192 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" }; 193 194 const char *s; 195 const struct port_info *p = netdev_priv(dev); 196 197 switch (p->link_cfg.speed) { 198 case 100: 199 s = "100Mbps"; 200 break; 201 case 1000: 202 s = "1Gbps"; 203 break; 204 case 10000: 205 s = "10Gbps"; 206 break; 207 case 25000: 208 s = "25Gbps"; 209 break; 210 case 40000: 211 s = "40Gbps"; 212 break; 213 case 50000: 214 s = "50Gbps"; 215 break; 216 case 100000: 217 s = "100Gbps"; 218 break; 219 default: 220 pr_info("%s: unsupported speed: %d\n", 221 dev->name, p->link_cfg.speed); 222 return; 223 } 224 225 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, 226 fc[p->link_cfg.fc]); 227 } 228 } 229 230 #ifdef CONFIG_CHELSIO_T4_DCB 231 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */ 232 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable) 233 { 234 struct port_info *pi = netdev_priv(dev); 235 struct adapter *adap = pi->adapter; 236 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset]; 237 int i; 238 239 /* We use a simple mapping of Port TX Queue Index to DCB 240 * Priority when we're enabling DCB. 241 */ 242 for (i = 0; i < pi->nqsets; i++, txq++) { 243 u32 name, value; 244 int err; 245 246 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 247 FW_PARAMS_PARAM_X_V( 248 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) | 249 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id)); 250 value = enable ? i : 0xffffffff; 251 252 /* Since we can be called while atomic (from "interrupt 253 * level") we need to issue the Set Parameters Commannd 254 * without sleeping (timeout < 0). 255 */ 256 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, 257 &name, &value, 258 -FW_CMD_MAX_TIMEOUT); 259 260 if (err) 261 dev_err(adap->pdev_dev, 262 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n", 263 enable ? "set" : "unset", pi->port_id, i, -err); 264 else 265 txq->dcb_prio = enable ? value : 0; 266 } 267 } 268 269 int cxgb4_dcb_enabled(const struct net_device *dev) 270 { 271 struct port_info *pi = netdev_priv(dev); 272 273 if (!pi->dcb.enabled) 274 return 0; 275 276 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) || 277 (pi->dcb.state == CXGB4_DCB_STATE_HOST)); 278 } 279 #endif /* CONFIG_CHELSIO_T4_DCB */ 280 281 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat) 282 { 283 struct net_device *dev = adapter->port[port_id]; 284 285 /* Skip changes from disabled ports. */ 286 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) { 287 if (link_stat) 288 netif_carrier_on(dev); 289 else { 290 #ifdef CONFIG_CHELSIO_T4_DCB 291 if (cxgb4_dcb_enabled(dev)) { 292 cxgb4_dcb_reset(dev); 293 dcb_tx_queue_prio_enable(dev, false); 294 } 295 #endif /* CONFIG_CHELSIO_T4_DCB */ 296 netif_carrier_off(dev); 297 } 298 299 link_report(dev); 300 } 301 } 302 303 void t4_os_portmod_changed(struct adapter *adap, int port_id) 304 { 305 static const char *mod_str[] = { 306 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 307 }; 308 309 struct net_device *dev = adap->port[port_id]; 310 struct port_info *pi = netdev_priv(dev); 311 312 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 313 netdev_info(dev, "port module unplugged\n"); 314 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 315 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]); 316 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 317 netdev_info(dev, "%s: unsupported port module inserted\n", 318 dev->name); 319 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 320 netdev_info(dev, "%s: unknown port module inserted\n", 321 dev->name); 322 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 323 netdev_info(dev, "%s: transceiver module error\n", dev->name); 324 else 325 netdev_info(dev, "%s: unknown module type %d inserted\n", 326 dev->name, pi->mod_type); 327 328 /* If the interface is running, then we'll need any "sticky" Link 329 * Parameters redone with a new Transceiver Module. 330 */ 331 pi->link_cfg.redo_l1cfg = netif_running(dev); 332 } 333 334 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ 335 module_param(dbfifo_int_thresh, int, 0644); 336 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); 337 338 /* 339 * usecs to sleep while draining the dbfifo 340 */ 341 static int dbfifo_drain_delay = 1000; 342 module_param(dbfifo_drain_delay, int, 0644); 343 MODULE_PARM_DESC(dbfifo_drain_delay, 344 "usecs to sleep while draining the dbfifo"); 345 346 static inline int cxgb4_set_addr_hash(struct port_info *pi) 347 { 348 struct adapter *adap = pi->adapter; 349 u64 vec = 0; 350 bool ucast = false; 351 struct hash_mac_addr *entry; 352 353 /* Calculate the hash vector for the updated list and program it */ 354 list_for_each_entry(entry, &adap->mac_hlist, list) { 355 ucast |= is_unicast_ether_addr(entry->addr); 356 vec |= (1ULL << hash_mac_addr(entry->addr)); 357 } 358 return t4_set_addr_hash(adap, adap->mbox, pi->viid, ucast, 359 vec, false); 360 } 361 362 static int cxgb4_mac_sync(struct net_device *netdev, const u8 *mac_addr) 363 { 364 struct port_info *pi = netdev_priv(netdev); 365 struct adapter *adap = pi->adapter; 366 int ret; 367 u64 mhash = 0; 368 u64 uhash = 0; 369 bool free = false; 370 bool ucast = is_unicast_ether_addr(mac_addr); 371 const u8 *maclist[1] = {mac_addr}; 372 struct hash_mac_addr *new_entry; 373 374 ret = t4_alloc_mac_filt(adap, adap->mbox, pi->viid, free, 1, maclist, 375 NULL, ucast ? &uhash : &mhash, false); 376 if (ret < 0) 377 goto out; 378 /* if hash != 0, then add the addr to hash addr list 379 * so on the end we will calculate the hash for the 380 * list and program it 381 */ 382 if (uhash || mhash) { 383 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC); 384 if (!new_entry) 385 return -ENOMEM; 386 ether_addr_copy(new_entry->addr, mac_addr); 387 list_add_tail(&new_entry->list, &adap->mac_hlist); 388 ret = cxgb4_set_addr_hash(pi); 389 } 390 out: 391 return ret < 0 ? ret : 0; 392 } 393 394 static int cxgb4_mac_unsync(struct net_device *netdev, const u8 *mac_addr) 395 { 396 struct port_info *pi = netdev_priv(netdev); 397 struct adapter *adap = pi->adapter; 398 int ret; 399 const u8 *maclist[1] = {mac_addr}; 400 struct hash_mac_addr *entry, *tmp; 401 402 /* If the MAC address to be removed is in the hash addr 403 * list, delete it from the list and update hash vector 404 */ 405 list_for_each_entry_safe(entry, tmp, &adap->mac_hlist, list) { 406 if (ether_addr_equal(entry->addr, mac_addr)) { 407 list_del(&entry->list); 408 kfree(entry); 409 return cxgb4_set_addr_hash(pi); 410 } 411 } 412 413 ret = t4_free_mac_filt(adap, adap->mbox, pi->viid, 1, maclist, false); 414 return ret < 0 ? -EINVAL : 0; 415 } 416 417 /* 418 * Set Rx properties of a port, such as promiscruity, address filters, and MTU. 419 * If @mtu is -1 it is left unchanged. 420 */ 421 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok) 422 { 423 struct port_info *pi = netdev_priv(dev); 424 struct adapter *adapter = pi->adapter; 425 426 __dev_uc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 427 __dev_mc_sync(dev, cxgb4_mac_sync, cxgb4_mac_unsync); 428 429 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, 430 (dev->flags & IFF_PROMISC) ? 1 : 0, 431 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1, 432 sleep_ok); 433 } 434 435 /** 436 * cxgb4_change_mac - Update match filter for a MAC address. 437 * @pi: the port_info 438 * @viid: the VI id 439 * @tcam_idx: TCAM index of existing filter for old value of MAC address, 440 * or -1 441 * @addr: the new MAC address value 442 * @persist: whether a new MAC allocation should be persistent 443 * @add_smt: if true also add the address to the HW SMT 444 * 445 * Modifies an MPS filter and sets it to the new MAC address if 446 * @tcam_idx >= 0, or adds the MAC address to a new filter if 447 * @tcam_idx < 0. In the latter case the address is added persistently 448 * if @persist is %true. 449 * Addresses are programmed to hash region, if tcam runs out of entries. 450 * 451 */ 452 static int cxgb4_change_mac(struct port_info *pi, unsigned int viid, 453 int *tcam_idx, const u8 *addr, bool persist, 454 u8 *smt_idx) 455 { 456 struct adapter *adapter = pi->adapter; 457 struct hash_mac_addr *entry, *new_entry; 458 int ret; 459 460 ret = t4_change_mac(adapter, adapter->mbox, viid, 461 *tcam_idx, addr, persist, smt_idx); 462 /* We ran out of TCAM entries. try programming hash region. */ 463 if (ret == -ENOMEM) { 464 /* If the MAC address to be updated is in the hash addr 465 * list, update it from the list 466 */ 467 list_for_each_entry(entry, &adapter->mac_hlist, list) { 468 if (entry->iface_mac) { 469 ether_addr_copy(entry->addr, addr); 470 goto set_hash; 471 } 472 } 473 new_entry = kzalloc(sizeof(*new_entry), GFP_KERNEL); 474 if (!new_entry) 475 return -ENOMEM; 476 ether_addr_copy(new_entry->addr, addr); 477 new_entry->iface_mac = true; 478 list_add_tail(&new_entry->list, &adapter->mac_hlist); 479 set_hash: 480 ret = cxgb4_set_addr_hash(pi); 481 } else if (ret >= 0) { 482 *tcam_idx = ret; 483 ret = 0; 484 } 485 486 return ret; 487 } 488 489 /* 490 * link_start - enable a port 491 * @dev: the port to enable 492 * 493 * Performs the MAC and PHY actions needed to enable a port. 494 */ 495 static int link_start(struct net_device *dev) 496 { 497 int ret; 498 struct port_info *pi = netdev_priv(dev); 499 unsigned int mb = pi->adapter->pf; 500 501 /* 502 * We do not set address filters and promiscuity here, the stack does 503 * that step explicitly. 504 */ 505 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1, 506 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true); 507 if (ret == 0) 508 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt, 509 dev->dev_addr, true, &pi->smt_idx); 510 if (ret == 0) 511 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan, 512 &pi->link_cfg); 513 if (ret == 0) { 514 local_bh_disable(); 515 ret = t4_enable_pi_params(pi->adapter, mb, pi, true, 516 true, CXGB4_DCB_ENABLED); 517 local_bh_enable(); 518 } 519 520 return ret; 521 } 522 523 #ifdef CONFIG_CHELSIO_T4_DCB 524 /* Handle a Data Center Bridging update message from the firmware. */ 525 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd) 526 { 527 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid)); 528 struct net_device *dev = adap->port[adap->chan_map[port]]; 529 int old_dcb_enabled = cxgb4_dcb_enabled(dev); 530 int new_dcb_enabled; 531 532 cxgb4_dcb_handle_fw_update(adap, pcmd); 533 new_dcb_enabled = cxgb4_dcb_enabled(dev); 534 535 /* If the DCB has become enabled or disabled on the port then we're 536 * going to need to set up/tear down DCB Priority parameters for the 537 * TX Queues associated with the port. 538 */ 539 if (new_dcb_enabled != old_dcb_enabled) 540 dcb_tx_queue_prio_enable(dev, new_dcb_enabled); 541 } 542 #endif /* CONFIG_CHELSIO_T4_DCB */ 543 544 /* Response queue handler for the FW event queue. 545 */ 546 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 547 const struct pkt_gl *gl) 548 { 549 u8 opcode = ((const struct rss_header *)rsp)->opcode; 550 551 rsp++; /* skip RSS header */ 552 553 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 554 */ 555 if (unlikely(opcode == CPL_FW4_MSG && 556 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) { 557 rsp++; 558 opcode = ((const struct rss_header *)rsp)->opcode; 559 rsp++; 560 if (opcode != CPL_SGE_EGR_UPDATE) { 561 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n" 562 , opcode); 563 goto out; 564 } 565 } 566 567 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 568 const struct cpl_sge_egr_update *p = (void *)rsp; 569 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid)); 570 struct sge_txq *txq; 571 572 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start]; 573 txq->restarts++; 574 if (txq->q_type == CXGB4_TXQ_ETH) { 575 struct sge_eth_txq *eq; 576 577 eq = container_of(txq, struct sge_eth_txq, q); 578 t4_sge_eth_txq_egress_update(q->adap, eq, -1); 579 } else { 580 struct sge_uld_txq *oq; 581 582 oq = container_of(txq, struct sge_uld_txq, q); 583 tasklet_schedule(&oq->qresume_tsk); 584 } 585 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 586 const struct cpl_fw6_msg *p = (void *)rsp; 587 588 #ifdef CONFIG_CHELSIO_T4_DCB 589 const struct fw_port_cmd *pcmd = (const void *)p->data; 590 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid)); 591 unsigned int action = 592 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16)); 593 594 if (cmd == FW_PORT_CMD && 595 (action == FW_PORT_ACTION_GET_PORT_INFO || 596 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 597 int port = FW_PORT_CMD_PORTID_G( 598 be32_to_cpu(pcmd->op_to_portid)); 599 struct net_device *dev; 600 int dcbxdis, state_input; 601 602 dev = q->adap->port[q->adap->chan_map[port]]; 603 dcbxdis = (action == FW_PORT_ACTION_GET_PORT_INFO 604 ? !!(pcmd->u.info.dcbxdis_pkd & FW_PORT_CMD_DCBXDIS_F) 605 : !!(be32_to_cpu(pcmd->u.info32.lstatus32_to_cbllen32) 606 & FW_PORT_CMD_DCBXDIS32_F)); 607 state_input = (dcbxdis 608 ? CXGB4_DCB_INPUT_FW_DISABLED 609 : CXGB4_DCB_INPUT_FW_ENABLED); 610 611 cxgb4_dcb_state_fsm(dev, state_input); 612 } 613 614 if (cmd == FW_PORT_CMD && 615 action == FW_PORT_ACTION_L2_DCB_CFG) 616 dcb_rpl(q->adap, pcmd); 617 else 618 #endif 619 if (p->type == 0) 620 t4_handle_fw_rpl(q->adap, p->data); 621 } else if (opcode == CPL_L2T_WRITE_RPL) { 622 const struct cpl_l2t_write_rpl *p = (void *)rsp; 623 624 do_l2t_write_rpl(q->adap, p); 625 } else if (opcode == CPL_SMT_WRITE_RPL) { 626 const struct cpl_smt_write_rpl *p = (void *)rsp; 627 628 do_smt_write_rpl(q->adap, p); 629 } else if (opcode == CPL_SET_TCB_RPL) { 630 const struct cpl_set_tcb_rpl *p = (void *)rsp; 631 632 filter_rpl(q->adap, p); 633 } else if (opcode == CPL_ACT_OPEN_RPL) { 634 const struct cpl_act_open_rpl *p = (void *)rsp; 635 636 hash_filter_rpl(q->adap, p); 637 } else if (opcode == CPL_ABORT_RPL_RSS) { 638 const struct cpl_abort_rpl_rss *p = (void *)rsp; 639 640 hash_del_filter_rpl(q->adap, p); 641 } else if (opcode == CPL_SRQ_TABLE_RPL) { 642 const struct cpl_srq_table_rpl *p = (void *)rsp; 643 644 do_srq_table_rpl(q->adap, p); 645 } else 646 dev_err(q->adap->pdev_dev, 647 "unexpected CPL %#x on FW event queue\n", opcode); 648 out: 649 return 0; 650 } 651 652 static void disable_msi(struct adapter *adapter) 653 { 654 if (adapter->flags & CXGB4_USING_MSIX) { 655 pci_disable_msix(adapter->pdev); 656 adapter->flags &= ~CXGB4_USING_MSIX; 657 } else if (adapter->flags & CXGB4_USING_MSI) { 658 pci_disable_msi(adapter->pdev); 659 adapter->flags &= ~CXGB4_USING_MSI; 660 } 661 } 662 663 /* 664 * Interrupt handler for non-data events used with MSI-X. 665 */ 666 static irqreturn_t t4_nondata_intr(int irq, void *cookie) 667 { 668 struct adapter *adap = cookie; 669 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A)); 670 671 if (v & PFSW_F) { 672 adap->swintr = 1; 673 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v); 674 } 675 if (adap->flags & CXGB4_MASTER_PF) 676 t4_slow_intr_handler(adap); 677 return IRQ_HANDLED; 678 } 679 680 /* 681 * Name the MSI-X interrupts. 682 */ 683 static void name_msix_vecs(struct adapter *adap) 684 { 685 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc); 686 687 /* non-data interrupts */ 688 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name); 689 690 /* FW events */ 691 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq", 692 adap->port[0]->name); 693 694 /* Ethernet queues */ 695 for_each_port(adap, j) { 696 struct net_device *d = adap->port[j]; 697 const struct port_info *pi = netdev_priv(d); 698 699 for (i = 0; i < pi->nqsets; i++, msi_idx++) 700 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d", 701 d->name, i); 702 } 703 } 704 705 int cxgb4_set_msix_aff(struct adapter *adap, unsigned short vec, 706 cpumask_var_t *aff_mask, int idx) 707 { 708 int rv; 709 710 if (!zalloc_cpumask_var(aff_mask, GFP_KERNEL)) { 711 dev_err(adap->pdev_dev, "alloc_cpumask_var failed\n"); 712 return -ENOMEM; 713 } 714 715 cpumask_set_cpu(cpumask_local_spread(idx, dev_to_node(adap->pdev_dev)), 716 *aff_mask); 717 718 rv = irq_set_affinity_hint(vec, *aff_mask); 719 if (rv) 720 dev_warn(adap->pdev_dev, 721 "irq_set_affinity_hint %u failed %d\n", 722 vec, rv); 723 724 return 0; 725 } 726 727 void cxgb4_clear_msix_aff(unsigned short vec, cpumask_var_t aff_mask) 728 { 729 irq_set_affinity_hint(vec, NULL); 730 free_cpumask_var(aff_mask); 731 } 732 733 static int request_msix_queue_irqs(struct adapter *adap) 734 { 735 struct sge *s = &adap->sge; 736 struct msix_info *minfo; 737 int err, ethqidx; 738 int msi_index = 2; 739 740 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, 741 adap->msix_info[1].desc, &s->fw_evtq); 742 if (err) 743 return err; 744 745 for_each_ethrxq(s, ethqidx) { 746 minfo = &adap->msix_info[msi_index]; 747 err = request_irq(minfo->vec, 748 t4_sge_intr_msix, 0, 749 minfo->desc, 750 &s->ethrxq[ethqidx].rspq); 751 if (err) 752 goto unwind; 753 754 cxgb4_set_msix_aff(adap, minfo->vec, 755 &minfo->aff_mask, ethqidx); 756 msi_index++; 757 } 758 return 0; 759 760 unwind: 761 while (--ethqidx >= 0) { 762 msi_index--; 763 minfo = &adap->msix_info[msi_index]; 764 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 765 free_irq(minfo->vec, &s->ethrxq[ethqidx].rspq); 766 } 767 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 768 return err; 769 } 770 771 static void free_msix_queue_irqs(struct adapter *adap) 772 { 773 struct sge *s = &adap->sge; 774 struct msix_info *minfo; 775 int i, msi_index = 2; 776 777 free_irq(adap->msix_info[1].vec, &s->fw_evtq); 778 for_each_ethrxq(s, i) { 779 minfo = &adap->msix_info[msi_index++]; 780 cxgb4_clear_msix_aff(minfo->vec, minfo->aff_mask); 781 free_irq(minfo->vec, &s->ethrxq[i].rspq); 782 } 783 } 784 785 static int setup_ppod_edram(struct adapter *adap) 786 { 787 unsigned int param, val; 788 int ret; 789 790 /* Driver sends FW_PARAMS_PARAM_DEV_PPOD_EDRAM read command to check 791 * if firmware supports ppod edram feature or not. If firmware 792 * returns 1, then driver can enable this feature by sending 793 * FW_PARAMS_PARAM_DEV_PPOD_EDRAM write command with value 1 to 794 * enable ppod edram feature. 795 */ 796 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 797 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PPOD_EDRAM)); 798 799 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 800 if (ret < 0) { 801 dev_warn(adap->pdev_dev, 802 "querying PPOD_EDRAM support failed: %d\n", 803 ret); 804 return -1; 805 } 806 807 if (val != 1) 808 return -1; 809 810 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 811 if (ret < 0) { 812 dev_err(adap->pdev_dev, 813 "setting PPOD_EDRAM failed: %d\n", ret); 814 return -1; 815 } 816 return 0; 817 } 818 819 /** 820 * cxgb4_write_rss - write the RSS table for a given port 821 * @pi: the port 822 * @queues: array of queue indices for RSS 823 * 824 * Sets up the portion of the HW RSS table for the port's VI to distribute 825 * packets to the Rx queues in @queues. 826 * Should never be called before setting up sge eth rx queues 827 */ 828 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 829 { 830 u16 *rss; 831 int i, err; 832 struct adapter *adapter = pi->adapter; 833 const struct sge_eth_rxq *rxq; 834 835 rxq = &adapter->sge.ethrxq[pi->first_qset]; 836 rss = kmalloc_array(pi->rss_size, sizeof(u16), GFP_KERNEL); 837 if (!rss) 838 return -ENOMEM; 839 840 /* map the queue indices to queue ids */ 841 for (i = 0; i < pi->rss_size; i++, queues++) 842 rss[i] = rxq[*queues].rspq.abs_id; 843 844 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 845 pi->rss_size, rss, pi->rss_size); 846 /* If Tunnel All Lookup isn't specified in the global RSS 847 * Configuration, then we need to specify a default Ingress 848 * Queue for any ingress packets which aren't hashed. We'll 849 * use our first ingress queue ... 850 */ 851 if (!err) 852 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 853 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F | 854 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F | 855 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F | 856 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F | 857 FW_RSS_VI_CONFIG_CMD_UDPEN_F, 858 rss[0]); 859 kfree(rss); 860 return err; 861 } 862 863 /** 864 * setup_rss - configure RSS 865 * @adap: the adapter 866 * 867 * Sets up RSS for each port. 868 */ 869 static int setup_rss(struct adapter *adap) 870 { 871 int i, j, err; 872 873 for_each_port(adap, i) { 874 const struct port_info *pi = adap2pinfo(adap, i); 875 876 /* Fill default values with equal distribution */ 877 for (j = 0; j < pi->rss_size; j++) 878 pi->rss[j] = j % pi->nqsets; 879 880 err = cxgb4_write_rss(pi, pi->rss); 881 if (err) 882 return err; 883 } 884 return 0; 885 } 886 887 /* 888 * Return the channel of the ingress queue with the given qid. 889 */ 890 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid) 891 { 892 qid -= p->ingr_start; 893 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan; 894 } 895 896 /* 897 * Wait until all NAPI handlers are descheduled. 898 */ 899 static void quiesce_rx(struct adapter *adap) 900 { 901 int i; 902 903 for (i = 0; i < adap->sge.ingr_sz; i++) { 904 struct sge_rspq *q = adap->sge.ingr_map[i]; 905 906 if (q && q->handler) 907 napi_disable(&q->napi); 908 } 909 } 910 911 /* Disable interrupt and napi handler */ 912 static void disable_interrupts(struct adapter *adap) 913 { 914 if (adap->flags & CXGB4_FULL_INIT_DONE) { 915 t4_intr_disable(adap); 916 if (adap->flags & CXGB4_USING_MSIX) { 917 free_msix_queue_irqs(adap); 918 free_irq(adap->msix_info[0].vec, adap); 919 } else { 920 free_irq(adap->pdev->irq, adap); 921 } 922 quiesce_rx(adap); 923 } 924 } 925 926 /* 927 * Enable NAPI scheduling and interrupt generation for all Rx queues. 928 */ 929 static void enable_rx(struct adapter *adap) 930 { 931 int i; 932 933 for (i = 0; i < adap->sge.ingr_sz; i++) { 934 struct sge_rspq *q = adap->sge.ingr_map[i]; 935 936 if (!q) 937 continue; 938 if (q->handler) 939 napi_enable(&q->napi); 940 941 /* 0-increment GTS to start the timer and enable interrupts */ 942 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A), 943 SEINTARM_V(q->intr_params) | 944 INGRESSQID_V(q->cntxt_id)); 945 } 946 } 947 948 949 static int setup_fw_sge_queues(struct adapter *adap) 950 { 951 struct sge *s = &adap->sge; 952 int err = 0; 953 954 bitmap_zero(s->starving_fl, s->egr_sz); 955 bitmap_zero(s->txq_maperr, s->egr_sz); 956 957 if (adap->flags & CXGB4_USING_MSIX) 958 adap->msi_idx = 1; /* vector 0 is for non-queue interrupts */ 959 else { 960 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0, 961 NULL, NULL, NULL, -1); 962 if (err) 963 return err; 964 adap->msi_idx = -((int)s->intrq.abs_id + 1); 965 } 966 967 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0], 968 adap->msi_idx, NULL, fwevtq_handler, NULL, -1); 969 return err; 970 } 971 972 /** 973 * setup_sge_queues - configure SGE Tx/Rx/response queues 974 * @adap: the adapter 975 * 976 * Determines how many sets of SGE queues to use and initializes them. 977 * We support multiple queue sets per port if we have MSI-X, otherwise 978 * just one queue set per port. 979 */ 980 static int setup_sge_queues(struct adapter *adap) 981 { 982 int err, i, j; 983 struct sge *s = &adap->sge; 984 struct sge_uld_rxq_info *rxq_info = NULL; 985 unsigned int cmplqid = 0; 986 987 if (is_uld(adap)) 988 rxq_info = s->uld_rxq_info[CXGB4_ULD_RDMA]; 989 990 for_each_port(adap, i) { 991 struct net_device *dev = adap->port[i]; 992 struct port_info *pi = netdev_priv(dev); 993 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset]; 994 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset]; 995 996 for (j = 0; j < pi->nqsets; j++, q++) { 997 if (adap->msi_idx > 0) 998 adap->msi_idx++; 999 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, 1000 adap->msi_idx, &q->fl, 1001 t4_ethrx_handler, 1002 NULL, 1003 t4_get_tp_ch_map(adap, 1004 pi->tx_chan)); 1005 if (err) 1006 goto freeout; 1007 q->rspq.idx = j; 1008 memset(&q->stats, 0, sizeof(q->stats)); 1009 } 1010 1011 q = &s->ethrxq[pi->first_qset]; 1012 for (j = 0; j < pi->nqsets; j++, t++, q++) { 1013 err = t4_sge_alloc_eth_txq(adap, t, dev, 1014 netdev_get_tx_queue(dev, j), 1015 q->rspq.cntxt_id, 1016 !!(adap->flags & CXGB4_SGE_DBQ_TIMER)); 1017 if (err) 1018 goto freeout; 1019 } 1020 } 1021 1022 for_each_port(adap, i) { 1023 /* Note that cmplqid below is 0 if we don't 1024 * have RDMA queues, and that's the right value. 1025 */ 1026 if (rxq_info) 1027 cmplqid = rxq_info->uldrxq[i].rspq.cntxt_id; 1028 1029 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i], 1030 s->fw_evtq.cntxt_id, cmplqid); 1031 if (err) 1032 goto freeout; 1033 } 1034 1035 if (!is_t4(adap->params.chip)) { 1036 err = t4_sge_alloc_eth_txq(adap, &s->ptptxq, adap->port[0], 1037 netdev_get_tx_queue(adap->port[0], 0) 1038 , s->fw_evtq.cntxt_id, false); 1039 if (err) 1040 goto freeout; 1041 } 1042 1043 t4_write_reg(adap, is_t4(adap->params.chip) ? 1044 MPS_TRC_RSS_CONTROL_A : 1045 MPS_T5_TRC_RSS_CONTROL_A, 1046 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) | 1047 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id)); 1048 return 0; 1049 freeout: 1050 dev_err(adap->pdev_dev, "Can't allocate queues, err=%d\n", -err); 1051 t4_free_sge_resources(adap); 1052 return err; 1053 } 1054 1055 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb, 1056 struct net_device *sb_dev) 1057 { 1058 int txq; 1059 1060 #ifdef CONFIG_CHELSIO_T4_DCB 1061 /* If a Data Center Bridging has been successfully negotiated on this 1062 * link then we'll use the skb's priority to map it to a TX Queue. 1063 * The skb's priority is determined via the VLAN Tag Priority Code 1064 * Point field. 1065 */ 1066 if (cxgb4_dcb_enabled(dev) && !is_kdump_kernel()) { 1067 u16 vlan_tci; 1068 int err; 1069 1070 err = vlan_get_tag(skb, &vlan_tci); 1071 if (unlikely(err)) { 1072 if (net_ratelimit()) 1073 netdev_warn(dev, 1074 "TX Packet without VLAN Tag on DCB Link\n"); 1075 txq = 0; 1076 } else { 1077 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; 1078 #ifdef CONFIG_CHELSIO_T4_FCOE 1079 if (skb->protocol == htons(ETH_P_FCOE)) 1080 txq = skb->priority & 0x7; 1081 #endif /* CONFIG_CHELSIO_T4_FCOE */ 1082 } 1083 return txq; 1084 } 1085 #endif /* CONFIG_CHELSIO_T4_DCB */ 1086 1087 if (select_queue) { 1088 txq = (skb_rx_queue_recorded(skb) 1089 ? skb_get_rx_queue(skb) 1090 : smp_processor_id()); 1091 1092 while (unlikely(txq >= dev->real_num_tx_queues)) 1093 txq -= dev->real_num_tx_queues; 1094 1095 return txq; 1096 } 1097 1098 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 1099 } 1100 1101 static int closest_timer(const struct sge *s, int time) 1102 { 1103 int i, delta, match = 0, min_delta = INT_MAX; 1104 1105 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 1106 delta = time - s->timer_val[i]; 1107 if (delta < 0) 1108 delta = -delta; 1109 if (delta < min_delta) { 1110 min_delta = delta; 1111 match = i; 1112 } 1113 } 1114 return match; 1115 } 1116 1117 static int closest_thres(const struct sge *s, int thres) 1118 { 1119 int i, delta, match = 0, min_delta = INT_MAX; 1120 1121 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 1122 delta = thres - s->counter_val[i]; 1123 if (delta < 0) 1124 delta = -delta; 1125 if (delta < min_delta) { 1126 min_delta = delta; 1127 match = i; 1128 } 1129 } 1130 return match; 1131 } 1132 1133 /** 1134 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 1135 * @q: the Rx queue 1136 * @us: the hold-off time in us, or 0 to disable timer 1137 * @cnt: the hold-off packet count, or 0 to disable counter 1138 * 1139 * Sets an Rx queue's interrupt hold-off time and packet count. At least 1140 * one of the two needs to be enabled for the queue to generate interrupts. 1141 */ 1142 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, 1143 unsigned int us, unsigned int cnt) 1144 { 1145 struct adapter *adap = q->adap; 1146 1147 if ((us | cnt) == 0) 1148 cnt = 1; 1149 1150 if (cnt) { 1151 int err; 1152 u32 v, new_idx; 1153 1154 new_idx = closest_thres(&adap->sge, cnt); 1155 if (q->desc && q->pktcnt_idx != new_idx) { 1156 /* the queue has already been created, update it */ 1157 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) | 1158 FW_PARAMS_PARAM_X_V( 1159 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 1160 FW_PARAMS_PARAM_YZ_V(q->cntxt_id); 1161 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 1162 &v, &new_idx); 1163 if (err) 1164 return err; 1165 } 1166 q->pktcnt_idx = new_idx; 1167 } 1168 1169 us = us == 0 ? 6 : closest_timer(&adap->sge, us); 1170 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0); 1171 return 0; 1172 } 1173 1174 static int cxgb_set_features(struct net_device *dev, netdev_features_t features) 1175 { 1176 const struct port_info *pi = netdev_priv(dev); 1177 netdev_features_t changed = dev->features ^ features; 1178 int err; 1179 1180 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX)) 1181 return 0; 1182 1183 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1, 1184 -1, -1, -1, 1185 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true); 1186 if (unlikely(err)) 1187 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX; 1188 return err; 1189 } 1190 1191 static int setup_debugfs(struct adapter *adap) 1192 { 1193 if (IS_ERR_OR_NULL(adap->debugfs_root)) 1194 return -1; 1195 1196 #ifdef CONFIG_DEBUG_FS 1197 t4_setup_debugfs(adap); 1198 #endif 1199 return 0; 1200 } 1201 1202 /* 1203 * upper-layer driver support 1204 */ 1205 1206 /* 1207 * Allocate an active-open TID and set it to the supplied value. 1208 */ 1209 int cxgb4_alloc_atid(struct tid_info *t, void *data) 1210 { 1211 int atid = -1; 1212 1213 spin_lock_bh(&t->atid_lock); 1214 if (t->afree) { 1215 union aopen_entry *p = t->afree; 1216 1217 atid = (p - t->atid_tab) + t->atid_base; 1218 t->afree = p->next; 1219 p->data = data; 1220 t->atids_in_use++; 1221 } 1222 spin_unlock_bh(&t->atid_lock); 1223 return atid; 1224 } 1225 EXPORT_SYMBOL(cxgb4_alloc_atid); 1226 1227 /* 1228 * Release an active-open TID. 1229 */ 1230 void cxgb4_free_atid(struct tid_info *t, unsigned int atid) 1231 { 1232 union aopen_entry *p = &t->atid_tab[atid - t->atid_base]; 1233 1234 spin_lock_bh(&t->atid_lock); 1235 p->next = t->afree; 1236 t->afree = p; 1237 t->atids_in_use--; 1238 spin_unlock_bh(&t->atid_lock); 1239 } 1240 EXPORT_SYMBOL(cxgb4_free_atid); 1241 1242 /* 1243 * Allocate a server TID and set it to the supplied value. 1244 */ 1245 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data) 1246 { 1247 int stid; 1248 1249 spin_lock_bh(&t->stid_lock); 1250 if (family == PF_INET) { 1251 stid = find_first_zero_bit(t->stid_bmap, t->nstids); 1252 if (stid < t->nstids) 1253 __set_bit(stid, t->stid_bmap); 1254 else 1255 stid = -1; 1256 } else { 1257 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1); 1258 if (stid < 0) 1259 stid = -1; 1260 } 1261 if (stid >= 0) { 1262 t->stid_tab[stid].data = data; 1263 stid += t->stid_base; 1264 /* IPv6 requires max of 520 bits or 16 cells in TCAM 1265 * This is equivalent to 4 TIDs. With CLIP enabled it 1266 * needs 2 TIDs. 1267 */ 1268 if (family == PF_INET6) { 1269 t->stids_in_use += 2; 1270 t->v6_stids_in_use += 2; 1271 } else { 1272 t->stids_in_use++; 1273 } 1274 } 1275 spin_unlock_bh(&t->stid_lock); 1276 return stid; 1277 } 1278 EXPORT_SYMBOL(cxgb4_alloc_stid); 1279 1280 /* Allocate a server filter TID and set it to the supplied value. 1281 */ 1282 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data) 1283 { 1284 int stid; 1285 1286 spin_lock_bh(&t->stid_lock); 1287 if (family == PF_INET) { 1288 stid = find_next_zero_bit(t->stid_bmap, 1289 t->nstids + t->nsftids, t->nstids); 1290 if (stid < (t->nstids + t->nsftids)) 1291 __set_bit(stid, t->stid_bmap); 1292 else 1293 stid = -1; 1294 } else { 1295 stid = -1; 1296 } 1297 if (stid >= 0) { 1298 t->stid_tab[stid].data = data; 1299 stid -= t->nstids; 1300 stid += t->sftid_base; 1301 t->sftids_in_use++; 1302 } 1303 spin_unlock_bh(&t->stid_lock); 1304 return stid; 1305 } 1306 EXPORT_SYMBOL(cxgb4_alloc_sftid); 1307 1308 /* Release a server TID. 1309 */ 1310 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family) 1311 { 1312 /* Is it a server filter TID? */ 1313 if (t->nsftids && (stid >= t->sftid_base)) { 1314 stid -= t->sftid_base; 1315 stid += t->nstids; 1316 } else { 1317 stid -= t->stid_base; 1318 } 1319 1320 spin_lock_bh(&t->stid_lock); 1321 if (family == PF_INET) 1322 __clear_bit(stid, t->stid_bmap); 1323 else 1324 bitmap_release_region(t->stid_bmap, stid, 1); 1325 t->stid_tab[stid].data = NULL; 1326 if (stid < t->nstids) { 1327 if (family == PF_INET6) { 1328 t->stids_in_use -= 2; 1329 t->v6_stids_in_use -= 2; 1330 } else { 1331 t->stids_in_use--; 1332 } 1333 } else { 1334 t->sftids_in_use--; 1335 } 1336 1337 spin_unlock_bh(&t->stid_lock); 1338 } 1339 EXPORT_SYMBOL(cxgb4_free_stid); 1340 1341 /* 1342 * Populate a TID_RELEASE WR. Caller must properly size the skb. 1343 */ 1344 static void mk_tid_release(struct sk_buff *skb, unsigned int chan, 1345 unsigned int tid) 1346 { 1347 struct cpl_tid_release *req; 1348 1349 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan); 1350 req = __skb_put(skb, sizeof(*req)); 1351 INIT_TP_WR(req, tid); 1352 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid)); 1353 } 1354 1355 /* 1356 * Queue a TID release request and if necessary schedule a work queue to 1357 * process it. 1358 */ 1359 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan, 1360 unsigned int tid) 1361 { 1362 void **p = &t->tid_tab[tid]; 1363 struct adapter *adap = container_of(t, struct adapter, tids); 1364 1365 spin_lock_bh(&adap->tid_release_lock); 1366 *p = adap->tid_release_head; 1367 /* Low 2 bits encode the Tx channel number */ 1368 adap->tid_release_head = (void **)((uintptr_t)p | chan); 1369 if (!adap->tid_release_task_busy) { 1370 adap->tid_release_task_busy = true; 1371 queue_work(adap->workq, &adap->tid_release_task); 1372 } 1373 spin_unlock_bh(&adap->tid_release_lock); 1374 } 1375 1376 /* 1377 * Process the list of pending TID release requests. 1378 */ 1379 static void process_tid_release_list(struct work_struct *work) 1380 { 1381 struct sk_buff *skb; 1382 struct adapter *adap; 1383 1384 adap = container_of(work, struct adapter, tid_release_task); 1385 1386 spin_lock_bh(&adap->tid_release_lock); 1387 while (adap->tid_release_head) { 1388 void **p = adap->tid_release_head; 1389 unsigned int chan = (uintptr_t)p & 3; 1390 p = (void *)p - chan; 1391 1392 adap->tid_release_head = *p; 1393 *p = NULL; 1394 spin_unlock_bh(&adap->tid_release_lock); 1395 1396 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release), 1397 GFP_KERNEL))) 1398 schedule_timeout_uninterruptible(1); 1399 1400 mk_tid_release(skb, chan, p - adap->tids.tid_tab); 1401 t4_ofld_send(adap, skb); 1402 spin_lock_bh(&adap->tid_release_lock); 1403 } 1404 adap->tid_release_task_busy = false; 1405 spin_unlock_bh(&adap->tid_release_lock); 1406 } 1407 1408 /* 1409 * Release a TID and inform HW. If we are unable to allocate the release 1410 * message we defer to a work queue. 1411 */ 1412 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid, 1413 unsigned short family) 1414 { 1415 struct sk_buff *skb; 1416 struct adapter *adap = container_of(t, struct adapter, tids); 1417 1418 WARN_ON(tid >= t->ntids); 1419 1420 if (t->tid_tab[tid]) { 1421 t->tid_tab[tid] = NULL; 1422 atomic_dec(&t->conns_in_use); 1423 if (t->hash_base && (tid >= t->hash_base)) { 1424 if (family == AF_INET6) 1425 atomic_sub(2, &t->hash_tids_in_use); 1426 else 1427 atomic_dec(&t->hash_tids_in_use); 1428 } else { 1429 if (family == AF_INET6) 1430 atomic_sub(2, &t->tids_in_use); 1431 else 1432 atomic_dec(&t->tids_in_use); 1433 } 1434 } 1435 1436 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC); 1437 if (likely(skb)) { 1438 mk_tid_release(skb, chan, tid); 1439 t4_ofld_send(adap, skb); 1440 } else 1441 cxgb4_queue_tid_release(t, chan, tid); 1442 } 1443 EXPORT_SYMBOL(cxgb4_remove_tid); 1444 1445 /* 1446 * Allocate and initialize the TID tables. Returns 0 on success. 1447 */ 1448 static int tid_init(struct tid_info *t) 1449 { 1450 struct adapter *adap = container_of(t, struct adapter, tids); 1451 unsigned int max_ftids = t->nftids + t->nsftids; 1452 unsigned int natids = t->natids; 1453 unsigned int stid_bmap_size; 1454 unsigned int ftid_bmap_size; 1455 size_t size; 1456 1457 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids); 1458 ftid_bmap_size = BITS_TO_LONGS(t->nftids); 1459 size = t->ntids * sizeof(*t->tid_tab) + 1460 natids * sizeof(*t->atid_tab) + 1461 t->nstids * sizeof(*t->stid_tab) + 1462 t->nsftids * sizeof(*t->stid_tab) + 1463 stid_bmap_size * sizeof(long) + 1464 max_ftids * sizeof(*t->ftid_tab) + 1465 ftid_bmap_size * sizeof(long); 1466 1467 t->tid_tab = kvzalloc(size, GFP_KERNEL); 1468 if (!t->tid_tab) 1469 return -ENOMEM; 1470 1471 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids]; 1472 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids]; 1473 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids]; 1474 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size]; 1475 t->ftid_bmap = (unsigned long *)&t->ftid_tab[max_ftids]; 1476 spin_lock_init(&t->stid_lock); 1477 spin_lock_init(&t->atid_lock); 1478 spin_lock_init(&t->ftid_lock); 1479 1480 t->stids_in_use = 0; 1481 t->v6_stids_in_use = 0; 1482 t->sftids_in_use = 0; 1483 t->afree = NULL; 1484 t->atids_in_use = 0; 1485 atomic_set(&t->tids_in_use, 0); 1486 atomic_set(&t->conns_in_use, 0); 1487 atomic_set(&t->hash_tids_in_use, 0); 1488 1489 /* Setup the free list for atid_tab and clear the stid bitmap. */ 1490 if (natids) { 1491 while (--natids) 1492 t->atid_tab[natids - 1].next = &t->atid_tab[natids]; 1493 t->afree = t->atid_tab; 1494 } 1495 1496 if (is_offload(adap)) { 1497 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids); 1498 /* Reserve stid 0 for T4/T5 adapters */ 1499 if (!t->stid_base && 1500 CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 1501 __set_bit(0, t->stid_bmap); 1502 } 1503 1504 bitmap_zero(t->ftid_bmap, t->nftids); 1505 return 0; 1506 } 1507 1508 /** 1509 * cxgb4_create_server - create an IP server 1510 * @dev: the device 1511 * @stid: the server TID 1512 * @sip: local IP address to bind server to 1513 * @sport: the server's TCP port 1514 * @queue: queue to direct messages from this server to 1515 * 1516 * Create an IP server for the given port and address. 1517 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1518 */ 1519 int cxgb4_create_server(const struct net_device *dev, unsigned int stid, 1520 __be32 sip, __be16 sport, __be16 vlan, 1521 unsigned int queue) 1522 { 1523 unsigned int chan; 1524 struct sk_buff *skb; 1525 struct adapter *adap; 1526 struct cpl_pass_open_req *req; 1527 int ret; 1528 1529 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1530 if (!skb) 1531 return -ENOMEM; 1532 1533 adap = netdev2adap(dev); 1534 req = __skb_put(skb, sizeof(*req)); 1535 INIT_TP_WR(req, 0); 1536 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid)); 1537 req->local_port = sport; 1538 req->peer_port = htons(0); 1539 req->local_ip = sip; 1540 req->peer_ip = htonl(0); 1541 chan = rxq_to_chan(&adap->sge, queue); 1542 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1543 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1544 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1545 ret = t4_mgmt_tx(adap, skb); 1546 return net_xmit_eval(ret); 1547 } 1548 EXPORT_SYMBOL(cxgb4_create_server); 1549 1550 /* cxgb4_create_server6 - create an IPv6 server 1551 * @dev: the device 1552 * @stid: the server TID 1553 * @sip: local IPv6 address to bind server to 1554 * @sport: the server's TCP port 1555 * @queue: queue to direct messages from this server to 1556 * 1557 * Create an IPv6 server for the given port and address. 1558 * Returns <0 on error and one of the %NET_XMIT_* values on success. 1559 */ 1560 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid, 1561 const struct in6_addr *sip, __be16 sport, 1562 unsigned int queue) 1563 { 1564 unsigned int chan; 1565 struct sk_buff *skb; 1566 struct adapter *adap; 1567 struct cpl_pass_open_req6 *req; 1568 int ret; 1569 1570 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1571 if (!skb) 1572 return -ENOMEM; 1573 1574 adap = netdev2adap(dev); 1575 req = __skb_put(skb, sizeof(*req)); 1576 INIT_TP_WR(req, 0); 1577 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid)); 1578 req->local_port = sport; 1579 req->peer_port = htons(0); 1580 req->local_ip_hi = *(__be64 *)(sip->s6_addr); 1581 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8); 1582 req->peer_ip_hi = cpu_to_be64(0); 1583 req->peer_ip_lo = cpu_to_be64(0); 1584 chan = rxq_to_chan(&adap->sge, queue); 1585 req->opt0 = cpu_to_be64(TX_CHAN_V(chan)); 1586 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) | 1587 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue)); 1588 ret = t4_mgmt_tx(adap, skb); 1589 return net_xmit_eval(ret); 1590 } 1591 EXPORT_SYMBOL(cxgb4_create_server6); 1592 1593 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid, 1594 unsigned int queue, bool ipv6) 1595 { 1596 struct sk_buff *skb; 1597 struct adapter *adap; 1598 struct cpl_close_listsvr_req *req; 1599 int ret; 1600 1601 adap = netdev2adap(dev); 1602 1603 skb = alloc_skb(sizeof(*req), GFP_KERNEL); 1604 if (!skb) 1605 return -ENOMEM; 1606 1607 req = __skb_put(skb, sizeof(*req)); 1608 INIT_TP_WR(req, 0); 1609 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid)); 1610 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) : 1611 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue)); 1612 ret = t4_mgmt_tx(adap, skb); 1613 return net_xmit_eval(ret); 1614 } 1615 EXPORT_SYMBOL(cxgb4_remove_server); 1616 1617 /** 1618 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU 1619 * @mtus: the HW MTU table 1620 * @mtu: the target MTU 1621 * @idx: index of selected entry in the MTU table 1622 * 1623 * Returns the index and the value in the HW MTU table that is closest to 1624 * but does not exceed @mtu, unless @mtu is smaller than any value in the 1625 * table, in which case that smallest available value is selected. 1626 */ 1627 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu, 1628 unsigned int *idx) 1629 { 1630 unsigned int i = 0; 1631 1632 while (i < NMTUS - 1 && mtus[i + 1] <= mtu) 1633 ++i; 1634 if (idx) 1635 *idx = i; 1636 return mtus[i]; 1637 } 1638 EXPORT_SYMBOL(cxgb4_best_mtu); 1639 1640 /** 1641 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned 1642 * @mtus: the HW MTU table 1643 * @header_size: Header Size 1644 * @data_size_max: maximum Data Segment Size 1645 * @data_size_align: desired Data Segment Size Alignment (2^N) 1646 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL) 1647 * 1648 * Similar to cxgb4_best_mtu() but instead of searching the Hardware 1649 * MTU Table based solely on a Maximum MTU parameter, we break that 1650 * parameter up into a Header Size and Maximum Data Segment Size, and 1651 * provide a desired Data Segment Size Alignment. If we find an MTU in 1652 * the Hardware MTU Table which will result in a Data Segment Size with 1653 * the requested alignment _and_ that MTU isn't "too far" from the 1654 * closest MTU, then we'll return that rather than the closest MTU. 1655 */ 1656 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus, 1657 unsigned short header_size, 1658 unsigned short data_size_max, 1659 unsigned short data_size_align, 1660 unsigned int *mtu_idxp) 1661 { 1662 unsigned short max_mtu = header_size + data_size_max; 1663 unsigned short data_size_align_mask = data_size_align - 1; 1664 int mtu_idx, aligned_mtu_idx; 1665 1666 /* Scan the MTU Table till we find an MTU which is larger than our 1667 * Maximum MTU or we reach the end of the table. Along the way, 1668 * record the last MTU found, if any, which will result in a Data 1669 * Segment Length matching the requested alignment. 1670 */ 1671 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) { 1672 unsigned short data_size = mtus[mtu_idx] - header_size; 1673 1674 /* If this MTU minus the Header Size would result in a 1675 * Data Segment Size of the desired alignment, remember it. 1676 */ 1677 if ((data_size & data_size_align_mask) == 0) 1678 aligned_mtu_idx = mtu_idx; 1679 1680 /* If we're not at the end of the Hardware MTU Table and the 1681 * next element is larger than our Maximum MTU, drop out of 1682 * the loop. 1683 */ 1684 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu) 1685 break; 1686 } 1687 1688 /* If we fell out of the loop because we ran to the end of the table, 1689 * then we just have to use the last [largest] entry. 1690 */ 1691 if (mtu_idx == NMTUS) 1692 mtu_idx--; 1693 1694 /* If we found an MTU which resulted in the requested Data Segment 1695 * Length alignment and that's "not far" from the largest MTU which is 1696 * less than or equal to the maximum MTU, then use that. 1697 */ 1698 if (aligned_mtu_idx >= 0 && 1699 mtu_idx - aligned_mtu_idx <= 1) 1700 mtu_idx = aligned_mtu_idx; 1701 1702 /* If the caller has passed in an MTU Index pointer, pass the 1703 * MTU Index back. Return the MTU value. 1704 */ 1705 if (mtu_idxp) 1706 *mtu_idxp = mtu_idx; 1707 return mtus[mtu_idx]; 1708 } 1709 EXPORT_SYMBOL(cxgb4_best_aligned_mtu); 1710 1711 /** 1712 * cxgb4_port_chan - get the HW channel of a port 1713 * @dev: the net device for the port 1714 * 1715 * Return the HW Tx channel of the given port. 1716 */ 1717 unsigned int cxgb4_port_chan(const struct net_device *dev) 1718 { 1719 return netdev2pinfo(dev)->tx_chan; 1720 } 1721 EXPORT_SYMBOL(cxgb4_port_chan); 1722 1723 /** 1724 * cxgb4_port_e2cchan - get the HW c-channel of a port 1725 * @dev: the net device for the port 1726 * 1727 * Return the HW RX c-channel of the given port. 1728 */ 1729 unsigned int cxgb4_port_e2cchan(const struct net_device *dev) 1730 { 1731 return netdev2pinfo(dev)->rx_cchan; 1732 } 1733 EXPORT_SYMBOL(cxgb4_port_e2cchan); 1734 1735 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo) 1736 { 1737 struct adapter *adap = netdev2adap(dev); 1738 u32 v1, v2, lp_count, hp_count; 1739 1740 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 1741 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 1742 if (is_t4(adap->params.chip)) { 1743 lp_count = LP_COUNT_G(v1); 1744 hp_count = HP_COUNT_G(v1); 1745 } else { 1746 lp_count = LP_COUNT_T5_G(v1); 1747 hp_count = HP_COUNT_T5_G(v2); 1748 } 1749 return lpfifo ? lp_count : hp_count; 1750 } 1751 EXPORT_SYMBOL(cxgb4_dbfifo_count); 1752 1753 /** 1754 * cxgb4_port_viid - get the VI id of a port 1755 * @dev: the net device for the port 1756 * 1757 * Return the VI id of the given port. 1758 */ 1759 unsigned int cxgb4_port_viid(const struct net_device *dev) 1760 { 1761 return netdev2pinfo(dev)->viid; 1762 } 1763 EXPORT_SYMBOL(cxgb4_port_viid); 1764 1765 /** 1766 * cxgb4_port_idx - get the index of a port 1767 * @dev: the net device for the port 1768 * 1769 * Return the index of the given port. 1770 */ 1771 unsigned int cxgb4_port_idx(const struct net_device *dev) 1772 { 1773 return netdev2pinfo(dev)->port_id; 1774 } 1775 EXPORT_SYMBOL(cxgb4_port_idx); 1776 1777 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4, 1778 struct tp_tcp_stats *v6) 1779 { 1780 struct adapter *adap = pci_get_drvdata(pdev); 1781 1782 spin_lock(&adap->stats_lock); 1783 t4_tp_get_tcp_stats(adap, v4, v6, false); 1784 spin_unlock(&adap->stats_lock); 1785 } 1786 EXPORT_SYMBOL(cxgb4_get_tcp_stats); 1787 1788 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask, 1789 const unsigned int *pgsz_order) 1790 { 1791 struct adapter *adap = netdev2adap(dev); 1792 1793 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask); 1794 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) | 1795 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) | 1796 HPZ3_V(pgsz_order[3])); 1797 } 1798 EXPORT_SYMBOL(cxgb4_iscsi_init); 1799 1800 int cxgb4_flush_eq_cache(struct net_device *dev) 1801 { 1802 struct adapter *adap = netdev2adap(dev); 1803 1804 return t4_sge_ctxt_flush(adap, adap->mbox, CTXT_EGRESS); 1805 } 1806 EXPORT_SYMBOL(cxgb4_flush_eq_cache); 1807 1808 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) 1809 { 1810 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8; 1811 __be64 indices; 1812 int ret; 1813 1814 spin_lock(&adap->win0_lock); 1815 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr, 1816 sizeof(indices), (__be32 *)&indices, 1817 T4_MEMORY_READ); 1818 spin_unlock(&adap->win0_lock); 1819 if (!ret) { 1820 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff; 1821 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff; 1822 } 1823 return ret; 1824 } 1825 1826 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx, 1827 u16 size) 1828 { 1829 struct adapter *adap = netdev2adap(dev); 1830 u16 hw_pidx, hw_cidx; 1831 int ret; 1832 1833 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx); 1834 if (ret) 1835 goto out; 1836 1837 if (pidx != hw_pidx) { 1838 u16 delta; 1839 u32 val; 1840 1841 if (pidx >= hw_pidx) 1842 delta = pidx - hw_pidx; 1843 else 1844 delta = size - hw_pidx + pidx; 1845 1846 if (is_t4(adap->params.chip)) 1847 val = PIDX_V(delta); 1848 else 1849 val = PIDX_T5_V(delta); 1850 wmb(); 1851 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 1852 QID_V(qid) | val); 1853 } 1854 out: 1855 return ret; 1856 } 1857 EXPORT_SYMBOL(cxgb4_sync_txq_pidx); 1858 1859 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte) 1860 { 1861 u32 edc0_size, edc1_size, mc0_size, mc1_size, size; 1862 u32 edc0_end, edc1_end, mc0_end, mc1_end; 1863 u32 offset, memtype, memaddr; 1864 struct adapter *adap; 1865 u32 hma_size = 0; 1866 int ret; 1867 1868 adap = netdev2adap(dev); 1869 1870 offset = ((stag >> 8) * 32) + adap->vres.stag.start; 1871 1872 /* Figure out where the offset lands in the Memory Type/Address scheme. 1873 * This code assumes that the memory is laid out starting at offset 0 1874 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0 1875 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have 1876 * MC0, and some have both MC0 and MC1. 1877 */ 1878 size = t4_read_reg(adap, MA_EDRAM0_BAR_A); 1879 edc0_size = EDRAM0_SIZE_G(size) << 20; 1880 size = t4_read_reg(adap, MA_EDRAM1_BAR_A); 1881 edc1_size = EDRAM1_SIZE_G(size) << 20; 1882 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A); 1883 mc0_size = EXT_MEM0_SIZE_G(size) << 20; 1884 1885 if (t4_read_reg(adap, MA_TARGET_MEM_ENABLE_A) & HMA_MUX_F) { 1886 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1887 hma_size = EXT_MEM1_SIZE_G(size) << 20; 1888 } 1889 edc0_end = edc0_size; 1890 edc1_end = edc0_end + edc1_size; 1891 mc0_end = edc1_end + mc0_size; 1892 1893 if (offset < edc0_end) { 1894 memtype = MEM_EDC0; 1895 memaddr = offset; 1896 } else if (offset < edc1_end) { 1897 memtype = MEM_EDC1; 1898 memaddr = offset - edc0_end; 1899 } else { 1900 if (hma_size && (offset < (edc1_end + hma_size))) { 1901 memtype = MEM_HMA; 1902 memaddr = offset - edc1_end; 1903 } else if (offset < mc0_end) { 1904 memtype = MEM_MC0; 1905 memaddr = offset - edc1_end; 1906 } else if (is_t5(adap->params.chip)) { 1907 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A); 1908 mc1_size = EXT_MEM1_SIZE_G(size) << 20; 1909 mc1_end = mc0_end + mc1_size; 1910 if (offset < mc1_end) { 1911 memtype = MEM_MC1; 1912 memaddr = offset - mc0_end; 1913 } else { 1914 /* offset beyond the end of any memory */ 1915 goto err; 1916 } 1917 } else { 1918 /* T4/T6 only has a single memory channel */ 1919 goto err; 1920 } 1921 } 1922 1923 spin_lock(&adap->win0_lock); 1924 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ); 1925 spin_unlock(&adap->win0_lock); 1926 return ret; 1927 1928 err: 1929 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n", 1930 stag, offset); 1931 return -EINVAL; 1932 } 1933 EXPORT_SYMBOL(cxgb4_read_tpte); 1934 1935 u64 cxgb4_read_sge_timestamp(struct net_device *dev) 1936 { 1937 u32 hi, lo; 1938 struct adapter *adap; 1939 1940 adap = netdev2adap(dev); 1941 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A); 1942 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A)); 1943 1944 return ((u64)hi << 32) | (u64)lo; 1945 } 1946 EXPORT_SYMBOL(cxgb4_read_sge_timestamp); 1947 1948 int cxgb4_bar2_sge_qregs(struct net_device *dev, 1949 unsigned int qid, 1950 enum cxgb4_bar2_qtype qtype, 1951 int user, 1952 u64 *pbar2_qoffset, 1953 unsigned int *pbar2_qid) 1954 { 1955 return t4_bar2_sge_qregs(netdev2adap(dev), 1956 qid, 1957 (qtype == CXGB4_BAR2_QTYPE_EGRESS 1958 ? T4_BAR2_QTYPE_EGRESS 1959 : T4_BAR2_QTYPE_INGRESS), 1960 user, 1961 pbar2_qoffset, 1962 pbar2_qid); 1963 } 1964 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs); 1965 1966 static struct pci_driver cxgb4_driver; 1967 1968 static void check_neigh_update(struct neighbour *neigh) 1969 { 1970 const struct device *parent; 1971 const struct net_device *netdev = neigh->dev; 1972 1973 if (is_vlan_dev(netdev)) 1974 netdev = vlan_dev_real_dev(netdev); 1975 parent = netdev->dev.parent; 1976 if (parent && parent->driver == &cxgb4_driver.driver) 1977 t4_l2t_update(dev_get_drvdata(parent), neigh); 1978 } 1979 1980 static int netevent_cb(struct notifier_block *nb, unsigned long event, 1981 void *data) 1982 { 1983 switch (event) { 1984 case NETEVENT_NEIGH_UPDATE: 1985 check_neigh_update(data); 1986 break; 1987 case NETEVENT_REDIRECT: 1988 default: 1989 break; 1990 } 1991 return 0; 1992 } 1993 1994 static bool netevent_registered; 1995 static struct notifier_block cxgb4_netevent_nb = { 1996 .notifier_call = netevent_cb 1997 }; 1998 1999 static void drain_db_fifo(struct adapter *adap, int usecs) 2000 { 2001 u32 v1, v2, lp_count, hp_count; 2002 2003 do { 2004 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A); 2005 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A); 2006 if (is_t4(adap->params.chip)) { 2007 lp_count = LP_COUNT_G(v1); 2008 hp_count = HP_COUNT_G(v1); 2009 } else { 2010 lp_count = LP_COUNT_T5_G(v1); 2011 hp_count = HP_COUNT_T5_G(v2); 2012 } 2013 2014 if (lp_count == 0 && hp_count == 0) 2015 break; 2016 set_current_state(TASK_UNINTERRUPTIBLE); 2017 schedule_timeout(usecs_to_jiffies(usecs)); 2018 } while (1); 2019 } 2020 2021 static void disable_txq_db(struct sge_txq *q) 2022 { 2023 unsigned long flags; 2024 2025 spin_lock_irqsave(&q->db_lock, flags); 2026 q->db_disabled = 1; 2027 spin_unlock_irqrestore(&q->db_lock, flags); 2028 } 2029 2030 static void enable_txq_db(struct adapter *adap, struct sge_txq *q) 2031 { 2032 spin_lock_irq(&q->db_lock); 2033 if (q->db_pidx_inc) { 2034 /* Make sure that all writes to the TX descriptors 2035 * are committed before we tell HW about them. 2036 */ 2037 wmb(); 2038 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2039 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc)); 2040 q->db_pidx_inc = 0; 2041 } 2042 q->db_disabled = 0; 2043 spin_unlock_irq(&q->db_lock); 2044 } 2045 2046 static void disable_dbs(struct adapter *adap) 2047 { 2048 int i; 2049 2050 for_each_ethrxq(&adap->sge, i) 2051 disable_txq_db(&adap->sge.ethtxq[i].q); 2052 if (is_offload(adap)) { 2053 struct sge_uld_txq_info *txq_info = 2054 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2055 2056 if (txq_info) { 2057 for_each_ofldtxq(&adap->sge, i) { 2058 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2059 2060 disable_txq_db(&txq->q); 2061 } 2062 } 2063 } 2064 for_each_port(adap, i) 2065 disable_txq_db(&adap->sge.ctrlq[i].q); 2066 } 2067 2068 static void enable_dbs(struct adapter *adap) 2069 { 2070 int i; 2071 2072 for_each_ethrxq(&adap->sge, i) 2073 enable_txq_db(adap, &adap->sge.ethtxq[i].q); 2074 if (is_offload(adap)) { 2075 struct sge_uld_txq_info *txq_info = 2076 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2077 2078 if (txq_info) { 2079 for_each_ofldtxq(&adap->sge, i) { 2080 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2081 2082 enable_txq_db(adap, &txq->q); 2083 } 2084 } 2085 } 2086 for_each_port(adap, i) 2087 enable_txq_db(adap, &adap->sge.ctrlq[i].q); 2088 } 2089 2090 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd) 2091 { 2092 enum cxgb4_uld type = CXGB4_ULD_RDMA; 2093 2094 if (adap->uld && adap->uld[type].handle) 2095 adap->uld[type].control(adap->uld[type].handle, cmd); 2096 } 2097 2098 static void process_db_full(struct work_struct *work) 2099 { 2100 struct adapter *adap; 2101 2102 adap = container_of(work, struct adapter, db_full_task); 2103 2104 drain_db_fifo(adap, dbfifo_drain_delay); 2105 enable_dbs(adap); 2106 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2107 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2108 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2109 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 2110 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F); 2111 else 2112 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2113 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F); 2114 } 2115 2116 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q) 2117 { 2118 u16 hw_pidx, hw_cidx; 2119 int ret; 2120 2121 spin_lock_irq(&q->db_lock); 2122 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx); 2123 if (ret) 2124 goto out; 2125 if (q->db_pidx != hw_pidx) { 2126 u16 delta; 2127 u32 val; 2128 2129 if (q->db_pidx >= hw_pidx) 2130 delta = q->db_pidx - hw_pidx; 2131 else 2132 delta = q->size - hw_pidx + q->db_pidx; 2133 2134 if (is_t4(adap->params.chip)) 2135 val = PIDX_V(delta); 2136 else 2137 val = PIDX_T5_V(delta); 2138 wmb(); 2139 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A), 2140 QID_V(q->cntxt_id) | val); 2141 } 2142 out: 2143 q->db_disabled = 0; 2144 q->db_pidx_inc = 0; 2145 spin_unlock_irq(&q->db_lock); 2146 if (ret) 2147 CH_WARN(adap, "DB drop recovery failed.\n"); 2148 } 2149 2150 static void recover_all_queues(struct adapter *adap) 2151 { 2152 int i; 2153 2154 for_each_ethrxq(&adap->sge, i) 2155 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q); 2156 if (is_offload(adap)) { 2157 struct sge_uld_txq_info *txq_info = 2158 adap->sge.uld_txq_info[CXGB4_TX_OFLD]; 2159 if (txq_info) { 2160 for_each_ofldtxq(&adap->sge, i) { 2161 struct sge_uld_txq *txq = &txq_info->uldtxq[i]; 2162 2163 sync_txq_pidx(adap, &txq->q); 2164 } 2165 } 2166 } 2167 for_each_port(adap, i) 2168 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q); 2169 } 2170 2171 static void process_db_drop(struct work_struct *work) 2172 { 2173 struct adapter *adap; 2174 2175 adap = container_of(work, struct adapter, db_drop_task); 2176 2177 if (is_t4(adap->params.chip)) { 2178 drain_db_fifo(adap, dbfifo_drain_delay); 2179 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP); 2180 drain_db_fifo(adap, dbfifo_drain_delay); 2181 recover_all_queues(adap); 2182 drain_db_fifo(adap, dbfifo_drain_delay); 2183 enable_dbs(adap); 2184 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY); 2185 } else if (is_t5(adap->params.chip)) { 2186 u32 dropped_db = t4_read_reg(adap, 0x010ac); 2187 u16 qid = (dropped_db >> 15) & 0x1ffff; 2188 u16 pidx_inc = dropped_db & 0x1fff; 2189 u64 bar2_qoffset; 2190 unsigned int bar2_qid; 2191 int ret; 2192 2193 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS, 2194 0, &bar2_qoffset, &bar2_qid); 2195 if (ret) 2196 dev_err(adap->pdev_dev, "doorbell drop recovery: " 2197 "qid=%d, pidx_inc=%d\n", qid, pidx_inc); 2198 else 2199 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid), 2200 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL); 2201 2202 /* Re-enable BAR2 WC */ 2203 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15); 2204 } 2205 2206 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) 2207 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0); 2208 } 2209 2210 void t4_db_full(struct adapter *adap) 2211 { 2212 if (is_t4(adap->params.chip)) { 2213 disable_dbs(adap); 2214 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2215 t4_set_reg_field(adap, SGE_INT_ENABLE3_A, 2216 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0); 2217 queue_work(adap->workq, &adap->db_full_task); 2218 } 2219 } 2220 2221 void t4_db_dropped(struct adapter *adap) 2222 { 2223 if (is_t4(adap->params.chip)) { 2224 disable_dbs(adap); 2225 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL); 2226 } 2227 queue_work(adap->workq, &adap->db_drop_task); 2228 } 2229 2230 void t4_register_netevent_notifier(void) 2231 { 2232 if (!netevent_registered) { 2233 register_netevent_notifier(&cxgb4_netevent_nb); 2234 netevent_registered = true; 2235 } 2236 } 2237 2238 static void detach_ulds(struct adapter *adap) 2239 { 2240 unsigned int i; 2241 2242 mutex_lock(&uld_mutex); 2243 list_del(&adap->list_node); 2244 2245 for (i = 0; i < CXGB4_ULD_MAX; i++) 2246 if (adap->uld && adap->uld[i].handle) 2247 adap->uld[i].state_change(adap->uld[i].handle, 2248 CXGB4_STATE_DETACH); 2249 2250 if (netevent_registered && list_empty(&adapter_list)) { 2251 unregister_netevent_notifier(&cxgb4_netevent_nb); 2252 netevent_registered = false; 2253 } 2254 mutex_unlock(&uld_mutex); 2255 } 2256 2257 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state) 2258 { 2259 unsigned int i; 2260 2261 mutex_lock(&uld_mutex); 2262 for (i = 0; i < CXGB4_ULD_MAX; i++) 2263 if (adap->uld && adap->uld[i].handle) 2264 adap->uld[i].state_change(adap->uld[i].handle, 2265 new_state); 2266 mutex_unlock(&uld_mutex); 2267 } 2268 2269 #if IS_ENABLED(CONFIG_IPV6) 2270 static int cxgb4_inet6addr_handler(struct notifier_block *this, 2271 unsigned long event, void *data) 2272 { 2273 struct inet6_ifaddr *ifa = data; 2274 struct net_device *event_dev = ifa->idev->dev; 2275 const struct device *parent = NULL; 2276 #if IS_ENABLED(CONFIG_BONDING) 2277 struct adapter *adap; 2278 #endif 2279 if (is_vlan_dev(event_dev)) 2280 event_dev = vlan_dev_real_dev(event_dev); 2281 #if IS_ENABLED(CONFIG_BONDING) 2282 if (event_dev->flags & IFF_MASTER) { 2283 list_for_each_entry(adap, &adapter_list, list_node) { 2284 switch (event) { 2285 case NETDEV_UP: 2286 cxgb4_clip_get(adap->port[0], 2287 (const u32 *)ifa, 1); 2288 break; 2289 case NETDEV_DOWN: 2290 cxgb4_clip_release(adap->port[0], 2291 (const u32 *)ifa, 1); 2292 break; 2293 default: 2294 break; 2295 } 2296 } 2297 return NOTIFY_OK; 2298 } 2299 #endif 2300 2301 if (event_dev) 2302 parent = event_dev->dev.parent; 2303 2304 if (parent && parent->driver == &cxgb4_driver.driver) { 2305 switch (event) { 2306 case NETDEV_UP: 2307 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1); 2308 break; 2309 case NETDEV_DOWN: 2310 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1); 2311 break; 2312 default: 2313 break; 2314 } 2315 } 2316 return NOTIFY_OK; 2317 } 2318 2319 static bool inet6addr_registered; 2320 static struct notifier_block cxgb4_inet6addr_notifier = { 2321 .notifier_call = cxgb4_inet6addr_handler 2322 }; 2323 2324 static void update_clip(const struct adapter *adap) 2325 { 2326 int i; 2327 struct net_device *dev; 2328 int ret; 2329 2330 rcu_read_lock(); 2331 2332 for (i = 0; i < MAX_NPORTS; i++) { 2333 dev = adap->port[i]; 2334 ret = 0; 2335 2336 if (dev) 2337 ret = cxgb4_update_root_dev_clip(dev); 2338 2339 if (ret < 0) 2340 break; 2341 } 2342 rcu_read_unlock(); 2343 } 2344 #endif /* IS_ENABLED(CONFIG_IPV6) */ 2345 2346 /** 2347 * cxgb_up - enable the adapter 2348 * @adap: adapter being enabled 2349 * 2350 * Called when the first port is enabled, this function performs the 2351 * actions necessary to make an adapter operational, such as completing 2352 * the initialization of HW modules, and enabling interrupts. 2353 * 2354 * Must be called with the rtnl lock held. 2355 */ 2356 static int cxgb_up(struct adapter *adap) 2357 { 2358 int err; 2359 2360 mutex_lock(&uld_mutex); 2361 err = setup_sge_queues(adap); 2362 if (err) 2363 goto rel_lock; 2364 err = setup_rss(adap); 2365 if (err) 2366 goto freeq; 2367 2368 if (adap->flags & CXGB4_USING_MSIX) { 2369 name_msix_vecs(adap); 2370 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0, 2371 adap->msix_info[0].desc, adap); 2372 if (err) 2373 goto irq_err; 2374 err = request_msix_queue_irqs(adap); 2375 if (err) { 2376 free_irq(adap->msix_info[0].vec, adap); 2377 goto irq_err; 2378 } 2379 } else { 2380 err = request_irq(adap->pdev->irq, t4_intr_handler(adap), 2381 (adap->flags & CXGB4_USING_MSI) ? 0 2382 : IRQF_SHARED, 2383 adap->port[0]->name, adap); 2384 if (err) 2385 goto irq_err; 2386 } 2387 2388 enable_rx(adap); 2389 t4_sge_start(adap); 2390 t4_intr_enable(adap); 2391 adap->flags |= CXGB4_FULL_INIT_DONE; 2392 mutex_unlock(&uld_mutex); 2393 2394 notify_ulds(adap, CXGB4_STATE_UP); 2395 #if IS_ENABLED(CONFIG_IPV6) 2396 update_clip(adap); 2397 #endif 2398 return err; 2399 2400 irq_err: 2401 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err); 2402 freeq: 2403 t4_free_sge_resources(adap); 2404 rel_lock: 2405 mutex_unlock(&uld_mutex); 2406 return err; 2407 } 2408 2409 static void cxgb_down(struct adapter *adapter) 2410 { 2411 cancel_work_sync(&adapter->tid_release_task); 2412 cancel_work_sync(&adapter->db_full_task); 2413 cancel_work_sync(&adapter->db_drop_task); 2414 adapter->tid_release_task_busy = false; 2415 adapter->tid_release_head = NULL; 2416 2417 t4_sge_stop(adapter); 2418 t4_free_sge_resources(adapter); 2419 2420 adapter->flags &= ~CXGB4_FULL_INIT_DONE; 2421 } 2422 2423 /* 2424 * net_device operations 2425 */ 2426 static int cxgb_open(struct net_device *dev) 2427 { 2428 int err; 2429 struct port_info *pi = netdev_priv(dev); 2430 struct adapter *adapter = pi->adapter; 2431 2432 netif_carrier_off(dev); 2433 2434 if (!(adapter->flags & CXGB4_FULL_INIT_DONE)) { 2435 err = cxgb_up(adapter); 2436 if (err < 0) 2437 return err; 2438 } 2439 2440 /* It's possible that the basic port information could have 2441 * changed since we first read it. 2442 */ 2443 err = t4_update_port_info(pi); 2444 if (err < 0) 2445 return err; 2446 2447 err = link_start(dev); 2448 if (!err) 2449 netif_tx_start_all_queues(dev); 2450 return err; 2451 } 2452 2453 static int cxgb_close(struct net_device *dev) 2454 { 2455 struct port_info *pi = netdev_priv(dev); 2456 struct adapter *adapter = pi->adapter; 2457 int ret; 2458 2459 netif_tx_stop_all_queues(dev); 2460 netif_carrier_off(dev); 2461 ret = t4_enable_pi_params(adapter, adapter->pf, pi, 2462 false, false, false); 2463 #ifdef CONFIG_CHELSIO_T4_DCB 2464 cxgb4_dcb_reset(dev); 2465 dcb_tx_queue_prio_enable(dev, false); 2466 #endif 2467 return ret; 2468 } 2469 2470 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid, 2471 __be32 sip, __be16 sport, __be16 vlan, 2472 unsigned int queue, unsigned char port, unsigned char mask) 2473 { 2474 int ret; 2475 struct filter_entry *f; 2476 struct adapter *adap; 2477 int i; 2478 u8 *val; 2479 2480 adap = netdev2adap(dev); 2481 2482 /* Adjust stid to correct filter index */ 2483 stid -= adap->tids.sftid_base; 2484 stid += adap->tids.nftids; 2485 2486 /* Check to make sure the filter requested is writable ... 2487 */ 2488 f = &adap->tids.ftid_tab[stid]; 2489 ret = writable_filter(f); 2490 if (ret) 2491 return ret; 2492 2493 /* Clear out any old resources being used by the filter before 2494 * we start constructing the new filter. 2495 */ 2496 if (f->valid) 2497 clear_filter(adap, f); 2498 2499 /* Clear out filter specifications */ 2500 memset(&f->fs, 0, sizeof(struct ch_filter_specification)); 2501 f->fs.val.lport = cpu_to_be16(sport); 2502 f->fs.mask.lport = ~0; 2503 val = (u8 *)&sip; 2504 if ((val[0] | val[1] | val[2] | val[3]) != 0) { 2505 for (i = 0; i < 4; i++) { 2506 f->fs.val.lip[i] = val[i]; 2507 f->fs.mask.lip[i] = ~0; 2508 } 2509 if (adap->params.tp.vlan_pri_map & PORT_F) { 2510 f->fs.val.iport = port; 2511 f->fs.mask.iport = mask; 2512 } 2513 } 2514 2515 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) { 2516 f->fs.val.proto = IPPROTO_TCP; 2517 f->fs.mask.proto = ~0; 2518 } 2519 2520 f->fs.dirsteer = 1; 2521 f->fs.iq = queue; 2522 /* Mark filter as locked */ 2523 f->locked = 1; 2524 f->fs.rpttid = 1; 2525 2526 /* Save the actual tid. We need this to get the corresponding 2527 * filter entry structure in filter_rpl. 2528 */ 2529 f->tid = stid + adap->tids.ftid_base; 2530 ret = set_filter_wr(adap, stid); 2531 if (ret) { 2532 clear_filter(adap, f); 2533 return ret; 2534 } 2535 2536 return 0; 2537 } 2538 EXPORT_SYMBOL(cxgb4_create_server_filter); 2539 2540 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid, 2541 unsigned int queue, bool ipv6) 2542 { 2543 struct filter_entry *f; 2544 struct adapter *adap; 2545 2546 adap = netdev2adap(dev); 2547 2548 /* Adjust stid to correct filter index */ 2549 stid -= adap->tids.sftid_base; 2550 stid += adap->tids.nftids; 2551 2552 f = &adap->tids.ftid_tab[stid]; 2553 /* Unlock the filter */ 2554 f->locked = 0; 2555 2556 return delete_filter(adap, stid); 2557 } 2558 EXPORT_SYMBOL(cxgb4_remove_server_filter); 2559 2560 static void cxgb_get_stats(struct net_device *dev, 2561 struct rtnl_link_stats64 *ns) 2562 { 2563 struct port_stats stats; 2564 struct port_info *p = netdev_priv(dev); 2565 struct adapter *adapter = p->adapter; 2566 2567 /* Block retrieving statistics during EEH error 2568 * recovery. Otherwise, the recovery might fail 2569 * and the PCI device will be removed permanently 2570 */ 2571 spin_lock(&adapter->stats_lock); 2572 if (!netif_device_present(dev)) { 2573 spin_unlock(&adapter->stats_lock); 2574 return; 2575 } 2576 t4_get_port_stats_offset(adapter, p->tx_chan, &stats, 2577 &p->stats_base); 2578 spin_unlock(&adapter->stats_lock); 2579 2580 ns->tx_bytes = stats.tx_octets; 2581 ns->tx_packets = stats.tx_frames; 2582 ns->rx_bytes = stats.rx_octets; 2583 ns->rx_packets = stats.rx_frames; 2584 ns->multicast = stats.rx_mcast_frames; 2585 2586 /* detailed rx_errors */ 2587 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long + 2588 stats.rx_runt; 2589 ns->rx_over_errors = 0; 2590 ns->rx_crc_errors = stats.rx_fcs_err; 2591 ns->rx_frame_errors = stats.rx_symbol_err; 2592 ns->rx_dropped = stats.rx_ovflow0 + stats.rx_ovflow1 + 2593 stats.rx_ovflow2 + stats.rx_ovflow3 + 2594 stats.rx_trunc0 + stats.rx_trunc1 + 2595 stats.rx_trunc2 + stats.rx_trunc3; 2596 ns->rx_missed_errors = 0; 2597 2598 /* detailed tx_errors */ 2599 ns->tx_aborted_errors = 0; 2600 ns->tx_carrier_errors = 0; 2601 ns->tx_fifo_errors = 0; 2602 ns->tx_heartbeat_errors = 0; 2603 ns->tx_window_errors = 0; 2604 2605 ns->tx_errors = stats.tx_error_frames; 2606 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err + 2607 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors; 2608 } 2609 2610 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 2611 { 2612 unsigned int mbox; 2613 int ret = 0, prtad, devad; 2614 struct port_info *pi = netdev_priv(dev); 2615 struct adapter *adapter = pi->adapter; 2616 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data; 2617 2618 switch (cmd) { 2619 case SIOCGMIIPHY: 2620 if (pi->mdio_addr < 0) 2621 return -EOPNOTSUPP; 2622 data->phy_id = pi->mdio_addr; 2623 break; 2624 case SIOCGMIIREG: 2625 case SIOCSMIIREG: 2626 if (mdio_phy_id_is_c45(data->phy_id)) { 2627 prtad = mdio_phy_id_prtad(data->phy_id); 2628 devad = mdio_phy_id_devad(data->phy_id); 2629 } else if (data->phy_id < 32) { 2630 prtad = data->phy_id; 2631 devad = 0; 2632 data->reg_num &= 0x1f; 2633 } else 2634 return -EINVAL; 2635 2636 mbox = pi->adapter->pf; 2637 if (cmd == SIOCGMIIREG) 2638 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad, 2639 data->reg_num, &data->val_out); 2640 else 2641 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad, 2642 data->reg_num, data->val_in); 2643 break; 2644 case SIOCGHWTSTAMP: 2645 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2646 sizeof(pi->tstamp_config)) ? 2647 -EFAULT : 0; 2648 case SIOCSHWTSTAMP: 2649 if (copy_from_user(&pi->tstamp_config, req->ifr_data, 2650 sizeof(pi->tstamp_config))) 2651 return -EFAULT; 2652 2653 if (!is_t4(adapter->params.chip)) { 2654 switch (pi->tstamp_config.tx_type) { 2655 case HWTSTAMP_TX_OFF: 2656 case HWTSTAMP_TX_ON: 2657 break; 2658 default: 2659 return -ERANGE; 2660 } 2661 2662 switch (pi->tstamp_config.rx_filter) { 2663 case HWTSTAMP_FILTER_NONE: 2664 pi->rxtstamp = false; 2665 break; 2666 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2667 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2668 cxgb4_ptprx_timestamping(pi, pi->port_id, 2669 PTP_TS_L4); 2670 break; 2671 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2672 cxgb4_ptprx_timestamping(pi, pi->port_id, 2673 PTP_TS_L2_L4); 2674 break; 2675 case HWTSTAMP_FILTER_ALL: 2676 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2677 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2678 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2679 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2680 pi->rxtstamp = true; 2681 break; 2682 default: 2683 pi->tstamp_config.rx_filter = 2684 HWTSTAMP_FILTER_NONE; 2685 return -ERANGE; 2686 } 2687 2688 if ((pi->tstamp_config.tx_type == HWTSTAMP_TX_OFF) && 2689 (pi->tstamp_config.rx_filter == 2690 HWTSTAMP_FILTER_NONE)) { 2691 if (cxgb4_ptp_txtype(adapter, pi->port_id) >= 0) 2692 pi->ptp_enable = false; 2693 } 2694 2695 if (pi->tstamp_config.rx_filter != 2696 HWTSTAMP_FILTER_NONE) { 2697 if (cxgb4_ptp_redirect_rx_packet(adapter, 2698 pi) >= 0) 2699 pi->ptp_enable = true; 2700 } 2701 } else { 2702 /* For T4 Adapters */ 2703 switch (pi->tstamp_config.rx_filter) { 2704 case HWTSTAMP_FILTER_NONE: 2705 pi->rxtstamp = false; 2706 break; 2707 case HWTSTAMP_FILTER_ALL: 2708 pi->rxtstamp = true; 2709 break; 2710 default: 2711 pi->tstamp_config.rx_filter = 2712 HWTSTAMP_FILTER_NONE; 2713 return -ERANGE; 2714 } 2715 } 2716 return copy_to_user(req->ifr_data, &pi->tstamp_config, 2717 sizeof(pi->tstamp_config)) ? 2718 -EFAULT : 0; 2719 default: 2720 return -EOPNOTSUPP; 2721 } 2722 return ret; 2723 } 2724 2725 static void cxgb_set_rxmode(struct net_device *dev) 2726 { 2727 /* unfortunately we can't return errors to the stack */ 2728 set_rxmode(dev, -1, false); 2729 } 2730 2731 static int cxgb_change_mtu(struct net_device *dev, int new_mtu) 2732 { 2733 int ret; 2734 struct port_info *pi = netdev_priv(dev); 2735 2736 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1, 2737 -1, -1, -1, true); 2738 if (!ret) 2739 dev->mtu = new_mtu; 2740 return ret; 2741 } 2742 2743 #ifdef CONFIG_PCI_IOV 2744 static int cxgb4_mgmt_open(struct net_device *dev) 2745 { 2746 /* Turn carrier off since we don't have to transmit anything on this 2747 * interface. 2748 */ 2749 netif_carrier_off(dev); 2750 return 0; 2751 } 2752 2753 /* Fill MAC address that will be assigned by the FW */ 2754 static void cxgb4_mgmt_fill_vf_station_mac_addr(struct adapter *adap) 2755 { 2756 u8 hw_addr[ETH_ALEN], macaddr[ETH_ALEN]; 2757 unsigned int i, vf, nvfs; 2758 u16 a, b; 2759 int err; 2760 u8 *na; 2761 2762 adap->params.pci.vpd_cap_addr = pci_find_capability(adap->pdev, 2763 PCI_CAP_ID_VPD); 2764 err = t4_get_raw_vpd_params(adap, &adap->params.vpd); 2765 if (err) 2766 return; 2767 2768 na = adap->params.vpd.na; 2769 for (i = 0; i < ETH_ALEN; i++) 2770 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 2771 hex2val(na[2 * i + 1])); 2772 2773 a = (hw_addr[0] << 8) | hw_addr[1]; 2774 b = (hw_addr[1] << 8) | hw_addr[2]; 2775 a ^= b; 2776 a |= 0x0200; /* locally assigned Ethernet MAC address */ 2777 a &= ~0x0100; /* not a multicast Ethernet MAC address */ 2778 macaddr[0] = a >> 8; 2779 macaddr[1] = a & 0xff; 2780 2781 for (i = 2; i < 5; i++) 2782 macaddr[i] = hw_addr[i + 1]; 2783 2784 for (vf = 0, nvfs = pci_sriov_get_totalvfs(adap->pdev); 2785 vf < nvfs; vf++) { 2786 macaddr[5] = adap->pf * nvfs + vf; 2787 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, macaddr); 2788 } 2789 } 2790 2791 static int cxgb4_mgmt_set_vf_mac(struct net_device *dev, int vf, u8 *mac) 2792 { 2793 struct port_info *pi = netdev_priv(dev); 2794 struct adapter *adap = pi->adapter; 2795 int ret; 2796 2797 /* verify MAC addr is valid */ 2798 if (!is_valid_ether_addr(mac)) { 2799 dev_err(pi->adapter->pdev_dev, 2800 "Invalid Ethernet address %pM for VF %d\n", 2801 mac, vf); 2802 return -EINVAL; 2803 } 2804 2805 dev_info(pi->adapter->pdev_dev, 2806 "Setting MAC %pM on VF %d\n", mac, vf); 2807 ret = t4_set_vf_mac_acl(adap, vf + 1, 1, mac); 2808 if (!ret) 2809 ether_addr_copy(adap->vfinfo[vf].vf_mac_addr, mac); 2810 return ret; 2811 } 2812 2813 static int cxgb4_mgmt_get_vf_config(struct net_device *dev, 2814 int vf, struct ifla_vf_info *ivi) 2815 { 2816 struct port_info *pi = netdev_priv(dev); 2817 struct adapter *adap = pi->adapter; 2818 struct vf_info *vfinfo; 2819 2820 if (vf >= adap->num_vfs) 2821 return -EINVAL; 2822 vfinfo = &adap->vfinfo[vf]; 2823 2824 ivi->vf = vf; 2825 ivi->max_tx_rate = vfinfo->tx_rate; 2826 ivi->min_tx_rate = 0; 2827 ether_addr_copy(ivi->mac, vfinfo->vf_mac_addr); 2828 ivi->vlan = vfinfo->vlan; 2829 ivi->linkstate = vfinfo->link_state; 2830 return 0; 2831 } 2832 2833 static int cxgb4_mgmt_get_phys_port_id(struct net_device *dev, 2834 struct netdev_phys_item_id *ppid) 2835 { 2836 struct port_info *pi = netdev_priv(dev); 2837 unsigned int phy_port_id; 2838 2839 phy_port_id = pi->adapter->adap_idx * 10 + pi->port_id; 2840 ppid->id_len = sizeof(phy_port_id); 2841 memcpy(ppid->id, &phy_port_id, ppid->id_len); 2842 return 0; 2843 } 2844 2845 static int cxgb4_mgmt_set_vf_rate(struct net_device *dev, int vf, 2846 int min_tx_rate, int max_tx_rate) 2847 { 2848 struct port_info *pi = netdev_priv(dev); 2849 struct adapter *adap = pi->adapter; 2850 unsigned int link_ok, speed, mtu; 2851 u32 fw_pfvf, fw_class; 2852 int class_id = vf; 2853 int ret; 2854 u16 pktsize; 2855 2856 if (vf >= adap->num_vfs) 2857 return -EINVAL; 2858 2859 if (min_tx_rate) { 2860 dev_err(adap->pdev_dev, 2861 "Min tx rate (%d) (> 0) for VF %d is Invalid.\n", 2862 min_tx_rate, vf); 2863 return -EINVAL; 2864 } 2865 2866 if (max_tx_rate == 0) { 2867 /* unbind VF to to any Traffic Class */ 2868 fw_pfvf = 2869 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2870 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2871 fw_class = 0xffffffff; 2872 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 2873 &fw_pfvf, &fw_class); 2874 if (ret) { 2875 dev_err(adap->pdev_dev, 2876 "Err %d in unbinding PF %d VF %d from TX Rate Limiting\n", 2877 ret, adap->pf, vf); 2878 return -EINVAL; 2879 } 2880 dev_info(adap->pdev_dev, 2881 "PF %d VF %d is unbound from TX Rate Limiting\n", 2882 adap->pf, vf); 2883 adap->vfinfo[vf].tx_rate = 0; 2884 return 0; 2885 } 2886 2887 ret = t4_get_link_params(pi, &link_ok, &speed, &mtu); 2888 if (ret != FW_SUCCESS) { 2889 dev_err(adap->pdev_dev, 2890 "Failed to get link information for VF %d\n", vf); 2891 return -EINVAL; 2892 } 2893 2894 if (!link_ok) { 2895 dev_err(adap->pdev_dev, "Link down for VF %d\n", vf); 2896 return -EINVAL; 2897 } 2898 2899 if (max_tx_rate > speed) { 2900 dev_err(adap->pdev_dev, 2901 "Max tx rate %d for VF %d can't be > link-speed %u", 2902 max_tx_rate, vf, speed); 2903 return -EINVAL; 2904 } 2905 2906 pktsize = mtu; 2907 /* subtract ethhdr size and 4 bytes crc since, f/w appends it */ 2908 pktsize = pktsize - sizeof(struct ethhdr) - 4; 2909 /* subtract ipv4 hdr size, tcp hdr size to get typical IPv4 MSS size */ 2910 pktsize = pktsize - sizeof(struct iphdr) - sizeof(struct tcphdr); 2911 /* configure Traffic Class for rate-limiting */ 2912 ret = t4_sched_params(adap, SCHED_CLASS_TYPE_PACKET, 2913 SCHED_CLASS_LEVEL_CL_RL, 2914 SCHED_CLASS_MODE_CLASS, 2915 SCHED_CLASS_RATEUNIT_BITS, 2916 SCHED_CLASS_RATEMODE_ABS, 2917 pi->tx_chan, class_id, 0, 2918 max_tx_rate * 1000, 0, pktsize); 2919 if (ret) { 2920 dev_err(adap->pdev_dev, "Err %d for Traffic Class config\n", 2921 ret); 2922 return -EINVAL; 2923 } 2924 dev_info(adap->pdev_dev, 2925 "Class %d with MSS %u configured with rate %u\n", 2926 class_id, pktsize, max_tx_rate); 2927 2928 /* bind VF to configured Traffic Class */ 2929 fw_pfvf = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2930 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH)); 2931 fw_class = class_id; 2932 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, &fw_pfvf, 2933 &fw_class); 2934 if (ret) { 2935 dev_err(adap->pdev_dev, 2936 "Err %d in binding PF %d VF %d to Traffic Class %d\n", 2937 ret, adap->pf, vf, class_id); 2938 return -EINVAL; 2939 } 2940 dev_info(adap->pdev_dev, "PF %d VF %d is bound to Class %d\n", 2941 adap->pf, vf, class_id); 2942 adap->vfinfo[vf].tx_rate = max_tx_rate; 2943 return 0; 2944 } 2945 2946 static int cxgb4_mgmt_set_vf_vlan(struct net_device *dev, int vf, 2947 u16 vlan, u8 qos, __be16 vlan_proto) 2948 { 2949 struct port_info *pi = netdev_priv(dev); 2950 struct adapter *adap = pi->adapter; 2951 int ret; 2952 2953 if (vf >= adap->num_vfs || vlan > 4095 || qos > 7) 2954 return -EINVAL; 2955 2956 if (vlan_proto != htons(ETH_P_8021Q) || qos != 0) 2957 return -EPROTONOSUPPORT; 2958 2959 ret = t4_set_vlan_acl(adap, adap->mbox, vf + 1, vlan); 2960 if (!ret) { 2961 adap->vfinfo[vf].vlan = vlan; 2962 return 0; 2963 } 2964 2965 dev_err(adap->pdev_dev, "Err %d %s VLAN ACL for PF/VF %d/%d\n", 2966 ret, (vlan ? "setting" : "clearing"), adap->pf, vf); 2967 return ret; 2968 } 2969 2970 static int cxgb4_mgmt_set_vf_link_state(struct net_device *dev, int vf, 2971 int link) 2972 { 2973 struct port_info *pi = netdev_priv(dev); 2974 struct adapter *adap = pi->adapter; 2975 u32 param, val; 2976 int ret = 0; 2977 2978 if (vf >= adap->num_vfs) 2979 return -EINVAL; 2980 2981 switch (link) { 2982 case IFLA_VF_LINK_STATE_AUTO: 2983 val = FW_VF_LINK_STATE_AUTO; 2984 break; 2985 2986 case IFLA_VF_LINK_STATE_ENABLE: 2987 val = FW_VF_LINK_STATE_ENABLE; 2988 break; 2989 2990 case IFLA_VF_LINK_STATE_DISABLE: 2991 val = FW_VF_LINK_STATE_DISABLE; 2992 break; 2993 2994 default: 2995 return -EINVAL; 2996 } 2997 2998 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | 2999 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_LINK_STATE)); 3000 ret = t4_set_params(adap, adap->mbox, adap->pf, vf + 1, 1, 3001 ¶m, &val); 3002 if (ret) { 3003 dev_err(adap->pdev_dev, 3004 "Error %d in setting PF %d VF %d link state\n", 3005 ret, adap->pf, vf); 3006 return -EINVAL; 3007 } 3008 3009 adap->vfinfo[vf].link_state = link; 3010 return ret; 3011 } 3012 #endif /* CONFIG_PCI_IOV */ 3013 3014 static int cxgb_set_mac_addr(struct net_device *dev, void *p) 3015 { 3016 int ret; 3017 struct sockaddr *addr = p; 3018 struct port_info *pi = netdev_priv(dev); 3019 3020 if (!is_valid_ether_addr(addr->sa_data)) 3021 return -EADDRNOTAVAIL; 3022 3023 ret = cxgb4_change_mac(pi, pi->viid, &pi->xact_addr_filt, 3024 addr->sa_data, true, &pi->smt_idx); 3025 if (ret < 0) 3026 return ret; 3027 3028 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 3029 pi->xact_addr_filt = ret; 3030 return 0; 3031 } 3032 3033 #ifdef CONFIG_NET_POLL_CONTROLLER 3034 static void cxgb_netpoll(struct net_device *dev) 3035 { 3036 struct port_info *pi = netdev_priv(dev); 3037 struct adapter *adap = pi->adapter; 3038 3039 if (adap->flags & CXGB4_USING_MSIX) { 3040 int i; 3041 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset]; 3042 3043 for (i = pi->nqsets; i; i--, rx++) 3044 t4_sge_intr_msix(0, &rx->rspq); 3045 } else 3046 t4_intr_handler(adap)(0, adap); 3047 } 3048 #endif 3049 3050 static int cxgb_set_tx_maxrate(struct net_device *dev, int index, u32 rate) 3051 { 3052 struct port_info *pi = netdev_priv(dev); 3053 struct adapter *adap = pi->adapter; 3054 struct sched_class *e; 3055 struct ch_sched_params p; 3056 struct ch_sched_queue qe; 3057 u32 req_rate; 3058 int err = 0; 3059 3060 if (!can_sched(dev)) 3061 return -ENOTSUPP; 3062 3063 if (index < 0 || index > pi->nqsets - 1) 3064 return -EINVAL; 3065 3066 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3067 dev_err(adap->pdev_dev, 3068 "Failed to rate limit on queue %d. Link Down?\n", 3069 index); 3070 return -EINVAL; 3071 } 3072 3073 /* Convert from Mbps to Kbps */ 3074 req_rate = rate * 1000; 3075 3076 /* Max rate is 100 Gbps */ 3077 if (req_rate > SCHED_MAX_RATE_KBPS) { 3078 dev_err(adap->pdev_dev, 3079 "Invalid rate %u Mbps, Max rate is %u Mbps\n", 3080 rate, SCHED_MAX_RATE_KBPS / 1000); 3081 return -ERANGE; 3082 } 3083 3084 /* First unbind the queue from any existing class */ 3085 memset(&qe, 0, sizeof(qe)); 3086 qe.queue = index; 3087 qe.class = SCHED_CLS_NONE; 3088 3089 err = cxgb4_sched_class_unbind(dev, (void *)(&qe), SCHED_QUEUE); 3090 if (err) { 3091 dev_err(adap->pdev_dev, 3092 "Unbinding Queue %d on port %d fail. Err: %d\n", 3093 index, pi->port_id, err); 3094 return err; 3095 } 3096 3097 /* Queue already unbound */ 3098 if (!req_rate) 3099 return 0; 3100 3101 /* Fetch any available unused or matching scheduling class */ 3102 memset(&p, 0, sizeof(p)); 3103 p.type = SCHED_CLASS_TYPE_PACKET; 3104 p.u.params.level = SCHED_CLASS_LEVEL_CL_RL; 3105 p.u.params.mode = SCHED_CLASS_MODE_CLASS; 3106 p.u.params.rateunit = SCHED_CLASS_RATEUNIT_BITS; 3107 p.u.params.ratemode = SCHED_CLASS_RATEMODE_ABS; 3108 p.u.params.channel = pi->tx_chan; 3109 p.u.params.class = SCHED_CLS_NONE; 3110 p.u.params.minrate = 0; 3111 p.u.params.maxrate = req_rate; 3112 p.u.params.weight = 0; 3113 p.u.params.pktsize = dev->mtu; 3114 3115 e = cxgb4_sched_class_alloc(dev, &p); 3116 if (!e) 3117 return -ENOMEM; 3118 3119 /* Bind the queue to a scheduling class */ 3120 memset(&qe, 0, sizeof(qe)); 3121 qe.queue = index; 3122 qe.class = e->idx; 3123 3124 err = cxgb4_sched_class_bind(dev, (void *)(&qe), SCHED_QUEUE); 3125 if (err) 3126 dev_err(adap->pdev_dev, 3127 "Queue rate limiting failed. Err: %d\n", err); 3128 return err; 3129 } 3130 3131 static int cxgb_setup_tc_flower(struct net_device *dev, 3132 struct tc_cls_flower_offload *cls_flower) 3133 { 3134 switch (cls_flower->command) { 3135 case TC_CLSFLOWER_REPLACE: 3136 return cxgb4_tc_flower_replace(dev, cls_flower); 3137 case TC_CLSFLOWER_DESTROY: 3138 return cxgb4_tc_flower_destroy(dev, cls_flower); 3139 case TC_CLSFLOWER_STATS: 3140 return cxgb4_tc_flower_stats(dev, cls_flower); 3141 default: 3142 return -EOPNOTSUPP; 3143 } 3144 } 3145 3146 static int cxgb_setup_tc_cls_u32(struct net_device *dev, 3147 struct tc_cls_u32_offload *cls_u32) 3148 { 3149 switch (cls_u32->command) { 3150 case TC_CLSU32_NEW_KNODE: 3151 case TC_CLSU32_REPLACE_KNODE: 3152 return cxgb4_config_knode(dev, cls_u32); 3153 case TC_CLSU32_DELETE_KNODE: 3154 return cxgb4_delete_knode(dev, cls_u32); 3155 default: 3156 return -EOPNOTSUPP; 3157 } 3158 } 3159 3160 static int cxgb_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3161 void *cb_priv) 3162 { 3163 struct net_device *dev = cb_priv; 3164 struct port_info *pi = netdev2pinfo(dev); 3165 struct adapter *adap = netdev2adap(dev); 3166 3167 if (!(adap->flags & CXGB4_FULL_INIT_DONE)) { 3168 dev_err(adap->pdev_dev, 3169 "Failed to setup tc on port %d. Link Down?\n", 3170 pi->port_id); 3171 return -EINVAL; 3172 } 3173 3174 if (!tc_cls_can_offload_and_chain0(dev, type_data)) 3175 return -EOPNOTSUPP; 3176 3177 switch (type) { 3178 case TC_SETUP_CLSU32: 3179 return cxgb_setup_tc_cls_u32(dev, type_data); 3180 case TC_SETUP_CLSFLOWER: 3181 return cxgb_setup_tc_flower(dev, type_data); 3182 default: 3183 return -EOPNOTSUPP; 3184 } 3185 } 3186 3187 static int cxgb_setup_tc_block(struct net_device *dev, 3188 struct tc_block_offload *f) 3189 { 3190 struct port_info *pi = netdev2pinfo(dev); 3191 3192 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) 3193 return -EOPNOTSUPP; 3194 3195 switch (f->command) { 3196 case TC_BLOCK_BIND: 3197 return tcf_block_cb_register(f->block, cxgb_setup_tc_block_cb, 3198 pi, dev, f->extack); 3199 case TC_BLOCK_UNBIND: 3200 tcf_block_cb_unregister(f->block, cxgb_setup_tc_block_cb, pi); 3201 return 0; 3202 default: 3203 return -EOPNOTSUPP; 3204 } 3205 } 3206 3207 static int cxgb_setup_tc(struct net_device *dev, enum tc_setup_type type, 3208 void *type_data) 3209 { 3210 switch (type) { 3211 case TC_SETUP_BLOCK: 3212 return cxgb_setup_tc_block(dev, type_data); 3213 default: 3214 return -EOPNOTSUPP; 3215 } 3216 } 3217 3218 static void cxgb_del_udp_tunnel(struct net_device *netdev, 3219 struct udp_tunnel_info *ti) 3220 { 3221 struct port_info *pi = netdev_priv(netdev); 3222 struct adapter *adapter = pi->adapter; 3223 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3224 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3225 int ret = 0, i; 3226 3227 if (chip_ver < CHELSIO_T6) 3228 return; 3229 3230 switch (ti->type) { 3231 case UDP_TUNNEL_TYPE_VXLAN: 3232 if (!adapter->vxlan_port_cnt || 3233 adapter->vxlan_port != ti->port) 3234 return; /* Invalid VxLAN destination port */ 3235 3236 adapter->vxlan_port_cnt--; 3237 if (adapter->vxlan_port_cnt) 3238 return; 3239 3240 adapter->vxlan_port = 0; 3241 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 0); 3242 break; 3243 case UDP_TUNNEL_TYPE_GENEVE: 3244 if (!adapter->geneve_port_cnt || 3245 adapter->geneve_port != ti->port) 3246 return; /* Invalid GENEVE destination port */ 3247 3248 adapter->geneve_port_cnt--; 3249 if (adapter->geneve_port_cnt) 3250 return; 3251 3252 adapter->geneve_port = 0; 3253 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 0); 3254 break; 3255 default: 3256 return; 3257 } 3258 3259 /* Matchall mac entries can be deleted only after all tunnel ports 3260 * are brought down or removed. 3261 */ 3262 if (!adapter->rawf_cnt) 3263 return; 3264 for_each_port(adapter, i) { 3265 pi = adap2pinfo(adapter, i); 3266 ret = t4_free_raw_mac_filt(adapter, pi->viid, 3267 match_all_mac, match_all_mac, 3268 adapter->rawf_start + 3269 pi->port_id, 3270 1, pi->port_id, false); 3271 if (ret < 0) { 3272 netdev_info(netdev, "Failed to free mac filter entry, for port %d\n", 3273 i); 3274 return; 3275 } 3276 atomic_dec(&adapter->mps_encap[adapter->rawf_start + 3277 pi->port_id].refcnt); 3278 } 3279 } 3280 3281 static void cxgb_add_udp_tunnel(struct net_device *netdev, 3282 struct udp_tunnel_info *ti) 3283 { 3284 struct port_info *pi = netdev_priv(netdev); 3285 struct adapter *adapter = pi->adapter; 3286 unsigned int chip_ver = CHELSIO_CHIP_VERSION(adapter->params.chip); 3287 u8 match_all_mac[] = { 0, 0, 0, 0, 0, 0 }; 3288 int i, ret; 3289 3290 if (chip_ver < CHELSIO_T6 || !adapter->rawf_cnt) 3291 return; 3292 3293 switch (ti->type) { 3294 case UDP_TUNNEL_TYPE_VXLAN: 3295 /* Callback for adding vxlan port can be called with the same 3296 * port for both IPv4 and IPv6. We should not disable the 3297 * offloading when the same port for both protocols is added 3298 * and later one of them is removed. 3299 */ 3300 if (adapter->vxlan_port_cnt && 3301 adapter->vxlan_port == ti->port) { 3302 adapter->vxlan_port_cnt++; 3303 return; 3304 } 3305 3306 /* We will support only one VxLAN port */ 3307 if (adapter->vxlan_port_cnt) { 3308 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3309 be16_to_cpu(adapter->vxlan_port), 3310 be16_to_cpu(ti->port)); 3311 return; 3312 } 3313 3314 adapter->vxlan_port = ti->port; 3315 adapter->vxlan_port_cnt = 1; 3316 3317 t4_write_reg(adapter, MPS_RX_VXLAN_TYPE_A, 3318 VXLAN_V(be16_to_cpu(ti->port)) | VXLAN_EN_F); 3319 break; 3320 case UDP_TUNNEL_TYPE_GENEVE: 3321 if (adapter->geneve_port_cnt && 3322 adapter->geneve_port == ti->port) { 3323 adapter->geneve_port_cnt++; 3324 return; 3325 } 3326 3327 /* We will support only one GENEVE port */ 3328 if (adapter->geneve_port_cnt) { 3329 netdev_info(netdev, "UDP port %d already offloaded, not adding port %d\n", 3330 be16_to_cpu(adapter->geneve_port), 3331 be16_to_cpu(ti->port)); 3332 return; 3333 } 3334 3335 adapter->geneve_port = ti->port; 3336 adapter->geneve_port_cnt = 1; 3337 3338 t4_write_reg(adapter, MPS_RX_GENEVE_TYPE_A, 3339 GENEVE_V(be16_to_cpu(ti->port)) | GENEVE_EN_F); 3340 break; 3341 default: 3342 return; 3343 } 3344 3345 /* Create a 'match all' mac filter entry for inner mac, 3346 * if raw mac interface is supported. Once the linux kernel provides 3347 * driver entry points for adding/deleting the inner mac addresses, 3348 * we will remove this 'match all' entry and fallback to adding 3349 * exact match filters. 3350 */ 3351 for_each_port(adapter, i) { 3352 pi = adap2pinfo(adapter, i); 3353 3354 ret = t4_alloc_raw_mac_filt(adapter, pi->viid, 3355 match_all_mac, 3356 match_all_mac, 3357 adapter->rawf_start + 3358 pi->port_id, 3359 1, pi->port_id, false); 3360 if (ret < 0) { 3361 netdev_info(netdev, "Failed to allocate a mac filter entry, not adding port %d\n", 3362 be16_to_cpu(ti->port)); 3363 cxgb_del_udp_tunnel(netdev, ti); 3364 return; 3365 } 3366 atomic_inc(&adapter->mps_encap[ret].refcnt); 3367 } 3368 } 3369 3370 static netdev_features_t cxgb_features_check(struct sk_buff *skb, 3371 struct net_device *dev, 3372 netdev_features_t features) 3373 { 3374 struct port_info *pi = netdev_priv(dev); 3375 struct adapter *adapter = pi->adapter; 3376 3377 if (CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3378 return features; 3379 3380 /* Check if hw supports offload for this packet */ 3381 if (!skb->encapsulation || cxgb_encap_offload_supported(skb)) 3382 return features; 3383 3384 /* Offload is not supported for this encapsulated packet */ 3385 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 3386 } 3387 3388 static netdev_features_t cxgb_fix_features(struct net_device *dev, 3389 netdev_features_t features) 3390 { 3391 /* Disable GRO, if RX_CSUM is disabled */ 3392 if (!(features & NETIF_F_RXCSUM)) 3393 features &= ~NETIF_F_GRO; 3394 3395 return features; 3396 } 3397 3398 static const struct net_device_ops cxgb4_netdev_ops = { 3399 .ndo_open = cxgb_open, 3400 .ndo_stop = cxgb_close, 3401 .ndo_start_xmit = t4_start_xmit, 3402 .ndo_select_queue = cxgb_select_queue, 3403 .ndo_get_stats64 = cxgb_get_stats, 3404 .ndo_set_rx_mode = cxgb_set_rxmode, 3405 .ndo_set_mac_address = cxgb_set_mac_addr, 3406 .ndo_set_features = cxgb_set_features, 3407 .ndo_validate_addr = eth_validate_addr, 3408 .ndo_do_ioctl = cxgb_ioctl, 3409 .ndo_change_mtu = cxgb_change_mtu, 3410 #ifdef CONFIG_NET_POLL_CONTROLLER 3411 .ndo_poll_controller = cxgb_netpoll, 3412 #endif 3413 #ifdef CONFIG_CHELSIO_T4_FCOE 3414 .ndo_fcoe_enable = cxgb_fcoe_enable, 3415 .ndo_fcoe_disable = cxgb_fcoe_disable, 3416 #endif /* CONFIG_CHELSIO_T4_FCOE */ 3417 .ndo_set_tx_maxrate = cxgb_set_tx_maxrate, 3418 .ndo_setup_tc = cxgb_setup_tc, 3419 .ndo_udp_tunnel_add = cxgb_add_udp_tunnel, 3420 .ndo_udp_tunnel_del = cxgb_del_udp_tunnel, 3421 .ndo_features_check = cxgb_features_check, 3422 .ndo_fix_features = cxgb_fix_features, 3423 }; 3424 3425 #ifdef CONFIG_PCI_IOV 3426 static const struct net_device_ops cxgb4_mgmt_netdev_ops = { 3427 .ndo_open = cxgb4_mgmt_open, 3428 .ndo_set_vf_mac = cxgb4_mgmt_set_vf_mac, 3429 .ndo_get_vf_config = cxgb4_mgmt_get_vf_config, 3430 .ndo_set_vf_rate = cxgb4_mgmt_set_vf_rate, 3431 .ndo_get_phys_port_id = cxgb4_mgmt_get_phys_port_id, 3432 .ndo_set_vf_vlan = cxgb4_mgmt_set_vf_vlan, 3433 .ndo_set_vf_link_state = cxgb4_mgmt_set_vf_link_state, 3434 }; 3435 #endif 3436 3437 static void cxgb4_mgmt_get_drvinfo(struct net_device *dev, 3438 struct ethtool_drvinfo *info) 3439 { 3440 struct adapter *adapter = netdev2adap(dev); 3441 3442 strlcpy(info->driver, cxgb4_driver_name, sizeof(info->driver)); 3443 strlcpy(info->version, cxgb4_driver_version, 3444 sizeof(info->version)); 3445 strlcpy(info->bus_info, pci_name(adapter->pdev), 3446 sizeof(info->bus_info)); 3447 } 3448 3449 static const struct ethtool_ops cxgb4_mgmt_ethtool_ops = { 3450 .get_drvinfo = cxgb4_mgmt_get_drvinfo, 3451 }; 3452 3453 static void notify_fatal_err(struct work_struct *work) 3454 { 3455 struct adapter *adap; 3456 3457 adap = container_of(work, struct adapter, fatal_err_notify_task); 3458 notify_ulds(adap, CXGB4_STATE_FATAL_ERROR); 3459 } 3460 3461 void t4_fatal_err(struct adapter *adap) 3462 { 3463 int port; 3464 3465 if (pci_channel_offline(adap->pdev)) 3466 return; 3467 3468 /* Disable the SGE since ULDs are going to free resources that 3469 * could be exposed to the adapter. RDMA MWs for example... 3470 */ 3471 t4_shutdown_adapter(adap); 3472 for_each_port(adap, port) { 3473 struct net_device *dev = adap->port[port]; 3474 3475 /* If we get here in very early initialization the network 3476 * devices may not have been set up yet. 3477 */ 3478 if (!dev) 3479 continue; 3480 3481 netif_tx_stop_all_queues(dev); 3482 netif_carrier_off(dev); 3483 } 3484 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n"); 3485 queue_work(adap->workq, &adap->fatal_err_notify_task); 3486 } 3487 3488 static void setup_memwin(struct adapter *adap) 3489 { 3490 u32 nic_win_base = t4_get_util_window(adap); 3491 3492 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC); 3493 } 3494 3495 static void setup_memwin_rdma(struct adapter *adap) 3496 { 3497 if (adap->vres.ocq.size) { 3498 u32 start; 3499 unsigned int sz_kb; 3500 3501 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2); 3502 start &= PCI_BASE_ADDRESS_MEM_MASK; 3503 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres); 3504 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10; 3505 t4_write_reg(adap, 3506 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3), 3507 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb))); 3508 t4_write_reg(adap, 3509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3), 3510 adap->vres.ocq.start); 3511 t4_read_reg(adap, 3512 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3)); 3513 } 3514 } 3515 3516 /* HMA Definitions */ 3517 3518 /* The maximum number of address that can be send in a single FW cmd */ 3519 #define HMA_MAX_ADDR_IN_CMD 5 3520 3521 #define HMA_PAGE_SIZE PAGE_SIZE 3522 3523 #define HMA_MAX_NO_FW_ADDRESS (16 << 10) /* FW supports 16K addresses */ 3524 3525 #define HMA_PAGE_ORDER \ 3526 ((HMA_PAGE_SIZE < HMA_MAX_NO_FW_ADDRESS) ? \ 3527 ilog2(HMA_MAX_NO_FW_ADDRESS / HMA_PAGE_SIZE) : 0) 3528 3529 /* The minimum and maximum possible HMA sizes that can be specified in the FW 3530 * configuration(in units of MB). 3531 */ 3532 #define HMA_MIN_TOTAL_SIZE 1 3533 #define HMA_MAX_TOTAL_SIZE \ 3534 (((HMA_PAGE_SIZE << HMA_PAGE_ORDER) * \ 3535 HMA_MAX_NO_FW_ADDRESS) >> 20) 3536 3537 static void adap_free_hma_mem(struct adapter *adapter) 3538 { 3539 struct scatterlist *iter; 3540 struct page *page; 3541 int i; 3542 3543 if (!adapter->hma.sgt) 3544 return; 3545 3546 if (adapter->hma.flags & HMA_DMA_MAPPED_FLAG) { 3547 dma_unmap_sg(adapter->pdev_dev, adapter->hma.sgt->sgl, 3548 adapter->hma.sgt->nents, PCI_DMA_BIDIRECTIONAL); 3549 adapter->hma.flags &= ~HMA_DMA_MAPPED_FLAG; 3550 } 3551 3552 for_each_sg(adapter->hma.sgt->sgl, iter, 3553 adapter->hma.sgt->orig_nents, i) { 3554 page = sg_page(iter); 3555 if (page) 3556 __free_pages(page, HMA_PAGE_ORDER); 3557 } 3558 3559 kfree(adapter->hma.phy_addr); 3560 sg_free_table(adapter->hma.sgt); 3561 kfree(adapter->hma.sgt); 3562 adapter->hma.sgt = NULL; 3563 } 3564 3565 static int adap_config_hma(struct adapter *adapter) 3566 { 3567 struct scatterlist *sgl, *iter; 3568 struct sg_table *sgt; 3569 struct page *newpage; 3570 unsigned int i, j, k; 3571 u32 param, hma_size; 3572 unsigned int ncmds; 3573 size_t page_size; 3574 u32 page_order; 3575 int node, ret; 3576 3577 /* HMA is supported only for T6+ cards. 3578 * Avoid initializing HMA in kdump kernels. 3579 */ 3580 if (is_kdump_kernel() || 3581 CHELSIO_CHIP_VERSION(adapter->params.chip) < CHELSIO_T6) 3582 return 0; 3583 3584 /* Get the HMA region size required by fw */ 3585 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 3586 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HMA_SIZE)); 3587 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3588 1, ¶m, &hma_size); 3589 /* An error means card has its own memory or HMA is not supported by 3590 * the firmware. Return without any errors. 3591 */ 3592 if (ret || !hma_size) 3593 return 0; 3594 3595 if (hma_size < HMA_MIN_TOTAL_SIZE || 3596 hma_size > HMA_MAX_TOTAL_SIZE) { 3597 dev_err(adapter->pdev_dev, 3598 "HMA size %uMB beyond bounds(%u-%lu)MB\n", 3599 hma_size, HMA_MIN_TOTAL_SIZE, HMA_MAX_TOTAL_SIZE); 3600 return -EINVAL; 3601 } 3602 3603 page_size = HMA_PAGE_SIZE; 3604 page_order = HMA_PAGE_ORDER; 3605 adapter->hma.sgt = kzalloc(sizeof(*adapter->hma.sgt), GFP_KERNEL); 3606 if (unlikely(!adapter->hma.sgt)) { 3607 dev_err(adapter->pdev_dev, "HMA SG table allocation failed\n"); 3608 return -ENOMEM; 3609 } 3610 sgt = adapter->hma.sgt; 3611 /* FW returned value will be in MB's 3612 */ 3613 sgt->orig_nents = (hma_size << 20) / (page_size << page_order); 3614 if (sg_alloc_table(sgt, sgt->orig_nents, GFP_KERNEL)) { 3615 dev_err(adapter->pdev_dev, "HMA SGL allocation failed\n"); 3616 kfree(adapter->hma.sgt); 3617 adapter->hma.sgt = NULL; 3618 return -ENOMEM; 3619 } 3620 3621 sgl = adapter->hma.sgt->sgl; 3622 node = dev_to_node(adapter->pdev_dev); 3623 for_each_sg(sgl, iter, sgt->orig_nents, i) { 3624 newpage = alloc_pages_node(node, __GFP_NOWARN | GFP_KERNEL | 3625 __GFP_ZERO, page_order); 3626 if (!newpage) { 3627 dev_err(adapter->pdev_dev, 3628 "Not enough memory for HMA page allocation\n"); 3629 ret = -ENOMEM; 3630 goto free_hma; 3631 } 3632 sg_set_page(iter, newpage, page_size << page_order, 0); 3633 } 3634 3635 sgt->nents = dma_map_sg(adapter->pdev_dev, sgl, sgt->orig_nents, 3636 DMA_BIDIRECTIONAL); 3637 if (!sgt->nents) { 3638 dev_err(adapter->pdev_dev, 3639 "Not enough memory for HMA DMA mapping"); 3640 ret = -ENOMEM; 3641 goto free_hma; 3642 } 3643 adapter->hma.flags |= HMA_DMA_MAPPED_FLAG; 3644 3645 adapter->hma.phy_addr = kcalloc(sgt->nents, sizeof(dma_addr_t), 3646 GFP_KERNEL); 3647 if (unlikely(!adapter->hma.phy_addr)) 3648 goto free_hma; 3649 3650 for_each_sg(sgl, iter, sgt->nents, i) { 3651 newpage = sg_page(iter); 3652 adapter->hma.phy_addr[i] = sg_dma_address(iter); 3653 } 3654 3655 ncmds = DIV_ROUND_UP(sgt->nents, HMA_MAX_ADDR_IN_CMD); 3656 /* Pass on the addresses to firmware */ 3657 for (i = 0, k = 0; i < ncmds; i++, k += HMA_MAX_ADDR_IN_CMD) { 3658 struct fw_hma_cmd hma_cmd; 3659 u8 naddr = HMA_MAX_ADDR_IN_CMD; 3660 u8 soc = 0, eoc = 0; 3661 u8 hma_mode = 1; /* Presently we support only Page table mode */ 3662 3663 soc = (i == 0) ? 1 : 0; 3664 eoc = (i == ncmds - 1) ? 1 : 0; 3665 3666 /* For last cmd, set naddr corresponding to remaining 3667 * addresses 3668 */ 3669 if (i == ncmds - 1) { 3670 naddr = sgt->nents % HMA_MAX_ADDR_IN_CMD; 3671 naddr = naddr ? naddr : HMA_MAX_ADDR_IN_CMD; 3672 } 3673 memset(&hma_cmd, 0, sizeof(hma_cmd)); 3674 hma_cmd.op_pkd = htonl(FW_CMD_OP_V(FW_HMA_CMD) | 3675 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3676 hma_cmd.retval_len16 = htonl(FW_LEN16(hma_cmd)); 3677 3678 hma_cmd.mode_to_pcie_params = 3679 htonl(FW_HMA_CMD_MODE_V(hma_mode) | 3680 FW_HMA_CMD_SOC_V(soc) | FW_HMA_CMD_EOC_V(eoc)); 3681 3682 /* HMA cmd size specified in MB's */ 3683 hma_cmd.naddr_size = 3684 htonl(FW_HMA_CMD_SIZE_V(hma_size) | 3685 FW_HMA_CMD_NADDR_V(naddr)); 3686 3687 /* Total Page size specified in units of 4K */ 3688 hma_cmd.addr_size_pkd = 3689 htonl(FW_HMA_CMD_ADDR_SIZE_V 3690 ((page_size << page_order) >> 12)); 3691 3692 /* Fill the 5 addresses */ 3693 for (j = 0; j < naddr; j++) { 3694 hma_cmd.phy_address[j] = 3695 cpu_to_be64(adapter->hma.phy_addr[j + k]); 3696 } 3697 ret = t4_wr_mbox(adapter, adapter->mbox, &hma_cmd, 3698 sizeof(hma_cmd), &hma_cmd); 3699 if (ret) { 3700 dev_err(adapter->pdev_dev, 3701 "HMA FW command failed with err %d\n", ret); 3702 goto free_hma; 3703 } 3704 } 3705 3706 if (!ret) 3707 dev_info(adapter->pdev_dev, 3708 "Reserved %uMB host memory for HMA\n", hma_size); 3709 return ret; 3710 3711 free_hma: 3712 adap_free_hma_mem(adapter); 3713 return ret; 3714 } 3715 3716 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c) 3717 { 3718 u32 v; 3719 int ret; 3720 3721 /* Now that we've successfully configured and initialized the adapter 3722 * can ask the Firmware what resources it has provisioned for us. 3723 */ 3724 ret = t4_get_pfres(adap); 3725 if (ret) { 3726 dev_err(adap->pdev_dev, 3727 "Unable to retrieve resource provisioning information\n"); 3728 return ret; 3729 } 3730 3731 /* get device capabilities */ 3732 memset(c, 0, sizeof(*c)); 3733 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3734 FW_CMD_REQUEST_F | FW_CMD_READ_F); 3735 c->cfvalid_to_len16 = htonl(FW_LEN16(*c)); 3736 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c); 3737 if (ret < 0) 3738 return ret; 3739 3740 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 3741 FW_CMD_REQUEST_F | FW_CMD_WRITE_F); 3742 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL); 3743 if (ret < 0) 3744 return ret; 3745 3746 ret = t4_config_glbl_rss(adap, adap->pf, 3747 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL, 3748 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F | 3749 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F); 3750 if (ret < 0) 3751 return ret; 3752 3753 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64, 3754 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, 3755 FW_CMD_CAP_PF); 3756 if (ret < 0) 3757 return ret; 3758 3759 t4_sge_init(adap); 3760 3761 /* tweak some settings */ 3762 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849); 3763 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12)); 3764 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A); 3765 v = t4_read_reg(adap, TP_PIO_DATA_A); 3766 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F); 3767 3768 /* first 4 Tx modulation queues point to consecutive Tx channels */ 3769 adap->params.tp.tx_modq_map = 0xE4; 3770 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A, 3771 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map)); 3772 3773 /* associate each Tx modulation queue with consecutive Tx channels */ 3774 v = 0x84218421; 3775 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3776 &v, 1, TP_TX_SCHED_HDR_A); 3777 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3778 &v, 1, TP_TX_SCHED_FIFO_A); 3779 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, 3780 &v, 1, TP_TX_SCHED_PCMD_A); 3781 3782 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 3783 if (is_offload(adap)) { 3784 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A, 3785 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3786 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3787 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3788 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3789 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A, 3790 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3791 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3792 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) | 3793 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT)); 3794 } 3795 3796 /* get basic stuff going */ 3797 return t4_early_init(adap, adap->pf); 3798 } 3799 3800 /* 3801 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower. 3802 */ 3803 #define MAX_ATIDS 8192U 3804 3805 /* 3806 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 3807 * 3808 * If the firmware we're dealing with has Configuration File support, then 3809 * we use that to perform all configuration 3810 */ 3811 3812 /* 3813 * Tweak configuration based on module parameters, etc. Most of these have 3814 * defaults assigned to them by Firmware Configuration Files (if we're using 3815 * them) but need to be explicitly set if we're using hard-coded 3816 * initialization. But even in the case of using Firmware Configuration 3817 * Files, we'd like to expose the ability to change these via module 3818 * parameters so these are essentially common tweaks/settings for 3819 * Configuration Files and hard-coded initialization ... 3820 */ 3821 static int adap_init0_tweaks(struct adapter *adapter) 3822 { 3823 /* 3824 * Fix up various Host-Dependent Parameters like Page Size, Cache 3825 * Line Size, etc. The firmware default is for a 4KB Page Size and 3826 * 64B Cache Line Size ... 3827 */ 3828 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES); 3829 3830 /* 3831 * Process module parameters which affect early initialization. 3832 */ 3833 if (rx_dma_offset != 2 && rx_dma_offset != 0) { 3834 dev_err(&adapter->pdev->dev, 3835 "Ignoring illegal rx_dma_offset=%d, using 2\n", 3836 rx_dma_offset); 3837 rx_dma_offset = 2; 3838 } 3839 t4_set_reg_field(adapter, SGE_CONTROL_A, 3840 PKTSHIFT_V(PKTSHIFT_M), 3841 PKTSHIFT_V(rx_dma_offset)); 3842 3843 /* 3844 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 3845 * adds the pseudo header itself. 3846 */ 3847 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A, 3848 CSUM_HAS_PSEUDO_HDR_F, 0); 3849 3850 return 0; 3851 } 3852 3853 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips 3854 * unto themselves and they contain their own firmware to perform their 3855 * tasks ... 3856 */ 3857 static int phy_aq1202_version(const u8 *phy_fw_data, 3858 size_t phy_fw_size) 3859 { 3860 int offset; 3861 3862 /* At offset 0x8 you're looking for the primary image's 3863 * starting offset which is 3 Bytes wide 3864 * 3865 * At offset 0xa of the primary image, you look for the offset 3866 * of the DRAM segment which is 3 Bytes wide. 3867 * 3868 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes 3869 * wide 3870 */ 3871 #define be16(__p) (((__p)[0] << 8) | (__p)[1]) 3872 #define le16(__p) ((__p)[0] | ((__p)[1] << 8)) 3873 #define le24(__p) (le16(__p) | ((__p)[2] << 16)) 3874 3875 offset = le24(phy_fw_data + 0x8) << 12; 3876 offset = le24(phy_fw_data + offset + 0xa); 3877 return be16(phy_fw_data + offset + 0x27e); 3878 3879 #undef be16 3880 #undef le16 3881 #undef le24 3882 } 3883 3884 static struct info_10gbt_phy_fw { 3885 unsigned int phy_fw_id; /* PCI Device ID */ 3886 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */ 3887 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size); 3888 int phy_flash; /* Has FLASH for PHY Firmware */ 3889 } phy_info_array[] = { 3890 { 3891 PHY_AQ1202_DEVICEID, 3892 PHY_AQ1202_FIRMWARE, 3893 phy_aq1202_version, 3894 1, 3895 }, 3896 { 3897 PHY_BCM84834_DEVICEID, 3898 PHY_BCM84834_FIRMWARE, 3899 NULL, 3900 0, 3901 }, 3902 { 0, NULL, NULL }, 3903 }; 3904 3905 static struct info_10gbt_phy_fw *find_phy_info(int devid) 3906 { 3907 int i; 3908 3909 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) { 3910 if (phy_info_array[i].phy_fw_id == devid) 3911 return &phy_info_array[i]; 3912 } 3913 return NULL; 3914 } 3915 3916 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to 3917 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error 3918 * we return a negative error number. If we transfer new firmware we return 1 3919 * (from t4_load_phy_fw()). If we don't do anything we return 0. 3920 */ 3921 static int adap_init0_phy(struct adapter *adap) 3922 { 3923 const struct firmware *phyf; 3924 int ret; 3925 struct info_10gbt_phy_fw *phy_info; 3926 3927 /* Use the device ID to determine which PHY file to flash. 3928 */ 3929 phy_info = find_phy_info(adap->pdev->device); 3930 if (!phy_info) { 3931 dev_warn(adap->pdev_dev, 3932 "No PHY Firmware file found for this PHY\n"); 3933 return -EOPNOTSUPP; 3934 } 3935 3936 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then 3937 * use that. The adapter firmware provides us with a memory buffer 3938 * where we can load a PHY firmware file from the host if we want to 3939 * override the PHY firmware File in flash. 3940 */ 3941 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file, 3942 adap->pdev_dev); 3943 if (ret < 0) { 3944 /* For adapters without FLASH attached to PHY for their 3945 * firmware, it's obviously a fatal error if we can't get the 3946 * firmware to the adapter. For adapters with PHY firmware 3947 * FLASH storage, it's worth a warning if we can't find the 3948 * PHY Firmware but we'll neuter the error ... 3949 */ 3950 dev_err(adap->pdev_dev, "unable to find PHY Firmware image " 3951 "/lib/firmware/%s, error %d\n", 3952 phy_info->phy_fw_file, -ret); 3953 if (phy_info->phy_flash) { 3954 int cur_phy_fw_ver = 0; 3955 3956 t4_phy_fw_ver(adap, &cur_phy_fw_ver); 3957 dev_warn(adap->pdev_dev, "continuing with, on-adapter " 3958 "FLASH copy, version %#x\n", cur_phy_fw_ver); 3959 ret = 0; 3960 } 3961 3962 return ret; 3963 } 3964 3965 /* Load PHY Firmware onto adapter. 3966 */ 3967 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock, 3968 phy_info->phy_fw_version, 3969 (u8 *)phyf->data, phyf->size); 3970 if (ret < 0) 3971 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n", 3972 -ret); 3973 else if (ret > 0) { 3974 int new_phy_fw_ver = 0; 3975 3976 if (phy_info->phy_fw_version) 3977 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data, 3978 phyf->size); 3979 dev_info(adap->pdev_dev, "Successfully transferred PHY " 3980 "Firmware /lib/firmware/%s, version %#x\n", 3981 phy_info->phy_fw_file, new_phy_fw_ver); 3982 } 3983 3984 release_firmware(phyf); 3985 3986 return ret; 3987 } 3988 3989 /* 3990 * Attempt to initialize the adapter via a Firmware Configuration File. 3991 */ 3992 static int adap_init0_config(struct adapter *adapter, int reset) 3993 { 3994 char *fw_config_file, fw_config_file_path[256]; 3995 u32 finiver, finicsum, cfcsum, param, val; 3996 struct fw_caps_config_cmd caps_cmd; 3997 unsigned long mtype = 0, maddr = 0; 3998 const struct firmware *cf; 3999 char *config_name = NULL; 4000 int config_issued = 0; 4001 int ret; 4002 4003 /* 4004 * Reset device if necessary. 4005 */ 4006 if (reset) { 4007 ret = t4_fw_reset(adapter, adapter->mbox, 4008 PIORSTMODE_F | PIORST_F); 4009 if (ret < 0) 4010 goto bye; 4011 } 4012 4013 /* If this is a 10Gb/s-BT adapter make sure the chip-external 4014 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs 4015 * to be performed after any global adapter RESET above since some 4016 * PHYs only have local RAM copies of the PHY firmware. 4017 */ 4018 if (is_10gbt_device(adapter->pdev->device)) { 4019 ret = adap_init0_phy(adapter); 4020 if (ret < 0) 4021 goto bye; 4022 } 4023 /* 4024 * If we have a T4 configuration file under /lib/firmware/cxgb4/, 4025 * then use that. Otherwise, use the configuration file stored 4026 * in the adapter flash ... 4027 */ 4028 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) { 4029 case CHELSIO_T4: 4030 fw_config_file = FW4_CFNAME; 4031 break; 4032 case CHELSIO_T5: 4033 fw_config_file = FW5_CFNAME; 4034 break; 4035 case CHELSIO_T6: 4036 fw_config_file = FW6_CFNAME; 4037 break; 4038 default: 4039 dev_err(adapter->pdev_dev, "Device %d is not supported\n", 4040 adapter->pdev->device); 4041 ret = -EINVAL; 4042 goto bye; 4043 } 4044 4045 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev); 4046 if (ret < 0) { 4047 config_name = "On FLASH"; 4048 mtype = FW_MEMTYPE_CF_FLASH; 4049 maddr = t4_flash_cfg_addr(adapter); 4050 } else { 4051 u32 params[7], val[7]; 4052 4053 sprintf(fw_config_file_path, 4054 "/lib/firmware/%s", fw_config_file); 4055 config_name = fw_config_file_path; 4056 4057 if (cf->size >= FLASH_CFG_MAX_SIZE) 4058 ret = -ENOMEM; 4059 else { 4060 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4061 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4062 ret = t4_query_params(adapter, adapter->mbox, 4063 adapter->pf, 0, 1, params, val); 4064 if (ret == 0) { 4065 /* 4066 * For t4_memory_rw() below addresses and 4067 * sizes have to be in terms of multiples of 4 4068 * bytes. So, if the Configuration File isn't 4069 * a multiple of 4 bytes in length we'll have 4070 * to write that out separately since we can't 4071 * guarantee that the bytes following the 4072 * residual byte in the buffer returned by 4073 * request_firmware() are zeroed out ... 4074 */ 4075 size_t resid = cf->size & 0x3; 4076 size_t size = cf->size & ~0x3; 4077 __be32 *data = (__be32 *)cf->data; 4078 4079 mtype = FW_PARAMS_PARAM_Y_G(val[0]); 4080 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16; 4081 4082 spin_lock(&adapter->win0_lock); 4083 ret = t4_memory_rw(adapter, 0, mtype, maddr, 4084 size, data, T4_MEMORY_WRITE); 4085 if (ret == 0 && resid != 0) { 4086 union { 4087 __be32 word; 4088 char buf[4]; 4089 } last; 4090 int i; 4091 4092 last.word = data[size >> 2]; 4093 for (i = resid; i < 4; i++) 4094 last.buf[i] = 0; 4095 ret = t4_memory_rw(adapter, 0, mtype, 4096 maddr + size, 4097 4, &last.word, 4098 T4_MEMORY_WRITE); 4099 } 4100 spin_unlock(&adapter->win0_lock); 4101 } 4102 } 4103 4104 release_firmware(cf); 4105 if (ret) 4106 goto bye; 4107 } 4108 4109 val = 0; 4110 4111 /* Ofld + Hash filter is supported. Older fw will fail this request and 4112 * it is fine. 4113 */ 4114 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4115 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD)); 4116 ret = t4_set_params(adapter, adapter->mbox, adapter->pf, 0, 4117 1, ¶m, &val); 4118 4119 /* FW doesn't know about Hash filter + ofld support, 4120 * it's not a problem, don't return an error. 4121 */ 4122 if (ret < 0) { 4123 dev_warn(adapter->pdev_dev, 4124 "Hash filter with ofld is not supported by FW\n"); 4125 } 4126 4127 /* 4128 * Issue a Capability Configuration command to the firmware to get it 4129 * to parse the Configuration File. We don't use t4_fw_config_file() 4130 * because we want the ability to modify various features after we've 4131 * processed the configuration file ... 4132 */ 4133 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4134 caps_cmd.op_to_write = 4135 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4136 FW_CMD_REQUEST_F | 4137 FW_CMD_READ_F); 4138 caps_cmd.cfvalid_to_len16 = 4139 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F | 4140 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) | 4141 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) | 4142 FW_LEN16(caps_cmd)); 4143 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4144 &caps_cmd); 4145 4146 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware 4147 * Configuration File in FLASH), our last gasp effort is to use the 4148 * Firmware Configuration File which is embedded in the firmware. A 4149 * very few early versions of the firmware didn't have one embedded 4150 * but we can ignore those. 4151 */ 4152 if (ret == -ENOENT) { 4153 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4154 caps_cmd.op_to_write = 4155 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4156 FW_CMD_REQUEST_F | 4157 FW_CMD_READ_F); 4158 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4159 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 4160 sizeof(caps_cmd), &caps_cmd); 4161 config_name = "Firmware Default"; 4162 } 4163 4164 config_issued = 1; 4165 if (ret < 0) 4166 goto bye; 4167 4168 finiver = ntohl(caps_cmd.finiver); 4169 finicsum = ntohl(caps_cmd.finicsum); 4170 cfcsum = ntohl(caps_cmd.cfcsum); 4171 if (finicsum != cfcsum) 4172 dev_warn(adapter->pdev_dev, "Configuration File checksum "\ 4173 "mismatch: [fini] csum=%#x, computed csum=%#x\n", 4174 finicsum, cfcsum); 4175 4176 /* 4177 * And now tell the firmware to use the configuration we just loaded. 4178 */ 4179 caps_cmd.op_to_write = 4180 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4181 FW_CMD_REQUEST_F | 4182 FW_CMD_WRITE_F); 4183 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4184 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 4185 NULL); 4186 if (ret < 0) 4187 goto bye; 4188 4189 /* 4190 * Tweak configuration based on system architecture, module 4191 * parameters, etc. 4192 */ 4193 ret = adap_init0_tweaks(adapter); 4194 if (ret < 0) 4195 goto bye; 4196 4197 /* We will proceed even if HMA init fails. */ 4198 ret = adap_config_hma(adapter); 4199 if (ret) 4200 dev_err(adapter->pdev_dev, 4201 "HMA configuration failed with error %d\n", ret); 4202 4203 if (is_t6(adapter->params.chip)) { 4204 ret = setup_ppod_edram(adapter); 4205 if (!ret) 4206 dev_info(adapter->pdev_dev, "Successfully enabled " 4207 "ppod edram feature\n"); 4208 } 4209 4210 /* 4211 * And finally tell the firmware to initialize itself using the 4212 * parameters from the Configuration File. 4213 */ 4214 ret = t4_fw_initialize(adapter, adapter->mbox); 4215 if (ret < 0) 4216 goto bye; 4217 4218 /* Emit Firmware Configuration File information and return 4219 * successfully. 4220 */ 4221 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\ 4222 "Configuration File \"%s\", version %#x, computed checksum %#x\n", 4223 config_name, finiver, cfcsum); 4224 return 0; 4225 4226 /* 4227 * Something bad happened. Return the error ... (If the "error" 4228 * is that there's no Configuration File on the adapter we don't 4229 * want to issue a warning since this is fairly common.) 4230 */ 4231 bye: 4232 if (config_issued && ret != -ENOENT) 4233 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n", 4234 config_name, -ret); 4235 return ret; 4236 } 4237 4238 static struct fw_info fw_info_array[] = { 4239 { 4240 .chip = CHELSIO_T4, 4241 .fs_name = FW4_CFNAME, 4242 .fw_mod_name = FW4_FNAME, 4243 .fw_hdr = { 4244 .chip = FW_HDR_CHIP_T4, 4245 .fw_ver = __cpu_to_be32(FW_VERSION(T4)), 4246 .intfver_nic = FW_INTFVER(T4, NIC), 4247 .intfver_vnic = FW_INTFVER(T4, VNIC), 4248 .intfver_ri = FW_INTFVER(T4, RI), 4249 .intfver_iscsi = FW_INTFVER(T4, ISCSI), 4250 .intfver_fcoe = FW_INTFVER(T4, FCOE), 4251 }, 4252 }, { 4253 .chip = CHELSIO_T5, 4254 .fs_name = FW5_CFNAME, 4255 .fw_mod_name = FW5_FNAME, 4256 .fw_hdr = { 4257 .chip = FW_HDR_CHIP_T5, 4258 .fw_ver = __cpu_to_be32(FW_VERSION(T5)), 4259 .intfver_nic = FW_INTFVER(T5, NIC), 4260 .intfver_vnic = FW_INTFVER(T5, VNIC), 4261 .intfver_ri = FW_INTFVER(T5, RI), 4262 .intfver_iscsi = FW_INTFVER(T5, ISCSI), 4263 .intfver_fcoe = FW_INTFVER(T5, FCOE), 4264 }, 4265 }, { 4266 .chip = CHELSIO_T6, 4267 .fs_name = FW6_CFNAME, 4268 .fw_mod_name = FW6_FNAME, 4269 .fw_hdr = { 4270 .chip = FW_HDR_CHIP_T6, 4271 .fw_ver = __cpu_to_be32(FW_VERSION(T6)), 4272 .intfver_nic = FW_INTFVER(T6, NIC), 4273 .intfver_vnic = FW_INTFVER(T6, VNIC), 4274 .intfver_ofld = FW_INTFVER(T6, OFLD), 4275 .intfver_ri = FW_INTFVER(T6, RI), 4276 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU), 4277 .intfver_iscsi = FW_INTFVER(T6, ISCSI), 4278 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU), 4279 .intfver_fcoe = FW_INTFVER(T6, FCOE), 4280 }, 4281 } 4282 4283 }; 4284 4285 static struct fw_info *find_fw_info(int chip) 4286 { 4287 int i; 4288 4289 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) { 4290 if (fw_info_array[i].chip == chip) 4291 return &fw_info_array[i]; 4292 } 4293 return NULL; 4294 } 4295 4296 /* 4297 * Phase 0 of initialization: contact FW, obtain config, perform basic init. 4298 */ 4299 static int adap_init0(struct adapter *adap) 4300 { 4301 int ret; 4302 u32 v, port_vec; 4303 enum dev_state state; 4304 u32 params[7], val[7]; 4305 struct fw_caps_config_cmd caps_cmd; 4306 int reset = 1; 4307 4308 /* Grab Firmware Device Log parameters as early as possible so we have 4309 * access to it for debugging, etc. 4310 */ 4311 ret = t4_init_devlog_params(adap); 4312 if (ret < 0) 4313 return ret; 4314 4315 /* Contact FW, advertising Master capability */ 4316 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, 4317 is_kdump_kernel() ? MASTER_MUST : MASTER_MAY, &state); 4318 if (ret < 0) { 4319 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n", 4320 ret); 4321 return ret; 4322 } 4323 if (ret == adap->mbox) 4324 adap->flags |= CXGB4_MASTER_PF; 4325 4326 /* 4327 * If we're the Master PF Driver and the device is uninitialized, 4328 * then let's consider upgrading the firmware ... (We always want 4329 * to check the firmware version number in order to A. get it for 4330 * later reporting and B. to warn if the currently loaded firmware 4331 * is excessively mismatched relative to the driver.) 4332 */ 4333 4334 t4_get_version_info(adap); 4335 ret = t4_check_fw_version(adap); 4336 /* If firmware is too old (not supported by driver) force an update. */ 4337 if (ret) 4338 state = DEV_STATE_UNINIT; 4339 if ((adap->flags & CXGB4_MASTER_PF) && state != DEV_STATE_INIT) { 4340 struct fw_info *fw_info; 4341 struct fw_hdr *card_fw; 4342 const struct firmware *fw; 4343 const u8 *fw_data = NULL; 4344 unsigned int fw_size = 0; 4345 4346 /* This is the firmware whose headers the driver was compiled 4347 * against 4348 */ 4349 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip)); 4350 if (fw_info == NULL) { 4351 dev_err(adap->pdev_dev, 4352 "unable to get firmware info for chip %d.\n", 4353 CHELSIO_CHIP_VERSION(adap->params.chip)); 4354 return -EINVAL; 4355 } 4356 4357 /* allocate memory to read the header of the firmware on the 4358 * card 4359 */ 4360 card_fw = kvzalloc(sizeof(*card_fw), GFP_KERNEL); 4361 if (!card_fw) { 4362 ret = -ENOMEM; 4363 goto bye; 4364 } 4365 4366 /* Get FW from from /lib/firmware/ */ 4367 ret = request_firmware(&fw, fw_info->fw_mod_name, 4368 adap->pdev_dev); 4369 if (ret < 0) { 4370 dev_err(adap->pdev_dev, 4371 "unable to load firmware image %s, error %d\n", 4372 fw_info->fw_mod_name, ret); 4373 } else { 4374 fw_data = fw->data; 4375 fw_size = fw->size; 4376 } 4377 4378 /* upgrade FW logic */ 4379 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw, 4380 state, &reset); 4381 4382 /* Cleaning up */ 4383 release_firmware(fw); 4384 kvfree(card_fw); 4385 4386 if (ret < 0) 4387 goto bye; 4388 } 4389 4390 /* If the firmware is initialized already, emit a simply note to that 4391 * effect. Otherwise, it's time to try initializing the adapter. 4392 */ 4393 if (state == DEV_STATE_INIT) { 4394 ret = adap_config_hma(adap); 4395 if (ret) 4396 dev_err(adap->pdev_dev, 4397 "HMA configuration failed with error %d\n", 4398 ret); 4399 dev_info(adap->pdev_dev, "Coming up as %s: "\ 4400 "Adapter already initialized\n", 4401 adap->flags & CXGB4_MASTER_PF ? "MASTER" : "SLAVE"); 4402 } else { 4403 dev_info(adap->pdev_dev, "Coming up as MASTER: "\ 4404 "Initializing adapter\n"); 4405 4406 /* Find out whether we're dealing with a version of the 4407 * firmware which has configuration file support. 4408 */ 4409 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4410 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF)); 4411 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, 4412 params, val); 4413 4414 /* If the firmware doesn't support Configuration Files, 4415 * return an error. 4416 */ 4417 if (ret < 0) { 4418 dev_err(adap->pdev_dev, "firmware doesn't support " 4419 "Firmware Configuration Files\n"); 4420 goto bye; 4421 } 4422 4423 /* The firmware provides us with a memory buffer where we can 4424 * load a Configuration File from the host if we want to 4425 * override the Configuration File in flash. 4426 */ 4427 ret = adap_init0_config(adap, reset); 4428 if (ret == -ENOENT) { 4429 dev_err(adap->pdev_dev, "no Configuration File " 4430 "present on adapter.\n"); 4431 goto bye; 4432 } 4433 if (ret < 0) { 4434 dev_err(adap->pdev_dev, "could not initialize " 4435 "adapter, error %d\n", -ret); 4436 goto bye; 4437 } 4438 } 4439 4440 /* Now that we've successfully configured and initialized the adapter 4441 * (or found it already initialized), we can ask the Firmware what 4442 * resources it has provisioned for us. 4443 */ 4444 ret = t4_get_pfres(adap); 4445 if (ret) { 4446 dev_err(adap->pdev_dev, 4447 "Unable to retrieve resource provisioning information\n"); 4448 goto bye; 4449 } 4450 4451 /* Grab VPD parameters. This should be done after we establish a 4452 * connection to the firmware since some of the VPD parameters 4453 * (notably the Core Clock frequency) are retrieved via requests to 4454 * the firmware. On the other hand, we need these fairly early on 4455 * so we do this right after getting ahold of the firmware. 4456 * 4457 * We need to do this after initializing the adapter because someone 4458 * could have FLASHed a new VPD which won't be read by the firmware 4459 * until we do the RESET ... 4460 */ 4461 ret = t4_get_vpd_params(adap, &adap->params.vpd); 4462 if (ret < 0) 4463 goto bye; 4464 4465 /* Find out what ports are available to us. Note that we need to do 4466 * this before calling adap_init0_no_config() since it needs nports 4467 * and portvec ... 4468 */ 4469 v = 4470 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4471 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC); 4472 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 4473 if (ret < 0) 4474 goto bye; 4475 4476 adap->params.nports = hweight32(port_vec); 4477 adap->params.portvec = port_vec; 4478 4479 /* Give the SGE code a chance to pull in anything that it needs ... 4480 * Note that this must be called after we retrieve our VPD parameters 4481 * in order to know how to convert core ticks to seconds, etc. 4482 */ 4483 ret = t4_sge_init(adap); 4484 if (ret < 0) 4485 goto bye; 4486 4487 /* Grab the SGE Doorbell Queue Timer values. If successful, that 4488 * indicates that the Firmware and Hardware support this. 4489 */ 4490 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | 4491 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK)); 4492 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4493 1, params, val); 4494 4495 if (!ret) { 4496 adap->sge.dbqtimer_tick = val[0]; 4497 ret = t4_read_sge_dbqtimers(adap, 4498 ARRAY_SIZE(adap->sge.dbqtimer_val), 4499 adap->sge.dbqtimer_val); 4500 } 4501 4502 if (!ret) 4503 adap->flags |= CXGB4_SGE_DBQ_TIMER; 4504 4505 if (is_bypass_device(adap->pdev->device)) 4506 adap->params.bypass = 1; 4507 4508 /* 4509 * Grab some of our basic fundamental operating parameters. 4510 */ 4511 #define FW_PARAM_DEV(param) \ 4512 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \ 4513 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param)) 4514 4515 #define FW_PARAM_PFVF(param) \ 4516 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \ 4517 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \ 4518 FW_PARAMS_PARAM_Y_V(0) | \ 4519 FW_PARAMS_PARAM_Z_V(0) 4520 4521 params[0] = FW_PARAM_PFVF(EQ_START); 4522 params[1] = FW_PARAM_PFVF(L2T_START); 4523 params[2] = FW_PARAM_PFVF(L2T_END); 4524 params[3] = FW_PARAM_PFVF(FILTER_START); 4525 params[4] = FW_PARAM_PFVF(FILTER_END); 4526 params[5] = FW_PARAM_PFVF(IQFLINT_START); 4527 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val); 4528 if (ret < 0) 4529 goto bye; 4530 adap->sge.egr_start = val[0]; 4531 adap->l2t_start = val[1]; 4532 adap->l2t_end = val[2]; 4533 adap->tids.ftid_base = val[3]; 4534 adap->tids.nftids = val[4] - val[3] + 1; 4535 adap->sge.ingr_start = val[5]; 4536 4537 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { 4538 /* Read the raw mps entries. In T6, the last 2 tcam entries 4539 * are reserved for raw mac addresses (rawf = 2, one per port). 4540 */ 4541 params[0] = FW_PARAM_PFVF(RAWF_START); 4542 params[1] = FW_PARAM_PFVF(RAWF_END); 4543 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4544 params, val); 4545 if (ret == 0) { 4546 adap->rawf_start = val[0]; 4547 adap->rawf_cnt = val[1] - val[0] + 1; 4548 } 4549 } 4550 4551 /* qids (ingress/egress) returned from firmware can be anywhere 4552 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END. 4553 * Hence driver needs to allocate memory for this range to 4554 * store the queue info. Get the highest IQFLINT/EQ index returned 4555 * in FW_EQ_*_CMD.alloc command. 4556 */ 4557 params[0] = FW_PARAM_PFVF(EQ_END); 4558 params[1] = FW_PARAM_PFVF(IQFLINT_END); 4559 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4560 if (ret < 0) 4561 goto bye; 4562 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1; 4563 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1; 4564 4565 adap->sge.egr_map = kcalloc(adap->sge.egr_sz, 4566 sizeof(*adap->sge.egr_map), GFP_KERNEL); 4567 if (!adap->sge.egr_map) { 4568 ret = -ENOMEM; 4569 goto bye; 4570 } 4571 4572 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz, 4573 sizeof(*adap->sge.ingr_map), GFP_KERNEL); 4574 if (!adap->sge.ingr_map) { 4575 ret = -ENOMEM; 4576 goto bye; 4577 } 4578 4579 /* Allocate the memory for the vaious egress queue bitmaps 4580 * ie starving_fl, txq_maperr and blocked_fl. 4581 */ 4582 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4583 sizeof(long), GFP_KERNEL); 4584 if (!adap->sge.starving_fl) { 4585 ret = -ENOMEM; 4586 goto bye; 4587 } 4588 4589 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4590 sizeof(long), GFP_KERNEL); 4591 if (!adap->sge.txq_maperr) { 4592 ret = -ENOMEM; 4593 goto bye; 4594 } 4595 4596 #ifdef CONFIG_DEBUG_FS 4597 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz), 4598 sizeof(long), GFP_KERNEL); 4599 if (!adap->sge.blocked_fl) { 4600 ret = -ENOMEM; 4601 goto bye; 4602 } 4603 #endif 4604 4605 params[0] = FW_PARAM_PFVF(CLIP_START); 4606 params[1] = FW_PARAM_PFVF(CLIP_END); 4607 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4608 if (ret < 0) 4609 goto bye; 4610 adap->clipt_start = val[0]; 4611 adap->clipt_end = val[1]; 4612 4613 /* We don't yet have a PARAMs calls to retrieve the number of Traffic 4614 * Classes supported by the hardware/firmware so we hard code it here 4615 * for now. 4616 */ 4617 adap->params.nsched_cls = is_t4(adap->params.chip) ? 15 : 16; 4618 4619 /* query params related to active filter region */ 4620 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START); 4621 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END); 4622 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val); 4623 /* If Active filter size is set we enable establishing 4624 * offload connection through firmware work request 4625 */ 4626 if ((val[0] != val[1]) && (ret >= 0)) { 4627 adap->flags |= CXGB4_FW_OFLD_CONN; 4628 adap->tids.aftid_base = val[0]; 4629 adap->tids.aftid_end = val[1]; 4630 } 4631 4632 /* If we're running on newer firmware, let it know that we're 4633 * prepared to deal with encapsulated CPL messages. Older 4634 * firmware won't understand this and we'll just get 4635 * unencapsulated messages ... 4636 */ 4637 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 4638 val[0] = 1; 4639 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 4640 4641 /* 4642 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 4643 * capability. Earlier versions of the firmware didn't have the 4644 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 4645 * permission to use ULPTX MEMWRITE DSGL. 4646 */ 4647 if (is_t4(adap->params.chip)) { 4648 adap->params.ulptx_memwrite_dsgl = false; 4649 } else { 4650 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 4651 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4652 1, params, val); 4653 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 4654 } 4655 4656 /* See if FW supports FW_RI_FR_NSMR_TPTE_WR work request */ 4657 params[0] = FW_PARAM_DEV(RI_FR_NSMR_TPTE_WR); 4658 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4659 1, params, val); 4660 adap->params.fr_nsmr_tpte_wr_support = (ret == 0 && val[0] != 0); 4661 4662 /* See if FW supports FW_FILTER2 work request */ 4663 if (is_t4(adap->params.chip)) { 4664 adap->params.filter2_wr_support = 0; 4665 } else { 4666 params[0] = FW_PARAM_DEV(FILTER2_WR); 4667 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4668 1, params, val); 4669 adap->params.filter2_wr_support = (ret == 0 && val[0] != 0); 4670 } 4671 4672 /* Check if FW supports returning vin and smt index. 4673 * If this is not supported, driver will interpret 4674 * these values from viid. 4675 */ 4676 params[0] = FW_PARAM_DEV(OPAQUE_VIID_SMT_EXTN); 4677 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4678 1, params, val); 4679 adap->params.viid_smt_extn_support = (ret == 0 && val[0] != 0); 4680 4681 /* 4682 * Get device capabilities so we can determine what resources we need 4683 * to manage. 4684 */ 4685 memset(&caps_cmd, 0, sizeof(caps_cmd)); 4686 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) | 4687 FW_CMD_REQUEST_F | FW_CMD_READ_F); 4688 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 4689 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd), 4690 &caps_cmd); 4691 if (ret < 0) 4692 goto bye; 4693 4694 /* hash filter has some mandatory register settings to be tested and for 4695 * that it needs to test whether offload is enabled or not, hence 4696 * checking and setting it here. 4697 */ 4698 if (caps_cmd.ofldcaps) 4699 adap->params.offload = 1; 4700 4701 if (caps_cmd.ofldcaps || 4702 (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER))) { 4703 /* query offload-related parameters */ 4704 params[0] = FW_PARAM_DEV(NTID); 4705 params[1] = FW_PARAM_PFVF(SERVER_START); 4706 params[2] = FW_PARAM_PFVF(SERVER_END); 4707 params[3] = FW_PARAM_PFVF(TDDP_START); 4708 params[4] = FW_PARAM_PFVF(TDDP_END); 4709 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ); 4710 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4711 params, val); 4712 if (ret < 0) 4713 goto bye; 4714 adap->tids.ntids = val[0]; 4715 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS); 4716 adap->tids.stid_base = val[1]; 4717 adap->tids.nstids = val[2] - val[1] + 1; 4718 /* 4719 * Setup server filter region. Divide the available filter 4720 * region into two parts. Regular filters get 1/3rd and server 4721 * filters get 2/3rd part. This is only enabled if workarond 4722 * path is enabled. 4723 * 1. For regular filters. 4724 * 2. Server filter: This are special filters which are used 4725 * to redirect SYN packets to offload queue. 4726 */ 4727 if (adap->flags & CXGB4_FW_OFLD_CONN && !is_bypass(adap)) { 4728 adap->tids.sftid_base = adap->tids.ftid_base + 4729 DIV_ROUND_UP(adap->tids.nftids, 3); 4730 adap->tids.nsftids = adap->tids.nftids - 4731 DIV_ROUND_UP(adap->tids.nftids, 3); 4732 adap->tids.nftids = adap->tids.sftid_base - 4733 adap->tids.ftid_base; 4734 } 4735 adap->vres.ddp.start = val[3]; 4736 adap->vres.ddp.size = val[4] - val[3] + 1; 4737 adap->params.ofldq_wr_cred = val[5]; 4738 4739 if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_HASHFILTER)) { 4740 init_hash_filter(adap); 4741 } else { 4742 adap->num_ofld_uld += 1; 4743 } 4744 } 4745 if (caps_cmd.rdmacaps) { 4746 params[0] = FW_PARAM_PFVF(STAG_START); 4747 params[1] = FW_PARAM_PFVF(STAG_END); 4748 params[2] = FW_PARAM_PFVF(RQ_START); 4749 params[3] = FW_PARAM_PFVF(RQ_END); 4750 params[4] = FW_PARAM_PFVF(PBL_START); 4751 params[5] = FW_PARAM_PFVF(PBL_END); 4752 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, 4753 params, val); 4754 if (ret < 0) 4755 goto bye; 4756 adap->vres.stag.start = val[0]; 4757 adap->vres.stag.size = val[1] - val[0] + 1; 4758 adap->vres.rq.start = val[2]; 4759 adap->vres.rq.size = val[3] - val[2] + 1; 4760 adap->vres.pbl.start = val[4]; 4761 adap->vres.pbl.size = val[5] - val[4] + 1; 4762 4763 params[0] = FW_PARAM_PFVF(SRQ_START); 4764 params[1] = FW_PARAM_PFVF(SRQ_END); 4765 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4766 params, val); 4767 if (!ret) { 4768 adap->vres.srq.start = val[0]; 4769 adap->vres.srq.size = val[1] - val[0] + 1; 4770 } 4771 if (adap->vres.srq.size) { 4772 adap->srq = t4_init_srq(adap->vres.srq.size); 4773 if (!adap->srq) 4774 dev_warn(&adap->pdev->dev, "could not allocate SRQ, continuing\n"); 4775 } 4776 4777 params[0] = FW_PARAM_PFVF(SQRQ_START); 4778 params[1] = FW_PARAM_PFVF(SQRQ_END); 4779 params[2] = FW_PARAM_PFVF(CQ_START); 4780 params[3] = FW_PARAM_PFVF(CQ_END); 4781 params[4] = FW_PARAM_PFVF(OCQ_START); 4782 params[5] = FW_PARAM_PFVF(OCQ_END); 4783 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, 4784 val); 4785 if (ret < 0) 4786 goto bye; 4787 adap->vres.qp.start = val[0]; 4788 adap->vres.qp.size = val[1] - val[0] + 1; 4789 adap->vres.cq.start = val[2]; 4790 adap->vres.cq.size = val[3] - val[2] + 1; 4791 adap->vres.ocq.start = val[4]; 4792 adap->vres.ocq.size = val[5] - val[4] + 1; 4793 4794 params[0] = FW_PARAM_DEV(MAXORDIRD_QP); 4795 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER); 4796 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, 4797 val); 4798 if (ret < 0) { 4799 adap->params.max_ordird_qp = 8; 4800 adap->params.max_ird_adapter = 32 * adap->tids.ntids; 4801 ret = 0; 4802 } else { 4803 adap->params.max_ordird_qp = val[0]; 4804 adap->params.max_ird_adapter = val[1]; 4805 } 4806 dev_info(adap->pdev_dev, 4807 "max_ordird_qp %d max_ird_adapter %d\n", 4808 adap->params.max_ordird_qp, 4809 adap->params.max_ird_adapter); 4810 4811 /* Enable write_with_immediate if FW supports it */ 4812 params[0] = FW_PARAM_DEV(RDMA_WRITE_WITH_IMM); 4813 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4814 val); 4815 adap->params.write_w_imm_support = (ret == 0 && val[0] != 0); 4816 4817 /* Enable write_cmpl if FW supports it */ 4818 params[0] = FW_PARAM_DEV(RI_WRITE_CMPL_WR); 4819 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, params, 4820 val); 4821 adap->params.write_cmpl_support = (ret == 0 && val[0] != 0); 4822 adap->num_ofld_uld += 2; 4823 } 4824 if (caps_cmd.iscsicaps) { 4825 params[0] = FW_PARAM_PFVF(ISCSI_START); 4826 params[1] = FW_PARAM_PFVF(ISCSI_END); 4827 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4828 params, val); 4829 if (ret < 0) 4830 goto bye; 4831 adap->vres.iscsi.start = val[0]; 4832 adap->vres.iscsi.size = val[1] - val[0] + 1; 4833 if (is_t6(adap->params.chip)) { 4834 params[0] = FW_PARAM_PFVF(PPOD_EDRAM_START); 4835 params[1] = FW_PARAM_PFVF(PPOD_EDRAM_END); 4836 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, 4837 params, val); 4838 if (!ret) { 4839 adap->vres.ppod_edram.start = val[0]; 4840 adap->vres.ppod_edram.size = 4841 val[1] - val[0] + 1; 4842 4843 dev_info(adap->pdev_dev, 4844 "ppod edram start 0x%x end 0x%x size 0x%x\n", 4845 val[0], val[1], 4846 adap->vres.ppod_edram.size); 4847 } 4848 } 4849 /* LIO target and cxgb4i initiaitor */ 4850 adap->num_ofld_uld += 2; 4851 } 4852 if (caps_cmd.cryptocaps) { 4853 if (ntohs(caps_cmd.cryptocaps) & 4854 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE) { 4855 params[0] = FW_PARAM_PFVF(NCRYPTO_LOOKASIDE); 4856 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4857 2, params, val); 4858 if (ret < 0) { 4859 if (ret != -EINVAL) 4860 goto bye; 4861 } else { 4862 adap->vres.ncrypto_fc = val[0]; 4863 } 4864 adap->num_ofld_uld += 1; 4865 } 4866 if (ntohs(caps_cmd.cryptocaps) & 4867 FW_CAPS_CONFIG_TLS_INLINE) { 4868 params[0] = FW_PARAM_PFVF(TLS_START); 4869 params[1] = FW_PARAM_PFVF(TLS_END); 4870 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 4871 2, params, val); 4872 if (ret < 0) 4873 goto bye; 4874 adap->vres.key.start = val[0]; 4875 adap->vres.key.size = val[1] - val[0] + 1; 4876 adap->num_uld += 1; 4877 } 4878 adap->params.crypto = ntohs(caps_cmd.cryptocaps); 4879 } 4880 #undef FW_PARAM_PFVF 4881 #undef FW_PARAM_DEV 4882 4883 /* The MTU/MSS Table is initialized by now, so load their values. If 4884 * we're initializing the adapter, then we'll make any modifications 4885 * we want to the MTU/MSS Table and also initialize the congestion 4886 * parameters. 4887 */ 4888 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 4889 if (state != DEV_STATE_INIT) { 4890 int i; 4891 4892 /* The default MTU Table contains values 1492 and 1500. 4893 * However, for TCP, it's better to have two values which are 4894 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 4895 * This allows us to have a TCP Data Payload which is a 4896 * multiple of 8 regardless of what combination of TCP Options 4897 * are in use (always a multiple of 4 bytes) which is 4898 * important for performance reasons. For instance, if no 4899 * options are in use, then we have a 20-byte IP header and a 4900 * 20-byte TCP header. In this case, a 1500-byte MSS would 4901 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 4902 * which is not a multiple of 8. So using an MSS of 1488 in 4903 * this case results in a TCP Data Payload of 1448 bytes which 4904 * is a multiple of 8. On the other hand, if 12-byte TCP Time 4905 * Stamps have been negotiated, then an MTU of 1500 bytes 4906 * results in a TCP Data Payload of 1448 bytes which, as 4907 * above, is a multiple of 8 bytes ... 4908 */ 4909 for (i = 0; i < NMTUS; i++) 4910 if (adap->params.mtus[i] == 1492) { 4911 adap->params.mtus[i] = 1488; 4912 break; 4913 } 4914 4915 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 4916 adap->params.b_wnd); 4917 } 4918 t4_init_sge_params(adap); 4919 adap->flags |= CXGB4_FW_OK; 4920 t4_init_tp_params(adap, true); 4921 return 0; 4922 4923 /* 4924 * Something bad happened. If a command timed out or failed with EIO 4925 * FW does not operate within its spec or something catastrophic 4926 * happened to HW/FW, stop issuing commands. 4927 */ 4928 bye: 4929 adap_free_hma_mem(adap); 4930 kfree(adap->sge.egr_map); 4931 kfree(adap->sge.ingr_map); 4932 kfree(adap->sge.starving_fl); 4933 kfree(adap->sge.txq_maperr); 4934 #ifdef CONFIG_DEBUG_FS 4935 kfree(adap->sge.blocked_fl); 4936 #endif 4937 if (ret != -ETIMEDOUT && ret != -EIO) 4938 t4_fw_bye(adap, adap->mbox); 4939 return ret; 4940 } 4941 4942 /* EEH callbacks */ 4943 4944 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev, 4945 pci_channel_state_t state) 4946 { 4947 int i; 4948 struct adapter *adap = pci_get_drvdata(pdev); 4949 4950 if (!adap) 4951 goto out; 4952 4953 rtnl_lock(); 4954 adap->flags &= ~CXGB4_FW_OK; 4955 notify_ulds(adap, CXGB4_STATE_START_RECOVERY); 4956 spin_lock(&adap->stats_lock); 4957 for_each_port(adap, i) { 4958 struct net_device *dev = adap->port[i]; 4959 if (dev) { 4960 netif_device_detach(dev); 4961 netif_carrier_off(dev); 4962 } 4963 } 4964 spin_unlock(&adap->stats_lock); 4965 disable_interrupts(adap); 4966 if (adap->flags & CXGB4_FULL_INIT_DONE) 4967 cxgb_down(adap); 4968 rtnl_unlock(); 4969 if ((adap->flags & CXGB4_DEV_ENABLED)) { 4970 pci_disable_device(pdev); 4971 adap->flags &= ~CXGB4_DEV_ENABLED; 4972 } 4973 out: return state == pci_channel_io_perm_failure ? 4974 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; 4975 } 4976 4977 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev) 4978 { 4979 int i, ret; 4980 struct fw_caps_config_cmd c; 4981 struct adapter *adap = pci_get_drvdata(pdev); 4982 4983 if (!adap) { 4984 pci_restore_state(pdev); 4985 pci_save_state(pdev); 4986 return PCI_ERS_RESULT_RECOVERED; 4987 } 4988 4989 if (!(adap->flags & CXGB4_DEV_ENABLED)) { 4990 if (pci_enable_device(pdev)) { 4991 dev_err(&pdev->dev, "Cannot reenable PCI " 4992 "device after reset\n"); 4993 return PCI_ERS_RESULT_DISCONNECT; 4994 } 4995 adap->flags |= CXGB4_DEV_ENABLED; 4996 } 4997 4998 pci_set_master(pdev); 4999 pci_restore_state(pdev); 5000 pci_save_state(pdev); 5001 5002 if (t4_wait_dev_ready(adap->regs) < 0) 5003 return PCI_ERS_RESULT_DISCONNECT; 5004 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0) 5005 return PCI_ERS_RESULT_DISCONNECT; 5006 adap->flags |= CXGB4_FW_OK; 5007 if (adap_init1(adap, &c)) 5008 return PCI_ERS_RESULT_DISCONNECT; 5009 5010 for_each_port(adap, i) { 5011 struct port_info *pi = adap2pinfo(adap, i); 5012 u8 vivld = 0, vin = 0; 5013 5014 ret = t4_alloc_vi(adap, adap->mbox, pi->tx_chan, adap->pf, 0, 1, 5015 NULL, NULL, &vivld, &vin); 5016 if (ret < 0) 5017 return PCI_ERS_RESULT_DISCONNECT; 5018 pi->viid = ret; 5019 pi->xact_addr_filt = -1; 5020 /* If fw supports returning the VIN as part of FW_VI_CMD, 5021 * save the returned values. 5022 */ 5023 if (adap->params.viid_smt_extn_support) { 5024 pi->vivld = vivld; 5025 pi->vin = vin; 5026 } else { 5027 /* Retrieve the values from VIID */ 5028 pi->vivld = FW_VIID_VIVLD_G(pi->viid); 5029 pi->vin = FW_VIID_VIN_G(pi->viid); 5030 } 5031 } 5032 5033 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 5034 adap->params.b_wnd); 5035 setup_memwin(adap); 5036 if (cxgb_up(adap)) 5037 return PCI_ERS_RESULT_DISCONNECT; 5038 return PCI_ERS_RESULT_RECOVERED; 5039 } 5040 5041 static void eeh_resume(struct pci_dev *pdev) 5042 { 5043 int i; 5044 struct adapter *adap = pci_get_drvdata(pdev); 5045 5046 if (!adap) 5047 return; 5048 5049 rtnl_lock(); 5050 for_each_port(adap, i) { 5051 struct net_device *dev = adap->port[i]; 5052 if (dev) { 5053 if (netif_running(dev)) { 5054 link_start(dev); 5055 cxgb_set_rxmode(dev); 5056 } 5057 netif_device_attach(dev); 5058 } 5059 } 5060 rtnl_unlock(); 5061 } 5062 5063 static const struct pci_error_handlers cxgb4_eeh = { 5064 .error_detected = eeh_err_detected, 5065 .slot_reset = eeh_slot_reset, 5066 .resume = eeh_resume, 5067 }; 5068 5069 /* Return true if the Link Configuration supports "High Speeds" (those greater 5070 * than 1Gb/s). 5071 */ 5072 static inline bool is_x_10g_port(const struct link_config *lc) 5073 { 5074 unsigned int speeds, high_speeds; 5075 5076 speeds = FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_G(lc->pcaps)); 5077 high_speeds = speeds & 5078 ~(FW_PORT_CAP32_SPEED_100M | FW_PORT_CAP32_SPEED_1G); 5079 5080 return high_speeds != 0; 5081 } 5082 5083 /* 5084 * Perform default configuration of DMA queues depending on the number and type 5085 * of ports we found and the number of available CPUs. Most settings can be 5086 * modified by the admin prior to actual use. 5087 */ 5088 static int cfg_queues(struct adapter *adap) 5089 { 5090 struct sge *s = &adap->sge; 5091 int i, n10g = 0, qidx = 0; 5092 int niqflint, neq, avail_eth_qsets; 5093 int max_eth_qsets = 32; 5094 #ifndef CONFIG_CHELSIO_T4_DCB 5095 int q10g = 0; 5096 #endif 5097 5098 /* Reduce memory usage in kdump environment, disable all offload. 5099 */ 5100 if (is_kdump_kernel() || (is_uld(adap) && t4_uld_mem_alloc(adap))) { 5101 adap->params.offload = 0; 5102 adap->params.crypto = 0; 5103 } 5104 5105 /* Calculate the number of Ethernet Queue Sets available based on 5106 * resources provisioned for us. We always have an Asynchronous 5107 * Firmware Event Ingress Queue. If we're operating in MSI or Legacy 5108 * IRQ Pin Interrupt mode, then we'll also have a Forwarded Interrupt 5109 * Ingress Queue. Meanwhile, we need two Egress Queues for each 5110 * Queue Set: one for the Free List and one for the Ethernet TX Queue. 5111 * 5112 * Note that we should also take into account all of the various 5113 * Offload Queues. But, in any situation where we're operating in 5114 * a Resource Constrained Provisioning environment, doing any Offload 5115 * at all is problematic ... 5116 */ 5117 niqflint = adap->params.pfres.niqflint - 1; 5118 if (!(adap->flags & CXGB4_USING_MSIX)) 5119 niqflint--; 5120 neq = adap->params.pfres.neq / 2; 5121 avail_eth_qsets = min(niqflint, neq); 5122 5123 if (avail_eth_qsets > max_eth_qsets) 5124 avail_eth_qsets = max_eth_qsets; 5125 5126 if (avail_eth_qsets < adap->params.nports) { 5127 dev_err(adap->pdev_dev, "avail_eth_qsets=%d < nports=%d\n", 5128 avail_eth_qsets, adap->params.nports); 5129 return -ENOMEM; 5130 } 5131 5132 /* Count the number of 10Gb/s or better ports */ 5133 for_each_port(adap, i) 5134 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg); 5135 5136 #ifdef CONFIG_CHELSIO_T4_DCB 5137 /* For Data Center Bridging support we need to be able to support up 5138 * to 8 Traffic Priorities; each of which will be assigned to its 5139 * own TX Queue in order to prevent Head-Of-Line Blocking. 5140 */ 5141 if (adap->params.nports * 8 > avail_eth_qsets) { 5142 dev_err(adap->pdev_dev, "DCB avail_eth_qsets=%d < %d!\n", 5143 avail_eth_qsets, adap->params.nports * 8); 5144 return -ENOMEM; 5145 } 5146 5147 for_each_port(adap, i) { 5148 struct port_info *pi = adap2pinfo(adap, i); 5149 5150 pi->first_qset = qidx; 5151 pi->nqsets = is_kdump_kernel() ? 1 : 8; 5152 qidx += pi->nqsets; 5153 } 5154 #else /* !CONFIG_CHELSIO_T4_DCB */ 5155 /* 5156 * We default to 1 queue per non-10G port and up to # of cores queues 5157 * per 10G port. 5158 */ 5159 if (n10g) 5160 q10g = (avail_eth_qsets - (adap->params.nports - n10g)) / n10g; 5161 if (q10g > netif_get_num_default_rss_queues()) 5162 q10g = netif_get_num_default_rss_queues(); 5163 5164 if (is_kdump_kernel()) 5165 q10g = 1; 5166 5167 for_each_port(adap, i) { 5168 struct port_info *pi = adap2pinfo(adap, i); 5169 5170 pi->first_qset = qidx; 5171 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1; 5172 qidx += pi->nqsets; 5173 } 5174 #endif /* !CONFIG_CHELSIO_T4_DCB */ 5175 5176 s->ethqsets = qidx; 5177 s->max_ethqsets = qidx; /* MSI-X may lower it later */ 5178 5179 if (is_uld(adap)) { 5180 /* 5181 * For offload we use 1 queue/channel if all ports are up to 1G, 5182 * otherwise we divide all available queues amongst the channels 5183 * capped by the number of available cores. 5184 */ 5185 if (n10g) { 5186 i = min_t(int, MAX_OFLD_QSETS, num_online_cpus()); 5187 s->ofldqsets = roundup(i, adap->params.nports); 5188 } else { 5189 s->ofldqsets = adap->params.nports; 5190 } 5191 } 5192 5193 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 5194 struct sge_eth_rxq *r = &s->ethrxq[i]; 5195 5196 init_rspq(adap, &r->rspq, 5, 10, 1024, 64); 5197 r->fl.size = 72; 5198 } 5199 5200 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 5201 s->ethtxq[i].q.size = 1024; 5202 5203 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) 5204 s->ctrlq[i].q.size = 512; 5205 5206 if (!is_t4(adap->params.chip)) 5207 s->ptptxq.q.size = 8; 5208 5209 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64); 5210 init_rspq(adap, &s->intrq, 0, 1, 512, 64); 5211 5212 return 0; 5213 } 5214 5215 /* 5216 * Reduce the number of Ethernet queues across all ports to at most n. 5217 * n provides at least one queue per port. 5218 */ 5219 static void reduce_ethqs(struct adapter *adap, int n) 5220 { 5221 int i; 5222 struct port_info *pi; 5223 5224 while (n < adap->sge.ethqsets) 5225 for_each_port(adap, i) { 5226 pi = adap2pinfo(adap, i); 5227 if (pi->nqsets > 1) { 5228 pi->nqsets--; 5229 adap->sge.ethqsets--; 5230 if (adap->sge.ethqsets <= n) 5231 break; 5232 } 5233 } 5234 5235 n = 0; 5236 for_each_port(adap, i) { 5237 pi = adap2pinfo(adap, i); 5238 pi->first_qset = n; 5239 n += pi->nqsets; 5240 } 5241 } 5242 5243 static int get_msix_info(struct adapter *adap) 5244 { 5245 struct uld_msix_info *msix_info; 5246 unsigned int max_ingq = 0; 5247 5248 if (is_offload(adap)) 5249 max_ingq += MAX_OFLD_QSETS * adap->num_ofld_uld; 5250 if (is_pci_uld(adap)) 5251 max_ingq += MAX_OFLD_QSETS * adap->num_uld; 5252 5253 if (!max_ingq) 5254 goto out; 5255 5256 msix_info = kcalloc(max_ingq, sizeof(*msix_info), GFP_KERNEL); 5257 if (!msix_info) 5258 return -ENOMEM; 5259 5260 adap->msix_bmap_ulds.msix_bmap = kcalloc(BITS_TO_LONGS(max_ingq), 5261 sizeof(long), GFP_KERNEL); 5262 if (!adap->msix_bmap_ulds.msix_bmap) { 5263 kfree(msix_info); 5264 return -ENOMEM; 5265 } 5266 spin_lock_init(&adap->msix_bmap_ulds.lock); 5267 adap->msix_info_ulds = msix_info; 5268 out: 5269 return 0; 5270 } 5271 5272 static void free_msix_info(struct adapter *adap) 5273 { 5274 if (!(adap->num_uld && adap->num_ofld_uld)) 5275 return; 5276 5277 kfree(adap->msix_info_ulds); 5278 kfree(adap->msix_bmap_ulds.msix_bmap); 5279 } 5280 5281 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */ 5282 #define EXTRA_VECS 2 5283 5284 static int enable_msix(struct adapter *adap) 5285 { 5286 int ofld_need = 0, uld_need = 0; 5287 int i, j, want, need, allocated; 5288 struct sge *s = &adap->sge; 5289 unsigned int nchan = adap->params.nports; 5290 struct msix_entry *entries; 5291 int max_ingq = MAX_INGQ; 5292 5293 if (is_pci_uld(adap)) 5294 max_ingq += (MAX_OFLD_QSETS * adap->num_uld); 5295 if (is_offload(adap)) 5296 max_ingq += (MAX_OFLD_QSETS * adap->num_ofld_uld); 5297 entries = kmalloc_array(max_ingq + 1, sizeof(*entries), 5298 GFP_KERNEL); 5299 if (!entries) 5300 return -ENOMEM; 5301 5302 /* map for msix */ 5303 if (get_msix_info(adap)) { 5304 adap->params.offload = 0; 5305 adap->params.crypto = 0; 5306 } 5307 5308 for (i = 0; i < max_ingq + 1; ++i) 5309 entries[i].entry = i; 5310 5311 want = s->max_ethqsets + EXTRA_VECS; 5312 if (is_offload(adap)) { 5313 want += adap->num_ofld_uld * s->ofldqsets; 5314 ofld_need = adap->num_ofld_uld * nchan; 5315 } 5316 if (is_pci_uld(adap)) { 5317 want += adap->num_uld * s->ofldqsets; 5318 uld_need = adap->num_uld * nchan; 5319 } 5320 #ifdef CONFIG_CHELSIO_T4_DCB 5321 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for 5322 * each port. 5323 */ 5324 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 5325 #else 5326 need = adap->params.nports + EXTRA_VECS + ofld_need + uld_need; 5327 #endif 5328 allocated = pci_enable_msix_range(adap->pdev, entries, need, want); 5329 if (allocated < 0) { 5330 dev_info(adap->pdev_dev, "not enough MSI-X vectors left," 5331 " not using MSI-X\n"); 5332 kfree(entries); 5333 return allocated; 5334 } 5335 5336 /* Distribute available vectors to the various queue groups. 5337 * Every group gets its minimum requirement and NIC gets top 5338 * priority for leftovers. 5339 */ 5340 i = allocated - EXTRA_VECS - ofld_need - uld_need; 5341 if (i < s->max_ethqsets) { 5342 s->max_ethqsets = i; 5343 if (i < s->ethqsets) 5344 reduce_ethqs(adap, i); 5345 } 5346 if (is_uld(adap)) { 5347 if (allocated < want) 5348 s->nqs_per_uld = nchan; 5349 else 5350 s->nqs_per_uld = s->ofldqsets; 5351 } 5352 5353 for (i = 0; i < (s->max_ethqsets + EXTRA_VECS); ++i) 5354 adap->msix_info[i].vec = entries[i].vector; 5355 if (is_uld(adap)) { 5356 for (j = 0 ; i < allocated; ++i, j++) { 5357 adap->msix_info_ulds[j].vec = entries[i].vector; 5358 adap->msix_info_ulds[j].idx = i; 5359 } 5360 adap->msix_bmap_ulds.mapsize = j; 5361 } 5362 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, " 5363 "nic %d per uld %d\n", 5364 allocated, s->max_ethqsets, s->nqs_per_uld); 5365 5366 kfree(entries); 5367 return 0; 5368 } 5369 5370 #undef EXTRA_VECS 5371 5372 static int init_rss(struct adapter *adap) 5373 { 5374 unsigned int i; 5375 int err; 5376 5377 err = t4_init_rss_mode(adap, adap->mbox); 5378 if (err) 5379 return err; 5380 5381 for_each_port(adap, i) { 5382 struct port_info *pi = adap2pinfo(adap, i); 5383 5384 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL); 5385 if (!pi->rss) 5386 return -ENOMEM; 5387 } 5388 return 0; 5389 } 5390 5391 /* Dump basic information about the adapter */ 5392 static void print_adapter_info(struct adapter *adapter) 5393 { 5394 /* Hardware/Firmware/etc. Version/Revision IDs */ 5395 t4_dump_version_info(adapter); 5396 5397 /* Software/Hardware configuration */ 5398 dev_info(adapter->pdev_dev, "Configuration: %sNIC %s, %s capable\n", 5399 is_offload(adapter) ? "R" : "", 5400 ((adapter->flags & CXGB4_USING_MSIX) ? "MSI-X" : 5401 (adapter->flags & CXGB4_USING_MSI) ? "MSI" : ""), 5402 is_offload(adapter) ? "Offload" : "non-Offload"); 5403 } 5404 5405 static void print_port_info(const struct net_device *dev) 5406 { 5407 char buf[80]; 5408 char *bufp = buf; 5409 const struct port_info *pi = netdev_priv(dev); 5410 const struct adapter *adap = pi->adapter; 5411 5412 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100M) 5413 bufp += sprintf(bufp, "100M/"); 5414 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_1G) 5415 bufp += sprintf(bufp, "1G/"); 5416 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_10G) 5417 bufp += sprintf(bufp, "10G/"); 5418 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_25G) 5419 bufp += sprintf(bufp, "25G/"); 5420 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_40G) 5421 bufp += sprintf(bufp, "40G/"); 5422 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_50G) 5423 bufp += sprintf(bufp, "50G/"); 5424 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_100G) 5425 bufp += sprintf(bufp, "100G/"); 5426 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_200G) 5427 bufp += sprintf(bufp, "200G/"); 5428 if (pi->link_cfg.pcaps & FW_PORT_CAP32_SPEED_400G) 5429 bufp += sprintf(bufp, "400G/"); 5430 if (bufp != buf) 5431 --bufp; 5432 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); 5433 5434 netdev_info(dev, "%s: Chelsio %s (%s) %s\n", 5435 dev->name, adap->params.vpd.id, adap->name, buf); 5436 } 5437 5438 /* 5439 * Free the following resources: 5440 * - memory used for tables 5441 * - MSI/MSI-X 5442 * - net devices 5443 * - resources FW is holding for us 5444 */ 5445 static void free_some_resources(struct adapter *adapter) 5446 { 5447 unsigned int i; 5448 5449 kvfree(adapter->mps_encap); 5450 kvfree(adapter->smt); 5451 kvfree(adapter->l2t); 5452 kvfree(adapter->srq); 5453 t4_cleanup_sched(adapter); 5454 kvfree(adapter->tids.tid_tab); 5455 cxgb4_cleanup_tc_flower(adapter); 5456 cxgb4_cleanup_tc_u32(adapter); 5457 kfree(adapter->sge.egr_map); 5458 kfree(adapter->sge.ingr_map); 5459 kfree(adapter->sge.starving_fl); 5460 kfree(adapter->sge.txq_maperr); 5461 #ifdef CONFIG_DEBUG_FS 5462 kfree(adapter->sge.blocked_fl); 5463 #endif 5464 disable_msi(adapter); 5465 5466 for_each_port(adapter, i) 5467 if (adapter->port[i]) { 5468 struct port_info *pi = adap2pinfo(adapter, i); 5469 5470 if (pi->viid != 0) 5471 t4_free_vi(adapter, adapter->mbox, adapter->pf, 5472 0, pi->viid); 5473 kfree(adap2pinfo(adapter, i)->rss); 5474 free_netdev(adapter->port[i]); 5475 } 5476 if (adapter->flags & CXGB4_FW_OK) 5477 t4_fw_bye(adapter, adapter->pf); 5478 } 5479 5480 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN) 5481 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \ 5482 NETIF_F_GRO | NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA) 5483 #define SEGMENT_SIZE 128 5484 5485 static int t4_get_chip_type(struct adapter *adap, int ver) 5486 { 5487 u32 pl_rev = REV_G(t4_read_reg(adap, PL_REV_A)); 5488 5489 switch (ver) { 5490 case CHELSIO_T4: 5491 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev); 5492 case CHELSIO_T5: 5493 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev); 5494 case CHELSIO_T6: 5495 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev); 5496 default: 5497 break; 5498 } 5499 return -EINVAL; 5500 } 5501 5502 #ifdef CONFIG_PCI_IOV 5503 static void cxgb4_mgmt_setup(struct net_device *dev) 5504 { 5505 dev->type = ARPHRD_NONE; 5506 dev->mtu = 0; 5507 dev->hard_header_len = 0; 5508 dev->addr_len = 0; 5509 dev->tx_queue_len = 0; 5510 dev->flags |= IFF_NOARP; 5511 dev->priv_flags |= IFF_NO_QUEUE; 5512 5513 /* Initialize the device structure. */ 5514 dev->netdev_ops = &cxgb4_mgmt_netdev_ops; 5515 dev->ethtool_ops = &cxgb4_mgmt_ethtool_ops; 5516 } 5517 5518 static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs) 5519 { 5520 struct adapter *adap = pci_get_drvdata(pdev); 5521 int err = 0; 5522 int current_vfs = pci_num_vf(pdev); 5523 u32 pcie_fw; 5524 5525 pcie_fw = readl(adap->regs + PCIE_FW_A); 5526 /* Check if fw is initialized */ 5527 if (!(pcie_fw & PCIE_FW_INIT_F)) { 5528 dev_warn(&pdev->dev, "Device not initialized\n"); 5529 return -EOPNOTSUPP; 5530 } 5531 5532 /* If any of the VF's is already assigned to Guest OS, then 5533 * SRIOV for the same cannot be modified 5534 */ 5535 if (current_vfs && pci_vfs_assigned(pdev)) { 5536 dev_err(&pdev->dev, 5537 "Cannot modify SR-IOV while VFs are assigned\n"); 5538 return current_vfs; 5539 } 5540 /* Note that the upper-level code ensures that we're never called with 5541 * a non-zero "num_vfs" when we already have VFs instantiated. But 5542 * it never hurts to code defensively. 5543 */ 5544 if (num_vfs != 0 && current_vfs != 0) 5545 return -EBUSY; 5546 5547 /* Nothing to do for no change. */ 5548 if (num_vfs == current_vfs) 5549 return num_vfs; 5550 5551 /* Disable SRIOV when zero is passed. */ 5552 if (!num_vfs) { 5553 pci_disable_sriov(pdev); 5554 /* free VF Management Interface */ 5555 unregister_netdev(adap->port[0]); 5556 free_netdev(adap->port[0]); 5557 adap->port[0] = NULL; 5558 5559 /* free VF resources */ 5560 adap->num_vfs = 0; 5561 kfree(adap->vfinfo); 5562 adap->vfinfo = NULL; 5563 return 0; 5564 } 5565 5566 if (!current_vfs) { 5567 struct fw_pfvf_cmd port_cmd, port_rpl; 5568 struct net_device *netdev; 5569 unsigned int pmask, port; 5570 struct pci_dev *pbridge; 5571 struct port_info *pi; 5572 char name[IFNAMSIZ]; 5573 u32 devcap2; 5574 u16 flags; 5575 int pos; 5576 5577 /* If we want to instantiate Virtual Functions, then our 5578 * parent bridge's PCI-E needs to support Alternative Routing 5579 * ID (ARI) because our VFs will show up at function offset 8 5580 * and above. 5581 */ 5582 pbridge = pdev->bus->self; 5583 pos = pci_find_capability(pbridge, PCI_CAP_ID_EXP); 5584 pci_read_config_word(pbridge, pos + PCI_EXP_FLAGS, &flags); 5585 pci_read_config_dword(pbridge, pos + PCI_EXP_DEVCAP2, &devcap2); 5586 5587 if ((flags & PCI_EXP_FLAGS_VERS) < 2 || 5588 !(devcap2 & PCI_EXP_DEVCAP2_ARI)) { 5589 /* Our parent bridge does not support ARI so issue a 5590 * warning and skip instantiating the VFs. They 5591 * won't be reachable. 5592 */ 5593 dev_warn(&pdev->dev, "Parent bridge %02x:%02x.%x doesn't support ARI; can't instantiate Virtual Functions\n", 5594 pbridge->bus->number, PCI_SLOT(pbridge->devfn), 5595 PCI_FUNC(pbridge->devfn)); 5596 return -ENOTSUPP; 5597 } 5598 memset(&port_cmd, 0, sizeof(port_cmd)); 5599 port_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | 5600 FW_CMD_REQUEST_F | 5601 FW_CMD_READ_F | 5602 FW_PFVF_CMD_PFN_V(adap->pf) | 5603 FW_PFVF_CMD_VFN_V(0)); 5604 port_cmd.retval_len16 = cpu_to_be32(FW_LEN16(port_cmd)); 5605 err = t4_wr_mbox(adap, adap->mbox, &port_cmd, sizeof(port_cmd), 5606 &port_rpl); 5607 if (err) 5608 return err; 5609 pmask = FW_PFVF_CMD_PMASK_G(be32_to_cpu(port_rpl.type_to_neq)); 5610 port = ffs(pmask) - 1; 5611 /* Allocate VF Management Interface. */ 5612 snprintf(name, IFNAMSIZ, "mgmtpf%d,%d", adap->adap_idx, 5613 adap->pf); 5614 netdev = alloc_netdev(sizeof(struct port_info), 5615 name, NET_NAME_UNKNOWN, cxgb4_mgmt_setup); 5616 if (!netdev) 5617 return -ENOMEM; 5618 5619 pi = netdev_priv(netdev); 5620 pi->adapter = adap; 5621 pi->lport = port; 5622 pi->tx_chan = port; 5623 SET_NETDEV_DEV(netdev, &pdev->dev); 5624 5625 adap->port[0] = netdev; 5626 pi->port_id = 0; 5627 5628 err = register_netdev(adap->port[0]); 5629 if (err) { 5630 pr_info("Unable to register VF mgmt netdev %s\n", name); 5631 free_netdev(adap->port[0]); 5632 adap->port[0] = NULL; 5633 return err; 5634 } 5635 /* Allocate and set up VF Information. */ 5636 adap->vfinfo = kcalloc(pci_sriov_get_totalvfs(pdev), 5637 sizeof(struct vf_info), GFP_KERNEL); 5638 if (!adap->vfinfo) { 5639 unregister_netdev(adap->port[0]); 5640 free_netdev(adap->port[0]); 5641 adap->port[0] = NULL; 5642 return -ENOMEM; 5643 } 5644 cxgb4_mgmt_fill_vf_station_mac_addr(adap); 5645 } 5646 /* Instantiate the requested number of VFs. */ 5647 err = pci_enable_sriov(pdev, num_vfs); 5648 if (err) { 5649 pr_info("Unable to instantiate %d VFs\n", num_vfs); 5650 if (!current_vfs) { 5651 unregister_netdev(adap->port[0]); 5652 free_netdev(adap->port[0]); 5653 adap->port[0] = NULL; 5654 kfree(adap->vfinfo); 5655 adap->vfinfo = NULL; 5656 } 5657 return err; 5658 } 5659 5660 adap->num_vfs = num_vfs; 5661 return num_vfs; 5662 } 5663 #endif /* CONFIG_PCI_IOV */ 5664 5665 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 5666 { 5667 struct net_device *netdev; 5668 struct adapter *adapter; 5669 static int adap_idx = 1; 5670 int s_qpp, qpp, num_seg; 5671 struct port_info *pi; 5672 bool highdma = false; 5673 enum chip_type chip; 5674 void __iomem *regs; 5675 int func, chip_ver; 5676 u16 device_id; 5677 int i, err; 5678 u32 whoami; 5679 5680 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION); 5681 5682 err = pci_request_regions(pdev, KBUILD_MODNAME); 5683 if (err) { 5684 /* Just info, some other driver may have claimed the device. */ 5685 dev_info(&pdev->dev, "cannot obtain PCI resources\n"); 5686 return err; 5687 } 5688 5689 err = pci_enable_device(pdev); 5690 if (err) { 5691 dev_err(&pdev->dev, "cannot enable PCI device\n"); 5692 goto out_release_regions; 5693 } 5694 5695 regs = pci_ioremap_bar(pdev, 0); 5696 if (!regs) { 5697 dev_err(&pdev->dev, "cannot map device registers\n"); 5698 err = -ENOMEM; 5699 goto out_disable_device; 5700 } 5701 5702 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL); 5703 if (!adapter) { 5704 err = -ENOMEM; 5705 goto out_unmap_bar0; 5706 } 5707 5708 adapter->regs = regs; 5709 err = t4_wait_dev_ready(regs); 5710 if (err < 0) 5711 goto out_free_adapter; 5712 5713 /* We control everything through one PF */ 5714 whoami = t4_read_reg(adapter, PL_WHOAMI_A); 5715 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 5716 chip = t4_get_chip_type(adapter, CHELSIO_PCI_ID_VER(device_id)); 5717 if (chip < 0) { 5718 dev_err(&pdev->dev, "Device %d is not supported\n", device_id); 5719 err = chip; 5720 goto out_free_adapter; 5721 } 5722 chip_ver = CHELSIO_CHIP_VERSION(chip); 5723 func = chip_ver <= CHELSIO_T5 ? 5724 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami); 5725 5726 adapter->pdev = pdev; 5727 adapter->pdev_dev = &pdev->dev; 5728 adapter->name = pci_name(pdev); 5729 adapter->mbox = func; 5730 adapter->pf = func; 5731 adapter->params.chip = chip; 5732 adapter->adap_idx = adap_idx; 5733 adapter->msg_enable = DFLT_MSG_ENABLE; 5734 adapter->mbox_log = kzalloc(sizeof(*adapter->mbox_log) + 5735 (sizeof(struct mbox_cmd) * 5736 T4_OS_LOG_MBOX_CMDS), 5737 GFP_KERNEL); 5738 if (!adapter->mbox_log) { 5739 err = -ENOMEM; 5740 goto out_free_adapter; 5741 } 5742 spin_lock_init(&adapter->mbox_lock); 5743 INIT_LIST_HEAD(&adapter->mlist.list); 5744 adapter->mbox_log->size = T4_OS_LOG_MBOX_CMDS; 5745 pci_set_drvdata(pdev, adapter); 5746 5747 if (func != ent->driver_data) { 5748 pci_disable_device(pdev); 5749 pci_save_state(pdev); /* to restore SR-IOV later */ 5750 return 0; 5751 } 5752 5753 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { 5754 highdma = true; 5755 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); 5756 if (err) { 5757 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for " 5758 "coherent allocations\n"); 5759 goto out_free_adapter; 5760 } 5761 } else { 5762 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 5763 if (err) { 5764 dev_err(&pdev->dev, "no usable DMA configuration\n"); 5765 goto out_free_adapter; 5766 } 5767 } 5768 5769 pci_enable_pcie_error_reporting(pdev); 5770 pci_set_master(pdev); 5771 pci_save_state(pdev); 5772 adap_idx++; 5773 adapter->workq = create_singlethread_workqueue("cxgb4"); 5774 if (!adapter->workq) { 5775 err = -ENOMEM; 5776 goto out_free_adapter; 5777 } 5778 5779 /* PCI device has been enabled */ 5780 adapter->flags |= CXGB4_DEV_ENABLED; 5781 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map)); 5782 5783 /* If possible, we use PCIe Relaxed Ordering Attribute to deliver 5784 * Ingress Packet Data to Free List Buffers in order to allow for 5785 * chipset performance optimizations between the Root Complex and 5786 * Memory Controllers. (Messages to the associated Ingress Queue 5787 * notifying new Packet Placement in the Free Lists Buffers will be 5788 * send without the Relaxed Ordering Attribute thus guaranteeing that 5789 * all preceding PCIe Transaction Layer Packets will be processed 5790 * first.) But some Root Complexes have various issues with Upstream 5791 * Transaction Layer Packets with the Relaxed Ordering Attribute set. 5792 * The PCIe devices which under the Root Complexes will be cleared the 5793 * Relaxed Ordering bit in the configuration space, So we check our 5794 * PCIe configuration space to see if it's flagged with advice against 5795 * using Relaxed Ordering. 5796 */ 5797 if (!pcie_relaxed_ordering_enabled(pdev)) 5798 adapter->flags |= CXGB4_ROOT_NO_RELAXED_ORDERING; 5799 5800 spin_lock_init(&adapter->stats_lock); 5801 spin_lock_init(&adapter->tid_release_lock); 5802 spin_lock_init(&adapter->win0_lock); 5803 5804 INIT_WORK(&adapter->tid_release_task, process_tid_release_list); 5805 INIT_WORK(&adapter->db_full_task, process_db_full); 5806 INIT_WORK(&adapter->db_drop_task, process_db_drop); 5807 INIT_WORK(&adapter->fatal_err_notify_task, notify_fatal_err); 5808 5809 err = t4_prep_adapter(adapter); 5810 if (err) 5811 goto out_free_adapter; 5812 5813 if (is_kdump_kernel()) { 5814 /* Collect hardware state and append to /proc/vmcore */ 5815 err = cxgb4_cudbg_vmcore_add_dump(adapter); 5816 if (err) { 5817 dev_warn(adapter->pdev_dev, 5818 "Fail collecting vmcore device dump, err: %d. Continuing\n", 5819 err); 5820 err = 0; 5821 } 5822 } 5823 5824 if (!is_t4(adapter->params.chip)) { 5825 s_qpp = (QUEUESPERPAGEPF0_S + 5826 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * 5827 adapter->pf); 5828 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter, 5829 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp); 5830 num_seg = PAGE_SIZE / SEGMENT_SIZE; 5831 5832 /* Each segment size is 128B. Write coalescing is enabled only 5833 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the 5834 * queue is less no of segments that can be accommodated in 5835 * a page size. 5836 */ 5837 if (qpp > num_seg) { 5838 dev_err(&pdev->dev, 5839 "Incorrect number of egress queues per page\n"); 5840 err = -EINVAL; 5841 goto out_free_adapter; 5842 } 5843 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2), 5844 pci_resource_len(pdev, 2)); 5845 if (!adapter->bar2) { 5846 dev_err(&pdev->dev, "cannot map device bar2 region\n"); 5847 err = -ENOMEM; 5848 goto out_free_adapter; 5849 } 5850 } 5851 5852 setup_memwin(adapter); 5853 err = adap_init0(adapter); 5854 #ifdef CONFIG_DEBUG_FS 5855 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz); 5856 #endif 5857 setup_memwin_rdma(adapter); 5858 if (err) 5859 goto out_unmap_bar; 5860 5861 /* configure SGE_STAT_CFG_A to read WC stats */ 5862 if (!is_t4(adapter->params.chip)) 5863 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) | 5864 (is_t5(adapter->params.chip) ? STATMODE_V(0) : 5865 T6_STATMODE_V(0))); 5866 5867 /* Initialize hash mac addr list */ 5868 INIT_LIST_HEAD(&adapter->mac_hlist); 5869 5870 for_each_port(adapter, i) { 5871 netdev = alloc_etherdev_mq(sizeof(struct port_info), 5872 MAX_ETH_QSETS); 5873 if (!netdev) { 5874 err = -ENOMEM; 5875 goto out_free_dev; 5876 } 5877 5878 SET_NETDEV_DEV(netdev, &pdev->dev); 5879 5880 adapter->port[i] = netdev; 5881 pi = netdev_priv(netdev); 5882 pi->adapter = adapter; 5883 pi->xact_addr_filt = -1; 5884 pi->port_id = i; 5885 netdev->irq = pdev->irq; 5886 5887 netdev->hw_features = NETIF_F_SG | TSO_FLAGS | 5888 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 5889 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_GRO | 5890 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | 5891 NETIF_F_HW_TC; 5892 5893 if (chip_ver > CHELSIO_T5) { 5894 netdev->hw_enc_features |= NETIF_F_IP_CSUM | 5895 NETIF_F_IPV6_CSUM | 5896 NETIF_F_RXCSUM | 5897 NETIF_F_GSO_UDP_TUNNEL | 5898 NETIF_F_GSO_UDP_TUNNEL_CSUM | 5899 NETIF_F_TSO | NETIF_F_TSO6; 5900 5901 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL | 5902 NETIF_F_GSO_UDP_TUNNEL_CSUM | 5903 NETIF_F_HW_TLS_RECORD; 5904 } 5905 5906 if (highdma) 5907 netdev->hw_features |= NETIF_F_HIGHDMA; 5908 netdev->features |= netdev->hw_features; 5909 netdev->vlan_features = netdev->features & VLAN_FEAT; 5910 5911 netdev->priv_flags |= IFF_UNICAST_FLT; 5912 5913 /* MTU range: 81 - 9600 */ 5914 netdev->min_mtu = 81; /* accommodate SACK */ 5915 netdev->max_mtu = MAX_MTU; 5916 5917 netdev->netdev_ops = &cxgb4_netdev_ops; 5918 #ifdef CONFIG_CHELSIO_T4_DCB 5919 netdev->dcbnl_ops = &cxgb4_dcb_ops; 5920 cxgb4_dcb_state_init(netdev); 5921 cxgb4_dcb_version_init(netdev); 5922 #endif 5923 cxgb4_set_ethtool_ops(netdev); 5924 } 5925 5926 cxgb4_init_ethtool_dump(adapter); 5927 5928 pci_set_drvdata(pdev, adapter); 5929 5930 if (adapter->flags & CXGB4_FW_OK) { 5931 err = t4_port_init(adapter, func, func, 0); 5932 if (err) 5933 goto out_free_dev; 5934 } else if (adapter->params.nports == 1) { 5935 /* If we don't have a connection to the firmware -- possibly 5936 * because of an error -- grab the raw VPD parameters so we 5937 * can set the proper MAC Address on the debug network 5938 * interface that we've created. 5939 */ 5940 u8 hw_addr[ETH_ALEN]; 5941 u8 *na = adapter->params.vpd.na; 5942 5943 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd); 5944 if (!err) { 5945 for (i = 0; i < ETH_ALEN; i++) 5946 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 + 5947 hex2val(na[2 * i + 1])); 5948 t4_set_hw_addr(adapter, 0, hw_addr); 5949 } 5950 } 5951 5952 if (!(adapter->flags & CXGB4_FW_OK)) 5953 goto fw_attach_fail; 5954 5955 /* Configure queues and allocate tables now, they can be needed as 5956 * soon as the first register_netdev completes. 5957 */ 5958 err = cfg_queues(adapter); 5959 if (err) 5960 goto out_free_dev; 5961 5962 adapter->smt = t4_init_smt(); 5963 if (!adapter->smt) { 5964 /* We tolerate a lack of SMT, giving up some functionality */ 5965 dev_warn(&pdev->dev, "could not allocate SMT, continuing\n"); 5966 } 5967 5968 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end); 5969 if (!adapter->l2t) { 5970 /* We tolerate a lack of L2T, giving up some functionality */ 5971 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n"); 5972 adapter->params.offload = 0; 5973 } 5974 5975 adapter->mps_encap = kvcalloc(adapter->params.arch.mps_tcam_size, 5976 sizeof(struct mps_encap_entry), 5977 GFP_KERNEL); 5978 if (!adapter->mps_encap) 5979 dev_warn(&pdev->dev, "could not allocate MPS Encap entries, continuing\n"); 5980 5981 #if IS_ENABLED(CONFIG_IPV6) 5982 if (chip_ver <= CHELSIO_T5 && 5983 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) { 5984 /* CLIP functionality is not present in hardware, 5985 * hence disable all offload features 5986 */ 5987 dev_warn(&pdev->dev, 5988 "CLIP not enabled in hardware, continuing\n"); 5989 adapter->params.offload = 0; 5990 } else { 5991 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start, 5992 adapter->clipt_end); 5993 if (!adapter->clipt) { 5994 /* We tolerate a lack of clip_table, giving up 5995 * some functionality 5996 */ 5997 dev_warn(&pdev->dev, 5998 "could not allocate Clip table, continuing\n"); 5999 adapter->params.offload = 0; 6000 } 6001 } 6002 #endif 6003 6004 for_each_port(adapter, i) { 6005 pi = adap2pinfo(adapter, i); 6006 pi->sched_tbl = t4_init_sched(adapter->params.nsched_cls); 6007 if (!pi->sched_tbl) 6008 dev_warn(&pdev->dev, 6009 "could not activate scheduling on port %d\n", 6010 i); 6011 } 6012 6013 if (tid_init(&adapter->tids) < 0) { 6014 dev_warn(&pdev->dev, "could not allocate TID table, " 6015 "continuing\n"); 6016 adapter->params.offload = 0; 6017 } else { 6018 adapter->tc_u32 = cxgb4_init_tc_u32(adapter); 6019 if (!adapter->tc_u32) 6020 dev_warn(&pdev->dev, 6021 "could not offload tc u32, continuing\n"); 6022 6023 if (cxgb4_init_tc_flower(adapter)) 6024 dev_warn(&pdev->dev, 6025 "could not offload tc flower, continuing\n"); 6026 } 6027 6028 if (is_offload(adapter) || is_hashfilter(adapter)) { 6029 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) { 6030 u32 hash_base, hash_reg; 6031 6032 if (chip_ver <= CHELSIO_T5) { 6033 hash_reg = LE_DB_TID_HASHBASE_A; 6034 hash_base = t4_read_reg(adapter, hash_reg); 6035 adapter->tids.hash_base = hash_base / 4; 6036 } else { 6037 hash_reg = T6_LE_DB_HASH_TID_BASE_A; 6038 hash_base = t4_read_reg(adapter, hash_reg); 6039 adapter->tids.hash_base = hash_base; 6040 } 6041 } 6042 } 6043 6044 /* See what interrupts we'll be using */ 6045 if (msi > 1 && enable_msix(adapter) == 0) 6046 adapter->flags |= CXGB4_USING_MSIX; 6047 else if (msi > 0 && pci_enable_msi(pdev) == 0) { 6048 adapter->flags |= CXGB4_USING_MSI; 6049 if (msi > 1) 6050 free_msix_info(adapter); 6051 } 6052 6053 /* check for PCI Express bandwidth capabiltites */ 6054 pcie_print_link_status(pdev); 6055 6056 err = init_rss(adapter); 6057 if (err) 6058 goto out_free_dev; 6059 6060 err = setup_fw_sge_queues(adapter); 6061 if (err) { 6062 dev_err(adapter->pdev_dev, 6063 "FW sge queue allocation failed, err %d", err); 6064 goto out_free_dev; 6065 } 6066 6067 fw_attach_fail: 6068 /* 6069 * The card is now ready to go. If any errors occur during device 6070 * registration we do not fail the whole card but rather proceed only 6071 * with the ports we manage to register successfully. However we must 6072 * register at least one net device. 6073 */ 6074 for_each_port(adapter, i) { 6075 pi = adap2pinfo(adapter, i); 6076 adapter->port[i]->dev_port = pi->lport; 6077 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets); 6078 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets); 6079 6080 netif_carrier_off(adapter->port[i]); 6081 6082 err = register_netdev(adapter->port[i]); 6083 if (err) 6084 break; 6085 adapter->chan_map[pi->tx_chan] = i; 6086 print_port_info(adapter->port[i]); 6087 } 6088 if (i == 0) { 6089 dev_err(&pdev->dev, "could not register any net devices\n"); 6090 goto out_free_dev; 6091 } 6092 if (err) { 6093 dev_warn(&pdev->dev, "only %d net devices registered\n", i); 6094 err = 0; 6095 } 6096 6097 if (cxgb4_debugfs_root) { 6098 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev), 6099 cxgb4_debugfs_root); 6100 setup_debugfs(adapter); 6101 } 6102 6103 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */ 6104 pdev->needs_freset = 1; 6105 6106 if (is_uld(adapter)) { 6107 mutex_lock(&uld_mutex); 6108 list_add_tail(&adapter->list_node, &adapter_list); 6109 mutex_unlock(&uld_mutex); 6110 } 6111 6112 if (!is_t4(adapter->params.chip)) 6113 cxgb4_ptp_init(adapter); 6114 6115 if (IS_REACHABLE(CONFIG_THERMAL) && 6116 !is_t4(adapter->params.chip) && (adapter->flags & CXGB4_FW_OK)) 6117 cxgb4_thermal_init(adapter); 6118 6119 print_adapter_info(adapter); 6120 return 0; 6121 6122 out_free_dev: 6123 t4_free_sge_resources(adapter); 6124 free_some_resources(adapter); 6125 if (adapter->flags & CXGB4_USING_MSIX) 6126 free_msix_info(adapter); 6127 if (adapter->num_uld || adapter->num_ofld_uld) 6128 t4_uld_mem_free(adapter); 6129 out_unmap_bar: 6130 if (!is_t4(adapter->params.chip)) 6131 iounmap(adapter->bar2); 6132 out_free_adapter: 6133 if (adapter->workq) 6134 destroy_workqueue(adapter->workq); 6135 6136 kfree(adapter->mbox_log); 6137 kfree(adapter); 6138 out_unmap_bar0: 6139 iounmap(regs); 6140 out_disable_device: 6141 pci_disable_pcie_error_reporting(pdev); 6142 pci_disable_device(pdev); 6143 out_release_regions: 6144 pci_release_regions(pdev); 6145 return err; 6146 } 6147 6148 static void remove_one(struct pci_dev *pdev) 6149 { 6150 struct adapter *adapter = pci_get_drvdata(pdev); 6151 struct hash_mac_addr *entry, *tmp; 6152 6153 if (!adapter) { 6154 pci_release_regions(pdev); 6155 return; 6156 } 6157 6158 /* If we allocated filters, free up state associated with any 6159 * valid filters ... 6160 */ 6161 clear_all_filters(adapter); 6162 6163 adapter->flags |= CXGB4_SHUTTING_DOWN; 6164 6165 if (adapter->pf == 4) { 6166 int i; 6167 6168 /* Tear down per-adapter Work Queue first since it can contain 6169 * references to our adapter data structure. 6170 */ 6171 destroy_workqueue(adapter->workq); 6172 6173 if (is_uld(adapter)) { 6174 detach_ulds(adapter); 6175 t4_uld_clean_up(adapter); 6176 } 6177 6178 adap_free_hma_mem(adapter); 6179 6180 disable_interrupts(adapter); 6181 6182 for_each_port(adapter, i) 6183 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 6184 unregister_netdev(adapter->port[i]); 6185 6186 debugfs_remove_recursive(adapter->debugfs_root); 6187 6188 if (!is_t4(adapter->params.chip)) 6189 cxgb4_ptp_stop(adapter); 6190 if (IS_REACHABLE(CONFIG_THERMAL)) 6191 cxgb4_thermal_remove(adapter); 6192 6193 if (adapter->flags & CXGB4_FULL_INIT_DONE) 6194 cxgb_down(adapter); 6195 6196 if (adapter->flags & CXGB4_USING_MSIX) 6197 free_msix_info(adapter); 6198 if (adapter->num_uld || adapter->num_ofld_uld) 6199 t4_uld_mem_free(adapter); 6200 free_some_resources(adapter); 6201 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist, 6202 list) { 6203 list_del(&entry->list); 6204 kfree(entry); 6205 } 6206 6207 #if IS_ENABLED(CONFIG_IPV6) 6208 t4_cleanup_clip_tbl(adapter); 6209 #endif 6210 if (!is_t4(adapter->params.chip)) 6211 iounmap(adapter->bar2); 6212 } 6213 #ifdef CONFIG_PCI_IOV 6214 else { 6215 cxgb4_iov_configure(adapter->pdev, 0); 6216 } 6217 #endif 6218 iounmap(adapter->regs); 6219 pci_disable_pcie_error_reporting(pdev); 6220 if ((adapter->flags & CXGB4_DEV_ENABLED)) { 6221 pci_disable_device(pdev); 6222 adapter->flags &= ~CXGB4_DEV_ENABLED; 6223 } 6224 pci_release_regions(pdev); 6225 kfree(adapter->mbox_log); 6226 synchronize_rcu(); 6227 kfree(adapter); 6228 } 6229 6230 /* "Shutdown" quiesces the device, stopping Ingress Packet and Interrupt 6231 * delivery. This is essentially a stripped down version of the PCI remove() 6232 * function where we do the minimal amount of work necessary to shutdown any 6233 * further activity. 6234 */ 6235 static void shutdown_one(struct pci_dev *pdev) 6236 { 6237 struct adapter *adapter = pci_get_drvdata(pdev); 6238 6239 /* As with remove_one() above (see extended comment), we only want do 6240 * do cleanup on PCI Devices which went all the way through init_one() 6241 * ... 6242 */ 6243 if (!adapter) { 6244 pci_release_regions(pdev); 6245 return; 6246 } 6247 6248 adapter->flags |= CXGB4_SHUTTING_DOWN; 6249 6250 if (adapter->pf == 4) { 6251 int i; 6252 6253 for_each_port(adapter, i) 6254 if (adapter->port[i]->reg_state == NETREG_REGISTERED) 6255 cxgb_close(adapter->port[i]); 6256 6257 if (is_uld(adapter)) { 6258 detach_ulds(adapter); 6259 t4_uld_clean_up(adapter); 6260 } 6261 6262 disable_interrupts(adapter); 6263 disable_msi(adapter); 6264 6265 t4_sge_stop(adapter); 6266 if (adapter->flags & CXGB4_FW_OK) 6267 t4_fw_bye(adapter, adapter->mbox); 6268 } 6269 } 6270 6271 static struct pci_driver cxgb4_driver = { 6272 .name = KBUILD_MODNAME, 6273 .id_table = cxgb4_pci_tbl, 6274 .probe = init_one, 6275 .remove = remove_one, 6276 .shutdown = shutdown_one, 6277 #ifdef CONFIG_PCI_IOV 6278 .sriov_configure = cxgb4_iov_configure, 6279 #endif 6280 .err_handler = &cxgb4_eeh, 6281 }; 6282 6283 static int __init cxgb4_init_module(void) 6284 { 6285 int ret; 6286 6287 /* Debugfs support is optional, just warn if this fails */ 6288 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); 6289 if (!cxgb4_debugfs_root) 6290 pr_warn("could not create debugfs entry, continuing\n"); 6291 6292 ret = pci_register_driver(&cxgb4_driver); 6293 if (ret < 0) 6294 goto err_pci; 6295 6296 #if IS_ENABLED(CONFIG_IPV6) 6297 if (!inet6addr_registered) { 6298 ret = register_inet6addr_notifier(&cxgb4_inet6addr_notifier); 6299 if (ret) 6300 pci_unregister_driver(&cxgb4_driver); 6301 else 6302 inet6addr_registered = true; 6303 } 6304 #endif 6305 6306 if (ret == 0) 6307 return ret; 6308 6309 err_pci: 6310 debugfs_remove(cxgb4_debugfs_root); 6311 6312 return ret; 6313 } 6314 6315 static void __exit cxgb4_cleanup_module(void) 6316 { 6317 #if IS_ENABLED(CONFIG_IPV6) 6318 if (inet6addr_registered) { 6319 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier); 6320 inet6addr_registered = false; 6321 } 6322 #endif 6323 pci_unregister_driver(&cxgb4_driver); 6324 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */ 6325 } 6326 6327 module_init(cxgb4_init_module); 6328 module_exit(cxgb4_cleanup_module); 6329