1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2026 Broadcom */ 3 4 #ifndef _BNGE_LINK_H_ 5 #define _BNGE_LINK_H_ 6 7 #include <linux/ethtool.h> 8 9 #define BNGE_PHY_CFG_ABLE(bd) \ 10 ((bd)->link_info.phy_enabled) 11 12 #define BNGE_PHY_AUTO_SPEEDS2_MASK \ 13 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEEDS2_MASK 14 #define BNGE_PHY_FLAGS_RESTART_AUTO \ 15 PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 16 #define BNGE_PHY_FLAGS_ENA_FORCE_SPEEDS2 \ 17 PORT_PHY_CFG_REQ_ENABLES_FORCE_LINK_SPEEDS2 18 19 #define BNGE_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK 20 21 enum bnge_link_state { 22 BNGE_LINK_STATE_UNKNOWN, 23 BNGE_LINK_STATE_DOWN, 24 BNGE_LINK_STATE_UP, 25 }; 26 27 #define BNGE_LINK_IS_UP(bd) \ 28 ((bd)->link_info.link_state == BNGE_LINK_STATE_UP) 29 30 #define BNGE_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 31 32 #define BNGE_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX 33 #define BNGE_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX 34 #define BNGE_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \ 35 PORT_PHY_QCFG_RESP_PAUSE_TX) 36 37 #define BNGE_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 38 #define BNGE_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 39 #define BNGE_AUTO_MODE(mode) ((mode) > BNGE_LINK_AUTO_NONE && \ 40 (mode) <= BNGE_LINK_AUTO_MSK) 41 42 #define BNGE_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 43 #define BNGE_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 44 #define BNGE_LINK_SPEED_200GB PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 45 #define BNGE_LINK_SPEED_400GB PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 46 #define BNGE_LINK_SPEED_800GB PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 47 48 #define BNGE_LINK_SPEEDS2_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB 49 #define BNGE_LINK_SPEEDS2_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB 50 #define BNGE_LINK_SPEEDS2_MSK_50GB_PAM4 \ 51 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_50GB_PAM4_56 52 #define BNGE_LINK_SPEEDS2_MSK_100GB_PAM4 \ 53 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_56 54 #define BNGE_LINK_SPEEDS2_MSK_200GB_PAM4 \ 55 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_56 56 #define BNGE_LINK_SPEEDS2_MSK_400GB_PAM4 \ 57 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_56 58 #define BNGE_LINK_SPEEDS2_MSK_100GB_PAM4_112 \ 59 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_100GB_PAM4_112 60 #define BNGE_LINK_SPEEDS2_MSK_200GB_PAM4_112 \ 61 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_200GB_PAM4_112 62 #define BNGE_LINK_SPEEDS2_MSK_400GB_PAM4_112 \ 63 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_400GB_PAM4_112 64 #define BNGE_LINK_SPEEDS2_MSK_800GB_PAM4_112 \ 65 PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS2_800GB_PAM4_112 66 67 #define BNGE_LINK_SPEED_50GB_PAM4 \ 68 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_50GB_PAM4_56 69 #define BNGE_LINK_SPEED_100GB_PAM4 \ 70 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_56 71 #define BNGE_LINK_SPEED_200GB_PAM4 \ 72 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_56 73 #define BNGE_LINK_SPEED_400GB_PAM4 \ 74 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_56 75 #define BNGE_LINK_SPEED_100GB_PAM4_112 \ 76 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 77 #define BNGE_LINK_SPEED_200GB_PAM4_112 \ 78 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 79 #define BNGE_LINK_SPEED_400GB_PAM4_112 \ 80 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 81 #define BNGE_LINK_SPEED_800GB_PAM4_112 \ 82 PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 83 84 #define BNGE_FEC_NONE PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 85 #define BNGE_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 86 #define BNGE_FEC_ENC_BASE_R_CAP \ 87 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 88 #define BNGE_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 89 #define BNGE_FEC_ENC_RS_CAP \ 90 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 91 #define BNGE_FEC_ENC_LLRS_CAP \ 92 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED | \ 93 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED) 94 #define BNGE_FEC_ENC_RS \ 95 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED | \ 96 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED | \ 97 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED) 98 #define BNGE_FEC_ENC_LLRS \ 99 (PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED | \ 100 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED) 101 102 struct bnge_link_info { 103 u8 phy_type; 104 u8 media_type; 105 u8 phy_addr; 106 u8 phy_link_status; 107 bool phy_enabled; 108 109 u8 link_state; 110 u8 active_lanes; 111 u8 duplex; 112 u8 pause; 113 u8 lp_pause; 114 u8 auto_pause_setting; 115 u8 force_pause_setting; 116 u8 duplex_setting; 117 u8 auto_mode; 118 u16 link_speed; 119 u16 support_speeds2; 120 u16 auto_link_speeds2; 121 u16 support_auto_speeds2; 122 u16 lp_auto_link_speeds; 123 u16 force_link_speed2; 124 125 u8 module_status; 126 u8 active_fec_sig_mode; 127 u16 fec_cfg; 128 129 /* A copy of phy_qcfg output used to report link 130 * info to VF 131 */ 132 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 133 134 bool phy_retry; 135 unsigned long phy_retry_expires; 136 }; 137 138 #define BNGE_AUTONEG_SPEED 1 139 #define BNGE_AUTONEG_FLOW_CTRL 2 140 141 #define BNGE_SIG_MODE_NRZ PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ 142 #define BNGE_SIG_MODE_PAM4 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4 143 #define BNGE_SIG_MODE_PAM4_112 PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4_112 144 #define BNGE_SIG_MODE_MAX (PORT_PHY_QCFG_RESP_SIGNAL_MODE_LAST + 1) 145 146 struct bnge_ethtool_link_info { 147 /* copy of requested setting from ethtool cmd */ 148 u8 autoneg; 149 u8 req_signal_mode; 150 u8 req_duplex; 151 u8 req_flow_ctrl; 152 u16 req_link_speed; 153 u16 advertising; /* user adv setting */ 154 bool force_link_chng; 155 }; 156 157 void bnge_hwrm_set_link_common(struct bnge_net *bn, 158 struct hwrm_port_phy_cfg_input *req); 159 void bnge_hwrm_set_pause_common(struct bnge_net *bn, 160 struct hwrm_port_phy_cfg_input *req); 161 int bnge_update_phy_setting(struct bnge_net *bn); 162 void bnge_get_port_module_status(struct bnge_net *bn); 163 void bnge_report_link(struct bnge_dev *bd); 164 bool bnge_support_speed_dropped(struct bnge_net *bn); 165 void bnge_init_ethtool_link_settings(struct bnge_net *bn); 166 int bnge_probe_phy(struct bnge_net *bn, bool fw_dflt); 167 int bnge_set_link_ksettings(struct net_device *dev, 168 const struct ethtool_link_ksettings *lk_ksettings); 169 int bnge_get_link_ksettings(struct net_device *dev, 170 struct ethtool_link_ksettings *lk_ksettings); 171 u32 bnge_get_link(struct net_device *dev); 172 void bnge_link_async_event_process(struct bnge_net *bn, u16 event_id); 173 #endif /* _BNGE_LINK_H_ */ 174