1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Motorcomm YT921x Switch 4 * 5 * Should work on YT9213/YT9214/YT9215/YT9218, but only tested on YT9215+SGMII, 6 * be sure to do your own checks before porting to another chip. 7 * 8 * Copyright (c) 2025 David Yang 9 */ 10 11 #include <linux/etherdevice.h> 12 #include <linux/if_bridge.h> 13 #include <linux/if_hsr.h> 14 #include <linux/if_vlan.h> 15 #include <linux/iopoll.h> 16 #include <linux/mdio.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 22 #include <net/dsa.h> 23 24 #include "yt921x.h" 25 26 struct yt921x_mib_desc { 27 unsigned int size; 28 unsigned int offset; 29 const char *name; 30 }; 31 32 #define MIB_DESC(_size, _offset, _name) \ 33 {_size, _offset, _name} 34 35 /* Must agree with yt921x_mib 36 * 37 * Unstructured fields (name != NULL) will appear in get_ethtool_stats(), 38 * structured go to their *_stats() methods, but we need their sizes and offsets 39 * to perform 32bit MIB overflow wraparound. 40 */ 41 static const struct yt921x_mib_desc yt921x_mib_descs[] = { 42 MIB_DESC(1, YT921X_MIB_DATA_RX_BROADCAST, NULL), 43 MIB_DESC(1, YT921X_MIB_DATA_RX_PAUSE, NULL), 44 MIB_DESC(1, YT921X_MIB_DATA_RX_MULTICAST, NULL), 45 MIB_DESC(1, YT921X_MIB_DATA_RX_CRC_ERR, NULL), 46 47 MIB_DESC(1, YT921X_MIB_DATA_RX_ALIGN_ERR, NULL), 48 MIB_DESC(1, YT921X_MIB_DATA_RX_UNDERSIZE_ERR, NULL), 49 MIB_DESC(1, YT921X_MIB_DATA_RX_FRAG_ERR, NULL), 50 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_64, NULL), 51 52 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_65_TO_127, NULL), 53 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_128_TO_255, NULL), 54 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_256_TO_511, NULL), 55 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_512_TO_1023, NULL), 56 57 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_1024_TO_1518, NULL), 58 MIB_DESC(1, YT921X_MIB_DATA_RX_PKT_SZ_1519_TO_MAX, NULL), 59 MIB_DESC(2, YT921X_MIB_DATA_RX_GOOD_BYTES, NULL), 60 61 MIB_DESC(2, YT921X_MIB_DATA_RX_BAD_BYTES, "RxBadBytes"), 62 MIB_DESC(1, YT921X_MIB_DATA_RX_OVERSIZE_ERR, NULL), 63 64 MIB_DESC(1, YT921X_MIB_DATA_RX_DROPPED, NULL), 65 MIB_DESC(1, YT921X_MIB_DATA_TX_BROADCAST, NULL), 66 MIB_DESC(1, YT921X_MIB_DATA_TX_PAUSE, NULL), 67 MIB_DESC(1, YT921X_MIB_DATA_TX_MULTICAST, NULL), 68 69 MIB_DESC(1, YT921X_MIB_DATA_TX_UNDERSIZE_ERR, NULL), 70 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_64, NULL), 71 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_65_TO_127, NULL), 72 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_128_TO_255, NULL), 73 74 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_256_TO_511, NULL), 75 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_512_TO_1023, NULL), 76 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_1024_TO_1518, NULL), 77 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT_SZ_1519_TO_MAX, NULL), 78 79 MIB_DESC(2, YT921X_MIB_DATA_TX_GOOD_BYTES, NULL), 80 MIB_DESC(1, YT921X_MIB_DATA_TX_COLLISION, NULL), 81 82 MIB_DESC(1, YT921X_MIB_DATA_TX_EXCESSIVE_COLLISION, NULL), 83 MIB_DESC(1, YT921X_MIB_DATA_TX_MULTIPLE_COLLISION, NULL), 84 MIB_DESC(1, YT921X_MIB_DATA_TX_SINGLE_COLLISION, NULL), 85 MIB_DESC(1, YT921X_MIB_DATA_TX_PKT, NULL), 86 87 MIB_DESC(1, YT921X_MIB_DATA_TX_DEFERRED, NULL), 88 MIB_DESC(1, YT921X_MIB_DATA_TX_LATE_COLLISION, NULL), 89 MIB_DESC(1, YT921X_MIB_DATA_RX_OAM, "RxOAM"), 90 MIB_DESC(1, YT921X_MIB_DATA_TX_OAM, "TxOAM"), 91 }; 92 93 struct yt921x_info { 94 const char *name; 95 u16 major; 96 /* Unknown, seems to be plain enumeration */ 97 u8 mode; 98 u8 extmode; 99 /* Ports with integral GbE PHYs, not including MCU Port 10 */ 100 u16 internal_mask; 101 /* TODO: see comments in yt921x_dsa_phylink_get_caps() */ 102 u16 external_mask; 103 }; 104 105 #define YT921X_PORT_MASK_INTn(port) BIT(port) 106 #define YT921X_PORT_MASK_INT0_n(n) GENMASK((n) - 1, 0) 107 #define YT921X_PORT_MASK_EXT0 BIT(8) 108 #define YT921X_PORT_MASK_EXT1 BIT(9) 109 110 static const struct yt921x_info yt921x_infos[] = { 111 { 112 "YT9215SC", YT9215_MAJOR, 1, 0, 113 YT921X_PORT_MASK_INT0_n(5), 114 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 115 }, 116 { 117 "YT9215S", YT9215_MAJOR, 2, 0, 118 YT921X_PORT_MASK_INT0_n(5), 119 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 120 }, 121 { 122 "YT9215RB", YT9215_MAJOR, 3, 0, 123 YT921X_PORT_MASK_INT0_n(5), 124 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 125 }, 126 { 127 "YT9214NB", YT9215_MAJOR, 3, 2, 128 YT921X_PORT_MASK_INTn(1) | YT921X_PORT_MASK_INTn(3), 129 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 130 }, 131 { 132 "YT9213NB", YT9215_MAJOR, 3, 3, 133 YT921X_PORT_MASK_INTn(1) | YT921X_PORT_MASK_INTn(3), 134 YT921X_PORT_MASK_EXT1, 135 }, 136 { 137 "YT9218N", YT9218_MAJOR, 0, 0, 138 YT921X_PORT_MASK_INT0_n(8), 139 0, 140 }, 141 { 142 "YT9218MB", YT9218_MAJOR, 1, 0, 143 YT921X_PORT_MASK_INT0_n(8), 144 YT921X_PORT_MASK_EXT0 | YT921X_PORT_MASK_EXT1, 145 }, 146 {} 147 }; 148 149 #define YT921X_NAME "yt921x" 150 151 #define YT921X_VID_UNWARE 4095 152 153 #define YT921X_POLL_SLEEP_US 10000 154 #define YT921X_POLL_TIMEOUT_US 100000 155 156 /* The interval should be small enough to avoid overflow of 32bit MIBs. 157 * 158 * Until we can read MIBs from stats64 call directly (i.e. sleep 159 * there), we have to poll stats more frequently then it is actually needed. 160 * For overflow protection, normally, 100 sec interval should have been OK. 161 */ 162 #define YT921X_STATS_INTERVAL_JIFFIES (3 * HZ) 163 164 struct yt921x_reg_mdio { 165 struct mii_bus *bus; 166 int addr; 167 /* SWITCH_ID_1 / SWITCH_ID_0 of the device 168 * 169 * This is a way to multiplex multiple devices on the same MII phyaddr 170 * and should be configurable in DT. However, MDIO core simply doesn't 171 * allow multiple devices over one reg addr, so this is a fixed value 172 * for now until a solution is found. 173 * 174 * Keep this because we need switchid to form MII regaddrs anyway. 175 */ 176 unsigned char switchid; 177 }; 178 179 /* TODO: SPI/I2C */ 180 181 #define to_yt921x_priv(_ds) container_of_const(_ds, struct yt921x_priv, ds) 182 #define to_device(priv) ((priv)->ds.dev) 183 184 static int yt921x_reg_read(struct yt921x_priv *priv, u32 reg, u32 *valp) 185 { 186 WARN_ON(!mutex_is_locked(&priv->reg_lock)); 187 188 return priv->reg_ops->read(priv->reg_ctx, reg, valp); 189 } 190 191 static int yt921x_reg_write(struct yt921x_priv *priv, u32 reg, u32 val) 192 { 193 WARN_ON(!mutex_is_locked(&priv->reg_lock)); 194 195 return priv->reg_ops->write(priv->reg_ctx, reg, val); 196 } 197 198 static int 199 yt921x_reg_wait(struct yt921x_priv *priv, u32 reg, u32 mask, u32 *valp) 200 { 201 u32 val; 202 int res; 203 int ret; 204 205 ret = read_poll_timeout(yt921x_reg_read, res, 206 res || (val & mask) == *valp, 207 YT921X_POLL_SLEEP_US, YT921X_POLL_TIMEOUT_US, 208 false, priv, reg, &val); 209 if (ret) 210 return ret; 211 if (res) 212 return res; 213 214 *valp = val; 215 return 0; 216 } 217 218 static int 219 yt921x_reg_update_bits(struct yt921x_priv *priv, u32 reg, u32 mask, u32 val) 220 { 221 int res; 222 u32 v; 223 u32 u; 224 225 res = yt921x_reg_read(priv, reg, &v); 226 if (res) 227 return res; 228 229 u = v; 230 u &= ~mask; 231 u |= val; 232 if (u == v) 233 return 0; 234 235 return yt921x_reg_write(priv, reg, u); 236 } 237 238 static int yt921x_reg_set_bits(struct yt921x_priv *priv, u32 reg, u32 mask) 239 { 240 return yt921x_reg_update_bits(priv, reg, 0, mask); 241 } 242 243 static int yt921x_reg_clear_bits(struct yt921x_priv *priv, u32 reg, u32 mask) 244 { 245 return yt921x_reg_update_bits(priv, reg, mask, 0); 246 } 247 248 static int 249 yt921x_reg_toggle_bits(struct yt921x_priv *priv, u32 reg, u32 mask, bool set) 250 { 251 return yt921x_reg_update_bits(priv, reg, mask, !set ? 0 : mask); 252 } 253 254 /* Some registers, like VLANn_CTRL, should always be written in 64-bit, even if 255 * you are to write only the lower / upper 32 bits. 256 * 257 * There is no such restriction for reading, but we still provide 64-bit read 258 * wrappers so that we always handle u64 values. 259 */ 260 261 static int yt921x_reg64_read(struct yt921x_priv *priv, u32 reg, u64 *valp) 262 { 263 u32 lo; 264 u32 hi; 265 int res; 266 267 res = yt921x_reg_read(priv, reg, &lo); 268 if (res) 269 return res; 270 res = yt921x_reg_read(priv, reg + 4, &hi); 271 if (res) 272 return res; 273 274 *valp = ((u64)hi << 32) | lo; 275 return 0; 276 } 277 278 static int yt921x_reg64_write(struct yt921x_priv *priv, u32 reg, u64 val) 279 { 280 int res; 281 282 res = yt921x_reg_write(priv, reg, (u32)val); 283 if (res) 284 return res; 285 return yt921x_reg_write(priv, reg + 4, (u32)(val >> 32)); 286 } 287 288 static int 289 yt921x_reg64_update_bits(struct yt921x_priv *priv, u32 reg, u64 mask, u64 val) 290 { 291 int res; 292 u64 v; 293 u64 u; 294 295 res = yt921x_reg64_read(priv, reg, &v); 296 if (res) 297 return res; 298 299 u = v; 300 u &= ~mask; 301 u |= val; 302 if (u == v) 303 return 0; 304 305 return yt921x_reg64_write(priv, reg, u); 306 } 307 308 static int yt921x_reg64_clear_bits(struct yt921x_priv *priv, u32 reg, u64 mask) 309 { 310 return yt921x_reg64_update_bits(priv, reg, mask, 0); 311 } 312 313 static int yt921x_reg_mdio_read(void *context, u32 reg, u32 *valp) 314 { 315 struct yt921x_reg_mdio *mdio = context; 316 struct mii_bus *bus = mdio->bus; 317 int addr = mdio->addr; 318 u32 reg_addr; 319 u32 reg_data; 320 u32 val; 321 int res; 322 323 /* Hold the mdio bus lock to avoid (un)locking for 4 times */ 324 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 325 326 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 327 YT921X_SMI_READ; 328 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 329 if (res) 330 goto end; 331 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 332 if (res) 333 goto end; 334 335 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 336 YT921X_SMI_READ; 337 res = __mdiobus_read(bus, addr, reg_data); 338 if (res < 0) 339 goto end; 340 val = (u16)res; 341 res = __mdiobus_read(bus, addr, reg_data); 342 if (res < 0) 343 goto end; 344 val = (val << 16) | (u16)res; 345 346 *valp = val; 347 res = 0; 348 349 end: 350 mutex_unlock(&bus->mdio_lock); 351 return res; 352 } 353 354 static int yt921x_reg_mdio_write(void *context, u32 reg, u32 val) 355 { 356 struct yt921x_reg_mdio *mdio = context; 357 struct mii_bus *bus = mdio->bus; 358 int addr = mdio->addr; 359 u32 reg_addr; 360 u32 reg_data; 361 int res; 362 363 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 364 365 reg_addr = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_ADDR | 366 YT921X_SMI_WRITE; 367 res = __mdiobus_write(bus, addr, reg_addr, (u16)(reg >> 16)); 368 if (res) 369 goto end; 370 res = __mdiobus_write(bus, addr, reg_addr, (u16)reg); 371 if (res) 372 goto end; 373 374 reg_data = YT921X_SMI_SWITCHID(mdio->switchid) | YT921X_SMI_DATA | 375 YT921X_SMI_WRITE; 376 res = __mdiobus_write(bus, addr, reg_data, (u16)(val >> 16)); 377 if (res) 378 goto end; 379 res = __mdiobus_write(bus, addr, reg_data, (u16)val); 380 if (res) 381 goto end; 382 383 res = 0; 384 385 end: 386 mutex_unlock(&bus->mdio_lock); 387 return res; 388 } 389 390 static const struct yt921x_reg_ops yt921x_reg_ops_mdio = { 391 .read = yt921x_reg_mdio_read, 392 .write = yt921x_reg_mdio_write, 393 }; 394 395 /* TODO: SPI/I2C */ 396 397 static int yt921x_intif_wait(struct yt921x_priv *priv) 398 { 399 u32 val = 0; 400 401 return yt921x_reg_wait(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START, 402 &val); 403 } 404 405 static int 406 yt921x_intif_read(struct yt921x_priv *priv, int port, int reg, u16 *valp) 407 { 408 struct device *dev = to_device(priv); 409 u32 mask; 410 u32 ctrl; 411 u32 val; 412 int res; 413 414 res = yt921x_intif_wait(priv); 415 if (res) 416 return res; 417 418 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 419 YT921X_MBUS_CTRL_OP_M; 420 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 421 YT921X_MBUS_CTRL_READ; 422 res = yt921x_reg_update_bits(priv, YT921X_INT_MBUS_CTRL, mask, ctrl); 423 if (res) 424 return res; 425 res = yt921x_reg_write(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START); 426 if (res) 427 return res; 428 429 res = yt921x_intif_wait(priv); 430 if (res) 431 return res; 432 res = yt921x_reg_read(priv, YT921X_INT_MBUS_DIN, &val); 433 if (res) 434 return res; 435 436 if ((u16)val != val) 437 dev_info(dev, 438 "%s: port %d, reg 0x%x: Expected u16, got 0x%08x\n", 439 __func__, port, reg, val); 440 *valp = (u16)val; 441 return 0; 442 } 443 444 static int 445 yt921x_intif_write(struct yt921x_priv *priv, int port, int reg, u16 val) 446 { 447 u32 mask; 448 u32 ctrl; 449 int res; 450 451 res = yt921x_intif_wait(priv); 452 if (res) 453 return res; 454 455 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 456 YT921X_MBUS_CTRL_OP_M; 457 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 458 YT921X_MBUS_CTRL_WRITE; 459 res = yt921x_reg_update_bits(priv, YT921X_INT_MBUS_CTRL, mask, ctrl); 460 if (res) 461 return res; 462 res = yt921x_reg_write(priv, YT921X_INT_MBUS_DOUT, val); 463 if (res) 464 return res; 465 res = yt921x_reg_write(priv, YT921X_INT_MBUS_OP, YT921X_MBUS_OP_START); 466 if (res) 467 return res; 468 469 return yt921x_intif_wait(priv); 470 } 471 472 static int yt921x_mbus_int_read(struct mii_bus *mbus, int port, int reg) 473 { 474 struct yt921x_priv *priv = mbus->priv; 475 u16 val; 476 int res; 477 478 if (port >= YT921X_PORT_NUM) 479 return U16_MAX; 480 481 mutex_lock(&priv->reg_lock); 482 res = yt921x_intif_read(priv, port, reg, &val); 483 mutex_unlock(&priv->reg_lock); 484 485 if (res) 486 return res; 487 return val; 488 } 489 490 static int 491 yt921x_mbus_int_write(struct mii_bus *mbus, int port, int reg, u16 data) 492 { 493 struct yt921x_priv *priv = mbus->priv; 494 int res; 495 496 if (port >= YT921X_PORT_NUM) 497 return -ENODEV; 498 499 mutex_lock(&priv->reg_lock); 500 res = yt921x_intif_write(priv, port, reg, data); 501 mutex_unlock(&priv->reg_lock); 502 503 return res; 504 } 505 506 static int 507 yt921x_mbus_int_init(struct yt921x_priv *priv, struct device_node *mnp) 508 { 509 struct device *dev = to_device(priv); 510 struct mii_bus *mbus; 511 int res; 512 513 mbus = devm_mdiobus_alloc(dev); 514 if (!mbus) 515 return -ENOMEM; 516 517 mbus->name = "YT921x internal MDIO bus"; 518 snprintf(mbus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev)); 519 mbus->priv = priv; 520 mbus->read = yt921x_mbus_int_read; 521 mbus->write = yt921x_mbus_int_write; 522 mbus->parent = dev; 523 mbus->phy_mask = (u32)~GENMASK(YT921X_PORT_NUM - 1, 0); 524 525 res = devm_of_mdiobus_register(dev, mbus, mnp); 526 if (res) 527 return res; 528 529 priv->mbus_int = mbus; 530 531 return 0; 532 } 533 534 static int yt921x_extif_wait(struct yt921x_priv *priv) 535 { 536 u32 val = 0; 537 538 return yt921x_reg_wait(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START, 539 &val); 540 } 541 542 static int 543 yt921x_extif_read(struct yt921x_priv *priv, int port, int reg, u16 *valp) 544 { 545 struct device *dev = to_device(priv); 546 u32 mask; 547 u32 ctrl; 548 u32 val; 549 int res; 550 551 res = yt921x_extif_wait(priv); 552 if (res) 553 return res; 554 555 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 556 YT921X_MBUS_CTRL_TYPE_M | YT921X_MBUS_CTRL_OP_M; 557 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 558 YT921X_MBUS_CTRL_TYPE_C22 | YT921X_MBUS_CTRL_READ; 559 res = yt921x_reg_update_bits(priv, YT921X_EXT_MBUS_CTRL, mask, ctrl); 560 if (res) 561 return res; 562 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START); 563 if (res) 564 return res; 565 566 res = yt921x_extif_wait(priv); 567 if (res) 568 return res; 569 res = yt921x_reg_read(priv, YT921X_EXT_MBUS_DIN, &val); 570 if (res) 571 return res; 572 573 if ((u16)val != val) 574 dev_info(dev, 575 "%s: port %d, reg 0x%x: Expected u16, got 0x%08x\n", 576 __func__, port, reg, val); 577 *valp = (u16)val; 578 return 0; 579 } 580 581 static int 582 yt921x_extif_write(struct yt921x_priv *priv, int port, int reg, u16 val) 583 { 584 u32 mask; 585 u32 ctrl; 586 int res; 587 588 res = yt921x_extif_wait(priv); 589 if (res) 590 return res; 591 592 mask = YT921X_MBUS_CTRL_PORT_M | YT921X_MBUS_CTRL_REG_M | 593 YT921X_MBUS_CTRL_TYPE_M | YT921X_MBUS_CTRL_OP_M; 594 ctrl = YT921X_MBUS_CTRL_PORT(port) | YT921X_MBUS_CTRL_REG(reg) | 595 YT921X_MBUS_CTRL_TYPE_C22 | YT921X_MBUS_CTRL_WRITE; 596 res = yt921x_reg_update_bits(priv, YT921X_EXT_MBUS_CTRL, mask, ctrl); 597 if (res) 598 return res; 599 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_DOUT, val); 600 if (res) 601 return res; 602 res = yt921x_reg_write(priv, YT921X_EXT_MBUS_OP, YT921X_MBUS_OP_START); 603 if (res) 604 return res; 605 606 return yt921x_extif_wait(priv); 607 } 608 609 static int yt921x_mbus_ext_read(struct mii_bus *mbus, int port, int reg) 610 { 611 struct yt921x_priv *priv = mbus->priv; 612 u16 val; 613 int res; 614 615 mutex_lock(&priv->reg_lock); 616 res = yt921x_extif_read(priv, port, reg, &val); 617 mutex_unlock(&priv->reg_lock); 618 619 if (res) 620 return res; 621 return val; 622 } 623 624 static int 625 yt921x_mbus_ext_write(struct mii_bus *mbus, int port, int reg, u16 data) 626 { 627 struct yt921x_priv *priv = mbus->priv; 628 int res; 629 630 mutex_lock(&priv->reg_lock); 631 res = yt921x_extif_write(priv, port, reg, data); 632 mutex_unlock(&priv->reg_lock); 633 634 return res; 635 } 636 637 static int 638 yt921x_mbus_ext_init(struct yt921x_priv *priv, struct device_node *mnp) 639 { 640 struct device *dev = to_device(priv); 641 struct mii_bus *mbus; 642 int res; 643 644 mbus = devm_mdiobus_alloc(dev); 645 if (!mbus) 646 return -ENOMEM; 647 648 mbus->name = "YT921x external MDIO bus"; 649 snprintf(mbus->id, MII_BUS_ID_SIZE, "%s@ext", dev_name(dev)); 650 mbus->priv = priv; 651 /* TODO: c45? */ 652 mbus->read = yt921x_mbus_ext_read; 653 mbus->write = yt921x_mbus_ext_write; 654 mbus->parent = dev; 655 656 res = devm_of_mdiobus_register(dev, mbus, mnp); 657 if (res) 658 return res; 659 660 priv->mbus_ext = mbus; 661 662 return 0; 663 } 664 665 /* Read and handle overflow of 32bit MIBs. MIB buffer must be zeroed before. */ 666 static int yt921x_read_mib(struct yt921x_priv *priv, int port) 667 { 668 struct yt921x_port *pp = &priv->ports[port]; 669 struct device *dev = to_device(priv); 670 struct yt921x_mib *mib = &pp->mib; 671 int res = 0; 672 673 /* Reading of yt921x_port::mib is not protected by a lock and it's vain 674 * to keep its consistency, since we have to read registers one by one 675 * and there is no way to make a snapshot of MIB stats. 676 * 677 * Writing (by this function only) is and should be protected by 678 * reg_lock. 679 */ 680 681 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 682 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 683 u32 reg = YT921X_MIBn_DATA0(port) + desc->offset; 684 u64 *valp = &((u64 *)mib)[i]; 685 u64 val = *valp; 686 u32 val0; 687 u32 val1; 688 689 res = yt921x_reg_read(priv, reg, &val0); 690 if (res) 691 break; 692 693 if (desc->size <= 1) { 694 if (val < (u32)val) 695 /* overflow */ 696 val += (u64)U32_MAX + 1; 697 val &= ~U32_MAX; 698 val |= val0; 699 } else { 700 res = yt921x_reg_read(priv, reg + 4, &val1); 701 if (res) 702 break; 703 val = ((u64)val1 << 32) | val0; 704 } 705 706 WRITE_ONCE(*valp, val); 707 } 708 709 pp->rx_frames = mib->rx_64byte + mib->rx_65_127byte + 710 mib->rx_128_255byte + mib->rx_256_511byte + 711 mib->rx_512_1023byte + mib->rx_1024_1518byte + 712 mib->rx_jumbo; 713 pp->tx_frames = mib->tx_64byte + mib->tx_65_127byte + 714 mib->tx_128_255byte + mib->tx_256_511byte + 715 mib->tx_512_1023byte + mib->tx_1024_1518byte + 716 mib->tx_jumbo; 717 718 if (res) 719 dev_err(dev, "Failed to %s port %d: %i\n", "read stats for", 720 port, res); 721 return res; 722 } 723 724 static void yt921x_poll_mib(struct work_struct *work) 725 { 726 struct yt921x_port *pp = container_of_const(work, struct yt921x_port, 727 mib_read.work); 728 struct yt921x_priv *priv = (void *)(pp - pp->index) - 729 offsetof(struct yt921x_priv, ports); 730 unsigned long delay = YT921X_STATS_INTERVAL_JIFFIES; 731 int port = pp->index; 732 int res; 733 734 mutex_lock(&priv->reg_lock); 735 res = yt921x_read_mib(priv, port); 736 mutex_unlock(&priv->reg_lock); 737 if (res) 738 delay *= 4; 739 740 schedule_delayed_work(&pp->mib_read, delay); 741 } 742 743 static void 744 yt921x_dsa_get_strings(struct dsa_switch *ds, int port, u32 stringset, 745 uint8_t *data) 746 { 747 if (stringset != ETH_SS_STATS) 748 return; 749 750 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 751 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 752 753 if (desc->name) 754 ethtool_puts(&data, desc->name); 755 } 756 } 757 758 static void 759 yt921x_dsa_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data) 760 { 761 struct yt921x_priv *priv = to_yt921x_priv(ds); 762 struct yt921x_port *pp = &priv->ports[port]; 763 struct yt921x_mib *mib = &pp->mib; 764 size_t j; 765 766 mutex_lock(&priv->reg_lock); 767 yt921x_read_mib(priv, port); 768 mutex_unlock(&priv->reg_lock); 769 770 j = 0; 771 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 772 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 773 774 if (!desc->name) 775 continue; 776 777 data[j] = ((u64 *)mib)[i]; 778 j++; 779 } 780 } 781 782 static int yt921x_dsa_get_sset_count(struct dsa_switch *ds, int port, int sset) 783 { 784 int cnt = 0; 785 786 if (sset != ETH_SS_STATS) 787 return 0; 788 789 for (size_t i = 0; i < ARRAY_SIZE(yt921x_mib_descs); i++) { 790 const struct yt921x_mib_desc *desc = &yt921x_mib_descs[i]; 791 792 if (desc->name) 793 cnt++; 794 } 795 796 return cnt; 797 } 798 799 static void 800 yt921x_dsa_get_eth_mac_stats(struct dsa_switch *ds, int port, 801 struct ethtool_eth_mac_stats *mac_stats) 802 { 803 struct yt921x_priv *priv = to_yt921x_priv(ds); 804 struct yt921x_port *pp = &priv->ports[port]; 805 struct yt921x_mib *mib = &pp->mib; 806 807 mutex_lock(&priv->reg_lock); 808 yt921x_read_mib(priv, port); 809 mutex_unlock(&priv->reg_lock); 810 811 mac_stats->FramesTransmittedOK = pp->tx_frames; 812 mac_stats->SingleCollisionFrames = mib->tx_single_collisions; 813 mac_stats->MultipleCollisionFrames = mib->tx_multiple_collisions; 814 mac_stats->FramesReceivedOK = pp->rx_frames; 815 mac_stats->FrameCheckSequenceErrors = mib->rx_crc_errors; 816 mac_stats->AlignmentErrors = mib->rx_alignment_errors; 817 mac_stats->OctetsTransmittedOK = mib->tx_good_bytes; 818 mac_stats->FramesWithDeferredXmissions = mib->tx_deferred; 819 mac_stats->LateCollisions = mib->tx_late_collisions; 820 mac_stats->FramesAbortedDueToXSColls = mib->tx_aborted_errors; 821 /* mac_stats->FramesLostDueToIntMACXmitError */ 822 /* mac_stats->CarrierSenseErrors */ 823 mac_stats->OctetsReceivedOK = mib->rx_good_bytes; 824 /* mac_stats->FramesLostDueToIntMACRcvError */ 825 mac_stats->MulticastFramesXmittedOK = mib->tx_multicast; 826 mac_stats->BroadcastFramesXmittedOK = mib->tx_broadcast; 827 /* mac_stats->FramesWithExcessiveDeferral */ 828 mac_stats->MulticastFramesReceivedOK = mib->rx_multicast; 829 mac_stats->BroadcastFramesReceivedOK = mib->rx_broadcast; 830 /* mac_stats->InRangeLengthErrors */ 831 /* mac_stats->OutOfRangeLengthField */ 832 mac_stats->FrameTooLongErrors = mib->rx_oversize_errors; 833 } 834 835 static void 836 yt921x_dsa_get_eth_ctrl_stats(struct dsa_switch *ds, int port, 837 struct ethtool_eth_ctrl_stats *ctrl_stats) 838 { 839 struct yt921x_priv *priv = to_yt921x_priv(ds); 840 struct yt921x_port *pp = &priv->ports[port]; 841 struct yt921x_mib *mib = &pp->mib; 842 843 mutex_lock(&priv->reg_lock); 844 yt921x_read_mib(priv, port); 845 mutex_unlock(&priv->reg_lock); 846 847 ctrl_stats->MACControlFramesTransmitted = mib->tx_pause; 848 ctrl_stats->MACControlFramesReceived = mib->rx_pause; 849 /* ctrl_stats->UnsupportedOpcodesReceived */ 850 } 851 852 static const struct ethtool_rmon_hist_range yt921x_rmon_ranges[] = { 853 { 0, 64 }, 854 { 65, 127 }, 855 { 128, 255 }, 856 { 256, 511 }, 857 { 512, 1023 }, 858 { 1024, 1518 }, 859 { 1519, YT921X_FRAME_SIZE_MAX }, 860 {} 861 }; 862 863 static void 864 yt921x_dsa_get_rmon_stats(struct dsa_switch *ds, int port, 865 struct ethtool_rmon_stats *rmon_stats, 866 const struct ethtool_rmon_hist_range **ranges) 867 { 868 struct yt921x_priv *priv = to_yt921x_priv(ds); 869 struct yt921x_port *pp = &priv->ports[port]; 870 struct yt921x_mib *mib = &pp->mib; 871 872 mutex_lock(&priv->reg_lock); 873 yt921x_read_mib(priv, port); 874 mutex_unlock(&priv->reg_lock); 875 876 *ranges = yt921x_rmon_ranges; 877 878 rmon_stats->undersize_pkts = mib->rx_undersize_errors; 879 rmon_stats->oversize_pkts = mib->rx_oversize_errors; 880 rmon_stats->fragments = mib->rx_alignment_errors; 881 /* rmon_stats->jabbers */ 882 883 rmon_stats->hist[0] = mib->rx_64byte; 884 rmon_stats->hist[1] = mib->rx_65_127byte; 885 rmon_stats->hist[2] = mib->rx_128_255byte; 886 rmon_stats->hist[3] = mib->rx_256_511byte; 887 rmon_stats->hist[4] = mib->rx_512_1023byte; 888 rmon_stats->hist[5] = mib->rx_1024_1518byte; 889 rmon_stats->hist[6] = mib->rx_jumbo; 890 891 rmon_stats->hist_tx[0] = mib->tx_64byte; 892 rmon_stats->hist_tx[1] = mib->tx_65_127byte; 893 rmon_stats->hist_tx[2] = mib->tx_128_255byte; 894 rmon_stats->hist_tx[3] = mib->tx_256_511byte; 895 rmon_stats->hist_tx[4] = mib->tx_512_1023byte; 896 rmon_stats->hist_tx[5] = mib->tx_1024_1518byte; 897 rmon_stats->hist_tx[6] = mib->tx_jumbo; 898 } 899 900 static void 901 yt921x_dsa_get_stats64(struct dsa_switch *ds, int port, 902 struct rtnl_link_stats64 *stats) 903 { 904 struct yt921x_priv *priv = to_yt921x_priv(ds); 905 struct yt921x_port *pp = &priv->ports[port]; 906 struct yt921x_mib *mib = &pp->mib; 907 908 stats->rx_length_errors = mib->rx_undersize_errors + 909 mib->rx_fragment_errors; 910 stats->rx_over_errors = mib->rx_oversize_errors; 911 stats->rx_crc_errors = mib->rx_crc_errors; 912 stats->rx_frame_errors = mib->rx_alignment_errors; 913 /* stats->rx_fifo_errors */ 914 /* stats->rx_missed_errors */ 915 916 stats->tx_aborted_errors = mib->tx_aborted_errors; 917 /* stats->tx_carrier_errors */ 918 stats->tx_fifo_errors = mib->tx_undersize_errors; 919 /* stats->tx_heartbeat_errors */ 920 stats->tx_window_errors = mib->tx_late_collisions; 921 922 stats->rx_packets = pp->rx_frames; 923 stats->tx_packets = pp->tx_frames; 924 stats->rx_bytes = mib->rx_good_bytes - ETH_FCS_LEN * stats->rx_packets; 925 stats->tx_bytes = mib->tx_good_bytes - ETH_FCS_LEN * stats->tx_packets; 926 stats->rx_errors = stats->rx_length_errors + stats->rx_over_errors + 927 stats->rx_crc_errors + stats->rx_frame_errors; 928 stats->tx_errors = stats->tx_aborted_errors + stats->tx_fifo_errors + 929 stats->tx_window_errors; 930 stats->rx_dropped = mib->rx_dropped; 931 /* stats->tx_dropped */ 932 stats->multicast = mib->rx_multicast; 933 stats->collisions = mib->tx_collisions; 934 } 935 936 static void 937 yt921x_dsa_get_pause_stats(struct dsa_switch *ds, int port, 938 struct ethtool_pause_stats *pause_stats) 939 { 940 struct yt921x_priv *priv = to_yt921x_priv(ds); 941 struct yt921x_port *pp = &priv->ports[port]; 942 struct yt921x_mib *mib = &pp->mib; 943 944 mutex_lock(&priv->reg_lock); 945 yt921x_read_mib(priv, port); 946 mutex_unlock(&priv->reg_lock); 947 948 pause_stats->tx_pause_frames = mib->tx_pause; 949 pause_stats->rx_pause_frames = mib->rx_pause; 950 } 951 952 static int 953 yt921x_set_eee(struct yt921x_priv *priv, int port, struct ethtool_keee *e) 954 { 955 /* Poor datasheet for EEE operations; don't ask if you are confused */ 956 957 bool enable = e->eee_enabled; 958 u16 new_mask; 959 int res; 960 961 /* Enable / disable global EEE */ 962 new_mask = priv->eee_ports_mask; 963 new_mask &= ~BIT(port); 964 new_mask |= !enable ? 0 : BIT(port); 965 966 if (!!new_mask != !!priv->eee_ports_mask) { 967 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_FUNC, 968 YT921X_PON_STRAP_EEE, !!new_mask); 969 if (res) 970 return res; 971 res = yt921x_reg_toggle_bits(priv, YT921X_PON_STRAP_VAL, 972 YT921X_PON_STRAP_EEE, !!new_mask); 973 if (res) 974 return res; 975 } 976 977 priv->eee_ports_mask = new_mask; 978 979 /* Enable / disable port EEE */ 980 res = yt921x_reg_toggle_bits(priv, YT921X_EEE_CTRL, 981 YT921X_EEE_CTRL_ENn(port), enable); 982 if (res) 983 return res; 984 res = yt921x_reg_toggle_bits(priv, YT921X_EEEn_VAL(port), 985 YT921X_EEE_VAL_DATA, enable); 986 if (res) 987 return res; 988 989 return 0; 990 } 991 992 static int 993 yt921x_dsa_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e) 994 { 995 struct yt921x_priv *priv = to_yt921x_priv(ds); 996 int res; 997 998 mutex_lock(&priv->reg_lock); 999 res = yt921x_set_eee(priv, port, e); 1000 mutex_unlock(&priv->reg_lock); 1001 1002 return res; 1003 } 1004 1005 static int 1006 yt921x_dsa_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1007 { 1008 /* Only serves as packet filter, since the frame size is always set to 1009 * maximum after reset 1010 */ 1011 1012 struct yt921x_priv *priv = to_yt921x_priv(ds); 1013 struct dsa_port *dp = dsa_to_port(ds, port); 1014 int frame_size; 1015 int res; 1016 1017 frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN; 1018 if (dsa_port_is_cpu(dp)) 1019 frame_size += YT921X_TAG_LEN; 1020 1021 mutex_lock(&priv->reg_lock); 1022 res = yt921x_reg_update_bits(priv, YT921X_MACn_FRAME(port), 1023 YT921X_MAC_FRAME_SIZE_M, 1024 YT921X_MAC_FRAME_SIZE(frame_size)); 1025 mutex_unlock(&priv->reg_lock); 1026 1027 return res; 1028 } 1029 1030 static int yt921x_dsa_port_max_mtu(struct dsa_switch *ds, int port) 1031 { 1032 /* Only called for user ports, exclude tag len here */ 1033 return YT921X_FRAME_SIZE_MAX - ETH_HLEN - ETH_FCS_LEN - YT921X_TAG_LEN; 1034 } 1035 1036 static int 1037 yt921x_mirror_del(struct yt921x_priv *priv, int port, bool ingress) 1038 { 1039 u32 mask; 1040 1041 if (ingress) 1042 mask = YT921X_MIRROR_IGR_PORTn(port); 1043 else 1044 mask = YT921X_MIRROR_EGR_PORTn(port); 1045 return yt921x_reg_clear_bits(priv, YT921X_MIRROR, mask); 1046 } 1047 1048 static int 1049 yt921x_mirror_add(struct yt921x_priv *priv, int port, bool ingress, 1050 int to_local_port, struct netlink_ext_ack *extack) 1051 { 1052 u32 srcs; 1053 u32 ctrl; 1054 u32 val; 1055 u32 dst; 1056 int res; 1057 1058 if (ingress) 1059 srcs = YT921X_MIRROR_IGR_PORTn(port); 1060 else 1061 srcs = YT921X_MIRROR_EGR_PORTn(port); 1062 dst = YT921X_MIRROR_PORT(to_local_port); 1063 1064 res = yt921x_reg_read(priv, YT921X_MIRROR, &val); 1065 if (res) 1066 return res; 1067 1068 /* other mirror tasks & different dst port -> conflict */ 1069 if ((val & ~srcs & (YT921X_MIRROR_EGR_PORTS_M | 1070 YT921X_MIRROR_IGR_PORTS_M)) && 1071 (val & YT921X_MIRROR_PORT_M) != dst) { 1072 NL_SET_ERR_MSG_MOD(extack, 1073 "Sniffer port is already configured, delete existing rules & retry"); 1074 return -EBUSY; 1075 } 1076 1077 ctrl = val & ~YT921X_MIRROR_PORT_M; 1078 ctrl |= srcs; 1079 ctrl |= dst; 1080 1081 if (ctrl == val) 1082 return 0; 1083 1084 return yt921x_reg_write(priv, YT921X_MIRROR, ctrl); 1085 } 1086 1087 static void 1088 yt921x_dsa_port_mirror_del(struct dsa_switch *ds, int port, 1089 struct dsa_mall_mirror_tc_entry *mirror) 1090 { 1091 struct yt921x_priv *priv = to_yt921x_priv(ds); 1092 struct device *dev = to_device(priv); 1093 int res; 1094 1095 mutex_lock(&priv->reg_lock); 1096 res = yt921x_mirror_del(priv, port, mirror->ingress); 1097 mutex_unlock(&priv->reg_lock); 1098 1099 if (res) 1100 dev_err(dev, "Failed to %s port %d: %i\n", "unmirror", 1101 port, res); 1102 } 1103 1104 static int 1105 yt921x_dsa_port_mirror_add(struct dsa_switch *ds, int port, 1106 struct dsa_mall_mirror_tc_entry *mirror, 1107 bool ingress, struct netlink_ext_ack *extack) 1108 { 1109 struct yt921x_priv *priv = to_yt921x_priv(ds); 1110 int res; 1111 1112 mutex_lock(&priv->reg_lock); 1113 res = yt921x_mirror_add(priv, port, ingress, 1114 mirror->to_local_port, extack); 1115 mutex_unlock(&priv->reg_lock); 1116 1117 return res; 1118 } 1119 1120 static int yt921x_fdb_wait(struct yt921x_priv *priv, u32 *valp) 1121 { 1122 struct device *dev = to_device(priv); 1123 u32 val = YT921X_FDB_RESULT_DONE; 1124 int res; 1125 1126 res = yt921x_reg_wait(priv, YT921X_FDB_RESULT, YT921X_FDB_RESULT_DONE, 1127 &val); 1128 if (res) { 1129 dev_err(dev, "FDB probably stuck\n"); 1130 return res; 1131 } 1132 1133 *valp = val; 1134 return 0; 1135 } 1136 1137 static int 1138 yt921x_fdb_in01(struct yt921x_priv *priv, const unsigned char *addr, 1139 u16 vid, u32 ctrl1) 1140 { 1141 u32 ctrl; 1142 int res; 1143 1144 ctrl = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 1145 res = yt921x_reg_write(priv, YT921X_FDB_IN0, ctrl); 1146 if (res) 1147 return res; 1148 1149 ctrl = ctrl1 | YT921X_FDB_IO1_FID(vid) | (addr[4] << 8) | addr[5]; 1150 return yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 1151 } 1152 1153 static int 1154 yt921x_fdb_has(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1155 u16 *indexp) 1156 { 1157 u32 ctrl; 1158 u32 val; 1159 int res; 1160 1161 res = yt921x_fdb_in01(priv, addr, vid, 0); 1162 if (res) 1163 return res; 1164 1165 ctrl = 0; 1166 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1167 if (res) 1168 return res; 1169 1170 ctrl = YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 1171 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1172 if (res) 1173 return res; 1174 1175 res = yt921x_fdb_wait(priv, &val); 1176 if (res) 1177 return res; 1178 if (val & YT921X_FDB_RESULT_NOTFOUND) { 1179 *indexp = YT921X_FDB_NUM; 1180 return 0; 1181 } 1182 1183 *indexp = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 1184 return 0; 1185 } 1186 1187 static int 1188 yt921x_fdb_read(struct yt921x_priv *priv, unsigned char *addr, u16 *vidp, 1189 u16 *ports_maskp, u16 *indexp, u8 *statusp) 1190 { 1191 struct device *dev = to_device(priv); 1192 u16 index; 1193 u32 data0; 1194 u32 data1; 1195 u32 data2; 1196 u32 val; 1197 int res; 1198 1199 res = yt921x_fdb_wait(priv, &val); 1200 if (res) 1201 return res; 1202 if (val & YT921X_FDB_RESULT_NOTFOUND) { 1203 *ports_maskp = 0; 1204 return 0; 1205 } 1206 index = FIELD_GET(YT921X_FDB_RESULT_INDEX_M, val); 1207 1208 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &data1); 1209 if (res) 1210 return res; 1211 if ((data1 & YT921X_FDB_IO1_STATUS_M) == 1212 YT921X_FDB_IO1_STATUS_INVALID) { 1213 *ports_maskp = 0; 1214 return 0; 1215 } 1216 1217 res = yt921x_reg_read(priv, YT921X_FDB_OUT0, &data0); 1218 if (res) 1219 return res; 1220 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &data2); 1221 if (res) 1222 return res; 1223 1224 addr[0] = data0 >> 24; 1225 addr[1] = data0 >> 16; 1226 addr[2] = data0 >> 8; 1227 addr[3] = data0; 1228 addr[4] = data1 >> 8; 1229 addr[5] = data1; 1230 *vidp = FIELD_GET(YT921X_FDB_IO1_FID_M, data1); 1231 *indexp = index; 1232 *ports_maskp = FIELD_GET(YT921X_FDB_IO2_EGR_PORTS_M, data2); 1233 *statusp = FIELD_GET(YT921X_FDB_IO1_STATUS_M, data1); 1234 1235 dev_dbg(dev, 1236 "%s: index 0x%x, mac %02x:%02x:%02x:%02x:%02x:%02x, vid %d, ports 0x%x, status %d\n", 1237 __func__, *indexp, addr[0], addr[1], addr[2], addr[3], 1238 addr[4], addr[5], *vidp, *ports_maskp, *statusp); 1239 return 0; 1240 } 1241 1242 static int 1243 yt921x_fdb_dump(struct yt921x_priv *priv, u16 ports_mask, 1244 dsa_fdb_dump_cb_t *cb, void *data) 1245 { 1246 unsigned char addr[ETH_ALEN]; 1247 u8 status; 1248 u16 pmask; 1249 u16 index; 1250 u32 ctrl; 1251 u16 vid; 1252 int res; 1253 1254 ctrl = YT921X_FDB_OP_INDEX(0) | YT921X_FDB_OP_MODE_INDEX | 1255 YT921X_FDB_OP_OP_GET_ONE | YT921X_FDB_OP_START; 1256 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1257 if (res) 1258 return res; 1259 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, &status); 1260 if (res) 1261 return res; 1262 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 1263 res = cb(addr, vid, 1264 status == YT921X_FDB_ENTRY_STATUS_STATIC, data); 1265 if (res) 1266 return res; 1267 } 1268 1269 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1270 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1271 if (res) 1272 return res; 1273 1274 index = 0; 1275 do { 1276 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 1277 YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT | 1278 YT921X_FDB_OP_OP_GET_NEXT | YT921X_FDB_OP_START; 1279 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1280 if (res) 1281 return res; 1282 1283 res = yt921x_fdb_read(priv, addr, &vid, &pmask, &index, 1284 &status); 1285 if (res) 1286 return res; 1287 if (!pmask) 1288 break; 1289 1290 if ((pmask & ports_mask) && !is_multicast_ether_addr(addr)) { 1291 res = cb(addr, vid, 1292 status == YT921X_FDB_ENTRY_STATUS_STATIC, 1293 data); 1294 if (res) 1295 return res; 1296 } 1297 1298 /* Never call GET_NEXT with 4095, otherwise it will hang 1299 * forever until a reset! 1300 */ 1301 } while (index < YT921X_FDB_NUM - 1); 1302 1303 return 0; 1304 } 1305 1306 static int 1307 yt921x_fdb_flush_raw(struct yt921x_priv *priv, u16 ports_mask, u16 vid, 1308 bool flush_static) 1309 { 1310 u32 ctrl; 1311 u32 val; 1312 int res; 1313 1314 if (vid < 4096) { 1315 ctrl = YT921X_FDB_IO1_FID(vid); 1316 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl); 1317 if (res) 1318 return res; 1319 } 1320 1321 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1322 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1323 if (res) 1324 return res; 1325 1326 ctrl = YT921X_FDB_OP_OP_FLUSH | YT921X_FDB_OP_START; 1327 if (vid >= 4096) 1328 ctrl |= YT921X_FDB_OP_FLUSH_PORT; 1329 else 1330 ctrl |= YT921X_FDB_OP_FLUSH_PORT_VID; 1331 if (flush_static) 1332 ctrl |= YT921X_FDB_OP_FLUSH_STATIC; 1333 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1334 if (res) 1335 return res; 1336 1337 res = yt921x_fdb_wait(priv, &val); 1338 if (res) 1339 return res; 1340 1341 return 0; 1342 } 1343 1344 static int 1345 yt921x_fdb_flush_port(struct yt921x_priv *priv, int port, bool flush_static) 1346 { 1347 return yt921x_fdb_flush_raw(priv, BIT(port), 4096, flush_static); 1348 } 1349 1350 static int 1351 yt921x_fdb_add_index_in12(struct yt921x_priv *priv, u16 index, u16 ctrl1, 1352 u16 ctrl2) 1353 { 1354 u32 ctrl; 1355 u32 val; 1356 int res; 1357 1358 res = yt921x_reg_write(priv, YT921X_FDB_IN1, ctrl1); 1359 if (res) 1360 return res; 1361 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl2); 1362 if (res) 1363 return res; 1364 1365 ctrl = YT921X_FDB_OP_INDEX(index) | YT921X_FDB_OP_MODE_INDEX | 1366 YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 1367 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1368 if (res) 1369 return res; 1370 1371 return yt921x_fdb_wait(priv, &val); 1372 } 1373 1374 static int 1375 yt921x_fdb_add(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1376 u16 ports_mask) 1377 { 1378 u32 ctrl; 1379 u32 val; 1380 int res; 1381 1382 ctrl = YT921X_FDB_IO1_STATUS_STATIC; 1383 res = yt921x_fdb_in01(priv, addr, vid, ctrl); 1384 if (res) 1385 return res; 1386 1387 ctrl = YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1388 res = yt921x_reg_write(priv, YT921X_FDB_IN2, ctrl); 1389 if (res) 1390 return res; 1391 1392 ctrl = YT921X_FDB_OP_OP_ADD | YT921X_FDB_OP_START; 1393 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1394 if (res) 1395 return res; 1396 1397 return yt921x_fdb_wait(priv, &val); 1398 } 1399 1400 static int 1401 yt921x_fdb_leave(struct yt921x_priv *priv, const unsigned char *addr, 1402 u16 vid, u16 ports_mask) 1403 { 1404 u16 index; 1405 u32 ctrl1; 1406 u32 ctrl2; 1407 u32 ctrl; 1408 u32 val2; 1409 u32 val; 1410 int res; 1411 1412 /* Check for presence */ 1413 res = yt921x_fdb_has(priv, addr, vid, &index); 1414 if (res) 1415 return res; 1416 if (index >= YT921X_FDB_NUM) 1417 return 0; 1418 1419 /* Check if action required */ 1420 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 1421 if (res) 1422 return res; 1423 1424 ctrl2 = val2 & ~YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1425 if (ctrl2 == val2) 1426 return 0; 1427 if (!(ctrl2 & YT921X_FDB_IO2_EGR_PORTS_M)) { 1428 ctrl = YT921X_FDB_OP_OP_DEL | YT921X_FDB_OP_START; 1429 res = yt921x_reg_write(priv, YT921X_FDB_OP, ctrl); 1430 if (res) 1431 return res; 1432 1433 return yt921x_fdb_wait(priv, &val); 1434 } 1435 1436 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &ctrl1); 1437 if (res) 1438 return res; 1439 1440 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 1441 } 1442 1443 static int 1444 yt921x_fdb_join(struct yt921x_priv *priv, const unsigned char *addr, u16 vid, 1445 u16 ports_mask) 1446 { 1447 u16 index; 1448 u32 ctrl1; 1449 u32 ctrl2; 1450 u32 val1; 1451 u32 val2; 1452 int res; 1453 1454 /* Check for presence */ 1455 res = yt921x_fdb_has(priv, addr, vid, &index); 1456 if (res) 1457 return res; 1458 if (index >= YT921X_FDB_NUM) 1459 return yt921x_fdb_add(priv, addr, vid, ports_mask); 1460 1461 /* Check if action required */ 1462 res = yt921x_reg_read(priv, YT921X_FDB_OUT1, &val1); 1463 if (res) 1464 return res; 1465 res = yt921x_reg_read(priv, YT921X_FDB_OUT2, &val2); 1466 if (res) 1467 return res; 1468 1469 ctrl1 = val1 & ~YT921X_FDB_IO1_STATUS_M; 1470 ctrl1 |= YT921X_FDB_IO1_STATUS_STATIC; 1471 ctrl2 = val2 | YT921X_FDB_IO2_EGR_PORTS(ports_mask); 1472 if (ctrl1 == val1 && ctrl2 == val2) 1473 return 0; 1474 1475 return yt921x_fdb_add_index_in12(priv, index, ctrl1, ctrl2); 1476 } 1477 1478 static int 1479 yt921x_dsa_port_fdb_dump(struct dsa_switch *ds, int port, 1480 dsa_fdb_dump_cb_t *cb, void *data) 1481 { 1482 struct yt921x_priv *priv = to_yt921x_priv(ds); 1483 int res; 1484 1485 mutex_lock(&priv->reg_lock); 1486 /* Hardware FDB is shared for fdb and mdb, "bridge fdb show" 1487 * only wants to see unicast 1488 */ 1489 res = yt921x_fdb_dump(priv, BIT(port), cb, data); 1490 mutex_unlock(&priv->reg_lock); 1491 1492 return res; 1493 } 1494 1495 static void yt921x_dsa_port_fast_age(struct dsa_switch *ds, int port) 1496 { 1497 struct yt921x_priv *priv = to_yt921x_priv(ds); 1498 struct device *dev = to_device(priv); 1499 int res; 1500 1501 mutex_lock(&priv->reg_lock); 1502 res = yt921x_fdb_flush_port(priv, port, false); 1503 mutex_unlock(&priv->reg_lock); 1504 1505 if (res) 1506 dev_err(dev, "Failed to %s port %d: %i\n", "clear FDB for", 1507 port, res); 1508 } 1509 1510 static int 1511 yt921x_dsa_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 1512 { 1513 struct yt921x_priv *priv = to_yt921x_priv(ds); 1514 u32 ctrl; 1515 int res; 1516 1517 /* AGEING reg is set in 5s step */ 1518 ctrl = clamp(msecs / 5000, 1, U16_MAX); 1519 1520 mutex_lock(&priv->reg_lock); 1521 res = yt921x_reg_write(priv, YT921X_AGEING, ctrl); 1522 mutex_unlock(&priv->reg_lock); 1523 1524 return res; 1525 } 1526 1527 static int 1528 yt921x_dsa_port_fdb_del(struct dsa_switch *ds, int port, 1529 const unsigned char *addr, u16 vid, struct dsa_db db) 1530 { 1531 struct yt921x_priv *priv = to_yt921x_priv(ds); 1532 int res; 1533 1534 mutex_lock(&priv->reg_lock); 1535 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 1536 mutex_unlock(&priv->reg_lock); 1537 1538 return res; 1539 } 1540 1541 static int 1542 yt921x_dsa_port_fdb_add(struct dsa_switch *ds, int port, 1543 const unsigned char *addr, u16 vid, struct dsa_db db) 1544 { 1545 struct yt921x_priv *priv = to_yt921x_priv(ds); 1546 int res; 1547 1548 mutex_lock(&priv->reg_lock); 1549 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 1550 mutex_unlock(&priv->reg_lock); 1551 1552 return res; 1553 } 1554 1555 static int 1556 yt921x_dsa_port_mdb_del(struct dsa_switch *ds, int port, 1557 const struct switchdev_obj_port_mdb *mdb, 1558 struct dsa_db db) 1559 { 1560 struct yt921x_priv *priv = to_yt921x_priv(ds); 1561 const unsigned char *addr = mdb->addr; 1562 u16 vid = mdb->vid; 1563 int res; 1564 1565 mutex_lock(&priv->reg_lock); 1566 res = yt921x_fdb_leave(priv, addr, vid, BIT(port)); 1567 mutex_unlock(&priv->reg_lock); 1568 1569 return res; 1570 } 1571 1572 static int 1573 yt921x_dsa_port_mdb_add(struct dsa_switch *ds, int port, 1574 const struct switchdev_obj_port_mdb *mdb, 1575 struct dsa_db db) 1576 { 1577 struct yt921x_priv *priv = to_yt921x_priv(ds); 1578 const unsigned char *addr = mdb->addr; 1579 u16 vid = mdb->vid; 1580 int res; 1581 1582 mutex_lock(&priv->reg_lock); 1583 res = yt921x_fdb_join(priv, addr, vid, BIT(port)); 1584 mutex_unlock(&priv->reg_lock); 1585 1586 return res; 1587 } 1588 1589 static int 1590 yt921x_port_set_pvid(struct yt921x_priv *priv, int port, u16 vid) 1591 { 1592 u32 mask; 1593 u32 ctrl; 1594 1595 mask = YT921X_PORT_VLAN_CTRL_CVID_M; 1596 ctrl = YT921X_PORT_VLAN_CTRL_CVID(vid); 1597 return yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL(port), 1598 mask, ctrl); 1599 } 1600 1601 static int 1602 yt921x_vlan_filtering(struct yt921x_priv *priv, int port, bool vlan_filtering) 1603 { 1604 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1605 struct net_device *bdev; 1606 u16 pvid; 1607 u32 mask; 1608 u32 ctrl; 1609 int res; 1610 1611 bdev = dsa_port_bridge_dev_get(dp); 1612 1613 if (!bdev || !vlan_filtering) 1614 pvid = YT921X_VID_UNWARE; 1615 else 1616 br_vlan_get_pvid(bdev, &pvid); 1617 res = yt921x_port_set_pvid(priv, port, pvid); 1618 if (res) 1619 return res; 1620 1621 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED | 1622 YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1623 ctrl = 0; 1624 /* Do not drop tagged frames here; let VLAN_IGR_FILTER do it */ 1625 if (vlan_filtering && !pvid) 1626 ctrl |= YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1627 res = yt921x_reg_update_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 1628 mask, ctrl); 1629 if (res) 1630 return res; 1631 1632 res = yt921x_reg_toggle_bits(priv, YT921X_VLAN_IGR_FILTER, 1633 YT921X_VLAN_IGR_FILTER_PORTn(port), 1634 vlan_filtering); 1635 if (res) 1636 return res; 1637 1638 /* Turn on / off VLAN awareness */ 1639 mask = YT921X_PORT_IGR_TPIDn_CTAG_M; 1640 if (!vlan_filtering) 1641 ctrl = 0; 1642 else 1643 ctrl = YT921X_PORT_IGR_TPIDn_CTAG(0); 1644 res = yt921x_reg_update_bits(priv, YT921X_PORTn_IGR_TPID(port), 1645 mask, ctrl); 1646 if (res) 1647 return res; 1648 1649 return 0; 1650 } 1651 1652 static int 1653 yt921x_vlan_del(struct yt921x_priv *priv, int port, u16 vid) 1654 { 1655 u64 mask64; 1656 1657 mask64 = YT921X_VLAN_CTRL_PORTS(port) | 1658 YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1659 1660 return yt921x_reg64_clear_bits(priv, YT921X_VLANn_CTRL(vid), mask64); 1661 } 1662 1663 static int 1664 yt921x_vlan_add(struct yt921x_priv *priv, int port, u16 vid, bool untagged) 1665 { 1666 u64 mask64; 1667 u64 ctrl64; 1668 1669 mask64 = YT921X_VLAN_CTRL_PORTn(port) | 1670 YT921X_VLAN_CTRL_PORTS(priv->cpu_ports_mask); 1671 ctrl64 = mask64; 1672 1673 mask64 |= YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1674 if (untagged) 1675 ctrl64 |= YT921X_VLAN_CTRL_UNTAG_PORTn(port); 1676 1677 return yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(vid), 1678 mask64, ctrl64); 1679 } 1680 1681 static int 1682 yt921x_pvid_clear(struct yt921x_priv *priv, int port) 1683 { 1684 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1685 bool vlan_filtering; 1686 u32 mask; 1687 int res; 1688 1689 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1690 1691 res = yt921x_port_set_pvid(priv, port, 1692 vlan_filtering ? 0 : YT921X_VID_UNWARE); 1693 if (res) 1694 return res; 1695 1696 if (vlan_filtering) { 1697 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1698 res = yt921x_reg_set_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), 1699 mask); 1700 if (res) 1701 return res; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int 1708 yt921x_pvid_set(struct yt921x_priv *priv, int port, u16 vid) 1709 { 1710 struct dsa_port *dp = dsa_to_port(&priv->ds, port); 1711 bool vlan_filtering; 1712 u32 mask; 1713 int res; 1714 1715 vlan_filtering = dsa_port_is_vlan_filtering(dp); 1716 1717 if (vlan_filtering) { 1718 res = yt921x_port_set_pvid(priv, port, vid); 1719 if (res) 1720 return res; 1721 } 1722 1723 mask = YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED; 1724 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_VLAN_CTRL1(port), mask); 1725 if (res) 1726 return res; 1727 1728 return 0; 1729 } 1730 1731 static int 1732 yt921x_dsa_port_vlan_filtering(struct dsa_switch *ds, int port, 1733 bool vlan_filtering, 1734 struct netlink_ext_ack *extack) 1735 { 1736 struct yt921x_priv *priv = to_yt921x_priv(ds); 1737 int res; 1738 1739 if (dsa_is_cpu_port(ds, port)) 1740 return 0; 1741 1742 mutex_lock(&priv->reg_lock); 1743 res = yt921x_vlan_filtering(priv, port, vlan_filtering); 1744 mutex_unlock(&priv->reg_lock); 1745 1746 return res; 1747 } 1748 1749 static int 1750 yt921x_dsa_port_vlan_del(struct dsa_switch *ds, int port, 1751 const struct switchdev_obj_port_vlan *vlan) 1752 { 1753 struct yt921x_priv *priv = to_yt921x_priv(ds); 1754 u16 vid = vlan->vid; 1755 u16 pvid; 1756 int res; 1757 1758 if (dsa_is_cpu_port(ds, port)) 1759 return 0; 1760 1761 mutex_lock(&priv->reg_lock); 1762 do { 1763 struct dsa_port *dp = dsa_to_port(ds, port); 1764 struct net_device *bdev; 1765 1766 res = yt921x_vlan_del(priv, port, vid); 1767 if (res) 1768 break; 1769 1770 bdev = dsa_port_bridge_dev_get(dp); 1771 if (bdev) { 1772 br_vlan_get_pvid(bdev, &pvid); 1773 if (pvid == vid) 1774 res = yt921x_pvid_clear(priv, port); 1775 } 1776 } while (0); 1777 mutex_unlock(&priv->reg_lock); 1778 1779 return res; 1780 } 1781 1782 static int 1783 yt921x_dsa_port_vlan_add(struct dsa_switch *ds, int port, 1784 const struct switchdev_obj_port_vlan *vlan, 1785 struct netlink_ext_ack *extack) 1786 { 1787 struct yt921x_priv *priv = to_yt921x_priv(ds); 1788 u16 vid = vlan->vid; 1789 u16 pvid; 1790 int res; 1791 1792 /* CPU port is supposed to be a member of every VLAN; see 1793 * yt921x_vlan_add() and yt921x_port_setup() 1794 */ 1795 if (dsa_is_cpu_port(ds, port)) 1796 return 0; 1797 1798 mutex_lock(&priv->reg_lock); 1799 do { 1800 struct dsa_port *dp = dsa_to_port(ds, port); 1801 struct net_device *bdev; 1802 1803 res = yt921x_vlan_add(priv, port, vid, 1804 vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1805 if (res) 1806 break; 1807 1808 bdev = dsa_port_bridge_dev_get(dp); 1809 if (bdev) { 1810 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { 1811 res = yt921x_pvid_set(priv, port, vid); 1812 } else { 1813 br_vlan_get_pvid(bdev, &pvid); 1814 if (pvid == vid) 1815 res = yt921x_pvid_clear(priv, port); 1816 } 1817 } 1818 } while (0); 1819 mutex_unlock(&priv->reg_lock); 1820 1821 return res; 1822 } 1823 1824 static int yt921x_userport_standalone(struct yt921x_priv *priv, int port) 1825 { 1826 u32 mask; 1827 u32 ctrl; 1828 int res; 1829 1830 ctrl = ~priv->cpu_ports_mask; 1831 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), ctrl); 1832 if (res) 1833 return res; 1834 1835 /* Turn off FDB learning to prevent FDB pollution */ 1836 mask = YT921X_PORT_LEARN_DIS; 1837 res = yt921x_reg_set_bits(priv, YT921X_PORTn_LEARN(port), mask); 1838 if (res) 1839 return res; 1840 1841 /* Turn off VLAN awareness */ 1842 mask = YT921X_PORT_IGR_TPIDn_CTAG_M; 1843 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_IGR_TPID(port), mask); 1844 if (res) 1845 return res; 1846 1847 /* Unrelated since learning is off and all packets are trapped; 1848 * set it anyway 1849 */ 1850 res = yt921x_port_set_pvid(priv, port, YT921X_VID_UNWARE); 1851 if (res) 1852 return res; 1853 1854 return 0; 1855 } 1856 1857 static int yt921x_userport_bridge(struct yt921x_priv *priv, int port) 1858 { 1859 u32 mask; 1860 int res; 1861 1862 mask = YT921X_PORT_LEARN_DIS; 1863 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_LEARN(port), mask); 1864 if (res) 1865 return res; 1866 1867 return 0; 1868 } 1869 1870 static int yt921x_isolate(struct yt921x_priv *priv, int port) 1871 { 1872 u32 mask; 1873 int res; 1874 1875 mask = BIT(port); 1876 for (int i = 0; i < YT921X_PORT_NUM; i++) { 1877 if ((BIT(i) & priv->cpu_ports_mask) || i == port) 1878 continue; 1879 1880 res = yt921x_reg_set_bits(priv, YT921X_PORTn_ISOLATION(i), 1881 mask); 1882 if (res) 1883 return res; 1884 } 1885 1886 return 0; 1887 } 1888 1889 /* Make sure to include the CPU port in ports_mask, or your bridge will 1890 * not have it. 1891 */ 1892 static int yt921x_bridge(struct yt921x_priv *priv, u16 ports_mask) 1893 { 1894 unsigned long targets_mask = ports_mask & ~priv->cpu_ports_mask; 1895 u32 isolated_mask; 1896 u32 ctrl; 1897 int port; 1898 int res; 1899 1900 isolated_mask = 0; 1901 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1902 struct yt921x_port *pp = &priv->ports[port]; 1903 1904 if (pp->isolated) 1905 isolated_mask |= BIT(port); 1906 } 1907 1908 /* Block from non-cpu bridge ports ... */ 1909 for_each_set_bit(port, &targets_mask, YT921X_PORT_NUM) { 1910 struct yt921x_port *pp = &priv->ports[port]; 1911 1912 /* to non-bridge ports */ 1913 ctrl = ~ports_mask; 1914 /* to isolated ports when isolated */ 1915 if (pp->isolated) 1916 ctrl |= isolated_mask; 1917 /* to itself when non-hairpin */ 1918 if (!pp->hairpin) 1919 ctrl |= BIT(port); 1920 else 1921 ctrl &= ~BIT(port); 1922 1923 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 1924 ctrl); 1925 if (res) 1926 return res; 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int yt921x_bridge_leave(struct yt921x_priv *priv, int port) 1933 { 1934 int res; 1935 1936 res = yt921x_userport_standalone(priv, port); 1937 if (res) 1938 return res; 1939 1940 res = yt921x_isolate(priv, port); 1941 if (res) 1942 return res; 1943 1944 return 0; 1945 } 1946 1947 static int 1948 yt921x_bridge_join(struct yt921x_priv *priv, int port, u16 ports_mask) 1949 { 1950 int res; 1951 1952 res = yt921x_userport_bridge(priv, port); 1953 if (res) 1954 return res; 1955 1956 res = yt921x_bridge(priv, ports_mask); 1957 if (res) 1958 return res; 1959 1960 return 0; 1961 } 1962 1963 static u32 1964 dsa_bridge_ports(struct dsa_switch *ds, const struct net_device *bdev) 1965 { 1966 struct dsa_port *dp; 1967 u32 mask = 0; 1968 1969 dsa_switch_for_each_user_port(dp, ds) 1970 if (dsa_port_offloads_bridge_dev(dp, bdev)) 1971 mask |= BIT(dp->index); 1972 1973 return mask; 1974 } 1975 1976 static int 1977 yt921x_bridge_flags(struct yt921x_priv *priv, int port, 1978 struct switchdev_brport_flags flags) 1979 { 1980 struct yt921x_port *pp = &priv->ports[port]; 1981 bool do_flush; 1982 u32 mask; 1983 int res; 1984 1985 if (flags.mask & BR_LEARNING) { 1986 bool learning = flags.val & BR_LEARNING; 1987 1988 mask = YT921X_PORT_LEARN_DIS; 1989 res = yt921x_reg_toggle_bits(priv, YT921X_PORTn_LEARN(port), 1990 mask, !learning); 1991 if (res) 1992 return res; 1993 } 1994 1995 /* BR_FLOOD, BR_MCAST_FLOOD: see the comment where ACT_UNK_ACTn_TRAP 1996 * is set 1997 */ 1998 1999 /* BR_BCAST_FLOOD: we can filter bcast, but cannot trap them */ 2000 2001 do_flush = false; 2002 if (flags.mask & BR_HAIRPIN_MODE) { 2003 pp->hairpin = flags.val & BR_HAIRPIN_MODE; 2004 do_flush = true; 2005 } 2006 if (flags.mask & BR_ISOLATED) { 2007 pp->isolated = flags.val & BR_ISOLATED; 2008 do_flush = true; 2009 } 2010 if (do_flush) { 2011 struct dsa_switch *ds = &priv->ds; 2012 struct dsa_port *dp = dsa_to_port(ds, port); 2013 struct net_device *bdev; 2014 2015 bdev = dsa_port_bridge_dev_get(dp); 2016 if (bdev) { 2017 u32 ports_mask; 2018 2019 ports_mask = dsa_bridge_ports(ds, bdev); 2020 ports_mask |= priv->cpu_ports_mask; 2021 res = yt921x_bridge(priv, ports_mask); 2022 if (res) 2023 return res; 2024 } 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int 2031 yt921x_dsa_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2032 struct switchdev_brport_flags flags, 2033 struct netlink_ext_ack *extack) 2034 { 2035 if (flags.mask & ~(BR_HAIRPIN_MODE | BR_LEARNING | BR_FLOOD | 2036 BR_MCAST_FLOOD | BR_ISOLATED)) 2037 return -EINVAL; 2038 return 0; 2039 } 2040 2041 static int 2042 yt921x_dsa_port_bridge_flags(struct dsa_switch *ds, int port, 2043 struct switchdev_brport_flags flags, 2044 struct netlink_ext_ack *extack) 2045 { 2046 struct yt921x_priv *priv = to_yt921x_priv(ds); 2047 int res; 2048 2049 if (dsa_is_cpu_port(ds, port)) 2050 return 0; 2051 2052 mutex_lock(&priv->reg_lock); 2053 res = yt921x_bridge_flags(priv, port, flags); 2054 mutex_unlock(&priv->reg_lock); 2055 2056 return res; 2057 } 2058 2059 static void 2060 yt921x_dsa_port_bridge_leave(struct dsa_switch *ds, int port, 2061 struct dsa_bridge bridge) 2062 { 2063 struct yt921x_priv *priv = to_yt921x_priv(ds); 2064 struct device *dev = to_device(priv); 2065 int res; 2066 2067 if (dsa_is_cpu_port(ds, port)) 2068 return; 2069 2070 mutex_lock(&priv->reg_lock); 2071 res = yt921x_bridge_leave(priv, port); 2072 mutex_unlock(&priv->reg_lock); 2073 2074 if (res) 2075 dev_err(dev, "Failed to %s port %d: %i\n", "unbridge", 2076 port, res); 2077 } 2078 2079 static int 2080 yt921x_dsa_port_bridge_join(struct dsa_switch *ds, int port, 2081 struct dsa_bridge bridge, bool *tx_fwd_offload, 2082 struct netlink_ext_ack *extack) 2083 { 2084 struct yt921x_priv *priv = to_yt921x_priv(ds); 2085 u16 ports_mask; 2086 int res; 2087 2088 if (dsa_is_cpu_port(ds, port)) 2089 return 0; 2090 2091 ports_mask = dsa_bridge_ports(ds, bridge.dev); 2092 ports_mask |= priv->cpu_ports_mask; 2093 2094 mutex_lock(&priv->reg_lock); 2095 res = yt921x_bridge_join(priv, port, ports_mask); 2096 mutex_unlock(&priv->reg_lock); 2097 2098 return res; 2099 } 2100 2101 static int 2102 yt921x_dsa_port_mst_state_set(struct dsa_switch *ds, int port, 2103 const struct switchdev_mst_state *st) 2104 { 2105 struct yt921x_priv *priv = to_yt921x_priv(ds); 2106 u32 mask; 2107 u32 ctrl; 2108 int res; 2109 2110 mask = YT921X_STP_PORTn_M(port); 2111 switch (st->state) { 2112 case BR_STATE_DISABLED: 2113 ctrl = YT921X_STP_PORTn_DISABLED(port); 2114 break; 2115 case BR_STATE_LISTENING: 2116 case BR_STATE_LEARNING: 2117 ctrl = YT921X_STP_PORTn_LEARNING(port); 2118 break; 2119 case BR_STATE_FORWARDING: 2120 default: 2121 ctrl = YT921X_STP_PORTn_FORWARD(port); 2122 break; 2123 case BR_STATE_BLOCKING: 2124 ctrl = YT921X_STP_PORTn_BLOCKING(port); 2125 break; 2126 } 2127 2128 mutex_lock(&priv->reg_lock); 2129 res = yt921x_reg_update_bits(priv, YT921X_STPn(st->msti), mask, ctrl); 2130 mutex_unlock(&priv->reg_lock); 2131 2132 return res; 2133 } 2134 2135 static int 2136 yt921x_dsa_vlan_msti_set(struct dsa_switch *ds, struct dsa_bridge bridge, 2137 const struct switchdev_vlan_msti *msti) 2138 { 2139 struct yt921x_priv *priv = to_yt921x_priv(ds); 2140 u64 mask64; 2141 u64 ctrl64; 2142 int res; 2143 2144 if (!msti->vid) 2145 return -EINVAL; 2146 if (!msti->msti || msti->msti >= YT921X_MSTI_NUM) 2147 return -EINVAL; 2148 2149 mask64 = YT921X_VLAN_CTRL_STP_ID_M; 2150 ctrl64 = YT921X_VLAN_CTRL_STP_ID(msti->msti); 2151 2152 mutex_lock(&priv->reg_lock); 2153 res = yt921x_reg64_update_bits(priv, YT921X_VLANn_CTRL(msti->vid), 2154 mask64, ctrl64); 2155 mutex_unlock(&priv->reg_lock); 2156 2157 return res; 2158 } 2159 2160 static void 2161 yt921x_dsa_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 2162 { 2163 struct yt921x_priv *priv = to_yt921x_priv(ds); 2164 struct dsa_port *dp = dsa_to_port(ds, port); 2165 struct device *dev = to_device(priv); 2166 bool learning; 2167 u32 mask; 2168 u32 ctrl; 2169 int res; 2170 2171 mask = YT921X_STP_PORTn_M(port); 2172 learning = false; 2173 switch (state) { 2174 case BR_STATE_DISABLED: 2175 ctrl = YT921X_STP_PORTn_DISABLED(port); 2176 break; 2177 case BR_STATE_LISTENING: 2178 ctrl = YT921X_STP_PORTn_LEARNING(port); 2179 break; 2180 case BR_STATE_LEARNING: 2181 ctrl = YT921X_STP_PORTn_LEARNING(port); 2182 learning = dp->learning; 2183 break; 2184 case BR_STATE_FORWARDING: 2185 default: 2186 ctrl = YT921X_STP_PORTn_FORWARD(port); 2187 learning = dp->learning; 2188 break; 2189 case BR_STATE_BLOCKING: 2190 ctrl = YT921X_STP_PORTn_BLOCKING(port); 2191 break; 2192 } 2193 2194 mutex_lock(&priv->reg_lock); 2195 do { 2196 res = yt921x_reg_update_bits(priv, YT921X_STPn(0), mask, ctrl); 2197 if (res) 2198 break; 2199 2200 mask = YT921X_PORT_LEARN_DIS; 2201 ctrl = !learning ? YT921X_PORT_LEARN_DIS : 0; 2202 res = yt921x_reg_update_bits(priv, YT921X_PORTn_LEARN(port), 2203 mask, ctrl); 2204 } while (0); 2205 mutex_unlock(&priv->reg_lock); 2206 2207 if (res) 2208 dev_err(dev, "Failed to %s port %d: %i\n", "set STP state for", 2209 port, res); 2210 } 2211 2212 static int yt921x_port_down(struct yt921x_priv *priv, int port) 2213 { 2214 u32 mask; 2215 int res; 2216 2217 mask = YT921X_PORT_LINK | YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_MAC_EN; 2218 res = yt921x_reg_clear_bits(priv, YT921X_PORTn_CTRL(port), mask); 2219 if (res) 2220 return res; 2221 2222 if (yt921x_port_is_external(port)) { 2223 mask = YT921X_SERDES_LINK; 2224 res = yt921x_reg_clear_bits(priv, YT921X_SERDESn(port), mask); 2225 if (res) 2226 return res; 2227 2228 mask = YT921X_XMII_LINK; 2229 res = yt921x_reg_clear_bits(priv, YT921X_XMIIn(port), mask); 2230 if (res) 2231 return res; 2232 } 2233 2234 return 0; 2235 } 2236 2237 static int 2238 yt921x_port_up(struct yt921x_priv *priv, int port, unsigned int mode, 2239 phy_interface_t interface, int speed, int duplex, 2240 bool tx_pause, bool rx_pause) 2241 { 2242 u32 mask; 2243 u32 ctrl; 2244 int res; 2245 2246 switch (speed) { 2247 case SPEED_10: 2248 ctrl = YT921X_PORT_SPEED_10; 2249 break; 2250 case SPEED_100: 2251 ctrl = YT921X_PORT_SPEED_100; 2252 break; 2253 case SPEED_1000: 2254 ctrl = YT921X_PORT_SPEED_1000; 2255 break; 2256 case SPEED_2500: 2257 ctrl = YT921X_PORT_SPEED_2500; 2258 break; 2259 case SPEED_10000: 2260 ctrl = YT921X_PORT_SPEED_10000; 2261 break; 2262 default: 2263 return -EINVAL; 2264 } 2265 if (duplex == DUPLEX_FULL) 2266 ctrl |= YT921X_PORT_DUPLEX_FULL; 2267 if (tx_pause) 2268 ctrl |= YT921X_PORT_TX_PAUSE; 2269 if (rx_pause) 2270 ctrl |= YT921X_PORT_RX_PAUSE; 2271 ctrl |= YT921X_PORT_RX_MAC_EN | YT921X_PORT_TX_MAC_EN; 2272 res = yt921x_reg_write(priv, YT921X_PORTn_CTRL(port), ctrl); 2273 if (res) 2274 return res; 2275 2276 if (yt921x_port_is_external(port)) { 2277 mask = YT921X_SERDES_SPEED_M; 2278 switch (speed) { 2279 case SPEED_10: 2280 ctrl = YT921X_SERDES_SPEED_10; 2281 break; 2282 case SPEED_100: 2283 ctrl = YT921X_SERDES_SPEED_100; 2284 break; 2285 case SPEED_1000: 2286 ctrl = YT921X_SERDES_SPEED_1000; 2287 break; 2288 case SPEED_2500: 2289 ctrl = YT921X_SERDES_SPEED_2500; 2290 break; 2291 case SPEED_10000: 2292 ctrl = YT921X_SERDES_SPEED_10000; 2293 break; 2294 default: 2295 return -EINVAL; 2296 } 2297 mask |= YT921X_SERDES_DUPLEX_FULL; 2298 if (duplex == DUPLEX_FULL) 2299 ctrl |= YT921X_SERDES_DUPLEX_FULL; 2300 mask |= YT921X_SERDES_TX_PAUSE; 2301 if (tx_pause) 2302 ctrl |= YT921X_SERDES_TX_PAUSE; 2303 mask |= YT921X_SERDES_RX_PAUSE; 2304 if (rx_pause) 2305 ctrl |= YT921X_SERDES_RX_PAUSE; 2306 mask |= YT921X_SERDES_LINK; 2307 ctrl |= YT921X_SERDES_LINK; 2308 res = yt921x_reg_update_bits(priv, YT921X_SERDESn(port), 2309 mask, ctrl); 2310 if (res) 2311 return res; 2312 2313 mask = YT921X_XMII_LINK; 2314 res = yt921x_reg_set_bits(priv, YT921X_XMIIn(port), mask); 2315 if (res) 2316 return res; 2317 2318 switch (speed) { 2319 case SPEED_10: 2320 ctrl = YT921X_MDIO_POLLING_SPEED_10; 2321 break; 2322 case SPEED_100: 2323 ctrl = YT921X_MDIO_POLLING_SPEED_100; 2324 break; 2325 case SPEED_1000: 2326 ctrl = YT921X_MDIO_POLLING_SPEED_1000; 2327 break; 2328 case SPEED_2500: 2329 ctrl = YT921X_MDIO_POLLING_SPEED_2500; 2330 break; 2331 case SPEED_10000: 2332 ctrl = YT921X_MDIO_POLLING_SPEED_10000; 2333 break; 2334 default: 2335 return -EINVAL; 2336 } 2337 if (duplex == DUPLEX_FULL) 2338 ctrl |= YT921X_MDIO_POLLING_DUPLEX_FULL; 2339 ctrl |= YT921X_MDIO_POLLING_LINK; 2340 res = yt921x_reg_write(priv, YT921X_MDIO_POLLINGn(port), ctrl); 2341 if (res) 2342 return res; 2343 } 2344 2345 return 0; 2346 } 2347 2348 static int 2349 yt921x_port_config(struct yt921x_priv *priv, int port, unsigned int mode, 2350 phy_interface_t interface) 2351 { 2352 struct device *dev = to_device(priv); 2353 u32 mask; 2354 u32 ctrl; 2355 int res; 2356 2357 if (!yt921x_port_is_external(port)) { 2358 if (interface != PHY_INTERFACE_MODE_INTERNAL) { 2359 dev_err(dev, "Wrong mode %d on port %d\n", 2360 interface, port); 2361 return -EINVAL; 2362 } 2363 return 0; 2364 } 2365 2366 switch (interface) { 2367 /* SERDES */ 2368 case PHY_INTERFACE_MODE_SGMII: 2369 case PHY_INTERFACE_MODE_100BASEX: 2370 case PHY_INTERFACE_MODE_1000BASEX: 2371 case PHY_INTERFACE_MODE_2500BASEX: 2372 mask = YT921X_SERDES_CTRL_PORTn(port); 2373 res = yt921x_reg_set_bits(priv, YT921X_SERDES_CTRL, mask); 2374 if (res) 2375 return res; 2376 2377 mask = YT921X_XMII_CTRL_PORTn(port); 2378 res = yt921x_reg_clear_bits(priv, YT921X_XMII_CTRL, mask); 2379 if (res) 2380 return res; 2381 2382 mask = YT921X_SERDES_MODE_M; 2383 switch (interface) { 2384 case PHY_INTERFACE_MODE_SGMII: 2385 ctrl = YT921X_SERDES_MODE_SGMII; 2386 break; 2387 case PHY_INTERFACE_MODE_100BASEX: 2388 ctrl = YT921X_SERDES_MODE_100BASEX; 2389 break; 2390 case PHY_INTERFACE_MODE_1000BASEX: 2391 ctrl = YT921X_SERDES_MODE_1000BASEX; 2392 break; 2393 case PHY_INTERFACE_MODE_2500BASEX: 2394 ctrl = YT921X_SERDES_MODE_2500BASEX; 2395 break; 2396 default: 2397 return -EINVAL; 2398 } 2399 res = yt921x_reg_update_bits(priv, YT921X_SERDESn(port), 2400 mask, ctrl); 2401 if (res) 2402 return res; 2403 2404 break; 2405 /* add XMII support here */ 2406 default: 2407 return -EINVAL; 2408 } 2409 2410 return 0; 2411 } 2412 2413 static void 2414 yt921x_phylink_mac_link_down(struct phylink_config *config, unsigned int mode, 2415 phy_interface_t interface) 2416 { 2417 struct dsa_port *dp = dsa_phylink_to_port(config); 2418 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2419 int port = dp->index; 2420 int res; 2421 2422 /* No need to sync; port control block is hold until device remove */ 2423 cancel_delayed_work(&priv->ports[port].mib_read); 2424 2425 mutex_lock(&priv->reg_lock); 2426 res = yt921x_port_down(priv, port); 2427 mutex_unlock(&priv->reg_lock); 2428 2429 if (res) 2430 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring down", 2431 port, res); 2432 } 2433 2434 static void 2435 yt921x_phylink_mac_link_up(struct phylink_config *config, 2436 struct phy_device *phydev, unsigned int mode, 2437 phy_interface_t interface, int speed, int duplex, 2438 bool tx_pause, bool rx_pause) 2439 { 2440 struct dsa_port *dp = dsa_phylink_to_port(config); 2441 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2442 int port = dp->index; 2443 int res; 2444 2445 mutex_lock(&priv->reg_lock); 2446 res = yt921x_port_up(priv, port, mode, interface, speed, duplex, 2447 tx_pause, rx_pause); 2448 mutex_unlock(&priv->reg_lock); 2449 2450 if (res) 2451 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "bring up", 2452 port, res); 2453 2454 schedule_delayed_work(&priv->ports[port].mib_read, 0); 2455 } 2456 2457 static void 2458 yt921x_phylink_mac_config(struct phylink_config *config, unsigned int mode, 2459 const struct phylink_link_state *state) 2460 { 2461 struct dsa_port *dp = dsa_phylink_to_port(config); 2462 struct yt921x_priv *priv = to_yt921x_priv(dp->ds); 2463 int port = dp->index; 2464 int res; 2465 2466 mutex_lock(&priv->reg_lock); 2467 res = yt921x_port_config(priv, port, mode, state->interface); 2468 mutex_unlock(&priv->reg_lock); 2469 2470 if (res) 2471 dev_err(dp->ds->dev, "Failed to %s port %d: %i\n", "config", 2472 port, res); 2473 } 2474 2475 static void 2476 yt921x_dsa_phylink_get_caps(struct dsa_switch *ds, int port, 2477 struct phylink_config *config) 2478 { 2479 struct yt921x_priv *priv = to_yt921x_priv(ds); 2480 const struct yt921x_info *info = priv->info; 2481 2482 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2483 MAC_10 | MAC_100 | MAC_1000; 2484 2485 if (info->internal_mask & BIT(port)) { 2486 /* Port 10 for MCU should probably go here too. But since that 2487 * is untested yet, turn it down for the moment by letting it 2488 * fall to the default branch. 2489 */ 2490 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2491 config->supported_interfaces); 2492 } else if (info->external_mask & BIT(port)) { 2493 /* TODO: external ports may support SERDES only, XMII only, or 2494 * SERDES + XMII depending on the chip. However, we can't get 2495 * the accurate config table due to lack of document, thus 2496 * we simply declare SERDES + XMII and rely on the correctness 2497 * of devicetree for now. 2498 */ 2499 2500 /* SERDES */ 2501 __set_bit(PHY_INTERFACE_MODE_SGMII, 2502 config->supported_interfaces); 2503 /* REVSGMII (SGMII in PHY role) should go here, once 2504 * PHY_INTERFACE_MODE_REVSGMII is introduced. 2505 */ 2506 __set_bit(PHY_INTERFACE_MODE_100BASEX, 2507 config->supported_interfaces); 2508 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2509 config->supported_interfaces); 2510 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2511 config->supported_interfaces); 2512 config->mac_capabilities |= MAC_2500FD; 2513 2514 /* XMII */ 2515 2516 /* Not tested. To add support for XMII: 2517 * - Add proper interface modes below 2518 * - Handle them in yt921x_port_config() 2519 */ 2520 } 2521 /* no such port: empty supported_interfaces causes phylink to turn it 2522 * down 2523 */ 2524 } 2525 2526 static int yt921x_port_setup(struct yt921x_priv *priv, int port) 2527 { 2528 struct dsa_switch *ds = &priv->ds; 2529 u32 ctrl; 2530 int res; 2531 2532 res = yt921x_userport_standalone(priv, port); 2533 if (res) 2534 return res; 2535 2536 if (dsa_is_cpu_port(ds, port)) { 2537 /* Egress of CPU port is supposed to be completely controlled 2538 * via tagging, so set to oneway isolated (drop all packets 2539 * without tag). 2540 */ 2541 ctrl = ~(u32)0; 2542 res = yt921x_reg_write(priv, YT921X_PORTn_ISOLATION(port), 2543 ctrl); 2544 if (res) 2545 return res; 2546 2547 /* To simplify FDB "isolation" simulation, we also disable 2548 * learning on the CPU port, and let software identify packets 2549 * towarding CPU (either trapped or a static FDB entry is 2550 * matched, no matter which bridge that entry is for), which is 2551 * already done by yt921x_userport_standalone(). As a result, 2552 * VLAN-awareness becomes unrelated on the CPU port (set to 2553 * VLAN-unaware by the way). 2554 */ 2555 } 2556 2557 return 0; 2558 } 2559 2560 static enum dsa_tag_protocol 2561 yt921x_dsa_get_tag_protocol(struct dsa_switch *ds, int port, 2562 enum dsa_tag_protocol m) 2563 { 2564 return DSA_TAG_PROTO_YT921X; 2565 } 2566 2567 static int yt921x_dsa_port_setup(struct dsa_switch *ds, int port) 2568 { 2569 struct yt921x_priv *priv = to_yt921x_priv(ds); 2570 int res; 2571 2572 mutex_lock(&priv->reg_lock); 2573 res = yt921x_port_setup(priv, port); 2574 mutex_unlock(&priv->reg_lock); 2575 2576 return res; 2577 } 2578 2579 static int yt921x_edata_wait(struct yt921x_priv *priv, u32 *valp) 2580 { 2581 u32 val = YT921X_EDATA_DATA_IDLE; 2582 int res; 2583 2584 res = yt921x_reg_wait(priv, YT921X_EDATA_DATA, 2585 YT921X_EDATA_DATA_STATUS_M, &val); 2586 if (res) 2587 return res; 2588 2589 *valp = val; 2590 return 0; 2591 } 2592 2593 static int 2594 yt921x_edata_read_cont(struct yt921x_priv *priv, u8 addr, u8 *valp) 2595 { 2596 u32 ctrl; 2597 u32 val; 2598 int res; 2599 2600 ctrl = YT921X_EDATA_CTRL_ADDR(addr) | YT921X_EDATA_CTRL_READ; 2601 res = yt921x_reg_write(priv, YT921X_EDATA_CTRL, ctrl); 2602 if (res) 2603 return res; 2604 res = yt921x_edata_wait(priv, &val); 2605 if (res) 2606 return res; 2607 2608 *valp = FIELD_GET(YT921X_EDATA_DATA_DATA_M, val); 2609 return 0; 2610 } 2611 2612 static int yt921x_edata_read(struct yt921x_priv *priv, u8 addr, u8 *valp) 2613 { 2614 u32 val; 2615 int res; 2616 2617 res = yt921x_edata_wait(priv, &val); 2618 if (res) 2619 return res; 2620 return yt921x_edata_read_cont(priv, addr, valp); 2621 } 2622 2623 static int yt921x_chip_detect(struct yt921x_priv *priv) 2624 { 2625 struct device *dev = to_device(priv); 2626 const struct yt921x_info *info; 2627 u8 extmode; 2628 u32 chipid; 2629 u32 major; 2630 u32 mode; 2631 int res; 2632 2633 res = yt921x_reg_read(priv, YT921X_CHIP_ID, &chipid); 2634 if (res) 2635 return res; 2636 2637 major = FIELD_GET(YT921X_CHIP_ID_MAJOR, chipid); 2638 2639 for (info = yt921x_infos; info->name; info++) 2640 if (info->major == major) 2641 break; 2642 if (!info->name) { 2643 dev_err(dev, "Unexpected chipid 0x%x\n", chipid); 2644 return -ENODEV; 2645 } 2646 2647 res = yt921x_reg_read(priv, YT921X_CHIP_MODE, &mode); 2648 if (res) 2649 return res; 2650 res = yt921x_edata_read(priv, YT921X_EDATA_EXTMODE, &extmode); 2651 if (res) 2652 return res; 2653 2654 for (; info->name; info++) 2655 if (info->major == major && info->mode == mode && 2656 info->extmode == extmode) 2657 break; 2658 if (!info->name) { 2659 dev_err(dev, 2660 "Unsupported chipid 0x%x with chipmode 0x%x 0x%x\n", 2661 chipid, mode, extmode); 2662 return -ENODEV; 2663 } 2664 2665 /* Print chipid here since we are interested in lower 16 bits */ 2666 dev_info(dev, 2667 "Motorcomm %s ethernet switch, chipid: 0x%x, chipmode: 0x%x 0x%x\n", 2668 info->name, chipid, mode, extmode); 2669 2670 priv->info = info; 2671 return 0; 2672 } 2673 2674 static int yt921x_chip_reset(struct yt921x_priv *priv) 2675 { 2676 struct device *dev = to_device(priv); 2677 u16 eth_p_tag; 2678 u32 val; 2679 int res; 2680 2681 res = yt921x_chip_detect(priv); 2682 if (res) 2683 return res; 2684 2685 /* Reset */ 2686 res = yt921x_reg_write(priv, YT921X_RST, YT921X_RST_HW); 2687 if (res) 2688 return res; 2689 2690 /* RST_HW is almost same as GPIO hard reset, so we need this delay. */ 2691 fsleep(YT921X_RST_DELAY_US); 2692 2693 val = 0; 2694 res = yt921x_reg_wait(priv, YT921X_RST, ~0, &val); 2695 if (res) 2696 return res; 2697 2698 /* Check for tag EtherType; do it after reset in case you messed it up 2699 * before. 2700 */ 2701 res = yt921x_reg_read(priv, YT921X_CPU_TAG_TPID, &val); 2702 if (res) 2703 return res; 2704 eth_p_tag = FIELD_GET(YT921X_CPU_TAG_TPID_TPID_M, val); 2705 if (eth_p_tag != ETH_P_YT921X) { 2706 dev_err(dev, "Tag type 0x%x != 0x%x\n", eth_p_tag, 2707 ETH_P_YT921X); 2708 /* Despite being possible, we choose not to set CPU_TAG_TPID, 2709 * since there is no way it can be different unless you have the 2710 * wrong chip. 2711 */ 2712 return -EINVAL; 2713 } 2714 2715 return 0; 2716 } 2717 2718 static int yt921x_chip_setup(struct yt921x_priv *priv) 2719 { 2720 struct dsa_switch *ds = &priv->ds; 2721 unsigned long cpu_ports_mask; 2722 u64 ctrl64; 2723 u32 ctrl; 2724 int port; 2725 int res; 2726 2727 /* Enable DSA */ 2728 priv->cpu_ports_mask = dsa_cpu_ports(ds); 2729 2730 ctrl = YT921X_EXT_CPU_PORT_TAG_EN | YT921X_EXT_CPU_PORT_PORT_EN | 2731 YT921X_EXT_CPU_PORT_PORT(__ffs(priv->cpu_ports_mask)); 2732 res = yt921x_reg_write(priv, YT921X_EXT_CPU_PORT, ctrl); 2733 if (res) 2734 return res; 2735 2736 /* Enable and clear MIB */ 2737 res = yt921x_reg_set_bits(priv, YT921X_FUNC, YT921X_FUNC_MIB); 2738 if (res) 2739 return res; 2740 2741 ctrl = YT921X_MIB_CTRL_CLEAN | YT921X_MIB_CTRL_ALL_PORT; 2742 res = yt921x_reg_write(priv, YT921X_MIB_CTRL, ctrl); 2743 if (res) 2744 return res; 2745 2746 /* Setup software switch */ 2747 ctrl = YT921X_CPU_COPY_TO_EXT_CPU; 2748 res = yt921x_reg_write(priv, YT921X_CPU_COPY, ctrl); 2749 if (res) 2750 return res; 2751 2752 ctrl = GENMASK(10, 0); 2753 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_UCAST, ctrl); 2754 if (res) 2755 return res; 2756 res = yt921x_reg_write(priv, YT921X_FILTER_UNK_MCAST, ctrl); 2757 if (res) 2758 return res; 2759 2760 /* YT921x does not support native DSA port bridging, so we use port 2761 * isolation to emulate it. However, be especially careful that port 2762 * isolation takes _after_ FDB lookups, i.e. if an FDB entry (from 2763 * another bridge) is matched and the destination port (in another 2764 * bridge) is blocked, the packet will be dropped instead of flooding to 2765 * the "bridged" ports, thus we need to trap and handle those packets by 2766 * software. 2767 * 2768 * If there is no more than one bridge, we might be able to drop them 2769 * directly given some conditions are met, but we trap them in all cases 2770 * for now. 2771 */ 2772 ctrl = 0; 2773 for (int i = 0; i < YT921X_PORT_NUM; i++) 2774 ctrl |= YT921X_ACT_UNK_ACTn_TRAP(i); 2775 /* Except for CPU ports, if any packets are sent via CPU ports without 2776 * tag, they should be dropped. 2777 */ 2778 cpu_ports_mask = priv->cpu_ports_mask; 2779 for_each_set_bit(port, &cpu_ports_mask, YT921X_PORT_NUM) { 2780 ctrl &= ~YT921X_ACT_UNK_ACTn_M(port); 2781 ctrl |= YT921X_ACT_UNK_ACTn_DROP(port); 2782 } 2783 res = yt921x_reg_write(priv, YT921X_ACT_UNK_UCAST, ctrl); 2784 if (res) 2785 return res; 2786 res = yt921x_reg_write(priv, YT921X_ACT_UNK_MCAST, ctrl); 2787 if (res) 2788 return res; 2789 2790 /* Tagged VID 0 should be treated as untagged, which confuses the 2791 * hardware a lot 2792 */ 2793 ctrl64 = YT921X_VLAN_CTRL_LEARN_DIS | YT921X_VLAN_CTRL_PORTS_M; 2794 res = yt921x_reg64_write(priv, YT921X_VLANn_CTRL(0), ctrl64); 2795 if (res) 2796 return res; 2797 2798 /* Miscellaneous */ 2799 res = yt921x_reg_set_bits(priv, YT921X_SENSOR, YT921X_SENSOR_TEMP); 2800 if (res) 2801 return res; 2802 2803 return 0; 2804 } 2805 2806 static int yt921x_dsa_setup(struct dsa_switch *ds) 2807 { 2808 struct yt921x_priv *priv = to_yt921x_priv(ds); 2809 struct device *dev = to_device(priv); 2810 struct device_node *np = dev->of_node; 2811 struct device_node *child; 2812 int res; 2813 2814 mutex_lock(&priv->reg_lock); 2815 res = yt921x_chip_reset(priv); 2816 mutex_unlock(&priv->reg_lock); 2817 2818 if (res) 2819 return res; 2820 2821 /* Register the internal mdio bus. Nodes for internal ports should have 2822 * proper phy-handle pointing to their PHYs. Not enabling the internal 2823 * bus is possible, though pretty wired, if internal ports are not used. 2824 */ 2825 child = of_get_child_by_name(np, "mdio"); 2826 if (child) { 2827 res = yt921x_mbus_int_init(priv, child); 2828 of_node_put(child); 2829 if (res) 2830 return res; 2831 } 2832 2833 /* External mdio bus is optional */ 2834 child = of_get_child_by_name(np, "mdio-external"); 2835 if (child) { 2836 res = yt921x_mbus_ext_init(priv, child); 2837 of_node_put(child); 2838 if (res) 2839 return res; 2840 2841 dev_err(dev, "Untested external mdio bus\n"); 2842 return -ENODEV; 2843 } 2844 2845 mutex_lock(&priv->reg_lock); 2846 res = yt921x_chip_setup(priv); 2847 mutex_unlock(&priv->reg_lock); 2848 2849 if (res) 2850 return res; 2851 2852 return 0; 2853 } 2854 2855 static const struct phylink_mac_ops yt921x_phylink_mac_ops = { 2856 .mac_link_down = yt921x_phylink_mac_link_down, 2857 .mac_link_up = yt921x_phylink_mac_link_up, 2858 .mac_config = yt921x_phylink_mac_config, 2859 }; 2860 2861 static const struct dsa_switch_ops yt921x_dsa_switch_ops = { 2862 /* mib */ 2863 .get_strings = yt921x_dsa_get_strings, 2864 .get_ethtool_stats = yt921x_dsa_get_ethtool_stats, 2865 .get_sset_count = yt921x_dsa_get_sset_count, 2866 .get_eth_mac_stats = yt921x_dsa_get_eth_mac_stats, 2867 .get_eth_ctrl_stats = yt921x_dsa_get_eth_ctrl_stats, 2868 .get_rmon_stats = yt921x_dsa_get_rmon_stats, 2869 .get_stats64 = yt921x_dsa_get_stats64, 2870 .get_pause_stats = yt921x_dsa_get_pause_stats, 2871 /* eee */ 2872 .support_eee = dsa_supports_eee, 2873 .set_mac_eee = yt921x_dsa_set_mac_eee, 2874 /* mtu */ 2875 .port_change_mtu = yt921x_dsa_port_change_mtu, 2876 .port_max_mtu = yt921x_dsa_port_max_mtu, 2877 /* hsr */ 2878 .port_hsr_leave = dsa_port_simple_hsr_leave, 2879 .port_hsr_join = dsa_port_simple_hsr_join, 2880 /* mirror */ 2881 .port_mirror_del = yt921x_dsa_port_mirror_del, 2882 .port_mirror_add = yt921x_dsa_port_mirror_add, 2883 /* fdb */ 2884 .port_fdb_dump = yt921x_dsa_port_fdb_dump, 2885 .port_fast_age = yt921x_dsa_port_fast_age, 2886 .set_ageing_time = yt921x_dsa_set_ageing_time, 2887 .port_fdb_del = yt921x_dsa_port_fdb_del, 2888 .port_fdb_add = yt921x_dsa_port_fdb_add, 2889 .port_mdb_del = yt921x_dsa_port_mdb_del, 2890 .port_mdb_add = yt921x_dsa_port_mdb_add, 2891 /* vlan */ 2892 .port_vlan_filtering = yt921x_dsa_port_vlan_filtering, 2893 .port_vlan_del = yt921x_dsa_port_vlan_del, 2894 .port_vlan_add = yt921x_dsa_port_vlan_add, 2895 /* bridge */ 2896 .port_pre_bridge_flags = yt921x_dsa_port_pre_bridge_flags, 2897 .port_bridge_flags = yt921x_dsa_port_bridge_flags, 2898 .port_bridge_leave = yt921x_dsa_port_bridge_leave, 2899 .port_bridge_join = yt921x_dsa_port_bridge_join, 2900 /* mst */ 2901 .port_mst_state_set = yt921x_dsa_port_mst_state_set, 2902 .vlan_msti_set = yt921x_dsa_vlan_msti_set, 2903 .port_stp_state_set = yt921x_dsa_port_stp_state_set, 2904 /* port */ 2905 .get_tag_protocol = yt921x_dsa_get_tag_protocol, 2906 .phylink_get_caps = yt921x_dsa_phylink_get_caps, 2907 .port_setup = yt921x_dsa_port_setup, 2908 /* chip */ 2909 .setup = yt921x_dsa_setup, 2910 }; 2911 2912 static void yt921x_mdio_shutdown(struct mdio_device *mdiodev) 2913 { 2914 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2915 2916 if (!priv) 2917 return; 2918 2919 dsa_switch_shutdown(&priv->ds); 2920 } 2921 2922 static void yt921x_mdio_remove(struct mdio_device *mdiodev) 2923 { 2924 struct yt921x_priv *priv = mdiodev_get_drvdata(mdiodev); 2925 2926 if (!priv) 2927 return; 2928 2929 for (size_t i = ARRAY_SIZE(priv->ports); i-- > 0; ) { 2930 struct yt921x_port *pp = &priv->ports[i]; 2931 2932 disable_delayed_work_sync(&pp->mib_read); 2933 } 2934 2935 dsa_unregister_switch(&priv->ds); 2936 2937 mutex_destroy(&priv->reg_lock); 2938 } 2939 2940 static int yt921x_mdio_probe(struct mdio_device *mdiodev) 2941 { 2942 struct device *dev = &mdiodev->dev; 2943 struct yt921x_reg_mdio *mdio; 2944 struct yt921x_priv *priv; 2945 struct dsa_switch *ds; 2946 2947 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2948 if (!priv) 2949 return -ENOMEM; 2950 2951 mdio = devm_kzalloc(dev, sizeof(*mdio), GFP_KERNEL); 2952 if (!mdio) 2953 return -ENOMEM; 2954 2955 mdio->bus = mdiodev->bus; 2956 mdio->addr = mdiodev->addr; 2957 mdio->switchid = 0; 2958 2959 mutex_init(&priv->reg_lock); 2960 2961 priv->reg_ops = &yt921x_reg_ops_mdio; 2962 priv->reg_ctx = mdio; 2963 2964 for (size_t i = 0; i < ARRAY_SIZE(priv->ports); i++) { 2965 struct yt921x_port *pp = &priv->ports[i]; 2966 2967 pp->index = i; 2968 INIT_DELAYED_WORK(&pp->mib_read, yt921x_poll_mib); 2969 } 2970 2971 ds = &priv->ds; 2972 ds->dev = dev; 2973 ds->assisted_learning_on_cpu_port = true; 2974 ds->priv = priv; 2975 ds->ops = &yt921x_dsa_switch_ops; 2976 ds->ageing_time_min = 1 * 5000; 2977 ds->ageing_time_max = U16_MAX * 5000; 2978 ds->phylink_mac_ops = &yt921x_phylink_mac_ops; 2979 ds->num_ports = YT921X_PORT_NUM; 2980 2981 mdiodev_set_drvdata(mdiodev, priv); 2982 2983 return dsa_register_switch(ds); 2984 } 2985 2986 static const struct of_device_id yt921x_of_match[] = { 2987 { .compatible = "motorcomm,yt9215" }, 2988 {} 2989 }; 2990 MODULE_DEVICE_TABLE(of, yt921x_of_match); 2991 2992 static struct mdio_driver yt921x_mdio_driver = { 2993 .probe = yt921x_mdio_probe, 2994 .remove = yt921x_mdio_remove, 2995 .shutdown = yt921x_mdio_shutdown, 2996 .mdiodrv.driver = { 2997 .name = YT921X_NAME, 2998 .of_match_table = yt921x_of_match, 2999 }, 3000 }; 3001 3002 mdio_module_driver(yt921x_mdio_driver); 3003 3004 MODULE_AUTHOR("David Yang <mmyangfl@gmail.com>"); 3005 MODULE_DESCRIPTION("Driver for Motorcomm YT921x Switch"); 3006 MODULE_LICENSE("GPL"); 3007