1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII, SGMII and HSGMII interfaces are implemented 44 * in this driver. 45 * 46 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 47 * custom irqchip to handle this interrupt and demultiplex the events by reading 48 * the status registers via SMI. Interrupts are then propagated to the relevant 49 * PHY device. 50 * 51 * The EEPROM contains initial register values which the chip will read over I2C 52 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 53 * the driver will manually reprogram some registers using jam tables to reach 54 * an initial state defined by the vendor driver. 55 * 56 * This Linux driver is written based on an OS-agnostic vendor driver from 57 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 58 * source tree under the name rtl8367c. The vendor driver claims to support a 59 * number of similar switch controllers from Realtek, but the only hardware we 60 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 61 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 62 * common hardware revision, there exist examples of chips with the suffix -VC 63 * which are explicitly not supported by the rtl8367c driver and which instead 64 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 65 * been modestly named rtl8365mb. Future implementors may wish to rename things 66 * accordingly. 67 * 68 * In the same family of chips, some carry up to 8 user ports and up to 2 69 * extension ports. Where possible this driver tries to make things generic, but 70 * more work must be done to support these configurations. According to 71 * documentation from Realtek, the family should include the following chips: 72 * 73 * - RTL8363NB 74 * - RTL8363NB-VB 75 * - RTL8363SC 76 * - RTL8363SC-VB 77 * - RTL8364NB 78 * - RTL8364NB-VB 79 * - RTL8365MB-VC 80 * - RTL8366SC 81 * - RTL8367RB-VB 82 * - RTL8367SB 83 * - RTL8367S 84 * - RTL8370MB 85 * - RTL8310SR 86 * 87 * Some of the register logic for these additional chips has been skipped over 88 * while implementing this driver. It is therefore not possible to assume that 89 * things will work out-of-the-box for other chips, and a careful review of the 90 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 91 * one of the simpler chips. 92 */ 93 94 #include <linux/bitfield.h> 95 #include <linux/bitops.h> 96 #include <linux/interrupt.h> 97 #include <linux/irqdomain.h> 98 #include <linux/mii.h> 99 #include <linux/mutex.h> 100 #include <linux/of_irq.h> 101 #include <linux/regmap.h> 102 #include <linux/if_bridge.h> 103 #include <linux/if_vlan.h> 104 #include <linux/phylink.h> 105 106 #include "realtek.h" 107 #include "realtek-smi.h" 108 #include "realtek-mdio.h" 109 #include "rtl83xx.h" 110 #include "rtl8365mb_l2.h" 111 #include "rtl8365mb_vlan.h" 112 113 /* Family-specific data and limits */ 114 #define RTL8365MB_PHYADDRMAX 7 115 #define RTL8365MB_NUM_PHYREGS 32 116 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 117 #define RTL8365MB_MAX_NUM_PORTS 11 118 /* Valid for the whole family except RTL8370B, which has 4160 entries. 119 * RTL8370B is mentioned in vendor code but it might not even belong 120 * to the same RTL8367C family. 121 */ 122 #define RTL8365MB_LEARN_LIMIT_MAX 2112 123 #define RTL8365MB_MAX_NUM_EXTINTS 3 124 125 /* Chip identification registers */ 126 #define RTL8365MB_CHIP_ID_REG 0x1300 127 128 #define RTL8365MB_CHIP_VER_REG 0x1301 129 130 #define RTL8365MB_MAGIC_REG 0x13C2 131 #define RTL8365MB_MAGIC_VALUE 0x0249 132 133 /* Chip reset register */ 134 #define RTL8365MB_CHIP_RESET_REG 0x1322 135 #define RTL8365MB_CHIP_RESET_DW8051_MASK 0x0010 136 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 137 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 138 139 /* Interrupt polarity register */ 140 #define RTL8365MB_INTR_POLARITY_REG 0x1100 141 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 142 #define RTL8365MB_INTR_POLARITY_HIGH 0 143 #define RTL8365MB_INTR_POLARITY_LOW 1 144 145 /* Interrupt control/status register - enable/check specific interrupt types */ 146 #define RTL8365MB_INTR_CTRL_REG 0x1101 147 #define RTL8365MB_INTR_STATUS_REG 0x1102 148 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 149 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 150 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 151 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 152 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 153 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 154 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 155 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 156 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 157 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 158 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 159 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 160 #define RTL8365MB_INTR_ALL_MASK \ 161 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 162 RTL8365MB_INTR_SLIENT_START_MASK | \ 163 RTL8365MB_INTR_ACL_ACTION_MASK | \ 164 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 165 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 166 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 167 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 168 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 169 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 170 RTL8365MB_INTR_LEARN_OVER_MASK | \ 171 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 172 RTL8365MB_INTR_LINK_CHANGE_MASK) 173 174 /* Per-port interrupt type status registers */ 175 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 176 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 177 178 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 179 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 180 181 /* PHY indirect access registers */ 182 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 183 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 184 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 185 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 186 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 187 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 188 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 189 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 190 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 191 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 192 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 193 #define RTL8365MB_PHY_BASE 0x2000 194 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 195 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 196 197 /* PHY OCP address prefix register */ 198 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 199 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 200 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 201 202 /* The PHY OCP addresses of PHY registers 0~31 start here */ 203 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 204 205 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 206 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 207 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 208 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 209 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 210 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 211 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 212 #define RTL8365MB_EXT_PORT_MODE_GMII 6 213 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 214 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 215 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 216 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 217 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 218 #define RTL8365MB_EXT_PORT_MODE_1000X 12 219 #define RTL8365MB_EXT_PORT_MODE_100FX 13 220 221 /* External interface mode configuration registers 0~1 */ 222 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT0,EXT1 */ 223 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 224 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 225 ((_extint) <= 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 226 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 227 0x0) 228 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 229 (0xF << (((_extint) % 2) * 4)) 230 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 231 (((_extint) % 2) * 4) 232 233 /* External interface RGMII TX/RX delay configuration registers 0~2 */ 234 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 235 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 236 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 237 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 238 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 239 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 240 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 241 0x0) 242 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 243 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 244 245 /* External interface line rate bypass register - one bit per external 246 * interface, indexed by the external port number with port 5 (the first 247 * external port) as the base. Other RTL8367 families index this register 248 * differently (e.g. the RTL8367R uses (id + 1) % 2), so this mapping only 249 * holds for the RTL8367C-style parts this driver supports. 250 */ 251 #define RTL8365MB_BYPASS_LINE_RATE_REG 0x03F7 252 #define RTL8365MB_BYPASS_LINE_RATE_MASK(_port) BIT((_port) - 5) 253 254 /* Port 6 ingress and egress rate limiter registers. Each limit is a 19-bit 255 * value in units of 8 Kbps, split across a 16-bit LSB register (CTRL0) and a 256 * 3-bit MSB field (CTRL1). The chip resets them to 0x1FFFF; see 257 * rtl8365mb_sds_raise_rate_limits(). 258 */ 259 #define RTL8365MB_INGRESSBW_PORT6_RATE_CTRL0_REG 0x00CF 260 #define RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_REG 0x00D0 261 #define RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_MASK 0x0007 262 #define RTL8365MB_PORT6_EGRESSBW_CTRL0_REG 0x0398 263 #define RTL8365MB_PORT6_EGRESSBW_CTRL1_REG 0x0399 264 #define RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK 0x0007 265 266 /* SerDes indirect access registers */ 267 #define RTL8365MB_SDS_INDACS_CMD_REG 0x6600 268 #define RTL8365MB_SDS_INDACS_CMD_BUSY_MASK 0x0100 269 #define RTL8365MB_SDS_INDACS_CMD_RUN_MASK 0x0080 270 #define RTL8365MB_SDS_INDACS_CMD_WR_MASK 0x0040 271 #define RTL8365MB_SDS_INDACS_ADR_REG 0x6601 272 #define RTL8365MB_SDS_INDACS_DATA_REG 0x6602 273 274 /* SerDes miscellaneous configuration register */ 275 #define RTL8365MB_SDS_MISC_REG 0x1D11 276 #define RTL8365MB_SDS_MISC_SGMII_RXFC_MASK 0x4000 277 #define RTL8365MB_SDS_MISC_SGMII_TXFC_MASK 0x2000 278 #define RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK 0x0800 279 #define RTL8365MB_SDS_MISC_SGMII_FDUP_MASK 0x0400 280 #define RTL8365MB_SDS_MISC_SGMII_LINK_MASK 0x0200 281 #define RTL8365MB_SDS_MISC_SGMII_SPD_MASK 0x0180 282 #define RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK 0x0040 283 284 /* SerDes internal registers, accessed via the SDS_INDACS registers. The BMCR 285 * data path reset holds BMCR_ANENABLE | BMCR_ISOLATE while toggling the 286 * vendor-specific low bits from phase 1 to phase 2, which triggers a data path 287 * reset and PLL resync. 288 */ 289 #define RTL8365MB_SDS_REG_BMCR 0x0000 290 #define RTL8365MB_SDS_BMCR_DPRST_PHASE1 (BMCR_ANENABLE | BMCR_ISOLATE | 0x1) 291 #define RTL8365MB_SDS_BMCR_DPRST_PHASE2 (BMCR_ANENABLE | BMCR_ISOLATE | 0x3) 292 #define RTL8365MB_SDS_REG_NWAY 0x0002 293 #define RTL8365MB_SDS_NWAY_EN_MASK 0x0200 294 #define RTL8365MB_SDS_NWAY_RESTART_MASK 0x0100 295 #define RTL8365MB_SDS_REG_RESET 0x0003 296 #define RTL8365MB_SDS_RESET_DEASSERT 0x7106 297 #define RTL8365MB_SDS_REG_LINK_STATUS 0x003d 298 #define RTL8365MB_SDS_LINK_STATUS_LINK_MASK 0x0010 299 300 /* The embedded SerDes can only be muxed to external interface 1 (MAC8), 301 * which is port 6. 302 */ 303 #define RTL8365MB_SDS_EXT_INTERFACE_ID 1 304 #define RTL8365MB_SDS_EXT_INTERFACE_PORT 6 305 306 /* Line rate bypass bit for the SerDes external interface */ 307 #define RTL8365MB_SDS_BYPASS_LINE_RATE_MASK \ 308 RTL8365MB_BYPASS_LINE_RATE_MASK(RTL8365MB_SDS_EXT_INTERFACE_PORT) 309 310 /* SerDes tuning parameter variant selector. The vendor driver picks between 311 * two sets of SerDes tuning parameters based on this chip option. Reading it 312 * requires first arming the read by writing a magic key to the arm register, 313 * then disarming it afterwards. 314 */ 315 #define RTL8365MB_SDS_OPTION_ARM_REG 0x13C0 316 #define RTL8365MB_SDS_OPTION_ARM_KEY 0x0249 317 #define RTL8365MB_SDS_OPTION_REG 0x13C1 318 319 /* Embedded DW8051 microcontroller control registers. The microcontroller 320 * can run firmware to manage the SerDes link, but this driver keeps it in 321 * reset and disabled: phylink already performs the link management that 322 * the firmware would otherwise do. 323 */ 324 #define RTL8365MB_MISC_CFG0_REG 0x130C 325 #define RTL8365MB_MISC_CFG0_DW8051_EN_MASK 0x0020 326 327 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 328 #define RTL8365MB_PORT_SPEED_10M 0 329 #define RTL8365MB_PORT_SPEED_100M 1 330 #define RTL8365MB_PORT_SPEED_1000M 2 331 332 /* External interface force configuration registers 0~2 */ 333 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 334 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 335 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 336 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 337 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 338 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 339 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 340 0x0) 341 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 342 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 343 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 344 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 345 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 346 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 347 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 348 349 /* CPU port mask register - controls which ports are treated as CPU ports */ 350 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 351 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 352 353 /* CPU control register */ 354 #define RTL8365MB_CPU_CTRL_REG 0x121A 355 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 356 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 357 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 358 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 359 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 360 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 361 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 362 363 /* Maximum packet length register */ 364 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 365 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 366 #define RTL8365MB_CFG0_MAX_LEN_MAX 0x3FFF 367 368 /* Port learning limit registers */ 369 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 370 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 371 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 372 373 /* Port isolation (forwarding mask) registers */ 374 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 375 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 376 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 377 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 378 379 /* Extended filter ID registers - used to key forwarding database with IVL */ 380 #define RTL8365MB_EFID_MASK GENMASK(2, 0) 381 #define RTL8365MB_PORT_EFID_REG_BASE 0x0A32 382 #define RTL8365MB_PORT_EFID_REG(_p) \ 383 (RTL8365MB_PORT_EFID_REG_BASE + ((_p) >> 2)) 384 #define RTL8365MB_PORT_EFID_OFFSET(_p) (((_p) & 0x3) << 2) 385 #define RTL8365MB_PORT_EFID_MASK(_p) \ 386 (RTL8365MB_EFID_MASK << RTL8365MB_PORT_EFID_OFFSET(_p)) 387 388 /* MSTP port state registers - indexed by tree instance */ 389 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 390 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 391 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 392 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 393 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 394 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 395 396 /* Unknown unicast DA flooding port mask */ 397 #define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG 0x0890 398 #define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_MASK 0x07FF 399 400 /* Unknown multicast DA flooding port mask */ 401 #define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG 0x0891 402 #define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_MASK 0x07FF 403 404 /* Broadcast flooding port mask */ 405 #define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG 0x0892 406 #define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_MASK 0x07FF 407 408 #define RTL8365MB_SUPPORTED_BRIDGE_FLAGS \ 409 (BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD) 410 411 /* Miscellaneous port configuration register, incl. VLAN egress mode */ 412 #define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E 413 #define RTL8365MB_PORT_MISC_CFG_REG(_p) \ 414 (RTL8365MB_PORT_MISC_CFG_REG_BASE + ((_p) << 5)) 415 #define RTL8365MB_PORT_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 416 #define RTL8365MB_PORT_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 417 #define RTL8365MB_PORT_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 418 #define RTL8365MB_PORT_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 419 #define RTL8365MB_PORT_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x0800 420 #define RTL8365MB_PORT_MISC_CFG_INGRESSBW_IFG_MASK 0x0400 421 #define RTL8365MB_PORT_MISC_CFG_RX_SPC_MASK 0x0200 422 #define RTL8365MB_PORT_MISC_CFG_CRC_SKIP_MASK 0x0100 423 #define RTL8365MB_PORT_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x0080 424 #define RTL8365MB_PORT_MISC_CFG_MAC_LOOPBACK_MASK 0x0040 425 /* See &rtl8365mb_vlan_egress_mode */ 426 #define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x0030 427 #define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0x000F 428 429 /** 430 * enum rtl8365mb_vlan_egress_mode - port VLAN egress mode 431 * @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table entry 432 * @RTL8365MB_VLAN_EGRESS_MODE_KEEP: the VLAN tag format of egressed packets 433 * will remain the same as their ingressed format, but the priority and VID 434 * fields may be altered 435 * @RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG: always egress with priority tag 436 * @RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP: the VLAN tag format of egressed 437 * packets will remain the same as their ingressed format, and neither the 438 * priority nor VID fields can be altered 439 */ 440 enum rtl8365mb_vlan_egress_mode { 441 RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL = 0, 442 RTL8365MB_VLAN_EGRESS_MODE_KEEP = 1, 443 RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG = 2, 444 RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP = 3, 445 }; 446 447 /* VLAN control register */ 448 #define RTL8365MB_VLAN_CTRL_REG 0x07A8 449 #define RTL8365MB_VLAN_CTRL_EN_MASK 0x0001 450 451 /* VLAN ingress filter register */ 452 #define RTL8365MB_VLAN_INGRESS_REG 0x07A9 453 #define RTL8365MB_VLAN_INGRESS_MASK GENMASK(10, 0) 454 #define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_OFFSET(_p) (_p) 455 #define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(_p) BIT(_p) 456 457 /* VLAN "transparent" setting registers */ 458 #define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE 0x09D0 459 #define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(_p) \ 460 (RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE + (_p)) 461 462 /* MIB counter value registers */ 463 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 464 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 465 466 /* MIB counter address register */ 467 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 468 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 469 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 470 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 471 472 #define RTL8365MB_MIB_CTRL0_REG 0x1005 473 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 474 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 475 476 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 477 * to block. On the other hand, accessing MIB counters absolutely requires us to 478 * block. The solution is thus to schedule work which polls the MIB counters 479 * asynchronously and updates some private data, which the callback can then 480 * fetch atomically. Three seconds should be a good enough polling interval. 481 */ 482 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 483 484 enum rtl8365mb_mib_counter_index { 485 RTL8365MB_MIB_ifInOctets, 486 RTL8365MB_MIB_dot3StatsFCSErrors, 487 RTL8365MB_MIB_dot3StatsSymbolErrors, 488 RTL8365MB_MIB_dot3InPauseFrames, 489 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 490 RTL8365MB_MIB_etherStatsFragments, 491 RTL8365MB_MIB_etherStatsJabbers, 492 RTL8365MB_MIB_ifInUcastPkts, 493 RTL8365MB_MIB_etherStatsDropEvents, 494 RTL8365MB_MIB_ifInMulticastPkts, 495 RTL8365MB_MIB_ifInBroadcastPkts, 496 RTL8365MB_MIB_inMldChecksumError, 497 RTL8365MB_MIB_inIgmpChecksumError, 498 RTL8365MB_MIB_inMldSpecificQuery, 499 RTL8365MB_MIB_inMldGeneralQuery, 500 RTL8365MB_MIB_inIgmpSpecificQuery, 501 RTL8365MB_MIB_inIgmpGeneralQuery, 502 RTL8365MB_MIB_inMldLeaves, 503 RTL8365MB_MIB_inIgmpLeaves, 504 RTL8365MB_MIB_etherStatsOctets, 505 RTL8365MB_MIB_etherStatsUnderSizePkts, 506 RTL8365MB_MIB_etherOversizeStats, 507 RTL8365MB_MIB_etherStatsPkts64Octets, 508 RTL8365MB_MIB_etherStatsPkts65to127Octets, 509 RTL8365MB_MIB_etherStatsPkts128to255Octets, 510 RTL8365MB_MIB_etherStatsPkts256to511Octets, 511 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 512 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 513 RTL8365MB_MIB_ifOutOctets, 514 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 515 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 516 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 517 RTL8365MB_MIB_dot3StatsLateCollisions, 518 RTL8365MB_MIB_etherStatsCollisions, 519 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 520 RTL8365MB_MIB_dot3OutPauseFrames, 521 RTL8365MB_MIB_ifOutDiscards, 522 RTL8365MB_MIB_dot1dTpPortInDiscards, 523 RTL8365MB_MIB_ifOutUcastPkts, 524 RTL8365MB_MIB_ifOutMulticastPkts, 525 RTL8365MB_MIB_ifOutBroadcastPkts, 526 RTL8365MB_MIB_outOampduPkts, 527 RTL8365MB_MIB_inOampduPkts, 528 RTL8365MB_MIB_inIgmpJoinsSuccess, 529 RTL8365MB_MIB_inIgmpJoinsFail, 530 RTL8365MB_MIB_inMldJoinsSuccess, 531 RTL8365MB_MIB_inMldJoinsFail, 532 RTL8365MB_MIB_inReportSuppressionDrop, 533 RTL8365MB_MIB_inLeaveSuppressionDrop, 534 RTL8365MB_MIB_outIgmpReports, 535 RTL8365MB_MIB_outIgmpLeaves, 536 RTL8365MB_MIB_outIgmpGeneralQuery, 537 RTL8365MB_MIB_outIgmpSpecificQuery, 538 RTL8365MB_MIB_outMldReports, 539 RTL8365MB_MIB_outMldLeaves, 540 RTL8365MB_MIB_outMldGeneralQuery, 541 RTL8365MB_MIB_outMldSpecificQuery, 542 RTL8365MB_MIB_inKnownMulticastPkts, 543 RTL8365MB_MIB_END, 544 }; 545 546 struct rtl8365mb_mib_counter { 547 u32 offset; 548 u32 length; 549 const char *name; 550 }; 551 552 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 553 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 554 555 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 556 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 557 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 558 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 559 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 560 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 561 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 562 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 563 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 564 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 565 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 566 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 567 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 568 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 569 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 570 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 571 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 572 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 573 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 574 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 575 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 576 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 577 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 578 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 579 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 580 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 581 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 582 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 583 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 584 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 585 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 586 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 587 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 588 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 589 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 590 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 591 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 592 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 593 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 594 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 595 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 596 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 597 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 598 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 599 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 600 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 601 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 602 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 603 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 604 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 605 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 606 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 607 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 608 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 609 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 610 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 611 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 612 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 613 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 614 }; 615 616 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 617 618 struct rtl8365mb_jam_tbl_entry { 619 u16 reg; 620 u16 val; 621 }; 622 623 /* Lifted from the vendor driver sources */ 624 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 625 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 626 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 627 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 628 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 629 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 630 { 0x13F0, 0x0000 }, 631 }; 632 633 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 634 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 635 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 636 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 637 { 0x1D32, 0x0002 }, 638 }; 639 640 /* SGMII SerDes tuning parameters, lifted from the vendor driver sources. The 641 * vendor driver keeps two variants of this table and selects between them 642 * based on the chip option register; these are the values for a non-zero 643 * option, which is what RTL8367S parts seen so far report. See 644 * rtl8365mb_sds_probe_option(). 645 */ 646 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_sds_jam_sgmii[] = { 647 { 0x0480, 0x04D7 }, { 0x0481, 0xF994 }, { 0x0482, 0x2420 }, 648 { 0x0483, 0x6960 }, { 0x0484, 0x9728 }, { 0x0423, 0x9D85 }, 649 { 0x0424, 0xD810 }, { 0x002E, 0x83F2 }, 650 }; 651 652 /* HSGMII SerDes tuning parameters, lifted from the vendor driver sources. As 653 * with the SGMII table, the vendor driver keeps several variants and selects 654 * one based on the chip option register; these are the values for a non-zero 655 * option, which is what RTL8367S parts seen so far report. See 656 * rtl8365mb_sds_probe_option(). 657 */ 658 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_sds_jam_hsgmii[] = { 659 { 0x0500, 0x82F0 }, { 0x0501, 0xF195 }, { 0x0502, 0x31A2 }, 660 { 0x0503, 0x7960 }, { 0x0504, 0x9728 }, { 0x0423, 0x9D85 }, 661 { 0x0424, 0xD810 }, { 0x0001, 0x0F80 }, { 0x002E, 0x83F2 }, 662 }; 663 664 enum rtl8365mb_phy_interface_mode { 665 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0, 666 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0), 667 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1), 668 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2), 669 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3), 670 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4), 671 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5), 672 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6), 673 }; 674 675 /** 676 * struct rtl8365mb_extint - external interface info 677 * @port: the port with an external interface 678 * @id: the external interface ID, which is either 0, 1, or 2 679 * @supported_interfaces: a bitmask of supported PHY interface modes 680 * 681 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded 682 * in &struct rtl8365mb_chip_info for every port with an external interface. 683 */ 684 struct rtl8365mb_extint { 685 int port; 686 int id; 687 unsigned int supported_interfaces; 688 }; 689 690 /** 691 * struct rtl8365mb_chip_info - static chip-specific info 692 * @name: human-readable chip name 693 * @chip_id: chip identifier 694 * @chip_ver: chip silicon revision 695 * @extints: available external interfaces 696 * @jam_table: chip-specific initialization jam table 697 * @jam_size: size of the chip's jam table 698 * 699 * These data are specific to a given chip in the family of switches supported 700 * by this driver. When adding support for another chip in the family, a new 701 * chip info should be added to the rtl8365mb_chip_infos array. 702 */ 703 struct rtl8365mb_chip_info { 704 const char *name; 705 u32 chip_id; 706 u32 chip_ver; 707 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS]; 708 const struct rtl8365mb_jam_tbl_entry *jam_table; 709 size_t jam_size; 710 }; 711 712 /* Chip info for each supported switch in the family */ 713 #define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode) 714 static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = { 715 { 716 .name = "RTL8365MB-VC", 717 .chip_id = 0x6367, 718 .chip_ver = 0x0040, 719 .extints = { 720 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 721 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 722 }, 723 .jam_table = rtl8365mb_init_jam_8365mb_vc, 724 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 725 }, 726 { 727 .name = "RTL8367S", 728 .chip_id = 0x6367, 729 .chip_ver = 0x00A0, 730 .extints = { 731 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, 732 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 733 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 734 }, 735 .jam_table = rtl8365mb_init_jam_8365mb_vc, 736 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 737 }, 738 { 739 .name = "RTL8367SB", 740 .chip_id = 0x6367, 741 .chip_ver = 0x0010, 742 .extints = { 743 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 744 PHY_INTF(RMII) | PHY_INTF(RGMII) | 745 PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, 746 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 747 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 748 }, 749 .jam_table = rtl8365mb_init_jam_8365mb_vc, 750 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 751 }, 752 { 753 .name = "RTL8367RB-VB", 754 .chip_id = 0x6367, 755 .chip_ver = 0x0020, 756 .extints = { 757 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 758 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 759 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 760 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 761 }, 762 .jam_table = rtl8365mb_init_jam_8365mb_vc, 763 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 764 }, 765 }; 766 767 enum rtl8365mb_stp_state { 768 RTL8365MB_STP_STATE_DISABLED = 0, 769 RTL8365MB_STP_STATE_BLOCKING = 1, 770 RTL8365MB_STP_STATE_LEARNING = 2, 771 RTL8365MB_STP_STATE_FORWARDING = 3, 772 }; 773 774 enum rtl8365mb_cpu_insert { 775 RTL8365MB_CPU_INSERT_TO_ALL = 0, 776 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 777 RTL8365MB_CPU_INSERT_TO_NONE = 2, 778 }; 779 780 enum rtl8365mb_cpu_position { 781 RTL8365MB_CPU_POS_AFTER_SA = 0, 782 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 783 }; 784 785 enum rtl8365mb_cpu_format { 786 RTL8365MB_CPU_FORMAT_8BYTES = 0, 787 RTL8365MB_CPU_FORMAT_4BYTES = 1, 788 }; 789 790 enum rtl8365mb_cpu_rxlen { 791 RTL8365MB_CPU_RXLEN_72BYTES = 0, 792 RTL8365MB_CPU_RXLEN_64BYTES = 1, 793 }; 794 795 /** 796 * struct rtl8365mb_cpu - CPU port configuration 797 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 798 * @mask: port mask of ports that parse should parse CPU tags 799 * @trap_port: forward trapped frames to this port 800 * @insert: CPU tag insertion mode in switch->CPU frames 801 * @position: position of CPU tag in frame 802 * @rx_length: minimum CPU RX length 803 * @format: CPU tag format 804 * 805 * Represents the CPU tagging and CPU port configuration of the switch. These 806 * settings are configurable at runtime. 807 */ 808 struct rtl8365mb_cpu { 809 bool enable; 810 u32 mask; 811 u32 trap_port; 812 enum rtl8365mb_cpu_insert insert; 813 enum rtl8365mb_cpu_position position; 814 enum rtl8365mb_cpu_rxlen rx_length; 815 enum rtl8365mb_cpu_format format; 816 }; 817 818 /** 819 * struct rtl8365mb_port - private per-port data 820 * @priv: pointer to parent realtek_priv data 821 * @index: DSA port index, same as dsa_port::index 822 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 823 * access via rtl8365mb_get_stats64 824 * @stats_lock: protect the stats structure during read/update 825 * @mib_work: delayed work for polling MIB counters 826 */ 827 struct rtl8365mb_port { 828 struct realtek_priv *priv; 829 unsigned int index; 830 struct rtnl_link_stats64 stats; 831 spinlock_t stats_lock; 832 struct delayed_work mib_work; 833 }; 834 835 /** 836 * struct rtl8365mb - driver private data 837 * @priv: pointer to parent realtek_priv data 838 * @irq: registered IRQ or zero 839 * @chip_info: chip-specific info about the attached switch 840 * @cpu: CPU tagging and CPU port configuration for this chip 841 * @mib_lock: prevent concurrent reads of MIB counters 842 * @ports: per-port data 843 * @pcs: PCS for the SerDes external interface 844 * @sds_supported: SerDes tuning parameters match the chip option, so the 845 * SerDes interface modes can be advertised 846 * 847 * Private data for this driver. 848 */ 849 struct rtl8365mb { 850 struct realtek_priv *priv; 851 int irq; 852 const struct rtl8365mb_chip_info *chip_info; 853 struct rtl8365mb_cpu cpu; 854 struct mutex mib_lock; 855 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 856 struct phylink_pcs pcs; 857 bool sds_supported; 858 }; 859 860 #define pcs_to_rtl8365mb(_pcs) container_of((_pcs), struct rtl8365mb, pcs) 861 862 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 863 { 864 u32 val; 865 866 return regmap_read_poll_timeout(priv->map_nolock, 867 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 868 val, !val, 10, 100); 869 } 870 871 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 872 u32 ocp_addr) 873 { 874 u32 val; 875 int ret; 876 877 /* Set OCP prefix */ 878 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 879 ret = regmap_update_bits( 880 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, 881 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 882 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 883 if (ret) 884 return ret; 885 886 /* Set PHY register address */ 887 val = RTL8365MB_PHY_BASE; 888 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 889 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 890 ocp_addr >> 1); 891 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 892 ocp_addr >> 6); 893 ret = regmap_write(priv->map_nolock, 894 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); 895 if (ret) 896 return ret; 897 898 return 0; 899 } 900 901 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 902 u32 ocp_addr, u16 *data) 903 { 904 u32 val; 905 int ret; 906 907 rtl83xx_lock(priv); 908 909 ret = rtl8365mb_phy_poll_busy(priv); 910 if (ret) 911 goto out; 912 913 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 914 if (ret) 915 goto out; 916 917 /* Execute read operation */ 918 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 919 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 920 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 921 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 922 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 923 val); 924 if (ret) 925 goto out; 926 927 ret = rtl8365mb_phy_poll_busy(priv); 928 if (ret) 929 goto out; 930 931 /* Get PHY register data */ 932 ret = regmap_read(priv->map_nolock, 933 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); 934 if (ret) 935 goto out; 936 937 *data = val & 0xFFFF; 938 939 out: 940 rtl83xx_unlock(priv); 941 942 return ret; 943 } 944 945 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 946 u32 ocp_addr, u16 data) 947 { 948 u32 val; 949 int ret; 950 951 rtl83xx_lock(priv); 952 953 ret = rtl8365mb_phy_poll_busy(priv); 954 if (ret) 955 goto out; 956 957 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 958 if (ret) 959 goto out; 960 961 /* Set PHY register data */ 962 ret = regmap_write(priv->map_nolock, 963 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); 964 if (ret) 965 goto out; 966 967 /* Execute write operation */ 968 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 969 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 970 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 971 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 972 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 973 val); 974 if (ret) 975 goto out; 976 977 ret = rtl8365mb_phy_poll_busy(priv); 978 if (ret) 979 goto out; 980 981 out: 982 rtl83xx_unlock(priv); 983 984 return ret; 985 } 986 987 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 988 { 989 u32 ocp_addr; 990 u16 val; 991 int ret; 992 993 if (phy > RTL8365MB_PHYADDRMAX) 994 return -EINVAL; 995 996 if (regnum > RTL8365MB_PHYREGMAX) 997 return -EINVAL; 998 999 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 1000 1001 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 1002 if (ret) { 1003 dev_err(priv->dev, 1004 "failed to read PHY%d reg %02x @ %04x, ret %pe\n", phy, 1005 regnum, ocp_addr, ERR_PTR(ret)); 1006 return ret; 1007 } 1008 1009 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 1010 phy, regnum, ocp_addr, val); 1011 1012 return val; 1013 } 1014 1015 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 1016 u16 val) 1017 { 1018 u32 ocp_addr; 1019 int ret; 1020 1021 if (phy > RTL8365MB_PHYADDRMAX) 1022 return -EINVAL; 1023 1024 if (regnum > RTL8365MB_PHYREGMAX) 1025 return -EINVAL; 1026 1027 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 1028 1029 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 1030 if (ret) { 1031 dev_err(priv->dev, 1032 "failed to write PHY%d reg %02x @ %04x, ret %pe\n", phy, 1033 regnum, ocp_addr, ERR_PTR(ret)); 1034 return ret; 1035 } 1036 1037 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 1038 phy, regnum, ocp_addr, val); 1039 1040 return 0; 1041 } 1042 1043 static const struct rtl8365mb_extint * 1044 rtl8365mb_get_port_extint(struct realtek_priv *priv, int port) 1045 { 1046 struct rtl8365mb *mb = priv->chip_data; 1047 int i; 1048 1049 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) { 1050 const struct rtl8365mb_extint *extint = 1051 &mb->chip_info->extints[i]; 1052 1053 if (!extint->supported_interfaces) 1054 continue; 1055 1056 if (extint->port == port) 1057 return extint; 1058 } 1059 1060 return NULL; 1061 } 1062 1063 static enum dsa_tag_protocol 1064 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 1065 enum dsa_tag_protocol mp) 1066 { 1067 struct realtek_priv *priv = ds->priv; 1068 struct rtl8365mb_cpu *cpu; 1069 struct rtl8365mb *mb; 1070 1071 mb = priv->chip_data; 1072 cpu = &mb->cpu; 1073 1074 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC) 1075 return DSA_TAG_PROTO_RTL8_4T; 1076 1077 return DSA_TAG_PROTO_RTL8_4; 1078 } 1079 1080 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 1081 phy_interface_t interface) 1082 { 1083 const struct rtl8365mb_extint *extint = 1084 rtl8365mb_get_port_extint(priv, port); 1085 struct dsa_switch *ds = &priv->ds; 1086 struct device_node *dn; 1087 struct dsa_port *dp; 1088 int tx_delay = 0; 1089 int rx_delay = 0; 1090 u32 val; 1091 int ret; 1092 1093 if (!extint) 1094 return -ENODEV; 1095 1096 dp = dsa_to_port(ds, port); 1097 dn = dp->dn; 1098 1099 /* Set the RGMII TX/RX delay 1100 * 1101 * The Realtek vendor driver indicates the following possible 1102 * configuration settings: 1103 * 1104 * TX delay: 1105 * 0 = no delay, 1 = 2 ns delay 1106 * RX delay: 1107 * 0 = no delay, 7 = maximum delay 1108 * Each step is approximately 0.3 ns, so the maximum delay is about 1109 * 2.1 ns. 1110 * 1111 * The vendor driver also states that this must be configured *before* 1112 * forcing the external interface into a particular mode, which is done 1113 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 1114 * 1115 * Only configure an RGMII TX (resp. RX) delay if the 1116 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 1117 * specified. We ignore the detail of the RGMII interface mode 1118 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 1119 * property. 1120 */ 1121 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 1122 val = val / 1000; /* convert to ns */ 1123 1124 if (val == 0 || val == 2) 1125 tx_delay = val / 2; 1126 else 1127 dev_warn(priv->dev, 1128 "RGMII TX delay must be 0 or 2 ns\n"); 1129 } 1130 1131 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 1132 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 1133 1134 if (val <= 7) 1135 rx_delay = val; 1136 else 1137 dev_warn(priv->dev, 1138 "RGMII RX delay must be 0 to 2.1 ns\n"); 1139 } 1140 1141 ret = regmap_update_bits( 1142 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id), 1143 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 1144 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 1145 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 1146 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 1147 if (ret) 1148 return ret; 1149 1150 ret = regmap_update_bits( 1151 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id), 1152 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id), 1153 RTL8365MB_EXT_PORT_MODE_RGMII 1154 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 1155 extint->id)); 1156 if (ret) 1157 return ret; 1158 1159 return 0; 1160 } 1161 1162 static int rtl8365mb_sds_write(struct realtek_priv *priv, u16 addr, u16 data) 1163 { 1164 int ret; 1165 1166 ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, data); 1167 if (ret) 1168 return ret; 1169 1170 ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr); 1171 if (ret) 1172 return ret; 1173 1174 /* The SerDes indirect access engine completes the command within the 1175 * register write transaction, so there is no need to wait or poll for 1176 * completion before the next access, matching the vendor driver. 1177 */ 1178 return regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, 1179 RTL8365MB_SDS_INDACS_CMD_RUN_MASK | 1180 RTL8365MB_SDS_INDACS_CMD_WR_MASK); 1181 } 1182 1183 static int rtl8365mb_sds_read(struct realtek_priv *priv, u16 addr, u16 *data) 1184 { 1185 u32 val; 1186 int ret; 1187 1188 ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_ADR_REG, addr); 1189 if (ret) 1190 return ret; 1191 1192 ret = regmap_write(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, 1193 RTL8365MB_SDS_INDACS_CMD_RUN_MASK); 1194 if (ret) 1195 return ret; 1196 1197 /* Wait for the indirect read to complete: the engine clears the BUSY 1198 * bit once the data register holds the result. 1199 */ 1200 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_SDS_INDACS_CMD_REG, 1201 val, 1202 !(val & RTL8365MB_SDS_INDACS_CMD_BUSY_MASK), 1203 10, 1000); 1204 if (ret) 1205 return ret; 1206 1207 ret = regmap_read(priv->map, RTL8365MB_SDS_INDACS_DATA_REG, &val); 1208 if (ret) 1209 return ret; 1210 1211 *data = val; 1212 1213 return 0; 1214 } 1215 1216 /* The vendor driver selects between two sets of SerDes tuning parameters based 1217 * on the chip option register. Only the variant for a non-zero option has been 1218 * tested on real hardware - the RTL8367S parts seen so far all report 1. The 1219 * variant for option 0 uses different tuning values that cannot be verified, 1220 * so probe the option once at setup and only advertise the SerDes interface 1221 * modes when the tuning parameters are known to match, so that an unsupported 1222 * variant fails at phylink validation time rather than when configuring the 1223 * link. 1224 */ 1225 static int rtl8365mb_sds_probe_option(struct realtek_priv *priv) 1226 { 1227 struct rtl8365mb *mb = priv->chip_data; 1228 const struct rtl8365mb_extint *extint; 1229 u32 option; 1230 int ret; 1231 int i; 1232 1233 /* Nothing to probe if no external interface is wired to the SerDes */ 1234 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) { 1235 extint = &mb->chip_info->extints[i]; 1236 1237 if (extint->supported_interfaces & 1238 (RTL8365MB_PHY_INTERFACE_MODE_SGMII | 1239 RTL8365MB_PHY_INTERFACE_MODE_HSGMII)) 1240 break; 1241 } 1242 if (i == RTL8365MB_MAX_NUM_EXTINTS) 1243 return 0; 1244 1245 ret = regmap_write(priv->map, RTL8365MB_SDS_OPTION_ARM_REG, 1246 RTL8365MB_SDS_OPTION_ARM_KEY); 1247 if (ret) 1248 return ret; 1249 1250 ret = regmap_read(priv->map, RTL8365MB_SDS_OPTION_REG, &option); 1251 if (ret) 1252 return ret; 1253 1254 ret = regmap_write(priv->map, RTL8365MB_SDS_OPTION_ARM_REG, 0); 1255 if (ret) 1256 return ret; 1257 1258 if (option == 0) { 1259 dev_warn(priv->dev, 1260 "unsupported SerDes tuning variant (chip option 0), disabling SerDes interface modes\n"); 1261 return 0; 1262 } 1263 1264 mb->sds_supported = true; 1265 1266 return 0; 1267 } 1268 1269 /* The vendor driver raises the port 6 ingress and egress rate limiters to 1270 * their maximum in its switch init, unconditionally for the whole chip 1271 * family. The chip reset in rtl8365mb_setup() puts them back to their reset 1272 * default of 0x1FFFF, a ~1.048 Gbps limit which caps the aggregate 1273 * throughput of an HSGMII CPU port at roughly 1 Gbps. The vendor 1274 * documentation describes the reset default as disabling the limiter, but 1275 * the cap has been observed on hardware. Raise them likewise, to 0x7FFFF 1276 * (~4.19 Gbps, above the HSGMII line rate). The related HSGMII scheduler 1277 * line rate register (LINE_RATE_HSG_H, 0x03FA) is already set to its 1278 * maximum by the common init jam table. 1279 */ 1280 static int rtl8365mb_sds_raise_rate_limits(struct realtek_priv *priv) 1281 { 1282 int ret; 1283 1284 ret = regmap_write(priv->map, RTL8365MB_INGRESSBW_PORT6_RATE_CTRL0_REG, 1285 0xFFFF); 1286 if (ret) 1287 return ret; 1288 1289 ret = regmap_update_bits(priv->map, 1290 RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_REG, 1291 RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_MASK, 1292 RTL8365MB_INGRESSBW_PORT6_RATE_CTRL1_MASK); 1293 if (ret) 1294 return ret; 1295 1296 ret = regmap_write(priv->map, RTL8365MB_PORT6_EGRESSBW_CTRL0_REG, 1297 0xFFFF); 1298 if (ret) 1299 return ret; 1300 1301 return regmap_update_bits(priv->map, RTL8365MB_PORT6_EGRESSBW_CTRL1_REG, 1302 RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK, 1303 RTL8365MB_PORT6_EGRESSBW_CTRL1_MASK); 1304 } 1305 1306 static int rtl8365mb_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode, 1307 phy_interface_t interface, 1308 const unsigned long *advertising, 1309 bool permit_pause_to_mac) 1310 { 1311 const struct rtl8365mb_jam_tbl_entry *sds_jam; 1312 const int id = RTL8365MB_SDS_EXT_INTERFACE_ID; 1313 struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs); 1314 struct realtek_priv *priv; 1315 size_t sds_jam_size; 1316 u32 mode; 1317 u16 val; 1318 int ret; 1319 int i; 1320 1321 priv = mb->priv; 1322 1323 if (interface == PHY_INTERFACE_MODE_2500BASEX) { 1324 sds_jam = rtl8365mb_sds_jam_hsgmii; 1325 sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_hsgmii); 1326 mode = RTL8365MB_EXT_PORT_MODE_HSGMII; 1327 } else { 1328 sds_jam = rtl8365mb_sds_jam_sgmii; 1329 sds_jam_size = ARRAY_SIZE(rtl8365mb_sds_jam_sgmii); 1330 mode = RTL8365MB_EXT_PORT_MODE_SGMII; 1331 } 1332 1333 /* Hold the embedded DW8051 microcontroller in reset and keep it 1334 * disabled. The vendor driver loads firmware into it to manage the 1335 * SerDes link, but the firmware only duplicates work that phylink 1336 * already does: it polls the port status and forces the external 1337 * interface configuration in the very registers this driver manages. 1338 * Letting it run would race with phylink. 1339 */ 1340 ret = regmap_update_bits(priv->map, RTL8365MB_CHIP_RESET_REG, 1341 RTL8365MB_CHIP_RESET_DW8051_MASK, 1342 RTL8365MB_CHIP_RESET_DW8051_MASK); 1343 if (ret) 1344 return ret; 1345 1346 ret = regmap_update_bits(priv->map, RTL8365MB_MISC_CFG0_REG, 1347 RTL8365MB_MISC_CFG0_DW8051_EN_MASK, 0); 1348 if (ret) 1349 return ret; 1350 1351 /* The vendor driver clears the line rate bypass for all interface 1352 * modes except TMII. 1353 */ 1354 ret = regmap_update_bits(priv->map, RTL8365MB_BYPASS_LINE_RATE_REG, 1355 RTL8365MB_SDS_BYPASS_LINE_RATE_MASK, 0); 1356 if (ret) 1357 return ret; 1358 1359 /* Tune the SerDes with vendor-prescribed parameters */ 1360 for (i = 0; i < sds_jam_size; i++) { 1361 ret = rtl8365mb_sds_write(priv, sds_jam[i].reg, 1362 sds_jam[i].val); 1363 if (ret) 1364 return ret; 1365 } 1366 1367 /* Mux the SerDes to MAC8 in the requested mode */ 1368 ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, 1369 RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK | 1370 RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK, 1371 mode == RTL8365MB_EXT_PORT_MODE_SGMII ? 1372 RTL8365MB_SDS_MISC_MAC8_SEL_SGMII_MASK : 1373 RTL8365MB_SDS_MISC_MAC8_SEL_HSGMII_MASK); 1374 if (ret) 1375 return ret; 1376 1377 val = mode << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(id); 1378 ret = regmap_update_bits(priv->map, 1379 RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(id), 1380 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(id), 1381 val); 1382 if (ret) 1383 return ret; 1384 1385 /* Take the SerDes out of reset. The vendor driver does this only 1386 * after the SerDes mux and the interface mode are configured. 1387 */ 1388 ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_RESET, 1389 RTL8365MB_SDS_RESET_DEASSERT); 1390 if (ret) 1391 return ret; 1392 1393 /* Reset the SerDes data path and resync its PLL, mirroring what the 1394 * vendor firmware does right after deasserting the SerDes reset. 1395 * This flushes the FIFOs and ensures a clean state for the link, 1396 * preventing silent drops and CRC errors. 1397 */ 1398 ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR, 1399 RTL8365MB_SDS_BMCR_DPRST_PHASE1); 1400 if (ret) 1401 return ret; 1402 1403 ret = rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_BMCR, 1404 RTL8365MB_SDS_BMCR_DPRST_PHASE2); 1405 if (ret) 1406 return ret; 1407 1408 /* Keep SGMII in-band autonegotiation disabled: the link parameters are 1409 * forced from rtl8365mb_pcs_link_up() instead. 1410 */ 1411 ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_NWAY, &val); 1412 if (ret) 1413 return ret; 1414 1415 val &= ~RTL8365MB_SDS_NWAY_EN_MASK; 1416 val |= RTL8365MB_SDS_NWAY_RESTART_MASK; 1417 1418 return rtl8365mb_sds_write(priv, RTL8365MB_SDS_REG_NWAY, val); 1419 } 1420 1421 static bool rtl8365mb_interface_is_serdes(phy_interface_t interface) 1422 { 1423 return interface == PHY_INTERFACE_MODE_SGMII || 1424 interface == PHY_INTERFACE_MODE_2500BASEX; 1425 } 1426 1427 static unsigned int rtl8365mb_pcs_inband_caps(struct phylink_pcs *pcs, 1428 phy_interface_t interface) 1429 { 1430 /* In-band autonegotiation is not implemented; the link is always 1431 * forced. Report that to phylink so that it never selects an 1432 * in-band-enabled negotiation mode for this PCS. 1433 */ 1434 return LINK_INBAND_DISABLE; 1435 } 1436 1437 static void rtl8365mb_pcs_get_state(struct phylink_pcs *pcs, 1438 unsigned int neg_mode, 1439 struct phylink_link_state *state) 1440 { 1441 struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs); 1442 struct realtek_priv *priv = mb->priv; 1443 u16 status; 1444 u32 val; 1445 int ret; 1446 1447 /* In-band autonegotiation is not implemented, so the link parameters are 1448 * forced from rtl8365mb_pcs_link_up(). The real link state must still be 1449 * read from the SerDes itself: the embedded DW8051 microcontroller that 1450 * the vendor firmware uses to poll the SerDes is kept disabled (see 1451 * rtl8365mb_pcs_config()), so the link status register can be read 1452 * directly through the SDS_INDACS window without racing the auto-poll. 1453 */ 1454 ret = rtl8365mb_sds_read(priv, RTL8365MB_SDS_REG_LINK_STATUS, &status); 1455 if (ret) { 1456 state->link = false; 1457 return; 1458 } 1459 1460 state->link = !!(status & RTL8365MB_SDS_LINK_STATUS_LINK_MASK); 1461 state->an_complete = state->link; 1462 if (!state->link) 1463 return; 1464 1465 /* The speed and duplex are forced; read them back from the values 1466 * programmed into the SerDes MISC register. 1467 */ 1468 ret = regmap_read(priv->map, RTL8365MB_SDS_MISC_REG, &val); 1469 if (ret) { 1470 state->link = false; 1471 return; 1472 } 1473 1474 state->duplex = (val & RTL8365MB_SDS_MISC_SGMII_FDUP_MASK) ? 1475 DUPLEX_FULL : DUPLEX_HALF; 1476 1477 switch (FIELD_GET(RTL8365MB_SDS_MISC_SGMII_SPD_MASK, val)) { 1478 case RTL8365MB_PORT_SPEED_1000M: 1479 state->speed = 1480 state->interface == PHY_INTERFACE_MODE_2500BASEX ? 1481 SPEED_2500 : SPEED_1000; 1482 break; 1483 case RTL8365MB_PORT_SPEED_100M: 1484 state->speed = SPEED_100; 1485 break; 1486 case RTL8365MB_PORT_SPEED_10M: 1487 state->speed = SPEED_10; 1488 break; 1489 } 1490 } 1491 1492 static void rtl8365mb_pcs_link_up(struct phylink_pcs *pcs, 1493 unsigned int neg_mode, 1494 phy_interface_t interface, int speed, 1495 int duplex) 1496 { 1497 struct rtl8365mb *mb = pcs_to_rtl8365mb(pcs); 1498 struct realtek_priv *priv = mb->priv; 1499 u32 mask = RTL8365MB_SDS_MISC_SGMII_FDUP_MASK | 1500 RTL8365MB_SDS_MISC_SGMII_LINK_MASK | 1501 RTL8365MB_SDS_MISC_SGMII_SPD_MASK; 1502 u32 val = RTL8365MB_SDS_MISC_SGMII_LINK_MASK; 1503 u32 r_speed; 1504 int ret; 1505 1506 /* The speed field has no value for 2.5 Gbps: the rate is determined by 1507 * the HSGMII SerDes configuration, and the vendor driver programs the 1508 * 1 Gbps value here. 1509 */ 1510 if (speed == SPEED_2500 || speed == SPEED_1000) { 1511 r_speed = RTL8365MB_PORT_SPEED_1000M; 1512 } else if (speed == SPEED_100) { 1513 r_speed = RTL8365MB_PORT_SPEED_100M; 1514 } else if (speed == SPEED_10) { 1515 r_speed = RTL8365MB_PORT_SPEED_10M; 1516 } else { 1517 dev_err(priv->dev, "unsupported SerDes speed %s\n", 1518 phy_speed_to_str(speed)); 1519 return; 1520 } 1521 1522 val |= FIELD_PREP(RTL8365MB_SDS_MISC_SGMII_SPD_MASK, r_speed); 1523 1524 if (duplex == DUPLEX_FULL) 1525 val |= RTL8365MB_SDS_MISC_SGMII_FDUP_MASK; 1526 1527 /* pcs_link_up() carries no pause information, so the SerDes flow 1528 * control bits are programmed together with the MAC external interface 1529 * force from rtl8365mb_phylink_mac_link_up(), where the resolved pause 1530 * modes are known. 1531 */ 1532 ret = regmap_update_bits(priv->map, RTL8365MB_SDS_MISC_REG, mask, val); 1533 if (ret) { 1534 dev_err(priv->dev, "failed to force SerDes link: %pe\n", 1535 ERR_PTR(ret)); 1536 return; 1537 } 1538 } 1539 1540 static const struct phylink_pcs_ops rtl8365mb_pcs_ops = { 1541 .pcs_inband_caps = rtl8365mb_pcs_inband_caps, 1542 .pcs_config = rtl8365mb_pcs_config, 1543 .pcs_get_state = rtl8365mb_pcs_get_state, 1544 .pcs_link_up = rtl8365mb_pcs_link_up, 1545 }; 1546 1547 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 1548 bool link, int speed, int duplex, 1549 bool tx_pause, bool rx_pause) 1550 { 1551 const struct rtl8365mb_extint *extint = 1552 rtl8365mb_get_port_extint(priv, port); 1553 u32 r_tx_pause; 1554 u32 r_rx_pause; 1555 u32 r_duplex; 1556 u32 r_speed; 1557 u32 r_link; 1558 int val; 1559 int ret; 1560 1561 if (!extint) 1562 return -ENODEV; 1563 1564 if (link) { 1565 /* Force the link up with the desired configuration */ 1566 r_link = 1; 1567 r_rx_pause = rx_pause ? 1 : 0; 1568 r_tx_pause = tx_pause ? 1 : 0; 1569 1570 /* The speed field has no value for 2.5 Gbps: the rate is 1571 * determined by the HSGMII SerDes configuration, and the 1572 * vendor driver programs the 1 Gbps value here. 1573 */ 1574 if (speed == SPEED_2500 || speed == SPEED_1000) { 1575 r_speed = RTL8365MB_PORT_SPEED_1000M; 1576 } else if (speed == SPEED_100) { 1577 r_speed = RTL8365MB_PORT_SPEED_100M; 1578 } else if (speed == SPEED_10) { 1579 r_speed = RTL8365MB_PORT_SPEED_10M; 1580 } else { 1581 dev_err(priv->dev, "unsupported port speed %s\n", 1582 phy_speed_to_str(speed)); 1583 return -EINVAL; 1584 } 1585 1586 if (duplex == DUPLEX_FULL) { 1587 r_duplex = 1; 1588 } else if (duplex == DUPLEX_HALF) { 1589 r_duplex = 0; 1590 } else { 1591 dev_err(priv->dev, "unsupported duplex %s\n", 1592 phy_duplex_to_str(duplex)); 1593 return -EINVAL; 1594 } 1595 } else { 1596 /* Force the link down and reset any programmed configuration */ 1597 r_link = 0; 1598 r_tx_pause = 0; 1599 r_rx_pause = 0; 1600 r_speed = 0; 1601 r_duplex = 0; 1602 } 1603 1604 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 1605 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 1606 r_tx_pause) | 1607 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 1608 r_rx_pause) | 1609 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 1610 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 1611 r_duplex) | 1612 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 1613 ret = regmap_write(priv->map, 1614 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), 1615 val); 1616 if (ret) 1617 return ret; 1618 1619 return 0; 1620 } 1621 1622 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, 1623 struct phylink_config *config) 1624 { 1625 const struct rtl8365mb_extint *extint = 1626 rtl8365mb_get_port_extint(ds->priv, port); 1627 struct realtek_priv *priv = ds->priv; 1628 struct rtl8365mb *mb = priv->chip_data; 1629 1630 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 1631 MAC_10 | MAC_100 | MAC_1000FD; 1632 1633 if (!extint) { 1634 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1635 config->supported_interfaces); 1636 1637 /* GMII is the default interface mode for phylib, so 1638 * we have to support it for ports with integrated PHY. 1639 */ 1640 __set_bit(PHY_INTERFACE_MODE_GMII, 1641 config->supported_interfaces); 1642 return; 1643 } 1644 1645 /* Populate according to the modes supported by _this driver_, 1646 * not necessarily the modes supported by the hardware, some of 1647 * which remain unimplemented. 1648 */ 1649 1650 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) 1651 phy_interface_set_rgmii(config->supported_interfaces); 1652 1653 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_SGMII && 1654 mb->sds_supported) 1655 __set_bit(PHY_INTERFACE_MODE_SGMII, 1656 config->supported_interfaces); 1657 1658 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_HSGMII && 1659 mb->sds_supported) { 1660 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 1661 config->supported_interfaces); 1662 config->mac_capabilities |= MAC_2500FD; 1663 } 1664 } 1665 1666 static struct phylink_pcs * 1667 rtl8365mb_phylink_mac_select_pcs(struct phylink_config *config, 1668 phy_interface_t interface) 1669 { 1670 struct dsa_port *dp = dsa_phylink_to_port(config); 1671 struct realtek_priv *priv = dp->ds->priv; 1672 struct rtl8365mb *mb = priv->chip_data; 1673 1674 if (rtl8365mb_interface_is_serdes(interface)) 1675 return &mb->pcs; 1676 1677 return NULL; 1678 } 1679 1680 static void rtl8365mb_phylink_mac_config(struct phylink_config *config, 1681 unsigned int mode, 1682 const struct phylink_link_state *state) 1683 { 1684 struct dsa_port *dp = dsa_phylink_to_port(config); 1685 struct realtek_priv *priv = dp->ds->priv; 1686 u8 port = dp->index; 1687 int ret; 1688 1689 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 1690 dev_err(priv->dev, 1691 "port %d supports only conventional PHY or fixed-link\n", 1692 port); 1693 return; 1694 } 1695 1696 if (phy_interface_mode_is_rgmii(state->interface)) { 1697 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 1698 if (ret) 1699 dev_err(priv->dev, 1700 "failed to configure RGMII mode on port %d: %pe\n", 1701 port, ERR_PTR(ret)); 1702 return; 1703 } 1704 1705 /* SGMII and 2500base-x are handled by the SerDes PCS, configured 1706 * through the phylink_pcs ops, so nothing to do here for them. 1707 */ 1708 if (rtl8365mb_interface_is_serdes(state->interface)) 1709 return; 1710 1711 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1712 * supports 1713 */ 1714 } 1715 1716 static void rtl8365mb_phylink_mac_link_down(struct phylink_config *config, 1717 unsigned int mode, 1718 phy_interface_t interface) 1719 { 1720 struct dsa_port *dp = dsa_phylink_to_port(config); 1721 struct realtek_priv *priv = dp->ds->priv; 1722 struct rtl8365mb_port *p; 1723 struct rtl8365mb *mb; 1724 u8 port = dp->index; 1725 int ret; 1726 1727 mb = priv->chip_data; 1728 p = &mb->ports[port]; 1729 cancel_delayed_work_sync(&p->mib_work); 1730 1731 /* phylink has no pcs_link_down callback, so on the SerDes path only the 1732 * MAC external interface force is reset here. Clearing the MAC force is 1733 * enough to bring the link down; the SerDes keeps presenting its last 1734 * forced state until the next pcs_link_up() reprograms it. 1735 */ 1736 if (phy_interface_mode_is_rgmii(interface) || 1737 rtl8365mb_interface_is_serdes(interface)) { 1738 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1739 false, false); 1740 if (ret) 1741 dev_err(priv->dev, 1742 "failed to reset forced mode on port %d: %pe\n", 1743 port, ERR_PTR(ret)); 1744 1745 return; 1746 } 1747 } 1748 1749 static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config, 1750 struct phy_device *phydev, 1751 unsigned int mode, 1752 phy_interface_t interface, 1753 int speed, int duplex, bool tx_pause, 1754 bool rx_pause) 1755 { 1756 struct dsa_port *dp = dsa_phylink_to_port(config); 1757 struct realtek_priv *priv = dp->ds->priv; 1758 struct rtl8365mb_port *p; 1759 struct rtl8365mb *mb; 1760 u8 port = dp->index; 1761 int ret; 1762 1763 mb = priv->chip_data; 1764 p = &mb->ports[port]; 1765 schedule_delayed_work(&p->mib_work, 0); 1766 1767 /* The SerDes forced link state is programmed by the PCS in 1768 * rtl8365mb_pcs_link_up(); here only the MAC external interface force 1769 * is configured, for both RGMII and SerDes. 1770 */ 1771 if (phy_interface_mode_is_rgmii(interface) || 1772 rtl8365mb_interface_is_serdes(interface)) { 1773 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1774 duplex, tx_pause, 1775 rx_pause); 1776 if (ret) { 1777 dev_err(priv->dev, 1778 "failed to force mode on port %d: %pe\n", port, 1779 ERR_PTR(ret)); 1780 return; 1781 } 1782 1783 /* The SerDes has its own pause enables; program them from 1784 * the resolved pause modes, as the vendor driver does when 1785 * forcing the link on a SerDes external interface. These 1786 * bits, not the MAC force pause bits, gate pause on the 1787 * SerDes external interface: flow control testing shows 1788 * that pause frames are only emitted with the SerDes TXFC 1789 * bit set, while the MAC force pause bits alone have no 1790 * effect on this port. This is done here rather than in 1791 * rtl8365mb_pcs_link_up() because pcs_link_up() carries no 1792 * pause information. 1793 */ 1794 if (rtl8365mb_interface_is_serdes(interface)) { 1795 u32 val = 0; 1796 1797 if (tx_pause) 1798 val |= RTL8365MB_SDS_MISC_SGMII_TXFC_MASK; 1799 if (rx_pause) 1800 val |= RTL8365MB_SDS_MISC_SGMII_RXFC_MASK; 1801 1802 ret = regmap_update_bits(priv->map, 1803 RTL8365MB_SDS_MISC_REG, 1804 RTL8365MB_SDS_MISC_SGMII_TXFC_MASK | 1805 RTL8365MB_SDS_MISC_SGMII_RXFC_MASK, 1806 val); 1807 if (ret) 1808 dev_err(priv->dev, 1809 "failed to force SerDes pause modes on port %d: %pe\n", 1810 port, ERR_PTR(ret)); 1811 } 1812 1813 return; 1814 } 1815 } 1816 1817 static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port, 1818 int new_mtu) 1819 { 1820 struct realtek_priv *priv = ds->priv; 1821 int frame_size; 1822 1823 /* When a new MTU is set, DSA always sets the CPU port's MTU to the 1824 * largest MTU of the user ports. Because the switch only has a global 1825 * RX length register, only allowing CPU port here is enough. 1826 */ 1827 if (!dsa_is_cpu_port(ds, port)) 1828 return 0; 1829 1830 frame_size = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 1831 1832 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n", 1833 new_mtu, frame_size); 1834 1835 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1836 RTL8365MB_CFG0_MAX_LEN_MASK, 1837 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1838 frame_size)); 1839 } 1840 1841 static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port) 1842 { 1843 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN; 1844 } 1845 1846 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1847 u8 state) 1848 { 1849 struct realtek_priv *priv = ds->priv; 1850 enum rtl8365mb_stp_state val; 1851 int msti = 0; 1852 1853 switch (state) { 1854 case BR_STATE_DISABLED: 1855 val = RTL8365MB_STP_STATE_DISABLED; 1856 break; 1857 case BR_STATE_BLOCKING: 1858 case BR_STATE_LISTENING: 1859 val = RTL8365MB_STP_STATE_BLOCKING; 1860 break; 1861 case BR_STATE_LEARNING: 1862 val = RTL8365MB_STP_STATE_LEARNING; 1863 break; 1864 case BR_STATE_FORWARDING: 1865 val = RTL8365MB_STP_STATE_FORWARDING; 1866 break; 1867 default: 1868 dev_err(priv->dev, "invalid STP state: %u\n", state); 1869 return; 1870 } 1871 1872 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1873 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1874 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1875 } 1876 1877 static int rtl8365mb_port_set_transparent(struct realtek_priv *priv, 1878 int igr_port, int egr_port, 1879 bool enable) 1880 { 1881 dev_dbg(priv->dev, "%s transparent VLAN from %d to %d\n", 1882 enable ? "Enable" : "Disable", igr_port, egr_port); 1883 1884 /* "Transparent" between the two ports means that packets forwarded by 1885 * igr_port and egressed on egr_port will not be filtered by the usual 1886 * VLAN membership settings. 1887 */ 1888 return regmap_update_bits(priv->map, 1889 RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(egr_port), 1890 BIT(igr_port), enable ? BIT(igr_port) : 0); 1891 } 1892 1893 static int rtl8365mb_port_set_ingress_filtering(struct realtek_priv *priv, 1894 int port, bool enable) 1895 { 1896 /* Ingress filtering enabled: Discard VLAN-tagged frames if the port is 1897 * not a member of the VLAN with which the packet is associated. 1898 * Untagged packets will also be discarded unless the port has a PVID 1899 * programmed. Priority-tagged frames are treated as untagged frames. 1900 * 1901 * Ingress filtering disabled: Accept all tagged and untagged frames. 1902 */ 1903 return regmap_update_bits(priv->map, RTL8365MB_VLAN_INGRESS_REG, 1904 RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port), 1905 enable ? 1906 RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port) : 1907 0); 1908 } 1909 1910 static int 1911 rtl8365mb_port_set_vlan_egress_mode(struct realtek_priv *priv, int port, 1912 enum rtl8365mb_vlan_egress_mode mode) 1913 { 1914 u32 val; 1915 1916 val = FIELD_PREP(RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, mode); 1917 return regmap_update_bits(priv->map, 1918 RTL8365MB_PORT_MISC_CFG_REG(port), 1919 RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, val); 1920 } 1921 1922 static int rtl8365mb_port_vlan_filtering(struct dsa_switch *ds, int port, 1923 bool vlan_filtering, 1924 struct netlink_ext_ack *extack) 1925 { 1926 enum rtl8365mb_frame_ingress accepted_frame, prev_accepted_frame; 1927 enum rtl8365mb_vlan_egress_mode mode; 1928 struct realtek_priv *priv = ds->priv; 1929 u32 configured_ports = 0; 1930 struct dsa_port *dp; 1931 u16 pvid_vid; 1932 int ret; 1933 1934 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, 1935 vlan_filtering ? "enable" : "disable"); 1936 1937 ret = rtl8365mb_vlan_port_get_framefilter(priv, port, 1938 &prev_accepted_frame); 1939 if (ret) { 1940 NL_SET_ERR_MSG_MOD(extack, 1941 "Failed to get current framefilter"); 1942 return ret; 1943 } 1944 1945 /* While filtering, only accepts untagged frames if PVID is enabled */ 1946 if (vlan_filtering) { 1947 ret = rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); 1948 if (ret) 1949 return ret; 1950 1951 if (pvid_vid) 1952 accepted_frame = RTL8365MB_FRAME_TYPE_ANY_FRAME; 1953 else 1954 accepted_frame = RTL8365MB_FRAME_TYPE_TAGGED_ONLY; 1955 } else { 1956 accepted_frame = RTL8365MB_FRAME_TYPE_ANY_FRAME; 1957 } 1958 1959 /* When vlan filter is enable/disabled in a bridge, this function is 1960 * called for all member ports. We need to enable/disable ingress 1961 * VLAN membership check. 1962 */ 1963 ret = rtl8365mb_port_set_ingress_filtering(priv, port, vlan_filtering); 1964 if (ret) 1965 return ret; 1966 1967 /* However, we also enable/disable egress filtering because the switch 1968 * still consider the egress interface VLAN membership to forward the 1969 * traffic. We enable/disable that check disabling/enabling transparent 1970 * VLAN between the ingress port and all other available ports. 1971 */ 1972 dsa_switch_for_each_available_port(dp, ds) { 1973 /* port isolation will still keep traffic inside the bridge */ 1974 ret = rtl8365mb_port_set_transparent(priv, port, dp->index, 1975 !vlan_filtering); 1976 if (ret) 1977 goto undo_transparent; 1978 1979 configured_ports |= BIT(dp->index); 1980 } 1981 1982 if (accepted_frame != prev_accepted_frame) { 1983 ret = rtl8365mb_vlan_port_set_framefilter(priv, port, 1984 accepted_frame); 1985 if (ret) { 1986 NL_SET_ERR_MSG_MOD(extack, 1987 "Failed to set port framefilter"); 1988 goto undo_transparent; 1989 } 1990 } 1991 1992 /* When VLAN filtering is disabled, preserve frames exactly as received. 1993 * Otherwise, the VLAN egress pipeline may still alter tag state 1994 * according to VLAN membership and untag configuration. 1995 */ 1996 if (vlan_filtering) 1997 mode = RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL; 1998 else 1999 mode = RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP; 2000 2001 ret = rtl8365mb_port_set_vlan_egress_mode(priv, port, mode); 2002 if (ret) 2003 goto undo_set_framefilter; 2004 2005 return ret; 2006 2007 undo_set_framefilter: 2008 if (prev_accepted_frame != accepted_frame) 2009 rtl8365mb_vlan_port_set_framefilter(priv, port, 2010 prev_accepted_frame); 2011 undo_transparent: 2012 /* The DSA core guarantees this callback is only invoked on an actual 2013 * state transition, ensuring the previous hardware state was the 2014 * opposite (!vlan_filtering). It is also called during setup but, in 2015 * that case, any failure here aborts the entire switch initialization. 2016 * 2017 * VLAN_INGRESS and VLAN_EGRESS_TRANSPARENT states are directly derived 2018 * from vlan_filtering. That way, we can simply undo it without 2019 * checking the current HW state as we do with VLAN_EGRESS_MODE. 2020 */ 2021 dsa_switch_for_each_port(dp, ds) { 2022 if (configured_ports & BIT(dp->index)) 2023 rtl8365mb_port_set_transparent(priv, port, dp->index, 2024 vlan_filtering); 2025 } 2026 2027 rtl8365mb_port_set_ingress_filtering(priv, port, !vlan_filtering); 2028 2029 return ret; 2030 } 2031 2032 static int rtl8365mb_port_vlan_add(struct dsa_switch *ds, int port, 2033 const struct switchdev_obj_port_vlan *vlan, 2034 struct netlink_ext_ack *extack) 2035 { 2036 bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 2037 bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); 2038 u16 pvid_vid; 2039 struct realtek_priv *priv = ds->priv; 2040 int ret; 2041 2042 dev_dbg(priv->dev, "add VLAN %d on port %d, %s, %s\n", 2043 vlan->vid, port, untagged ? "untagged" : "tagged", 2044 pvid ? "PVID" : "no PVID"); 2045 2046 /* VID == 0 is reserved in this driver */ 2047 if (vlan->vid == 0) { 2048 NL_SET_ERR_MSG_MOD(extack, 2049 "VLAN 0 is reserved by this driver"); 2050 return -EOPNOTSUPP; 2051 } 2052 2053 mutex_lock(&priv->vlan_lock); 2054 2055 ret = rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); 2056 if (ret) 2057 goto out_unlock; 2058 2059 /* Set PVID if needed */ 2060 if (pvid) { 2061 ret = rtl8365mb_vlan_pvid_port_set(ds, port, vlan->vid, 2062 extack); 2063 if (ret) 2064 goto out_unlock; 2065 } else { 2066 /* or try to unset it if not */ 2067 ret = rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); 2068 if (ret) 2069 goto out_unlock; 2070 } 2071 2072 /* add port to vlan4k. It knows nothing about PVID */ 2073 ret = rtl8365mb_vlan_4k_port_add(ds, port, vlan, extack); 2074 if (ret) 2075 goto undo_set_pvid; 2076 2077 ret = 0; 2078 goto out_unlock; 2079 2080 undo_set_pvid: 2081 /* undo the pvid definition */ 2082 if (pvid != (pvid_vid == vlan->vid)) { 2083 if (pvid_vid) 2084 (void)rtl8365mb_vlan_pvid_port_set(ds, port, pvid_vid, 2085 NULL); 2086 else 2087 (void)rtl8365mb_vlan_pvid_port_clear(ds, port, 2088 vlan->vid); 2089 } 2090 out_unlock: 2091 mutex_unlock(&priv->vlan_lock); 2092 return ret; 2093 } 2094 2095 static int rtl8365mb_port_vlan_del(struct dsa_switch *ds, int port, 2096 const struct switchdev_obj_port_vlan *vlan) 2097 { 2098 bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 2099 bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); 2100 struct realtek_priv *priv = ds->priv; 2101 int ret; 2102 2103 dev_dbg(priv->dev, "del VLAN %d on port %d, %s, %s\n", 2104 vlan->vid, port, untagged ? "untagged" : "tagged", 2105 pvid ? "PVID" : "no PVID"); 2106 2107 /* VID == 0 is reserved in this driver */ 2108 if (vlan->vid == 0) 2109 return -EOPNOTSUPP; 2110 2111 mutex_lock(&priv->vlan_lock); 2112 ret = rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); 2113 if (ret) 2114 goto out_unlock; 2115 2116 ret = rtl8365mb_vlan_4k_port_del(ds, port, vlan); 2117 /* There is little incentive to try to undo the removal of PVID (if it 2118 * was really in use) as an error here might indicate the ASIC stopped 2119 * to answer. 2120 */ 2121 2122 out_unlock: 2123 mutex_unlock(&priv->vlan_lock); 2124 return ret; 2125 } 2126 2127 /* VLAN support is always enabled in the switch. 2128 * 2129 * Standalone forwarding relies on transparent VLAN mode combined with per-port 2130 * isolation masks restricting egress to CPU ports only. 2131 * 2132 */ 2133 static int rtl8365mb_vlan_setup(struct dsa_switch *ds) 2134 { 2135 struct realtek_priv *priv = ds->priv; 2136 struct dsa_port *dp; 2137 int ret; 2138 2139 dsa_switch_for_each_available_port(dp, ds) { 2140 /* Disable vlan-filtering for all ports */ 2141 ret = rtl8365mb_port_vlan_filtering(ds, dp->index, false, NULL); 2142 if (ret) { 2143 dev_err(priv->dev, 2144 "Failed to disable vlan filtering on port %d\n", 2145 dp->index); 2146 return ret; 2147 } 2148 } 2149 2150 /* VLAN is always enabled. */ 2151 ret = regmap_update_bits(priv->map, RTL8365MB_VLAN_CTRL_REG, 2152 RTL8365MB_VLAN_CTRL_EN_MASK, 2153 FIELD_PREP(RTL8365MB_VLAN_CTRL_EN_MASK, 1)); 2154 return ret; 2155 } 2156 2157 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 2158 bool enable) 2159 { 2160 /* Enable/disable learning by limiting the number of L2 addresses the 2161 * port can learn. Realtek documentation states that a limit of zero 2162 * disables learning. When enabling learning, set it to the chip's 2163 * maximum. 2164 */ 2165 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 2166 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); 2167 } 2168 2169 static int rtl8365mb_port_set_ucast_flood(struct realtek_priv *priv, int port, 2170 bool enable) 2171 { 2172 /* Frames with unknown unicast DA will be flooded to a programmable 2173 * port mask that by default includes all ports. Add or remove 2174 * the specified port from this port mask accordingly. 2175 */ 2176 return regmap_update_bits(priv->map, 2177 RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG, 2178 BIT(port), enable ? BIT(port) : 0); 2179 } 2180 2181 static int rtl8365mb_port_set_mcast_flood(struct realtek_priv *priv, int port, 2182 bool enable) 2183 { 2184 return regmap_update_bits(priv->map, 2185 RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG, 2186 BIT(port), enable ? BIT(port) : 0); 2187 } 2188 2189 static int rtl8365mb_port_set_bcast_flood(struct realtek_priv *priv, int port, 2190 bool enable) 2191 { 2192 return regmap_update_bits(priv->map, 2193 RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG, 2194 BIT(port), enable ? BIT(port) : 0); 2195 } 2196 2197 static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port, 2198 struct switchdev_brport_flags flags, 2199 struct netlink_ext_ack *extack) 2200 { 2201 struct realtek_priv *priv = ds->priv; 2202 2203 dev_dbg(priv->dev, "pre_bridge_flags port:%d flags:%lx supported:%lx\n", 2204 port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS); 2205 2206 if (flags.mask & ~RTL8365MB_SUPPORTED_BRIDGE_FLAGS) 2207 return -EINVAL; 2208 2209 return 0; 2210 } 2211 2212 static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port, 2213 u32 efid) 2214 { 2215 return regmap_update_bits(priv->map, RTL8365MB_PORT_EFID_REG(port), 2216 RTL8365MB_PORT_EFID_MASK(port), 2217 efid << RTL8365MB_PORT_EFID_OFFSET(port)); 2218 } 2219 2220 /* Port isolation manipulation functions. 2221 * 2222 * The port isolation register controls the forwarding mask of a given 2223 * port. The switch will not forward packets ingressed on a given port 2224 * to ports which are not enabled in its forwarding mask. 2225 * 2226 * The port forwarding mask has the highest priority in forwarding 2227 * decisions. The only exception to this rule is when the switch 2228 * receives a packet on its CPU port with ALLOW=0. In that case the TX 2229 * field of the CPU tag will override the forwarding port mask. 2230 */ 2231 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 2232 u32 mask) 2233 { 2234 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 2235 mask); 2236 } 2237 2238 static int rtl8365mb_port_add_isolation(struct realtek_priv *priv, int port, 2239 u32 mask) 2240 { 2241 return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 2242 mask, mask); 2243 } 2244 2245 static int rtl8365mb_port_remove_isolation(struct realtek_priv *priv, int port, 2246 u32 mask) 2247 { 2248 return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 2249 mask, 0); 2250 } 2251 2252 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 2253 u32 offset, u32 length, u64 *mibvalue) 2254 { 2255 u64 tmpvalue = 0; 2256 u32 val; 2257 int ret; 2258 int i; 2259 2260 /* The MIB address is an SRAM address. We request a particular address 2261 * and then poll the control register before reading the value from some 2262 * counter registers. 2263 */ 2264 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 2265 RTL8365MB_MIB_ADDRESS(port, offset)); 2266 if (ret) 2267 return ret; 2268 2269 /* Poll for completion */ 2270 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 2271 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 2272 10, 100); 2273 if (ret) 2274 return ret; 2275 2276 /* Presumably this indicates a MIB counter read failure */ 2277 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 2278 return -EIO; 2279 2280 /* There are four MIB counter registers each holding a 16 bit word of a 2281 * MIB counter. Depending on the offset, we should read from the upper 2282 * two or lower two registers. In case the MIB counter is 4 words, we 2283 * read from all four registers. 2284 */ 2285 if (length == 4) 2286 offset = 3; 2287 else 2288 offset = (offset + 1) % 4; 2289 2290 /* Read the MIB counter 16 bits at a time */ 2291 for (i = 0; i < length; i++) { 2292 ret = regmap_read(priv->map, 2293 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 2294 if (ret) 2295 return ret; 2296 2297 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 2298 } 2299 2300 /* Only commit the result if no error occurred */ 2301 *mibvalue = tmpvalue; 2302 2303 return 0; 2304 } 2305 2306 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 2307 { 2308 struct realtek_priv *priv = ds->priv; 2309 struct rtl8365mb *mb; 2310 int ret; 2311 int i; 2312 2313 mb = priv->chip_data; 2314 2315 mutex_lock(&mb->mib_lock); 2316 for (i = 0; i < RTL8365MB_MIB_END; i++) { 2317 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 2318 2319 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 2320 mib->length, &data[i]); 2321 if (ret) { 2322 dev_err(priv->dev, 2323 "failed to read port %d counters: %pe\n", port, 2324 ERR_PTR(ret)); 2325 break; 2326 } 2327 } 2328 mutex_unlock(&mb->mib_lock); 2329 } 2330 2331 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 2332 { 2333 int i; 2334 2335 if (stringset != ETH_SS_STATS) 2336 return; 2337 2338 for (i = 0; i < RTL8365MB_MIB_END; i++) { 2339 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 2340 ethtool_puts(&data, mib->name); 2341 } 2342 } 2343 2344 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 2345 { 2346 if (sset != ETH_SS_STATS) 2347 return -EOPNOTSUPP; 2348 2349 return RTL8365MB_MIB_END; 2350 } 2351 2352 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 2353 struct ethtool_eth_phy_stats *phy_stats) 2354 { 2355 struct realtek_priv *priv = ds->priv; 2356 struct rtl8365mb_mib_counter *mib; 2357 struct rtl8365mb *mb; 2358 2359 mb = priv->chip_data; 2360 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 2361 2362 mutex_lock(&mb->mib_lock); 2363 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 2364 &phy_stats->SymbolErrorDuringCarrier); 2365 mutex_unlock(&mb->mib_lock); 2366 } 2367 2368 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 2369 struct ethtool_eth_mac_stats *mac_stats) 2370 { 2371 u64 cnt[RTL8365MB_MIB_END] = { 2372 [RTL8365MB_MIB_ifOutOctets] = 1, 2373 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 2374 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 2375 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 2376 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 2377 [RTL8365MB_MIB_ifOutDiscards] = 1, 2378 [RTL8365MB_MIB_ifInOctets] = 1, 2379 [RTL8365MB_MIB_ifInUcastPkts] = 1, 2380 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 2381 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 2382 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 2383 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 2384 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 2385 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 2386 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 2387 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 2388 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 2389 2390 }; 2391 struct realtek_priv *priv = ds->priv; 2392 struct rtl8365mb *mb; 2393 int ret; 2394 int i; 2395 2396 mb = priv->chip_data; 2397 2398 mutex_lock(&mb->mib_lock); 2399 for (i = 0; i < RTL8365MB_MIB_END; i++) { 2400 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 2401 2402 /* Only fetch required MIB counters (marked = 1 above) */ 2403 if (!cnt[i]) 2404 continue; 2405 2406 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 2407 mib->length, &cnt[i]); 2408 if (ret) 2409 break; 2410 } 2411 mutex_unlock(&mb->mib_lock); 2412 2413 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 2414 * IEEE 802.3 Managed Objects. This is not always completely faithful, 2415 * but we try out best. See RFC 3635 for a detailed treatment of the 2416 * subject. 2417 */ 2418 2419 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 2420 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 2421 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 2422 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 2423 cnt[RTL8365MB_MIB_ifOutDiscards]; 2424 mac_stats->SingleCollisionFrames = 2425 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 2426 mac_stats->MultipleCollisionFrames = 2427 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 2428 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 2429 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 2430 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 2431 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 2432 mac_stats->FrameCheckSequenceErrors = 2433 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 2434 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 2435 18 * mac_stats->FramesTransmittedOK; 2436 mac_stats->FramesWithDeferredXmissions = 2437 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 2438 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 2439 mac_stats->FramesAbortedDueToXSColls = 2440 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 2441 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 2442 18 * mac_stats->FramesReceivedOK; 2443 mac_stats->MulticastFramesXmittedOK = 2444 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 2445 mac_stats->BroadcastFramesXmittedOK = 2446 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 2447 mac_stats->MulticastFramesReceivedOK = 2448 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 2449 mac_stats->BroadcastFramesReceivedOK = 2450 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 2451 } 2452 2453 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 2454 struct ethtool_eth_ctrl_stats *ctrl_stats) 2455 { 2456 struct realtek_priv *priv = ds->priv; 2457 struct rtl8365mb_mib_counter *mib; 2458 struct rtl8365mb *mb; 2459 2460 mb = priv->chip_data; 2461 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 2462 2463 mutex_lock(&mb->mib_lock); 2464 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 2465 &ctrl_stats->UnsupportedOpcodesReceived); 2466 mutex_unlock(&mb->mib_lock); 2467 } 2468 2469 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 2470 { 2471 u64 cnt[RTL8365MB_MIB_END] = { 2472 [RTL8365MB_MIB_ifOutOctets] = 1, 2473 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 2474 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 2475 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 2476 [RTL8365MB_MIB_ifOutDiscards] = 1, 2477 [RTL8365MB_MIB_ifInOctets] = 1, 2478 [RTL8365MB_MIB_ifInUcastPkts] = 1, 2479 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 2480 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 2481 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 2482 [RTL8365MB_MIB_etherStatsCollisions] = 1, 2483 [RTL8365MB_MIB_etherStatsFragments] = 1, 2484 [RTL8365MB_MIB_etherStatsJabbers] = 1, 2485 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 2486 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 2487 }; 2488 struct rtl8365mb *mb = priv->chip_data; 2489 struct rtnl_link_stats64 *stats; 2490 int ret; 2491 int i; 2492 2493 stats = &mb->ports[port].stats; 2494 2495 mutex_lock(&mb->mib_lock); 2496 for (i = 0; i < RTL8365MB_MIB_END; i++) { 2497 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 2498 2499 /* Only fetch required MIB counters (marked = 1 above) */ 2500 if (!cnt[i]) 2501 continue; 2502 2503 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 2504 c->length, &cnt[i]); 2505 if (ret) 2506 break; 2507 } 2508 mutex_unlock(&mb->mib_lock); 2509 2510 /* Don't update statistics if there was an error reading the counters */ 2511 if (ret) 2512 return; 2513 2514 spin_lock(&mb->ports[port].stats_lock); 2515 2516 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 2517 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 2518 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 2519 2520 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 2521 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 2522 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 2523 2524 /* if{In,Out}Octets includes FCS - remove it */ 2525 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 2526 stats->tx_bytes = 2527 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 2528 2529 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 2530 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 2531 2532 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 2533 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 2534 2535 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 2536 cnt[RTL8365MB_MIB_etherStatsJabbers]; 2537 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 2538 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 2539 2540 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 2541 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 2542 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 2543 2544 spin_unlock(&mb->ports[port].stats_lock); 2545 } 2546 2547 static void rtl8365mb_stats_poll(struct work_struct *work) 2548 { 2549 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 2550 struct rtl8365mb_port, 2551 mib_work); 2552 struct realtek_priv *priv = p->priv; 2553 2554 rtl8365mb_stats_update(priv, p->index); 2555 2556 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 2557 } 2558 2559 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 2560 struct rtnl_link_stats64 *s) 2561 { 2562 struct realtek_priv *priv = ds->priv; 2563 struct rtl8365mb_port *p; 2564 struct rtl8365mb *mb; 2565 2566 mb = priv->chip_data; 2567 p = &mb->ports[port]; 2568 2569 spin_lock(&p->stats_lock); 2570 memcpy(s, &p->stats, sizeof(*s)); 2571 spin_unlock(&p->stats_lock); 2572 } 2573 2574 static int rtl8365mb_stats_setup(struct realtek_priv *priv) 2575 { 2576 struct rtl8365mb *mb = priv->chip_data; 2577 struct dsa_switch *ds = &priv->ds; 2578 struct dsa_port *dp; 2579 int ret; 2580 2581 /* Per-chip global mutex to protect MIB counter access, since doing 2582 * so requires accessing a series of registers in a particular order. 2583 */ 2584 ret = devm_mutex_init(priv->dev, &mb->mib_lock); 2585 if (ret) 2586 return ret; 2587 2588 dsa_switch_for_each_available_port(dp, ds) { 2589 struct rtl8365mb_port *p = &mb->ports[dp->index]; 2590 2591 /* Per-port spinlock to protect the stats64 data */ 2592 spin_lock_init(&p->stats_lock); 2593 2594 /* This work polls the MIB counters and keeps the stats64 data 2595 * up-to-date. 2596 */ 2597 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 2598 } 2599 2600 return 0; 2601 } 2602 2603 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 2604 { 2605 struct rtl8365mb *mb = priv->chip_data; 2606 struct dsa_switch *ds = &priv->ds; 2607 struct dsa_port *dp; 2608 2609 dsa_switch_for_each_available_port(dp, ds) { 2610 struct rtl8365mb_port *p = &mb->ports[dp->index]; 2611 2612 cancel_delayed_work_sync(&p->mib_work); 2613 } 2614 } 2615 2616 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 2617 u32 *val) 2618 { 2619 int ret; 2620 2621 ret = regmap_read(priv->map, reg, val); 2622 if (ret) 2623 return ret; 2624 2625 return regmap_write(priv->map, reg, *val); 2626 } 2627 2628 static irqreturn_t rtl8365mb_irq(int irq, void *data) 2629 { 2630 struct realtek_priv *priv = data; 2631 unsigned long line_changes = 0; 2632 u32 stat; 2633 int line; 2634 int ret; 2635 2636 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 2637 &stat); 2638 if (ret) 2639 goto out_error; 2640 2641 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 2642 u32 linkdown_ind; 2643 u32 linkup_ind; 2644 u32 val; 2645 2646 ret = rtl8365mb_get_and_clear_status_reg( 2647 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 2648 if (ret) 2649 goto out_error; 2650 2651 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 2652 2653 ret = rtl8365mb_get_and_clear_status_reg( 2654 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 2655 if (ret) 2656 goto out_error; 2657 2658 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 2659 2660 line_changes = linkup_ind | linkdown_ind; 2661 } 2662 2663 if (!line_changes) 2664 goto out_none; 2665 2666 for_each_set_bit(line, &line_changes, priv->num_ports) { 2667 int child_irq = irq_find_mapping(priv->irqdomain, line); 2668 2669 if (!child_irq) 2670 continue; 2671 2672 handle_nested_irq(child_irq); 2673 } 2674 2675 return IRQ_HANDLED; 2676 2677 out_error: 2678 dev_err(priv->dev, "failed to read interrupt status: %pe\n", 2679 ERR_PTR(ret)); 2680 2681 out_none: 2682 return IRQ_NONE; 2683 } 2684 2685 static struct irq_chip rtl8365mb_irq_chip = { 2686 .name = "rtl8365mb", 2687 /* The hardware doesn't support masking IRQs on a per-port basis */ 2688 }; 2689 2690 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 2691 irq_hw_number_t hwirq) 2692 { 2693 struct realtek_priv *priv = domain->host_data; 2694 struct rtl8365mb *mb = priv->chip_data; 2695 2696 irq_set_chip_data(irq, priv); 2697 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 2698 irq_set_nested_thread(irq, 1); 2699 irq_set_noprobe(irq); 2700 irq_set_parent(irq, mb->irq); 2701 2702 return 0; 2703 } 2704 2705 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 2706 { 2707 irq_set_nested_thread(irq, 0); 2708 irq_set_chip_and_handler(irq, NULL, NULL); 2709 irq_set_chip_data(irq, NULL); 2710 } 2711 2712 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 2713 .map = rtl8365mb_irq_map, 2714 .unmap = rtl8365mb_irq_unmap, 2715 .xlate = irq_domain_xlate_onecell, 2716 }; 2717 2718 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 2719 { 2720 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 2721 RTL8365MB_INTR_LINK_CHANGE_MASK, 2722 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 2723 enable ? 1 : 0)); 2724 } 2725 2726 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 2727 { 2728 return rtl8365mb_set_irq_enable(priv, true); 2729 } 2730 2731 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 2732 { 2733 return rtl8365mb_set_irq_enable(priv, false); 2734 } 2735 2736 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 2737 { 2738 struct rtl8365mb *mb = priv->chip_data; 2739 struct dsa_switch *ds = &priv->ds; 2740 struct device_node *intc; 2741 struct dsa_port *dp; 2742 u32 irq_trig; 2743 int virq; 2744 int irq; 2745 u32 val; 2746 int ret; 2747 2748 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 2749 if (!intc) { 2750 dev_err(priv->dev, "missing child interrupt-controller node\n"); 2751 return -EINVAL; 2752 } 2753 2754 /* rtl8365mb IRQs cascade off this one */ 2755 irq = of_irq_get(intc, 0); 2756 if (irq <= 0) { 2757 if (!irq) { 2758 dev_err(priv->dev, "failed to map IRQ\n"); 2759 ret = -EINVAL; 2760 } else { 2761 ret = dev_err_probe(priv->dev, irq, 2762 "failed to get parent irq\n"); 2763 } 2764 goto out_put_node; 2765 } 2766 2767 /* Store the irq so that we know to map and free it during teardown */ 2768 mb->irq = irq; 2769 2770 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), priv->num_ports, 2771 &rtl8365mb_irqdomain_ops, priv); 2772 if (!priv->irqdomain) { 2773 dev_err(priv->dev, "failed to add irq domain\n"); 2774 ret = -ENOMEM; 2775 goto out_put_node; 2776 } 2777 2778 dsa_switch_for_each_available_port(dp, ds) { 2779 virq = irq_create_mapping(priv->irqdomain, dp->index); 2780 if (!virq) { 2781 dev_err(priv->dev, 2782 "failed to create irq domain mapping\n"); 2783 ret = -EINVAL; 2784 goto out_remove_irqdomain; 2785 } 2786 2787 irq_set_parent(virq, irq); 2788 } 2789 2790 /* Configure chip interrupt signal polarity */ 2791 irq_trig = irq_get_trigger_type(irq); 2792 switch (irq_trig) { 2793 case IRQF_TRIGGER_RISING: 2794 case IRQF_TRIGGER_HIGH: 2795 val = RTL8365MB_INTR_POLARITY_HIGH; 2796 break; 2797 case IRQF_TRIGGER_FALLING: 2798 case IRQF_TRIGGER_LOW: 2799 val = RTL8365MB_INTR_POLARITY_LOW; 2800 break; 2801 default: 2802 dev_err(priv->dev, "unsupported irq trigger type %u\n", 2803 irq_trig); 2804 ret = -EINVAL; 2805 goto out_remove_irqdomain; 2806 } 2807 2808 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 2809 RTL8365MB_INTR_POLARITY_MASK, 2810 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 2811 if (ret) 2812 goto out_remove_irqdomain; 2813 2814 /* Disable the interrupt in case the chip has it enabled on reset */ 2815 ret = rtl8365mb_irq_disable(priv); 2816 if (ret) 2817 goto out_remove_irqdomain; 2818 2819 /* Clear the interrupt status register */ 2820 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 2821 RTL8365MB_INTR_ALL_MASK); 2822 if (ret) 2823 goto out_remove_irqdomain; 2824 2825 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 2826 "rtl8365mb", priv); 2827 if (ret) { 2828 dev_err(priv->dev, "failed to request irq: %pe\n", 2829 ERR_PTR(ret)); 2830 goto out_remove_irqdomain; 2831 } 2832 2833 ret = rtl8365mb_irq_enable(priv); 2834 if (ret) 2835 goto out_free_irq; 2836 2837 of_node_put(intc); 2838 2839 return 0; 2840 2841 out_free_irq: 2842 free_irq(mb->irq, priv); 2843 2844 out_remove_irqdomain: 2845 dsa_switch_for_each_port(dp, ds) { 2846 virq = irq_find_mapping(priv->irqdomain, dp->index); 2847 2848 if (virq) 2849 irq_dispose_mapping(virq); 2850 } 2851 2852 irq_domain_remove(priv->irqdomain); 2853 priv->irqdomain = NULL; 2854 2855 out_put_node: 2856 mb->irq = 0; 2857 of_node_put(intc); 2858 2859 return ret; 2860 } 2861 2862 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 2863 { 2864 struct rtl8365mb *mb = priv->chip_data; 2865 struct dsa_switch *ds = &priv->ds; 2866 struct dsa_port *dp; 2867 int virq; 2868 2869 if (mb->irq) { 2870 free_irq(mb->irq, priv); 2871 mb->irq = 0; 2872 } 2873 2874 if (priv->irqdomain) { 2875 /* Unused ports with a linked PHY still have an active IRQ 2876 * mapping that must be disposed of during teardown. Loop 2877 * through all ports. 2878 */ 2879 dsa_switch_for_each_port(dp, ds) { 2880 virq = irq_find_mapping(priv->irqdomain, dp->index); 2881 2882 if (virq) 2883 irq_dispose_mapping(virq); 2884 } 2885 2886 irq_domain_remove(priv->irqdomain); 2887 priv->irqdomain = NULL; 2888 } 2889 } 2890 2891 static int rtl8365mb_cpu_config(struct realtek_priv *priv) 2892 { 2893 struct rtl8365mb *mb = priv->chip_data; 2894 struct rtl8365mb_cpu *cpu = &mb->cpu; 2895 u32 val; 2896 int ret; 2897 2898 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 2899 RTL8365MB_CPU_PORT_MASK_MASK, 2900 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 2901 cpu->mask)); 2902 if (ret) 2903 return ret; 2904 2905 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 2906 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 2907 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 2908 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 2909 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 2910 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 2911 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 2912 cpu->trap_port >> 3 & 0x1); 2913 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 2914 if (ret) 2915 return ret; 2916 2917 return 0; 2918 } 2919 2920 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, 2921 enum dsa_tag_protocol proto) 2922 { 2923 struct realtek_priv *priv = ds->priv; 2924 struct rtl8365mb_cpu *cpu; 2925 struct rtl8365mb *mb; 2926 2927 mb = priv->chip_data; 2928 cpu = &mb->cpu; 2929 2930 switch (proto) { 2931 case DSA_TAG_PROTO_RTL8_4: 2932 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 2933 cpu->position = RTL8365MB_CPU_POS_AFTER_SA; 2934 break; 2935 case DSA_TAG_PROTO_RTL8_4T: 2936 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 2937 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC; 2938 break; 2939 /* The switch also supports a 4-byte format, similar to rtl4a but with 2940 * the same 0x04 8-bit version and probably 8-bit port source/dest. 2941 * There is no public doc about it. Not supported yet and it will probably 2942 * never be. 2943 */ 2944 default: 2945 return -EPROTONOSUPPORT; 2946 } 2947 2948 return rtl8365mb_cpu_config(priv); 2949 } 2950 2951 static int rtl8365mb_switch_init(struct realtek_priv *priv) 2952 { 2953 struct rtl8365mb *mb = priv->chip_data; 2954 const struct rtl8365mb_chip_info *ci; 2955 int ret; 2956 int i; 2957 2958 ci = mb->chip_info; 2959 2960 /* Do any chip-specific init jam before getting to the common stuff */ 2961 if (ci->jam_table) { 2962 for (i = 0; i < ci->jam_size; i++) { 2963 ret = regmap_write(priv->map, ci->jam_table[i].reg, 2964 ci->jam_table[i].val); 2965 if (ret) 2966 return ret; 2967 } 2968 } 2969 2970 /* Common init jam */ 2971 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 2972 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 2973 rtl8365mb_init_jam_common[i].val); 2974 if (ret) 2975 return ret; 2976 } 2977 2978 return 0; 2979 } 2980 2981 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 2982 { 2983 u32 val; 2984 2985 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 2986 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 2987 2988 /* Realtek documentation says the chip needs 1 second to reset. Sleep 2989 * for 100 ms before accessing any registers to prevent ACK timeouts. 2990 */ 2991 msleep(100); 2992 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 2993 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 2994 20000, 1e6); 2995 } 2996 2997 static int rtl8365mb_setup(struct dsa_switch *ds) 2998 { 2999 struct realtek_priv *priv = ds->priv; 3000 struct rtl8365mb_cpu *cpu; 3001 u32 downports_mask = 0; 3002 u32 upports_mask = 0; 3003 struct rtl8365mb *mb; 3004 struct dsa_port *dp; 3005 int ret; 3006 3007 mb = priv->chip_data; 3008 cpu = &mb->cpu; 3009 3010 mb->pcs.ops = &rtl8365mb_pcs_ops; 3011 3012 /* The SerDes has no link interrupt wired up, so phylink must poll the 3013 * PCS for link changes when it tracks the link through pcs_get_state() 3014 * (in-band mode with autonegotiation disabled). 3015 */ 3016 mb->pcs.poll = true; 3017 3018 ret = rtl8365mb_reset_chip(priv); 3019 if (ret) { 3020 dev_err(priv->dev, "failed to reset chip: %pe\n", 3021 ERR_PTR(ret)); 3022 goto out_error; 3023 } 3024 3025 ret = rtl8365mb_sds_probe_option(priv); 3026 if (ret) { 3027 dev_err(priv->dev, "failed to probe SerDes chip option: %pe\n", 3028 ERR_PTR(ret)); 3029 goto out_error; 3030 } 3031 3032 /* Configure switch to vendor-defined initial state */ 3033 ret = rtl8365mb_switch_init(priv); 3034 if (ret) { 3035 dev_err(priv->dev, "failed to initialize switch: %pe\n", 3036 ERR_PTR(ret)); 3037 goto out_error; 3038 } 3039 3040 if (mb->sds_supported) { 3041 ret = rtl8365mb_sds_raise_rate_limits(priv); 3042 if (ret) { 3043 dev_err(priv->dev, 3044 "failed to raise port rate limits: %pe\n", 3045 ERR_PTR(ret)); 3046 goto out_error; 3047 } 3048 } 3049 3050 /* Set up cascading IRQs */ 3051 ret = rtl8365mb_irq_setup(priv); 3052 if (ret == -EPROBE_DEFER) 3053 return ret; 3054 else if (ret) 3055 dev_info(priv->dev, "no interrupt support\n"); 3056 3057 dsa_switch_for_each_port(dp, ds) { 3058 /* Cascading (DSA links) is not supported yet. 3059 * Historically, the driver has always been broken 3060 * without a dedicated CPU port because CPU tagging 3061 * would be disabled, rendering the switch entirely 3062 * non-functional for DSA operations. 3063 */ 3064 if (dsa_port_is_dsa(dp)) { 3065 dev_err(priv->dev, "Cascading (DSA link) not supported\n"); 3066 ret = -EOPNOTSUPP; 3067 goto out_teardown_irq; 3068 } 3069 } 3070 3071 /* Start with all ports blocked, including unused ports */ 3072 dsa_switch_for_each_port(dp, ds) { 3073 struct rtl8365mb_port *p = &mb->ports[dp->index]; 3074 3075 /* Set the initial STP state of all ports to DISABLED, otherwise 3076 * ports will still forward frames to the CPU despite being 3077 * administratively down by default. 3078 */ 3079 rtl8365mb_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 3080 3081 /* Start with all port completely isolated */ 3082 ret = rtl8365mb_port_set_isolation(priv, dp->index, 0); 3083 if (ret) 3084 goto out_teardown_irq; 3085 3086 /* Set the default EFID 0 for standalone mode */ 3087 ret = rtl8365mb_port_set_efid(priv, dp->index, 0); 3088 if (ret) 3089 goto out_teardown_irq; 3090 3091 /* Disable learning */ 3092 ret = rtl8365mb_port_set_learning(priv, dp->index, false); 3093 if (ret) 3094 goto out_teardown_irq; 3095 3096 /* Enable all types of flooding */ 3097 ret = rtl83xx_setup_port_flood_control(priv, dp->index); 3098 if (ret) 3099 goto out_teardown_irq; 3100 3101 /* Set up per-port private data */ 3102 p->priv = priv; 3103 p->index = dp->index; 3104 3105 /* Collect CPU ports. If we support cascade switches, it should 3106 * also include the upstream DSA ports. 3107 */ 3108 if (!dsa_port_is_cpu(dp)) 3109 continue; 3110 3111 upports_mask |= BIT(dp->index); 3112 } 3113 3114 /* Configure user ports */ 3115 dsa_switch_for_each_port(dp, ds) { 3116 if (!dsa_port_is_user(dp)) 3117 continue; 3118 3119 /* Forward only to the CPU */ 3120 ret = rtl8365mb_port_set_isolation(priv, dp->index, 3121 upports_mask); 3122 if (ret) 3123 goto out_teardown_irq; 3124 3125 /* If we support cascade switches, it should also include the 3126 * downstream DSA ports. 3127 */ 3128 downports_mask |= BIT(dp->index); 3129 } 3130 3131 /* Configure CPU tagging */ 3132 /* If we support cascade switches, it should also include the upstream 3133 * DSA ports. 3134 */ 3135 dsa_switch_for_each_cpu_port(dp, ds) { 3136 /* Use the first CPU port as trap_port */ 3137 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS) 3138 cpu->trap_port = dp->index; 3139 3140 /* Forward to all user ports */ 3141 ret = rtl8365mb_port_set_isolation(priv, dp->index, 3142 downports_mask); 3143 if (ret) 3144 goto out_teardown_irq; 3145 } 3146 3147 cpu->mask = upports_mask; 3148 cpu->enable = cpu->mask > 0; 3149 3150 if (!cpu->enable) { 3151 dev_err(priv->dev, "no CPU port defined\n"); 3152 ret = -EINVAL; 3153 goto out_teardown_irq; 3154 } 3155 3156 ret = rtl8365mb_cpu_config(priv); 3157 if (ret) 3158 goto out_teardown_irq; 3159 3160 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN); 3161 if (ret) 3162 goto out_teardown_irq; 3163 3164 ds->assisted_learning_on_cpu_port = true; 3165 ds->fdb_isolation = true; 3166 /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */ 3167 ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK); 3168 3169 ds->configure_vlan_while_not_filtering = true; 3170 3171 /* Set up VLAN */ 3172 ret = rtl8365mb_vlan_setup(ds); 3173 if (ret) 3174 goto out_teardown_irq; 3175 3176 ret = rtl83xx_setup_user_mdio(ds); 3177 if (ret) { 3178 dev_err(priv->dev, "could not set up MDIO bus\n"); 3179 goto out_teardown_irq; 3180 } 3181 3182 /* Start statistics counter polling */ 3183 ret = rtl8365mb_stats_setup(priv); 3184 if (ret) { 3185 dev_err(priv->dev, "failed to setup stats: %pe\n", 3186 ERR_PTR(ret)); 3187 goto out_teardown_irq; 3188 } 3189 3190 return 0; 3191 3192 out_teardown_irq: 3193 rtl8365mb_irq_teardown(priv); 3194 3195 out_error: 3196 return ret; 3197 } 3198 3199 static void rtl8365mb_teardown(struct dsa_switch *ds) 3200 { 3201 struct realtek_priv *priv = ds->priv; 3202 3203 rtl8365mb_stats_teardown(priv); 3204 rtl8365mb_irq_teardown(priv); 3205 } 3206 3207 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 3208 { 3209 int ret; 3210 3211 /* For some reason we have to write a magic value to an arbitrary 3212 * register whenever accessing the chip ID/version registers. 3213 */ 3214 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 3215 if (ret) 3216 return ret; 3217 3218 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 3219 if (ret) 3220 return ret; 3221 3222 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 3223 if (ret) 3224 return ret; 3225 3226 /* Reset magic register */ 3227 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 3228 if (ret) 3229 return ret; 3230 3231 return 0; 3232 } 3233 3234 static int rtl8365mb_detect(struct realtek_priv *priv) 3235 { 3236 struct rtl8365mb *mb = priv->chip_data; 3237 u32 chip_id; 3238 u32 chip_ver; 3239 int ret; 3240 int i; 3241 3242 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 3243 if (ret) { 3244 dev_err(priv->dev, "failed to read chip id and version: %pe\n", 3245 ERR_PTR(ret)); 3246 return ret; 3247 } 3248 3249 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) { 3250 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i]; 3251 3252 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) { 3253 mb->chip_info = ci; 3254 break; 3255 } 3256 } 3257 3258 if (!mb->chip_info) { 3259 dev_err(priv->dev, 3260 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id, 3261 chip_ver); 3262 return -ENODEV; 3263 } 3264 3265 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name); 3266 3267 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 3268 mb->priv = priv; 3269 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 3270 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 3271 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 3272 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 3273 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 3274 3275 return 0; 3276 } 3277 3278 static const struct phylink_mac_ops rtl8365mb_phylink_mac_ops = { 3279 .mac_select_pcs = rtl8365mb_phylink_mac_select_pcs, 3280 .mac_config = rtl8365mb_phylink_mac_config, 3281 .mac_link_down = rtl8365mb_phylink_mac_link_down, 3282 .mac_link_up = rtl8365mb_phylink_mac_link_up, 3283 }; 3284 3285 static const struct dsa_switch_ops rtl8365mb_switch_ops = { 3286 .get_tag_protocol = rtl8365mb_get_tag_protocol, 3287 .change_tag_protocol = rtl8365mb_change_tag_protocol, 3288 .setup = rtl8365mb_setup, 3289 .teardown = rtl8365mb_teardown, 3290 .phylink_get_caps = rtl8365mb_phylink_get_caps, 3291 .port_bridge_join = rtl83xx_port_bridge_join, 3292 .port_bridge_leave = rtl83xx_port_bridge_leave, 3293 .port_pre_bridge_flags = rtl8365mb_port_pre_bridge_flags, 3294 .port_bridge_flags = rtl83xx_port_bridge_flags, 3295 .port_stp_state_set = rtl8365mb_port_stp_state_set, 3296 .port_fast_age = rtl83xx_port_fast_age, 3297 .port_fdb_add = rtl83xx_port_fdb_add, 3298 .port_fdb_del = rtl83xx_port_fdb_del, 3299 .port_fdb_dump = rtl83xx_port_fdb_dump, 3300 .port_mdb_add = rtl83xx_port_mdb_add, 3301 .port_mdb_del = rtl83xx_port_mdb_del, 3302 .port_vlan_add = rtl8365mb_port_vlan_add, 3303 .port_vlan_del = rtl8365mb_port_vlan_del, 3304 .port_vlan_filtering = rtl8365mb_port_vlan_filtering, 3305 .get_strings = rtl8365mb_get_strings, 3306 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 3307 .get_sset_count = rtl8365mb_get_sset_count, 3308 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 3309 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 3310 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 3311 .get_stats64 = rtl8365mb_get_stats64, 3312 .port_change_mtu = rtl8365mb_port_change_mtu, 3313 .port_max_mtu = rtl8365mb_port_max_mtu, 3314 .port_hsr_join = dsa_port_simple_hsr_join, 3315 .port_hsr_leave = dsa_port_simple_hsr_leave, 3316 }; 3317 3318 static const struct realtek_ops rtl8365mb_ops = { 3319 .detect = rtl8365mb_detect, 3320 .port_add_isolation = rtl8365mb_port_add_isolation, 3321 .port_remove_isolation = rtl8365mb_port_remove_isolation, 3322 .port_set_efid = rtl8365mb_port_set_efid, 3323 .port_set_learning = rtl8365mb_port_set_learning, 3324 .port_set_ucast_flood = rtl8365mb_port_set_ucast_flood, 3325 .port_set_mcast_flood = rtl8365mb_port_set_mcast_flood, 3326 .port_set_bcast_flood = rtl8365mb_port_set_bcast_flood, 3327 .l2_add_uc = rtl8365mb_l2_add_uc, 3328 .l2_del_uc = rtl8365mb_l2_del_uc, 3329 .l2_get_next_uc = rtl8365mb_l2_get_next_uc, 3330 .l2_add_mc = rtl8365mb_l2_add_mc, 3331 .l2_del_mc = rtl8365mb_l2_del_mc, 3332 .l2_flush = rtl8365mb_l2_flush, 3333 .phy_read = rtl8365mb_phy_read, 3334 .phy_write = rtl8365mb_phy_write, 3335 }; 3336 3337 const struct realtek_variant rtl8365mb_variant = { 3338 .ds_ops = &rtl8365mb_switch_ops, 3339 .ops = &rtl8365mb_ops, 3340 .phylink_mac_ops = &rtl8365mb_phylink_mac_ops, 3341 .clk_delay = 10, 3342 .cmd_read = 0xb9, 3343 .cmd_write = 0xb8, 3344 .chip_data_sz = sizeof(struct rtl8365mb), 3345 }; 3346 3347 static const struct of_device_id rtl8365mb_of_match[] = { 3348 { .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, }, 3349 { /* sentinel */ }, 3350 }; 3351 MODULE_DEVICE_TABLE(of, rtl8365mb_of_match); 3352 3353 static struct platform_driver rtl8365mb_smi_driver = { 3354 .driver = { 3355 .name = "rtl8365mb-smi", 3356 .of_match_table = rtl8365mb_of_match, 3357 }, 3358 .probe = realtek_smi_probe, 3359 .remove = realtek_smi_remove, 3360 .shutdown = realtek_smi_shutdown, 3361 }; 3362 3363 static struct mdio_driver rtl8365mb_mdio_driver = { 3364 .mdiodrv.driver = { 3365 .name = "rtl8365mb-mdio", 3366 .of_match_table = rtl8365mb_of_match, 3367 }, 3368 .probe = realtek_mdio_probe, 3369 .remove = realtek_mdio_remove, 3370 .shutdown = realtek_mdio_shutdown, 3371 }; 3372 3373 static int rtl8365mb_init(void) 3374 { 3375 int ret; 3376 3377 ret = realtek_mdio_driver_register(&rtl8365mb_mdio_driver); 3378 if (ret) 3379 return ret; 3380 3381 ret = realtek_smi_driver_register(&rtl8365mb_smi_driver); 3382 if (ret) { 3383 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 3384 return ret; 3385 } 3386 3387 return 0; 3388 } 3389 module_init(rtl8365mb_init); 3390 3391 static void __exit rtl8365mb_exit(void) 3392 { 3393 realtek_smi_driver_unregister(&rtl8365mb_smi_driver); 3394 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 3395 } 3396 module_exit(rtl8365mb_exit); 3397 3398 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 3399 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 3400 MODULE_LICENSE("GPL"); 3401 MODULE_IMPORT_NS("REALTEK_DSA"); 3402