1 // SPDX-License-Identifier: GPL-2.0 2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch. 3 * 4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk> 5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk> 6 * 7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4 8 * integrated PHYs for the user facing ports, and an extension interface which 9 * can be connected to the CPU - or another PHY - via either MII, RMII, or 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 11 * (SMI), which uses the MDIO/MDC lines. 12 * 13 * Below is a simplified block diagram of the chip and its relevant interfaces. 14 * 15 * .-----------------------------------. 16 * | | 17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC | 18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC | 19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC | 20 * UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC | 21 * | | 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 23 * | interface 1 GMAC 1 | 24 * | | 25 * SMI driver/ <-MDC/SCL---> Management ~~~~~~~~~~~~~~ | 26 * EEPROM <-MDIO/SDA--> interface ~REALTEK ~~~~~ | 27 * | ~RTL8365MB ~~~ | 28 * | ~GXXXC TAIWAN~ | 29 * GPIO <--------------> Reset ~~~~~~~~~~~~~~ | 30 * | | 31 * Interrupt <----------> Link UP/DOWN events | 32 * controller | | 33 * '-----------------------------------' 34 * 35 * The driver uses DSA to integrate the 4 user and 1 extension ports into the 36 * kernel. Netdevices are created for the user ports, as are PHY devices for 37 * their integrated PHYs. The device tree firmware should also specify the link 38 * partner of the extension port - either via a fixed-link or other phy-handle. 39 * See the device tree bindings for more detailed information. Note that the 40 * driver has only been tested with a fixed-link, but in principle it should not 41 * matter. 42 * 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 44 * 45 * The interrupt line is asserted on link UP/DOWN events. The driver creates a 46 * custom irqchip to handle this interrupt and demultiplex the events by reading 47 * the status registers via SMI. Interrupts are then propagated to the relevant 48 * PHY device. 49 * 50 * The EEPROM contains initial register values which the chip will read over I2C 51 * upon hardware reset. It is also possible to omit the EEPROM. In both cases, 52 * the driver will manually reprogram some registers using jam tables to reach 53 * an initial state defined by the vendor driver. 54 * 55 * This Linux driver is written based on an OS-agnostic vendor driver from 56 * Realtek. The reference GPL-licensed sources can be found in the OpenWrt 57 * source tree under the name rtl8367c. The vendor driver claims to support a 58 * number of similar switch controllers from Realtek, but the only hardware we 59 * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under 60 * the name RTL8367C. Although one wishes that the 'C' stood for some kind of 61 * common hardware revision, there exist examples of chips with the suffix -VC 62 * which are explicitly not supported by the rtl8367c driver and which instead 63 * require the rtl8367d vendor driver. With all this uncertainty, the driver has 64 * been modestly named rtl8365mb. Future implementors may wish to rename things 65 * accordingly. 66 * 67 * In the same family of chips, some carry up to 8 user ports and up to 2 68 * extension ports. Where possible this driver tries to make things generic, but 69 * more work must be done to support these configurations. According to 70 * documentation from Realtek, the family should include the following chips: 71 * 72 * - RTL8363NB 73 * - RTL8363NB-VB 74 * - RTL8363SC 75 * - RTL8363SC-VB 76 * - RTL8364NB 77 * - RTL8364NB-VB 78 * - RTL8365MB-VC 79 * - RTL8366SC 80 * - RTL8367RB-VB 81 * - RTL8367SB 82 * - RTL8367S 83 * - RTL8370MB 84 * - RTL8310SR 85 * 86 * Some of the register logic for these additional chips has been skipped over 87 * while implementing this driver. It is therefore not possible to assume that 88 * things will work out-of-the-box for other chips, and a careful review of the 89 * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be 90 * one of the simpler chips. 91 */ 92 93 #include <linux/bitfield.h> 94 #include <linux/bitops.h> 95 #include <linux/interrupt.h> 96 #include <linux/irqdomain.h> 97 #include <linux/mutex.h> 98 #include <linux/of_irq.h> 99 #include <linux/regmap.h> 100 #include <linux/if_bridge.h> 101 #include <linux/if_vlan.h> 102 103 #include "realtek.h" 104 #include "realtek-smi.h" 105 #include "realtek-mdio.h" 106 #include "rtl83xx.h" 107 #include "rtl8365mb_l2.h" 108 #include "rtl8365mb_vlan.h" 109 110 /* Family-specific data and limits */ 111 #define RTL8365MB_PHYADDRMAX 7 112 #define RTL8365MB_NUM_PHYREGS 32 113 #define RTL8365MB_PHYREGMAX (RTL8365MB_NUM_PHYREGS - 1) 114 #define RTL8365MB_MAX_NUM_PORTS 11 115 /* Valid for the whole family except RTL8370B, which has 4160 entries. 116 * RTL8370B is mentioned in vendor code but it might not even belong 117 * to the same RTL8367C family. 118 */ 119 #define RTL8365MB_LEARN_LIMIT_MAX 2112 120 #define RTL8365MB_MAX_NUM_EXTINTS 3 121 122 /* Chip identification registers */ 123 #define RTL8365MB_CHIP_ID_REG 0x1300 124 125 #define RTL8365MB_CHIP_VER_REG 0x1301 126 127 #define RTL8365MB_MAGIC_REG 0x13C2 128 #define RTL8365MB_MAGIC_VALUE 0x0249 129 130 /* Chip reset register */ 131 #define RTL8365MB_CHIP_RESET_REG 0x1322 132 #define RTL8365MB_CHIP_RESET_SW_MASK 0x0002 133 #define RTL8365MB_CHIP_RESET_HW_MASK 0x0001 134 135 /* Interrupt polarity register */ 136 #define RTL8365MB_INTR_POLARITY_REG 0x1100 137 #define RTL8365MB_INTR_POLARITY_MASK 0x0001 138 #define RTL8365MB_INTR_POLARITY_HIGH 0 139 #define RTL8365MB_INTR_POLARITY_LOW 1 140 141 /* Interrupt control/status register - enable/check specific interrupt types */ 142 #define RTL8365MB_INTR_CTRL_REG 0x1101 143 #define RTL8365MB_INTR_STATUS_REG 0x1102 144 #define RTL8365MB_INTR_SLIENT_START_2_MASK 0x1000 145 #define RTL8365MB_INTR_SLIENT_START_MASK 0x0800 146 #define RTL8365MB_INTR_ACL_ACTION_MASK 0x0200 147 #define RTL8365MB_INTR_CABLE_DIAG_FIN_MASK 0x0100 148 #define RTL8365MB_INTR_INTERRUPT_8051_MASK 0x0080 149 #define RTL8365MB_INTR_LOOP_DETECTION_MASK 0x0040 150 #define RTL8365MB_INTR_GREEN_TIMER_MASK 0x0020 151 #define RTL8365MB_INTR_SPECIAL_CONGEST_MASK 0x0010 152 #define RTL8365MB_INTR_SPEED_CHANGE_MASK 0x0008 153 #define RTL8365MB_INTR_LEARN_OVER_MASK 0x0004 154 #define RTL8365MB_INTR_METER_EXCEEDED_MASK 0x0002 155 #define RTL8365MB_INTR_LINK_CHANGE_MASK 0x0001 156 #define RTL8365MB_INTR_ALL_MASK \ 157 (RTL8365MB_INTR_SLIENT_START_2_MASK | \ 158 RTL8365MB_INTR_SLIENT_START_MASK | \ 159 RTL8365MB_INTR_ACL_ACTION_MASK | \ 160 RTL8365MB_INTR_CABLE_DIAG_FIN_MASK | \ 161 RTL8365MB_INTR_INTERRUPT_8051_MASK | \ 162 RTL8365MB_INTR_LOOP_DETECTION_MASK | \ 163 RTL8365MB_INTR_GREEN_TIMER_MASK | \ 164 RTL8365MB_INTR_SPECIAL_CONGEST_MASK | \ 165 RTL8365MB_INTR_SPEED_CHANGE_MASK | \ 166 RTL8365MB_INTR_LEARN_OVER_MASK | \ 167 RTL8365MB_INTR_METER_EXCEEDED_MASK | \ 168 RTL8365MB_INTR_LINK_CHANGE_MASK) 169 170 /* Per-port interrupt type status registers */ 171 #define RTL8365MB_PORT_LINKDOWN_IND_REG 0x1106 172 #define RTL8365MB_PORT_LINKDOWN_IND_MASK 0x07FF 173 174 #define RTL8365MB_PORT_LINKUP_IND_REG 0x1107 175 #define RTL8365MB_PORT_LINKUP_IND_MASK 0x07FF 176 177 /* PHY indirect access registers */ 178 #define RTL8365MB_INDIRECT_ACCESS_CTRL_REG 0x1F00 179 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK 0x0002 180 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ 0 181 #define RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE 1 182 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK 0x0001 183 #define RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE 1 184 #define RTL8365MB_INDIRECT_ACCESS_STATUS_REG 0x1F01 185 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG 0x1F02 186 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK GENMASK(4, 0) 187 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK GENMASK(7, 5) 188 #define RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK GENMASK(11, 8) 189 #define RTL8365MB_PHY_BASE 0x2000 190 #define RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG 0x1F03 191 #define RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG 0x1F04 192 193 /* PHY OCP address prefix register */ 194 #define RTL8365MB_GPHY_OCP_MSB_0_REG 0x1D15 195 #define RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK 0x0FC0 196 #define RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK 0xFC00 197 198 /* The PHY OCP addresses of PHY registers 0~31 start here */ 199 #define RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE 0xA400 200 201 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */ 202 #define RTL8365MB_EXT_PORT_MODE_DISABLE 0 203 #define RTL8365MB_EXT_PORT_MODE_RGMII 1 204 #define RTL8365MB_EXT_PORT_MODE_MII_MAC 2 205 #define RTL8365MB_EXT_PORT_MODE_MII_PHY 3 206 #define RTL8365MB_EXT_PORT_MODE_TMII_MAC 4 207 #define RTL8365MB_EXT_PORT_MODE_TMII_PHY 5 208 #define RTL8365MB_EXT_PORT_MODE_GMII 6 209 #define RTL8365MB_EXT_PORT_MODE_RMII_MAC 7 210 #define RTL8365MB_EXT_PORT_MODE_RMII_PHY 8 211 #define RTL8365MB_EXT_PORT_MODE_SGMII 9 212 #define RTL8365MB_EXT_PORT_MODE_HSGMII 10 213 #define RTL8365MB_EXT_PORT_MODE_1000X_100FX 11 214 #define RTL8365MB_EXT_PORT_MODE_1000X 12 215 #define RTL8365MB_EXT_PORT_MODE_100FX 13 216 217 /* External interface mode configuration registers 0~1 */ 218 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 0x1305 /* EXT0,EXT1 */ 219 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 0x13C3 /* EXT2 */ 220 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(_extint) \ 221 ((_extint) <= 1 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG0 : \ 222 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \ 223 0x0) 224 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \ 225 (0xF << (((_extint) % 2) * 4)) 226 #define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \ 227 (((_extint) % 2) * 4) 228 229 /* External interface RGMII TX/RX delay configuration registers 0~2 */ 230 #define RTL8365MB_EXT_RGMXF_REG0 0x1306 /* EXT0 */ 231 #define RTL8365MB_EXT_RGMXF_REG1 0x1307 /* EXT1 */ 232 #define RTL8365MB_EXT_RGMXF_REG2 0x13C5 /* EXT2 */ 233 #define RTL8365MB_EXT_RGMXF_REG(_extint) \ 234 ((_extint) == 0 ? RTL8365MB_EXT_RGMXF_REG0 : \ 235 (_extint) == 1 ? RTL8365MB_EXT_RGMXF_REG1 : \ 236 (_extint) == 2 ? RTL8365MB_EXT_RGMXF_REG2 : \ 237 0x0) 238 #define RTL8365MB_EXT_RGMXF_RXDELAY_MASK 0x0007 239 #define RTL8365MB_EXT_RGMXF_TXDELAY_MASK 0x0008 240 241 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */ 242 #define RTL8365MB_PORT_SPEED_10M 0 243 #define RTL8365MB_PORT_SPEED_100M 1 244 #define RTL8365MB_PORT_SPEED_1000M 2 245 246 /* External interface force configuration registers 0~2 */ 247 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 0x1310 /* EXT0 */ 248 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 0x1311 /* EXT1 */ 249 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 0x13C4 /* EXT2 */ 250 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(_extint) \ 251 ((_extint) == 0 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG0 : \ 252 (_extint) == 1 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG1 : \ 253 (_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_FORCE_REG2 : \ 254 0x0) 255 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK 0x1000 256 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_NWAY_MASK 0x0080 257 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK 0x0040 258 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK 0x0020 259 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK 0x0010 260 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK 0x0004 261 #define RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK 0x0003 262 263 /* CPU port mask register - controls which ports are treated as CPU ports */ 264 #define RTL8365MB_CPU_PORT_MASK_REG 0x1219 265 #define RTL8365MB_CPU_PORT_MASK_MASK 0x07FF 266 267 /* CPU control register */ 268 #define RTL8365MB_CPU_CTRL_REG 0x121A 269 #define RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK 0x0400 270 #define RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK 0x0200 271 #define RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK 0x0080 272 #define RTL8365MB_CPU_CTRL_TAG_POSITION_MASK 0x0040 273 #define RTL8365MB_CPU_CTRL_TRAP_PORT_MASK 0x0038 274 #define RTL8365MB_CPU_CTRL_INSERTMODE_MASK 0x0006 275 #define RTL8365MB_CPU_CTRL_EN_MASK 0x0001 276 277 /* Maximum packet length register */ 278 #define RTL8365MB_CFG0_MAX_LEN_REG 0x088C 279 #define RTL8365MB_CFG0_MAX_LEN_MASK 0x3FFF 280 #define RTL8365MB_CFG0_MAX_LEN_MAX 0x3FFF 281 282 /* Port learning limit registers */ 283 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE 0x0A20 284 #define RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(_physport) \ 285 (RTL8365MB_LUT_PORT_LEARN_LIMIT_BASE + (_physport)) 286 287 /* Port isolation (forwarding mask) registers */ 288 #define RTL8365MB_PORT_ISOLATION_REG_BASE 0x08A2 289 #define RTL8365MB_PORT_ISOLATION_REG(_physport) \ 290 (RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport)) 291 #define RTL8365MB_PORT_ISOLATION_MASK 0x07FF 292 293 /* Extended filter ID registers - used to key forwarding database with IVL */ 294 #define RTL8365MB_EFID_MASK GENMASK(2, 0) 295 #define RTL8365MB_PORT_EFID_REG_BASE 0x0A32 296 #define RTL8365MB_PORT_EFID_REG(_p) \ 297 (RTL8365MB_PORT_EFID_REG_BASE + ((_p) >> 2)) 298 #define RTL8365MB_PORT_EFID_OFFSET(_p) (((_p) & 0x3) << 2) 299 #define RTL8365MB_PORT_EFID_MASK(_p) \ 300 (RTL8365MB_EFID_MASK << RTL8365MB_PORT_EFID_OFFSET(_p)) 301 302 /* MSTP port state registers - indexed by tree instance */ 303 #define RTL8365MB_MSTI_CTRL_BASE 0x0A00 304 #define RTL8365MB_MSTI_CTRL_REG(_msti, _physport) \ 305 (RTL8365MB_MSTI_CTRL_BASE + ((_msti) << 1) + ((_physport) >> 3)) 306 #define RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(_physport) ((_physport) << 1) 307 #define RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(_physport) \ 308 (0x3 << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET((_physport))) 309 310 /* Unknown unicast DA flooding port mask */ 311 #define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG 0x0890 312 #define RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_MASK 0x07FF 313 314 /* Unknown multicast DA flooding port mask */ 315 #define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG 0x0891 316 #define RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_MASK 0x07FF 317 318 /* Broadcast flooding port mask */ 319 #define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG 0x0892 320 #define RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_MASK 0x07FF 321 322 #define RTL8365MB_SUPPORTED_BRIDGE_FLAGS \ 323 (BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD) 324 325 /* Miscellaneous port configuration register, incl. VLAN egress mode */ 326 #define RTL8365MB_PORT_MISC_CFG_REG_BASE 0x000E 327 #define RTL8365MB_PORT_MISC_CFG_REG(_p) \ 328 (RTL8365MB_PORT_MISC_CFG_REG_BASE + ((_p) << 5)) 329 #define RTL8365MB_PORT_MISC_CFG_SMALL_TAG_IPG_MASK 0x8000 330 #define RTL8365MB_PORT_MISC_CFG_TX_ITFSP_MODE_MASK 0x4000 331 #define RTL8365MB_PORT_MISC_CFG_FLOWCTRL_INDEP_MASK 0x2000 332 #define RTL8365MB_PORT_MISC_CFG_DOT1Q_REMARK_ENABLE_MASK 0x1000 333 #define RTL8365MB_PORT_MISC_CFG_INGRESSBW_FLOWCTRL_MASK 0x0800 334 #define RTL8365MB_PORT_MISC_CFG_INGRESSBW_IFG_MASK 0x0400 335 #define RTL8365MB_PORT_MISC_CFG_RX_SPC_MASK 0x0200 336 #define RTL8365MB_PORT_MISC_CFG_CRC_SKIP_MASK 0x0100 337 #define RTL8365MB_PORT_MISC_CFG_PKTGEN_TX_FIRST_MASK 0x0080 338 #define RTL8365MB_PORT_MISC_CFG_MAC_LOOPBACK_MASK 0x0040 339 /* See &rtl8365mb_vlan_egress_mode */ 340 #define RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK 0x0030 341 #define RTL8365MB_PORT_MISC_CFG_CONGESTION_SUSTAIN_TIME_MASK 0x000F 342 343 /** 344 * enum rtl8365mb_vlan_egress_mode - port VLAN egress mode 345 * @RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL: follow untag mask in VLAN4k table entry 346 * @RTL8365MB_VLAN_EGRESS_MODE_KEEP: the VLAN tag format of egressed packets 347 * will remain the same as their ingressed format, but the priority and VID 348 * fields may be altered 349 * @RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG: always egress with priority tag 350 * @RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP: the VLAN tag format of egressed 351 * packets will remain the same as their ingressed format, and neither the 352 * priority nor VID fields can be altered 353 */ 354 enum rtl8365mb_vlan_egress_mode { 355 RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL = 0, 356 RTL8365MB_VLAN_EGRESS_MODE_KEEP = 1, 357 RTL8365MB_VLAN_EGRESS_MODE_PRI_TAG = 2, 358 RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP = 3, 359 }; 360 361 /* VLAN control register */ 362 #define RTL8365MB_VLAN_CTRL_REG 0x07A8 363 #define RTL8365MB_VLAN_CTRL_EN_MASK 0x0001 364 365 /* VLAN ingress filter register */ 366 #define RTL8365MB_VLAN_INGRESS_REG 0x07A9 367 #define RTL8365MB_VLAN_INGRESS_MASK GENMASK(10, 0) 368 #define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_OFFSET(_p) (_p) 369 #define RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(_p) BIT(_p) 370 371 /* VLAN "transparent" setting registers */ 372 #define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE 0x09D0 373 #define RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(_p) \ 374 (RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG_BASE + (_p)) 375 376 /* MIB counter value registers */ 377 #define RTL8365MB_MIB_COUNTER_BASE 0x1000 378 #define RTL8365MB_MIB_COUNTER_REG(_x) (RTL8365MB_MIB_COUNTER_BASE + (_x)) 379 380 /* MIB counter address register */ 381 #define RTL8365MB_MIB_ADDRESS_REG 0x1004 382 #define RTL8365MB_MIB_ADDRESS_PORT_OFFSET 0x007C 383 #define RTL8365MB_MIB_ADDRESS(_p, _x) \ 384 (((RTL8365MB_MIB_ADDRESS_PORT_OFFSET) * (_p) + (_x)) >> 2) 385 386 #define RTL8365MB_MIB_CTRL0_REG 0x1005 387 #define RTL8365MB_MIB_CTRL0_RESET_MASK 0x0002 388 #define RTL8365MB_MIB_CTRL0_BUSY_MASK 0x0001 389 390 /* The DSA callback .get_stats64 runs in atomic context, so we are not allowed 391 * to block. On the other hand, accessing MIB counters absolutely requires us to 392 * block. The solution is thus to schedule work which polls the MIB counters 393 * asynchronously and updates some private data, which the callback can then 394 * fetch atomically. Three seconds should be a good enough polling interval. 395 */ 396 #define RTL8365MB_STATS_INTERVAL_JIFFIES (3 * HZ) 397 398 enum rtl8365mb_mib_counter_index { 399 RTL8365MB_MIB_ifInOctets, 400 RTL8365MB_MIB_dot3StatsFCSErrors, 401 RTL8365MB_MIB_dot3StatsSymbolErrors, 402 RTL8365MB_MIB_dot3InPauseFrames, 403 RTL8365MB_MIB_dot3ControlInUnknownOpcodes, 404 RTL8365MB_MIB_etherStatsFragments, 405 RTL8365MB_MIB_etherStatsJabbers, 406 RTL8365MB_MIB_ifInUcastPkts, 407 RTL8365MB_MIB_etherStatsDropEvents, 408 RTL8365MB_MIB_ifInMulticastPkts, 409 RTL8365MB_MIB_ifInBroadcastPkts, 410 RTL8365MB_MIB_inMldChecksumError, 411 RTL8365MB_MIB_inIgmpChecksumError, 412 RTL8365MB_MIB_inMldSpecificQuery, 413 RTL8365MB_MIB_inMldGeneralQuery, 414 RTL8365MB_MIB_inIgmpSpecificQuery, 415 RTL8365MB_MIB_inIgmpGeneralQuery, 416 RTL8365MB_MIB_inMldLeaves, 417 RTL8365MB_MIB_inIgmpLeaves, 418 RTL8365MB_MIB_etherStatsOctets, 419 RTL8365MB_MIB_etherStatsUnderSizePkts, 420 RTL8365MB_MIB_etherOversizeStats, 421 RTL8365MB_MIB_etherStatsPkts64Octets, 422 RTL8365MB_MIB_etherStatsPkts65to127Octets, 423 RTL8365MB_MIB_etherStatsPkts128to255Octets, 424 RTL8365MB_MIB_etherStatsPkts256to511Octets, 425 RTL8365MB_MIB_etherStatsPkts512to1023Octets, 426 RTL8365MB_MIB_etherStatsPkts1024to1518Octets, 427 RTL8365MB_MIB_ifOutOctets, 428 RTL8365MB_MIB_dot3StatsSingleCollisionFrames, 429 RTL8365MB_MIB_dot3StatsMultipleCollisionFrames, 430 RTL8365MB_MIB_dot3StatsDeferredTransmissions, 431 RTL8365MB_MIB_dot3StatsLateCollisions, 432 RTL8365MB_MIB_etherStatsCollisions, 433 RTL8365MB_MIB_dot3StatsExcessiveCollisions, 434 RTL8365MB_MIB_dot3OutPauseFrames, 435 RTL8365MB_MIB_ifOutDiscards, 436 RTL8365MB_MIB_dot1dTpPortInDiscards, 437 RTL8365MB_MIB_ifOutUcastPkts, 438 RTL8365MB_MIB_ifOutMulticastPkts, 439 RTL8365MB_MIB_ifOutBroadcastPkts, 440 RTL8365MB_MIB_outOampduPkts, 441 RTL8365MB_MIB_inOampduPkts, 442 RTL8365MB_MIB_inIgmpJoinsSuccess, 443 RTL8365MB_MIB_inIgmpJoinsFail, 444 RTL8365MB_MIB_inMldJoinsSuccess, 445 RTL8365MB_MIB_inMldJoinsFail, 446 RTL8365MB_MIB_inReportSuppressionDrop, 447 RTL8365MB_MIB_inLeaveSuppressionDrop, 448 RTL8365MB_MIB_outIgmpReports, 449 RTL8365MB_MIB_outIgmpLeaves, 450 RTL8365MB_MIB_outIgmpGeneralQuery, 451 RTL8365MB_MIB_outIgmpSpecificQuery, 452 RTL8365MB_MIB_outMldReports, 453 RTL8365MB_MIB_outMldLeaves, 454 RTL8365MB_MIB_outMldGeneralQuery, 455 RTL8365MB_MIB_outMldSpecificQuery, 456 RTL8365MB_MIB_inKnownMulticastPkts, 457 RTL8365MB_MIB_END, 458 }; 459 460 struct rtl8365mb_mib_counter { 461 u32 offset; 462 u32 length; 463 const char *name; 464 }; 465 466 #define RTL8365MB_MAKE_MIB_COUNTER(_offset, _length, _name) \ 467 [RTL8365MB_MIB_ ## _name] = { _offset, _length, #_name } 468 469 static struct rtl8365mb_mib_counter rtl8365mb_mib_counters[] = { 470 RTL8365MB_MAKE_MIB_COUNTER(0, 4, ifInOctets), 471 RTL8365MB_MAKE_MIB_COUNTER(4, 2, dot3StatsFCSErrors), 472 RTL8365MB_MAKE_MIB_COUNTER(6, 2, dot3StatsSymbolErrors), 473 RTL8365MB_MAKE_MIB_COUNTER(8, 2, dot3InPauseFrames), 474 RTL8365MB_MAKE_MIB_COUNTER(10, 2, dot3ControlInUnknownOpcodes), 475 RTL8365MB_MAKE_MIB_COUNTER(12, 2, etherStatsFragments), 476 RTL8365MB_MAKE_MIB_COUNTER(14, 2, etherStatsJabbers), 477 RTL8365MB_MAKE_MIB_COUNTER(16, 2, ifInUcastPkts), 478 RTL8365MB_MAKE_MIB_COUNTER(18, 2, etherStatsDropEvents), 479 RTL8365MB_MAKE_MIB_COUNTER(20, 2, ifInMulticastPkts), 480 RTL8365MB_MAKE_MIB_COUNTER(22, 2, ifInBroadcastPkts), 481 RTL8365MB_MAKE_MIB_COUNTER(24, 2, inMldChecksumError), 482 RTL8365MB_MAKE_MIB_COUNTER(26, 2, inIgmpChecksumError), 483 RTL8365MB_MAKE_MIB_COUNTER(28, 2, inMldSpecificQuery), 484 RTL8365MB_MAKE_MIB_COUNTER(30, 2, inMldGeneralQuery), 485 RTL8365MB_MAKE_MIB_COUNTER(32, 2, inIgmpSpecificQuery), 486 RTL8365MB_MAKE_MIB_COUNTER(34, 2, inIgmpGeneralQuery), 487 RTL8365MB_MAKE_MIB_COUNTER(36, 2, inMldLeaves), 488 RTL8365MB_MAKE_MIB_COUNTER(38, 2, inIgmpLeaves), 489 RTL8365MB_MAKE_MIB_COUNTER(40, 4, etherStatsOctets), 490 RTL8365MB_MAKE_MIB_COUNTER(44, 2, etherStatsUnderSizePkts), 491 RTL8365MB_MAKE_MIB_COUNTER(46, 2, etherOversizeStats), 492 RTL8365MB_MAKE_MIB_COUNTER(48, 2, etherStatsPkts64Octets), 493 RTL8365MB_MAKE_MIB_COUNTER(50, 2, etherStatsPkts65to127Octets), 494 RTL8365MB_MAKE_MIB_COUNTER(52, 2, etherStatsPkts128to255Octets), 495 RTL8365MB_MAKE_MIB_COUNTER(54, 2, etherStatsPkts256to511Octets), 496 RTL8365MB_MAKE_MIB_COUNTER(56, 2, etherStatsPkts512to1023Octets), 497 RTL8365MB_MAKE_MIB_COUNTER(58, 2, etherStatsPkts1024to1518Octets), 498 RTL8365MB_MAKE_MIB_COUNTER(60, 4, ifOutOctets), 499 RTL8365MB_MAKE_MIB_COUNTER(64, 2, dot3StatsSingleCollisionFrames), 500 RTL8365MB_MAKE_MIB_COUNTER(66, 2, dot3StatsMultipleCollisionFrames), 501 RTL8365MB_MAKE_MIB_COUNTER(68, 2, dot3StatsDeferredTransmissions), 502 RTL8365MB_MAKE_MIB_COUNTER(70, 2, dot3StatsLateCollisions), 503 RTL8365MB_MAKE_MIB_COUNTER(72, 2, etherStatsCollisions), 504 RTL8365MB_MAKE_MIB_COUNTER(74, 2, dot3StatsExcessiveCollisions), 505 RTL8365MB_MAKE_MIB_COUNTER(76, 2, dot3OutPauseFrames), 506 RTL8365MB_MAKE_MIB_COUNTER(78, 2, ifOutDiscards), 507 RTL8365MB_MAKE_MIB_COUNTER(80, 2, dot1dTpPortInDiscards), 508 RTL8365MB_MAKE_MIB_COUNTER(82, 2, ifOutUcastPkts), 509 RTL8365MB_MAKE_MIB_COUNTER(84, 2, ifOutMulticastPkts), 510 RTL8365MB_MAKE_MIB_COUNTER(86, 2, ifOutBroadcastPkts), 511 RTL8365MB_MAKE_MIB_COUNTER(88, 2, outOampduPkts), 512 RTL8365MB_MAKE_MIB_COUNTER(90, 2, inOampduPkts), 513 RTL8365MB_MAKE_MIB_COUNTER(92, 4, inIgmpJoinsSuccess), 514 RTL8365MB_MAKE_MIB_COUNTER(96, 2, inIgmpJoinsFail), 515 RTL8365MB_MAKE_MIB_COUNTER(98, 2, inMldJoinsSuccess), 516 RTL8365MB_MAKE_MIB_COUNTER(100, 2, inMldJoinsFail), 517 RTL8365MB_MAKE_MIB_COUNTER(102, 2, inReportSuppressionDrop), 518 RTL8365MB_MAKE_MIB_COUNTER(104, 2, inLeaveSuppressionDrop), 519 RTL8365MB_MAKE_MIB_COUNTER(106, 2, outIgmpReports), 520 RTL8365MB_MAKE_MIB_COUNTER(108, 2, outIgmpLeaves), 521 RTL8365MB_MAKE_MIB_COUNTER(110, 2, outIgmpGeneralQuery), 522 RTL8365MB_MAKE_MIB_COUNTER(112, 2, outIgmpSpecificQuery), 523 RTL8365MB_MAKE_MIB_COUNTER(114, 2, outMldReports), 524 RTL8365MB_MAKE_MIB_COUNTER(116, 2, outMldLeaves), 525 RTL8365MB_MAKE_MIB_COUNTER(118, 2, outMldGeneralQuery), 526 RTL8365MB_MAKE_MIB_COUNTER(120, 2, outMldSpecificQuery), 527 RTL8365MB_MAKE_MIB_COUNTER(122, 2, inKnownMulticastPkts), 528 }; 529 530 static_assert(ARRAY_SIZE(rtl8365mb_mib_counters) == RTL8365MB_MIB_END); 531 532 struct rtl8365mb_jam_tbl_entry { 533 u16 reg; 534 u16 val; 535 }; 536 537 /* Lifted from the vendor driver sources */ 538 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_8365mb_vc[] = { 539 { 0x13EB, 0x15BB }, { 0x1303, 0x06D6 }, { 0x1304, 0x0700 }, 540 { 0x13E2, 0x003F }, { 0x13F9, 0x0090 }, { 0x121E, 0x03CA }, 541 { 0x1233, 0x0352 }, { 0x1237, 0x00A0 }, { 0x123A, 0x0030 }, 542 { 0x1239, 0x0084 }, { 0x0301, 0x1000 }, { 0x1349, 0x001F }, 543 { 0x18E0, 0x4004 }, { 0x122B, 0x241C }, { 0x1305, 0xC000 }, 544 { 0x13F0, 0x0000 }, 545 }; 546 547 static const struct rtl8365mb_jam_tbl_entry rtl8365mb_init_jam_common[] = { 548 { 0x1200, 0x7FCB }, { 0x0884, 0x0003 }, { 0x06EB, 0x0001 }, 549 { 0x03Fa, 0x0007 }, { 0x08C8, 0x00C0 }, { 0x0A30, 0x020E }, 550 { 0x0800, 0x0000 }, { 0x0802, 0x0000 }, { 0x09DA, 0x0013 }, 551 { 0x1D32, 0x0002 }, 552 }; 553 554 enum rtl8365mb_phy_interface_mode { 555 RTL8365MB_PHY_INTERFACE_MODE_INVAL = 0, 556 RTL8365MB_PHY_INTERFACE_MODE_INTERNAL = BIT(0), 557 RTL8365MB_PHY_INTERFACE_MODE_MII = BIT(1), 558 RTL8365MB_PHY_INTERFACE_MODE_TMII = BIT(2), 559 RTL8365MB_PHY_INTERFACE_MODE_RMII = BIT(3), 560 RTL8365MB_PHY_INTERFACE_MODE_RGMII = BIT(4), 561 RTL8365MB_PHY_INTERFACE_MODE_SGMII = BIT(5), 562 RTL8365MB_PHY_INTERFACE_MODE_HSGMII = BIT(6), 563 }; 564 565 /** 566 * struct rtl8365mb_extint - external interface info 567 * @port: the port with an external interface 568 * @id: the external interface ID, which is either 0, 1, or 2 569 * @supported_interfaces: a bitmask of supported PHY interface modes 570 * 571 * Represents a mapping: port -> { id, supported_interfaces }. To be embedded 572 * in &struct rtl8365mb_chip_info for every port with an external interface. 573 */ 574 struct rtl8365mb_extint { 575 int port; 576 int id; 577 unsigned int supported_interfaces; 578 }; 579 580 /** 581 * struct rtl8365mb_chip_info - static chip-specific info 582 * @name: human-readable chip name 583 * @chip_id: chip identifier 584 * @chip_ver: chip silicon revision 585 * @extints: available external interfaces 586 * @jam_table: chip-specific initialization jam table 587 * @jam_size: size of the chip's jam table 588 * 589 * These data are specific to a given chip in the family of switches supported 590 * by this driver. When adding support for another chip in the family, a new 591 * chip info should be added to the rtl8365mb_chip_infos array. 592 */ 593 struct rtl8365mb_chip_info { 594 const char *name; 595 u32 chip_id; 596 u32 chip_ver; 597 const struct rtl8365mb_extint extints[RTL8365MB_MAX_NUM_EXTINTS]; 598 const struct rtl8365mb_jam_tbl_entry *jam_table; 599 size_t jam_size; 600 }; 601 602 /* Chip info for each supported switch in the family */ 603 #define PHY_INTF(_mode) (RTL8365MB_PHY_INTERFACE_MODE_ ## _mode) 604 static const struct rtl8365mb_chip_info rtl8365mb_chip_infos[] = { 605 { 606 .name = "RTL8365MB-VC", 607 .chip_id = 0x6367, 608 .chip_ver = 0x0040, 609 .extints = { 610 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 611 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 612 }, 613 .jam_table = rtl8365mb_init_jam_8365mb_vc, 614 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 615 }, 616 { 617 .name = "RTL8367S", 618 .chip_id = 0x6367, 619 .chip_ver = 0x00A0, 620 .extints = { 621 { 6, 1, PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, 622 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 623 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 624 }, 625 .jam_table = rtl8365mb_init_jam_8365mb_vc, 626 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 627 }, 628 { 629 .name = "RTL8367SB", 630 .chip_id = 0x6367, 631 .chip_ver = 0x0010, 632 .extints = { 633 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 634 PHY_INTF(RMII) | PHY_INTF(RGMII) | 635 PHY_INTF(SGMII) | PHY_INTF(HSGMII) }, 636 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 637 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 638 }, 639 .jam_table = rtl8365mb_init_jam_8365mb_vc, 640 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 641 }, 642 { 643 .name = "RTL8367RB-VB", 644 .chip_id = 0x6367, 645 .chip_ver = 0x0020, 646 .extints = { 647 { 6, 1, PHY_INTF(MII) | PHY_INTF(TMII) | 648 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 649 { 7, 2, PHY_INTF(MII) | PHY_INTF(TMII) | 650 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 651 }, 652 .jam_table = rtl8365mb_init_jam_8365mb_vc, 653 .jam_size = ARRAY_SIZE(rtl8365mb_init_jam_8365mb_vc), 654 }, 655 }; 656 657 enum rtl8365mb_stp_state { 658 RTL8365MB_STP_STATE_DISABLED = 0, 659 RTL8365MB_STP_STATE_BLOCKING = 1, 660 RTL8365MB_STP_STATE_LEARNING = 2, 661 RTL8365MB_STP_STATE_FORWARDING = 3, 662 }; 663 664 enum rtl8365mb_cpu_insert { 665 RTL8365MB_CPU_INSERT_TO_ALL = 0, 666 RTL8365MB_CPU_INSERT_TO_TRAPPING = 1, 667 RTL8365MB_CPU_INSERT_TO_NONE = 2, 668 }; 669 670 enum rtl8365mb_cpu_position { 671 RTL8365MB_CPU_POS_AFTER_SA = 0, 672 RTL8365MB_CPU_POS_BEFORE_CRC = 1, 673 }; 674 675 enum rtl8365mb_cpu_format { 676 RTL8365MB_CPU_FORMAT_8BYTES = 0, 677 RTL8365MB_CPU_FORMAT_4BYTES = 1, 678 }; 679 680 enum rtl8365mb_cpu_rxlen { 681 RTL8365MB_CPU_RXLEN_72BYTES = 0, 682 RTL8365MB_CPU_RXLEN_64BYTES = 1, 683 }; 684 685 /** 686 * struct rtl8365mb_cpu - CPU port configuration 687 * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames 688 * @mask: port mask of ports that parse should parse CPU tags 689 * @trap_port: forward trapped frames to this port 690 * @insert: CPU tag insertion mode in switch->CPU frames 691 * @position: position of CPU tag in frame 692 * @rx_length: minimum CPU RX length 693 * @format: CPU tag format 694 * 695 * Represents the CPU tagging and CPU port configuration of the switch. These 696 * settings are configurable at runtime. 697 */ 698 struct rtl8365mb_cpu { 699 bool enable; 700 u32 mask; 701 u32 trap_port; 702 enum rtl8365mb_cpu_insert insert; 703 enum rtl8365mb_cpu_position position; 704 enum rtl8365mb_cpu_rxlen rx_length; 705 enum rtl8365mb_cpu_format format; 706 }; 707 708 /** 709 * struct rtl8365mb_port - private per-port data 710 * @priv: pointer to parent realtek_priv data 711 * @index: DSA port index, same as dsa_port::index 712 * @stats: link statistics populated by rtl8365mb_stats_poll, ready for atomic 713 * access via rtl8365mb_get_stats64 714 * @stats_lock: protect the stats structure during read/update 715 * @mib_work: delayed work for polling MIB counters 716 */ 717 struct rtl8365mb_port { 718 struct realtek_priv *priv; 719 unsigned int index; 720 struct rtnl_link_stats64 stats; 721 spinlock_t stats_lock; 722 struct delayed_work mib_work; 723 }; 724 725 /** 726 * struct rtl8365mb - driver private data 727 * @priv: pointer to parent realtek_priv data 728 * @irq: registered IRQ or zero 729 * @chip_info: chip-specific info about the attached switch 730 * @cpu: CPU tagging and CPU port configuration for this chip 731 * @mib_lock: prevent concurrent reads of MIB counters 732 * @ports: per-port data 733 * 734 * Private data for this driver. 735 */ 736 struct rtl8365mb { 737 struct realtek_priv *priv; 738 int irq; 739 const struct rtl8365mb_chip_info *chip_info; 740 struct rtl8365mb_cpu cpu; 741 struct mutex mib_lock; 742 struct rtl8365mb_port ports[RTL8365MB_MAX_NUM_PORTS]; 743 }; 744 745 static int rtl8365mb_phy_poll_busy(struct realtek_priv *priv) 746 { 747 u32 val; 748 749 return regmap_read_poll_timeout(priv->map_nolock, 750 RTL8365MB_INDIRECT_ACCESS_STATUS_REG, 751 val, !val, 10, 100); 752 } 753 754 static int rtl8365mb_phy_ocp_prepare(struct realtek_priv *priv, int phy, 755 u32 ocp_addr) 756 { 757 u32 val; 758 int ret; 759 760 /* Set OCP prefix */ 761 val = FIELD_GET(RTL8365MB_PHY_OCP_ADDR_PREFIX_MASK, ocp_addr); 762 ret = regmap_update_bits( 763 priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG, 764 RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, 765 FIELD_PREP(RTL8365MB_GPHY_OCP_MSB_0_CFG_CPU_OCPADR_MASK, val)); 766 if (ret) 767 return ret; 768 769 /* Set PHY register address */ 770 val = RTL8365MB_PHY_BASE; 771 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_PHYNUM_MASK, phy); 772 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_5_1_MASK, 773 ocp_addr >> 1); 774 val |= FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_ADDRESS_OCPADR_9_6_MASK, 775 ocp_addr >> 6); 776 ret = regmap_write(priv->map_nolock, 777 RTL8365MB_INDIRECT_ACCESS_ADDRESS_REG, val); 778 if (ret) 779 return ret; 780 781 return 0; 782 } 783 784 static int rtl8365mb_phy_ocp_read(struct realtek_priv *priv, int phy, 785 u32 ocp_addr, u16 *data) 786 { 787 u32 val; 788 int ret; 789 790 rtl83xx_lock(priv); 791 792 ret = rtl8365mb_phy_poll_busy(priv); 793 if (ret) 794 goto out; 795 796 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 797 if (ret) 798 goto out; 799 800 /* Execute read operation */ 801 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 802 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 803 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 804 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_READ); 805 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 806 val); 807 if (ret) 808 goto out; 809 810 ret = rtl8365mb_phy_poll_busy(priv); 811 if (ret) 812 goto out; 813 814 /* Get PHY register data */ 815 ret = regmap_read(priv->map_nolock, 816 RTL8365MB_INDIRECT_ACCESS_READ_DATA_REG, &val); 817 if (ret) 818 goto out; 819 820 *data = val & 0xFFFF; 821 822 out: 823 rtl83xx_unlock(priv); 824 825 return ret; 826 } 827 828 static int rtl8365mb_phy_ocp_write(struct realtek_priv *priv, int phy, 829 u32 ocp_addr, u16 data) 830 { 831 u32 val; 832 int ret; 833 834 rtl83xx_lock(priv); 835 836 ret = rtl8365mb_phy_poll_busy(priv); 837 if (ret) 838 goto out; 839 840 ret = rtl8365mb_phy_ocp_prepare(priv, phy, ocp_addr); 841 if (ret) 842 goto out; 843 844 /* Set PHY register data */ 845 ret = regmap_write(priv->map_nolock, 846 RTL8365MB_INDIRECT_ACCESS_WRITE_DATA_REG, data); 847 if (ret) 848 goto out; 849 850 /* Execute write operation */ 851 val = FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_MASK, 852 RTL8365MB_INDIRECT_ACCESS_CTRL_CMD_VALUE) | 853 FIELD_PREP(RTL8365MB_INDIRECT_ACCESS_CTRL_RW_MASK, 854 RTL8365MB_INDIRECT_ACCESS_CTRL_RW_WRITE); 855 ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG, 856 val); 857 if (ret) 858 goto out; 859 860 ret = rtl8365mb_phy_poll_busy(priv); 861 if (ret) 862 goto out; 863 864 out: 865 rtl83xx_unlock(priv); 866 867 return ret; 868 } 869 870 static int rtl8365mb_phy_read(struct realtek_priv *priv, int phy, int regnum) 871 { 872 u32 ocp_addr; 873 u16 val; 874 int ret; 875 876 if (phy > RTL8365MB_PHYADDRMAX) 877 return -EINVAL; 878 879 if (regnum > RTL8365MB_PHYREGMAX) 880 return -EINVAL; 881 882 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 883 884 ret = rtl8365mb_phy_ocp_read(priv, phy, ocp_addr, &val); 885 if (ret) { 886 dev_err(priv->dev, 887 "failed to read PHY%d reg %02x @ %04x, ret %pe\n", phy, 888 regnum, ocp_addr, ERR_PTR(ret)); 889 return ret; 890 } 891 892 dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n", 893 phy, regnum, ocp_addr, val); 894 895 return val; 896 } 897 898 static int rtl8365mb_phy_write(struct realtek_priv *priv, int phy, int regnum, 899 u16 val) 900 { 901 u32 ocp_addr; 902 int ret; 903 904 if (phy > RTL8365MB_PHYADDRMAX) 905 return -EINVAL; 906 907 if (regnum > RTL8365MB_PHYREGMAX) 908 return -EINVAL; 909 910 ocp_addr = RTL8365MB_PHY_OCP_ADDR_PHYREG_BASE + regnum * 2; 911 912 ret = rtl8365mb_phy_ocp_write(priv, phy, ocp_addr, val); 913 if (ret) { 914 dev_err(priv->dev, 915 "failed to write PHY%d reg %02x @ %04x, ret %pe\n", phy, 916 regnum, ocp_addr, ERR_PTR(ret)); 917 return ret; 918 } 919 920 dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n", 921 phy, regnum, ocp_addr, val); 922 923 return 0; 924 } 925 926 static const struct rtl8365mb_extint * 927 rtl8365mb_get_port_extint(struct realtek_priv *priv, int port) 928 { 929 struct rtl8365mb *mb = priv->chip_data; 930 int i; 931 932 for (i = 0; i < RTL8365MB_MAX_NUM_EXTINTS; i++) { 933 const struct rtl8365mb_extint *extint = 934 &mb->chip_info->extints[i]; 935 936 if (!extint->supported_interfaces) 937 continue; 938 939 if (extint->port == port) 940 return extint; 941 } 942 943 return NULL; 944 } 945 946 static enum dsa_tag_protocol 947 rtl8365mb_get_tag_protocol(struct dsa_switch *ds, int port, 948 enum dsa_tag_protocol mp) 949 { 950 struct realtek_priv *priv = ds->priv; 951 struct rtl8365mb_cpu *cpu; 952 struct rtl8365mb *mb; 953 954 mb = priv->chip_data; 955 cpu = &mb->cpu; 956 957 if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC) 958 return DSA_TAG_PROTO_RTL8_4T; 959 960 return DSA_TAG_PROTO_RTL8_4; 961 } 962 963 static int rtl8365mb_ext_config_rgmii(struct realtek_priv *priv, int port, 964 phy_interface_t interface) 965 { 966 const struct rtl8365mb_extint *extint = 967 rtl8365mb_get_port_extint(priv, port); 968 struct dsa_switch *ds = &priv->ds; 969 struct device_node *dn; 970 struct dsa_port *dp; 971 int tx_delay = 0; 972 int rx_delay = 0; 973 u32 val; 974 int ret; 975 976 if (!extint) 977 return -ENODEV; 978 979 dp = dsa_to_port(ds, port); 980 dn = dp->dn; 981 982 /* Set the RGMII TX/RX delay 983 * 984 * The Realtek vendor driver indicates the following possible 985 * configuration settings: 986 * 987 * TX delay: 988 * 0 = no delay, 1 = 2 ns delay 989 * RX delay: 990 * 0 = no delay, 7 = maximum delay 991 * Each step is approximately 0.3 ns, so the maximum delay is about 992 * 2.1 ns. 993 * 994 * The vendor driver also states that this must be configured *before* 995 * forcing the external interface into a particular mode, which is done 996 * in the rtl8365mb_phylink_mac_link_{up,down} functions. 997 * 998 * Only configure an RGMII TX (resp. RX) delay if the 999 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is 1000 * specified. We ignore the detail of the RGMII interface mode 1001 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only 1002 * property. 1003 */ 1004 if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) { 1005 val = val / 1000; /* convert to ns */ 1006 1007 if (val == 0 || val == 2) 1008 tx_delay = val / 2; 1009 else 1010 dev_warn(priv->dev, 1011 "RGMII TX delay must be 0 or 2 ns\n"); 1012 } 1013 1014 if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) { 1015 val = DIV_ROUND_CLOSEST(val, 300); /* convert to 0.3 ns step */ 1016 1017 if (val <= 7) 1018 rx_delay = val; 1019 else 1020 dev_warn(priv->dev, 1021 "RGMII RX delay must be 0 to 2.1 ns\n"); 1022 } 1023 1024 ret = regmap_update_bits( 1025 priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id), 1026 RTL8365MB_EXT_RGMXF_TXDELAY_MASK | 1027 RTL8365MB_EXT_RGMXF_RXDELAY_MASK, 1028 FIELD_PREP(RTL8365MB_EXT_RGMXF_TXDELAY_MASK, tx_delay) | 1029 FIELD_PREP(RTL8365MB_EXT_RGMXF_RXDELAY_MASK, rx_delay)); 1030 if (ret) 1031 return ret; 1032 1033 ret = regmap_update_bits( 1034 priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id), 1035 RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id), 1036 RTL8365MB_EXT_PORT_MODE_RGMII 1037 << RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET( 1038 extint->id)); 1039 if (ret) 1040 return ret; 1041 1042 return 0; 1043 } 1044 1045 static int rtl8365mb_ext_config_forcemode(struct realtek_priv *priv, int port, 1046 bool link, int speed, int duplex, 1047 bool tx_pause, bool rx_pause) 1048 { 1049 const struct rtl8365mb_extint *extint = 1050 rtl8365mb_get_port_extint(priv, port); 1051 u32 r_tx_pause; 1052 u32 r_rx_pause; 1053 u32 r_duplex; 1054 u32 r_speed; 1055 u32 r_link; 1056 int val; 1057 int ret; 1058 1059 if (!extint) 1060 return -ENODEV; 1061 1062 if (link) { 1063 /* Force the link up with the desired configuration */ 1064 r_link = 1; 1065 r_rx_pause = rx_pause ? 1 : 0; 1066 r_tx_pause = tx_pause ? 1 : 0; 1067 1068 if (speed == SPEED_1000) { 1069 r_speed = RTL8365MB_PORT_SPEED_1000M; 1070 } else if (speed == SPEED_100) { 1071 r_speed = RTL8365MB_PORT_SPEED_100M; 1072 } else if (speed == SPEED_10) { 1073 r_speed = RTL8365MB_PORT_SPEED_10M; 1074 } else { 1075 dev_err(priv->dev, "unsupported port speed %s\n", 1076 phy_speed_to_str(speed)); 1077 return -EINVAL; 1078 } 1079 1080 if (duplex == DUPLEX_FULL) { 1081 r_duplex = 1; 1082 } else if (duplex == DUPLEX_HALF) { 1083 r_duplex = 0; 1084 } else { 1085 dev_err(priv->dev, "unsupported duplex %s\n", 1086 phy_duplex_to_str(duplex)); 1087 return -EINVAL; 1088 } 1089 } else { 1090 /* Force the link down and reset any programmed configuration */ 1091 r_link = 0; 1092 r_tx_pause = 0; 1093 r_rx_pause = 0; 1094 r_speed = 0; 1095 r_duplex = 0; 1096 } 1097 1098 val = FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_EN_MASK, 1) | 1099 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_TXPAUSE_MASK, 1100 r_tx_pause) | 1101 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_RXPAUSE_MASK, 1102 r_rx_pause) | 1103 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_LINK_MASK, r_link) | 1104 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_DUPLEX_MASK, 1105 r_duplex) | 1106 FIELD_PREP(RTL8365MB_DIGITAL_INTERFACE_FORCE_SPEED_MASK, r_speed); 1107 ret = regmap_write(priv->map, 1108 RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id), 1109 val); 1110 if (ret) 1111 return ret; 1112 1113 return 0; 1114 } 1115 1116 static void rtl8365mb_phylink_get_caps(struct dsa_switch *ds, int port, 1117 struct phylink_config *config) 1118 { 1119 const struct rtl8365mb_extint *extint = 1120 rtl8365mb_get_port_extint(ds->priv, port); 1121 1122 config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | 1123 MAC_10 | MAC_100 | MAC_1000FD; 1124 1125 if (!extint) { 1126 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1127 config->supported_interfaces); 1128 1129 /* GMII is the default interface mode for phylib, so 1130 * we have to support it for ports with integrated PHY. 1131 */ 1132 __set_bit(PHY_INTERFACE_MODE_GMII, 1133 config->supported_interfaces); 1134 return; 1135 } 1136 1137 /* Populate according to the modes supported by _this driver_, 1138 * not necessarily the modes supported by the hardware, some of 1139 * which remain unimplemented. 1140 */ 1141 1142 if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII) 1143 phy_interface_set_rgmii(config->supported_interfaces); 1144 } 1145 1146 static void rtl8365mb_phylink_mac_config(struct phylink_config *config, 1147 unsigned int mode, 1148 const struct phylink_link_state *state) 1149 { 1150 struct dsa_port *dp = dsa_phylink_to_port(config); 1151 struct realtek_priv *priv = dp->ds->priv; 1152 u8 port = dp->index; 1153 int ret; 1154 1155 if (mode != MLO_AN_PHY && mode != MLO_AN_FIXED) { 1156 dev_err(priv->dev, 1157 "port %d supports only conventional PHY or fixed-link\n", 1158 port); 1159 return; 1160 } 1161 1162 if (phy_interface_mode_is_rgmii(state->interface)) { 1163 ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface); 1164 if (ret) 1165 dev_err(priv->dev, 1166 "failed to configure RGMII mode on port %d: %pe\n", 1167 port, ERR_PTR(ret)); 1168 return; 1169 } 1170 1171 /* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also 1172 * supports 1173 */ 1174 } 1175 1176 static void rtl8365mb_phylink_mac_link_down(struct phylink_config *config, 1177 unsigned int mode, 1178 phy_interface_t interface) 1179 { 1180 struct dsa_port *dp = dsa_phylink_to_port(config); 1181 struct realtek_priv *priv = dp->ds->priv; 1182 struct rtl8365mb_port *p; 1183 struct rtl8365mb *mb; 1184 u8 port = dp->index; 1185 int ret; 1186 1187 mb = priv->chip_data; 1188 p = &mb->ports[port]; 1189 cancel_delayed_work_sync(&p->mib_work); 1190 1191 if (phy_interface_mode_is_rgmii(interface)) { 1192 ret = rtl8365mb_ext_config_forcemode(priv, port, false, 0, 0, 1193 false, false); 1194 if (ret) 1195 dev_err(priv->dev, 1196 "failed to reset forced mode on port %d: %pe\n", 1197 port, ERR_PTR(ret)); 1198 1199 return; 1200 } 1201 } 1202 1203 static void rtl8365mb_phylink_mac_link_up(struct phylink_config *config, 1204 struct phy_device *phydev, 1205 unsigned int mode, 1206 phy_interface_t interface, 1207 int speed, int duplex, bool tx_pause, 1208 bool rx_pause) 1209 { 1210 struct dsa_port *dp = dsa_phylink_to_port(config); 1211 struct realtek_priv *priv = dp->ds->priv; 1212 struct rtl8365mb_port *p; 1213 struct rtl8365mb *mb; 1214 u8 port = dp->index; 1215 int ret; 1216 1217 mb = priv->chip_data; 1218 p = &mb->ports[port]; 1219 schedule_delayed_work(&p->mib_work, 0); 1220 1221 if (phy_interface_mode_is_rgmii(interface)) { 1222 ret = rtl8365mb_ext_config_forcemode(priv, port, true, speed, 1223 duplex, tx_pause, 1224 rx_pause); 1225 if (ret) 1226 dev_err(priv->dev, 1227 "failed to force mode on port %d: %pe\n", port, 1228 ERR_PTR(ret)); 1229 1230 return; 1231 } 1232 } 1233 1234 static int rtl8365mb_port_change_mtu(struct dsa_switch *ds, int port, 1235 int new_mtu) 1236 { 1237 struct realtek_priv *priv = ds->priv; 1238 int frame_size; 1239 1240 /* When a new MTU is set, DSA always sets the CPU port's MTU to the 1241 * largest MTU of the user ports. Because the switch only has a global 1242 * RX length register, only allowing CPU port here is enough. 1243 */ 1244 if (!dsa_is_cpu_port(ds, port)) 1245 return 0; 1246 1247 frame_size = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; 1248 1249 dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n", 1250 new_mtu, frame_size); 1251 1252 return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG, 1253 RTL8365MB_CFG0_MAX_LEN_MASK, 1254 FIELD_PREP(RTL8365MB_CFG0_MAX_LEN_MASK, 1255 frame_size)); 1256 } 1257 1258 static int rtl8365mb_port_max_mtu(struct dsa_switch *ds, int port) 1259 { 1260 return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN; 1261 } 1262 1263 static void rtl8365mb_port_stp_state_set(struct dsa_switch *ds, int port, 1264 u8 state) 1265 { 1266 struct realtek_priv *priv = ds->priv; 1267 enum rtl8365mb_stp_state val; 1268 int msti = 0; 1269 1270 switch (state) { 1271 case BR_STATE_DISABLED: 1272 val = RTL8365MB_STP_STATE_DISABLED; 1273 break; 1274 case BR_STATE_BLOCKING: 1275 case BR_STATE_LISTENING: 1276 val = RTL8365MB_STP_STATE_BLOCKING; 1277 break; 1278 case BR_STATE_LEARNING: 1279 val = RTL8365MB_STP_STATE_LEARNING; 1280 break; 1281 case BR_STATE_FORWARDING: 1282 val = RTL8365MB_STP_STATE_FORWARDING; 1283 break; 1284 default: 1285 dev_err(priv->dev, "invalid STP state: %u\n", state); 1286 return; 1287 } 1288 1289 regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port), 1290 RTL8365MB_MSTI_CTRL_PORT_STATE_MASK(port), 1291 val << RTL8365MB_MSTI_CTRL_PORT_STATE_OFFSET(port)); 1292 } 1293 1294 static int rtl8365mb_port_set_transparent(struct realtek_priv *priv, 1295 int igr_port, int egr_port, 1296 bool enable) 1297 { 1298 dev_dbg(priv->dev, "%s transparent VLAN from %d to %d\n", 1299 enable ? "Enable" : "Disable", igr_port, egr_port); 1300 1301 /* "Transparent" between the two ports means that packets forwarded by 1302 * igr_port and egressed on egr_port will not be filtered by the usual 1303 * VLAN membership settings. 1304 */ 1305 return regmap_update_bits(priv->map, 1306 RTL8365MB_VLAN_EGRESS_TRANSPARENT_REG(egr_port), 1307 BIT(igr_port), enable ? BIT(igr_port) : 0); 1308 } 1309 1310 static int rtl8365mb_port_set_ingress_filtering(struct realtek_priv *priv, 1311 int port, bool enable) 1312 { 1313 /* Ingress filtering enabled: Discard VLAN-tagged frames if the port is 1314 * not a member of the VLAN with which the packet is associated. 1315 * Untagged packets will also be discarded unless the port has a PVID 1316 * programmed. Priority-tagged frames are treated as untagged frames. 1317 * 1318 * Ingress filtering disabled: Accept all tagged and untagged frames. 1319 */ 1320 return regmap_update_bits(priv->map, RTL8365MB_VLAN_INGRESS_REG, 1321 RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port), 1322 enable ? 1323 RTL8365MB_VLAN_INGRESS_FILTER_PORT_EN_MASK(port) : 1324 0); 1325 } 1326 1327 static int 1328 rtl8365mb_port_set_vlan_egress_mode(struct realtek_priv *priv, int port, 1329 enum rtl8365mb_vlan_egress_mode mode) 1330 { 1331 u32 val; 1332 1333 val = FIELD_PREP(RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, mode); 1334 return regmap_update_bits(priv->map, 1335 RTL8365MB_PORT_MISC_CFG_REG(port), 1336 RTL8365MB_PORT_MISC_CFG_VLAN_EGRESS_MODE_MASK, val); 1337 } 1338 1339 static int rtl8365mb_port_vlan_filtering(struct dsa_switch *ds, int port, 1340 bool vlan_filtering, 1341 struct netlink_ext_ack *extack) 1342 { 1343 enum rtl8365mb_frame_ingress accepted_frame, prev_accepted_frame; 1344 enum rtl8365mb_vlan_egress_mode mode; 1345 struct realtek_priv *priv = ds->priv; 1346 u32 configured_ports = 0; 1347 struct dsa_port *dp; 1348 u16 pvid_vid; 1349 int ret; 1350 1351 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, 1352 vlan_filtering ? "enable" : "disable"); 1353 1354 ret = rtl8365mb_vlan_port_get_framefilter(priv, port, 1355 &prev_accepted_frame); 1356 if (ret) { 1357 NL_SET_ERR_MSG_MOD(extack, 1358 "Failed to get current framefilter"); 1359 return ret; 1360 } 1361 1362 /* While filtering, only accepts untagged frames if PVID is enabled */ 1363 if (vlan_filtering) { 1364 ret = rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); 1365 if (ret) 1366 return ret; 1367 1368 if (pvid_vid) 1369 accepted_frame = RTL8365MB_FRAME_TYPE_ANY_FRAME; 1370 else 1371 accepted_frame = RTL8365MB_FRAME_TYPE_TAGGED_ONLY; 1372 } else { 1373 accepted_frame = RTL8365MB_FRAME_TYPE_ANY_FRAME; 1374 } 1375 1376 /* When vlan filter is enable/disabled in a bridge, this function is 1377 * called for all member ports. We need to enable/disable ingress 1378 * VLAN membership check. 1379 */ 1380 ret = rtl8365mb_port_set_ingress_filtering(priv, port, vlan_filtering); 1381 if (ret) 1382 return ret; 1383 1384 /* However, we also enable/disable egress filtering because the switch 1385 * still consider the egress interface VLAN membership to forward the 1386 * traffic. We enable/disable that check disabling/enabling transparent 1387 * VLAN between the ingress port and all other available ports. 1388 */ 1389 dsa_switch_for_each_available_port(dp, ds) { 1390 /* port isolation will still keep traffic inside the bridge */ 1391 ret = rtl8365mb_port_set_transparent(priv, port, dp->index, 1392 !vlan_filtering); 1393 if (ret) 1394 goto undo_transparent; 1395 1396 configured_ports |= BIT(dp->index); 1397 } 1398 1399 if (accepted_frame != prev_accepted_frame) { 1400 ret = rtl8365mb_vlan_port_set_framefilter(priv, port, 1401 accepted_frame); 1402 if (ret) { 1403 NL_SET_ERR_MSG_MOD(extack, 1404 "Failed to set port framefilter"); 1405 goto undo_transparent; 1406 } 1407 } 1408 1409 /* When VLAN filtering is disabled, preserve frames exactly as received. 1410 * Otherwise, the VLAN egress pipeline may still alter tag state 1411 * according to VLAN membership and untag configuration. 1412 */ 1413 if (vlan_filtering) 1414 mode = RTL8365MB_VLAN_EGRESS_MODE_ORIGINAL; 1415 else 1416 mode = RTL8365MB_VLAN_EGRESS_MODE_REAL_KEEP; 1417 1418 ret = rtl8365mb_port_set_vlan_egress_mode(priv, port, mode); 1419 if (ret) 1420 goto undo_set_framefilter; 1421 1422 return ret; 1423 1424 undo_set_framefilter: 1425 if (prev_accepted_frame != accepted_frame) 1426 rtl8365mb_vlan_port_set_framefilter(priv, port, 1427 prev_accepted_frame); 1428 undo_transparent: 1429 /* The DSA core guarantees this callback is only invoked on an actual 1430 * state transition, ensuring the previous hardware state was the 1431 * opposite (!vlan_filtering). It is also called during setup but, in 1432 * that case, any failure here aborts the entire switch initialization. 1433 * 1434 * VLAN_INGRESS and VLAN_EGRESS_TRANSPARENT states are directly derived 1435 * from vlan_filtering. That way, we can simply undo it without 1436 * checking the current HW state as we do with VLAN_EGRESS_MODE. 1437 */ 1438 dsa_switch_for_each_port(dp, ds) { 1439 if (configured_ports & BIT(dp->index)) 1440 rtl8365mb_port_set_transparent(priv, port, dp->index, 1441 vlan_filtering); 1442 } 1443 1444 rtl8365mb_port_set_ingress_filtering(priv, port, !vlan_filtering); 1445 1446 return ret; 1447 } 1448 1449 static int rtl8365mb_port_vlan_add(struct dsa_switch *ds, int port, 1450 const struct switchdev_obj_port_vlan *vlan, 1451 struct netlink_ext_ack *extack) 1452 { 1453 bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1454 bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); 1455 u16 pvid_vid; 1456 struct realtek_priv *priv = ds->priv; 1457 int ret; 1458 1459 dev_dbg(priv->dev, "add VLAN %d on port %d, %s, %s\n", 1460 vlan->vid, port, untagged ? "untagged" : "tagged", 1461 pvid ? "PVID" : "no PVID"); 1462 1463 /* VID == 0 is reserved in this driver */ 1464 if (vlan->vid == 0) { 1465 NL_SET_ERR_MSG_MOD(extack, 1466 "VLAN 0 is reserved by this driver"); 1467 return -EOPNOTSUPP; 1468 } 1469 1470 mutex_lock(&priv->vlan_lock); 1471 1472 ret = rtl8365mb_vlan_port_get_pvid(priv, port, &pvid_vid); 1473 if (ret) 1474 goto out_unlock; 1475 1476 /* Set PVID if needed */ 1477 if (pvid) { 1478 ret = rtl8365mb_vlan_pvid_port_set(ds, port, vlan->vid, 1479 extack); 1480 if (ret) 1481 goto out_unlock; 1482 } else { 1483 /* or try to unset it if not */ 1484 ret = rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); 1485 if (ret) 1486 goto out_unlock; 1487 } 1488 1489 /* add port to vlan4k. It knows nothing about PVID */ 1490 ret = rtl8365mb_vlan_4k_port_add(ds, port, vlan, extack); 1491 if (ret) 1492 goto undo_set_pvid; 1493 1494 ret = 0; 1495 goto out_unlock; 1496 1497 undo_set_pvid: 1498 /* undo the pvid definition */ 1499 if (pvid != (pvid_vid == vlan->vid)) { 1500 if (pvid_vid) 1501 (void)rtl8365mb_vlan_pvid_port_set(ds, port, pvid_vid, 1502 NULL); 1503 else 1504 (void)rtl8365mb_vlan_pvid_port_clear(ds, port, 1505 vlan->vid); 1506 } 1507 out_unlock: 1508 mutex_unlock(&priv->vlan_lock); 1509 return ret; 1510 } 1511 1512 static int rtl8365mb_port_vlan_del(struct dsa_switch *ds, int port, 1513 const struct switchdev_obj_port_vlan *vlan) 1514 { 1515 bool untagged = !!(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED); 1516 bool pvid = !!(vlan->flags & BRIDGE_VLAN_INFO_PVID); 1517 struct realtek_priv *priv = ds->priv; 1518 int ret; 1519 1520 dev_dbg(priv->dev, "del VLAN %d on port %d, %s, %s\n", 1521 vlan->vid, port, untagged ? "untagged" : "tagged", 1522 pvid ? "PVID" : "no PVID"); 1523 1524 /* VID == 0 is reserved in this driver */ 1525 if (vlan->vid == 0) 1526 return -EOPNOTSUPP; 1527 1528 mutex_lock(&priv->vlan_lock); 1529 ret = rtl8365mb_vlan_pvid_port_clear(ds, port, vlan->vid); 1530 if (ret) 1531 goto out_unlock; 1532 1533 ret = rtl8365mb_vlan_4k_port_del(ds, port, vlan); 1534 /* There is little incentive to try to undo the removal of PVID (if it 1535 * was really in use) as an error here might indicate the ASIC stopped 1536 * to answer. 1537 */ 1538 1539 out_unlock: 1540 mutex_unlock(&priv->vlan_lock); 1541 return ret; 1542 } 1543 1544 /* VLAN support is always enabled in the switch. 1545 * 1546 * Standalone forwarding relies on transparent VLAN mode combined with per-port 1547 * isolation masks restricting egress to CPU ports only. 1548 * 1549 */ 1550 static int rtl8365mb_vlan_setup(struct dsa_switch *ds) 1551 { 1552 struct realtek_priv *priv = ds->priv; 1553 struct dsa_port *dp; 1554 int ret; 1555 1556 dsa_switch_for_each_available_port(dp, ds) { 1557 /* Disable vlan-filtering for all ports */ 1558 ret = rtl8365mb_port_vlan_filtering(ds, dp->index, false, NULL); 1559 if (ret) { 1560 dev_err(priv->dev, 1561 "Failed to disable vlan filtering on port %d\n", 1562 dp->index); 1563 return ret; 1564 } 1565 } 1566 1567 /* VLAN is always enabled. */ 1568 ret = regmap_update_bits(priv->map, RTL8365MB_VLAN_CTRL_REG, 1569 RTL8365MB_VLAN_CTRL_EN_MASK, 1570 FIELD_PREP(RTL8365MB_VLAN_CTRL_EN_MASK, 1)); 1571 return ret; 1572 } 1573 1574 static int rtl8365mb_port_set_learning(struct realtek_priv *priv, int port, 1575 bool enable) 1576 { 1577 /* Enable/disable learning by limiting the number of L2 addresses the 1578 * port can learn. Realtek documentation states that a limit of zero 1579 * disables learning. When enabling learning, set it to the chip's 1580 * maximum. 1581 */ 1582 return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port), 1583 enable ? RTL8365MB_LEARN_LIMIT_MAX : 0); 1584 } 1585 1586 static int rtl8365mb_port_set_ucast_flood(struct realtek_priv *priv, int port, 1587 bool enable) 1588 { 1589 /* Frames with unknown unicast DA will be flooded to a programmable 1590 * port mask that by default includes all ports. Add or remove 1591 * the specified port from this port mask accordingly. 1592 */ 1593 return regmap_update_bits(priv->map, 1594 RTL8365MB_UNKNOWN_UNICAST_FLOODING_PMASK_REG, 1595 BIT(port), enable ? BIT(port) : 0); 1596 } 1597 1598 static int rtl8365mb_port_set_mcast_flood(struct realtek_priv *priv, int port, 1599 bool enable) 1600 { 1601 return regmap_update_bits(priv->map, 1602 RTL8365MB_UNKNOWN_MULTICAST_FLOODING_PMASK_REG, 1603 BIT(port), enable ? BIT(port) : 0); 1604 } 1605 1606 static int rtl8365mb_port_set_bcast_flood(struct realtek_priv *priv, int port, 1607 bool enable) 1608 { 1609 return regmap_update_bits(priv->map, 1610 RTL8365MB_UNKNOWN_BROADCAST_FLOODING_PMASK_REG, 1611 BIT(port), enable ? BIT(port) : 0); 1612 } 1613 1614 static int rtl8365mb_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1615 struct switchdev_brport_flags flags, 1616 struct netlink_ext_ack *extack) 1617 { 1618 struct realtek_priv *priv = ds->priv; 1619 1620 dev_dbg(priv->dev, "pre_bridge_flags port:%d flags:%lx supported:%lx\n", 1621 port, flags.mask, RTL8365MB_SUPPORTED_BRIDGE_FLAGS); 1622 1623 if (flags.mask & ~RTL8365MB_SUPPORTED_BRIDGE_FLAGS) 1624 return -EINVAL; 1625 1626 return 0; 1627 } 1628 1629 static int rtl8365mb_port_set_efid(struct realtek_priv *priv, int port, 1630 u32 efid) 1631 { 1632 return regmap_update_bits(priv->map, RTL8365MB_PORT_EFID_REG(port), 1633 RTL8365MB_PORT_EFID_MASK(port), 1634 efid << RTL8365MB_PORT_EFID_OFFSET(port)); 1635 } 1636 1637 /* Port isolation manipulation functions. 1638 * 1639 * The port isolation register controls the forwarding mask of a given 1640 * port. The switch will not forward packets ingressed on a given port 1641 * to ports which are not enabled in its forwarding mask. 1642 * 1643 * The port forwarding mask has the highest priority in forwarding 1644 * decisions. The only exception to this rule is when the switch 1645 * receives a packet on its CPU port with ALLOW=0. In that case the TX 1646 * field of the CPU tag will override the forwarding port mask. 1647 */ 1648 static int rtl8365mb_port_set_isolation(struct realtek_priv *priv, int port, 1649 u32 mask) 1650 { 1651 return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 1652 mask); 1653 } 1654 1655 static int rtl8365mb_port_add_isolation(struct realtek_priv *priv, int port, 1656 u32 mask) 1657 { 1658 return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 1659 mask, mask); 1660 } 1661 1662 static int rtl8365mb_port_remove_isolation(struct realtek_priv *priv, int port, 1663 u32 mask) 1664 { 1665 return regmap_update_bits(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), 1666 mask, 0); 1667 } 1668 1669 static int rtl8365mb_mib_counter_read(struct realtek_priv *priv, int port, 1670 u32 offset, u32 length, u64 *mibvalue) 1671 { 1672 u64 tmpvalue = 0; 1673 u32 val; 1674 int ret; 1675 int i; 1676 1677 /* The MIB address is an SRAM address. We request a particular address 1678 * and then poll the control register before reading the value from some 1679 * counter registers. 1680 */ 1681 ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG, 1682 RTL8365MB_MIB_ADDRESS(port, offset)); 1683 if (ret) 1684 return ret; 1685 1686 /* Poll for completion */ 1687 ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val, 1688 !(val & RTL8365MB_MIB_CTRL0_BUSY_MASK), 1689 10, 100); 1690 if (ret) 1691 return ret; 1692 1693 /* Presumably this indicates a MIB counter read failure */ 1694 if (val & RTL8365MB_MIB_CTRL0_RESET_MASK) 1695 return -EIO; 1696 1697 /* There are four MIB counter registers each holding a 16 bit word of a 1698 * MIB counter. Depending on the offset, we should read from the upper 1699 * two or lower two registers. In case the MIB counter is 4 words, we 1700 * read from all four registers. 1701 */ 1702 if (length == 4) 1703 offset = 3; 1704 else 1705 offset = (offset + 1) % 4; 1706 1707 /* Read the MIB counter 16 bits at a time */ 1708 for (i = 0; i < length; i++) { 1709 ret = regmap_read(priv->map, 1710 RTL8365MB_MIB_COUNTER_REG(offset - i), &val); 1711 if (ret) 1712 return ret; 1713 1714 tmpvalue = ((tmpvalue) << 16) | (val & 0xFFFF); 1715 } 1716 1717 /* Only commit the result if no error occurred */ 1718 *mibvalue = tmpvalue; 1719 1720 return 0; 1721 } 1722 1723 static void rtl8365mb_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data) 1724 { 1725 struct realtek_priv *priv = ds->priv; 1726 struct rtl8365mb *mb; 1727 int ret; 1728 int i; 1729 1730 mb = priv->chip_data; 1731 1732 mutex_lock(&mb->mib_lock); 1733 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1734 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1735 1736 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1737 mib->length, &data[i]); 1738 if (ret) { 1739 dev_err(priv->dev, 1740 "failed to read port %d counters: %pe\n", port, 1741 ERR_PTR(ret)); 1742 break; 1743 } 1744 } 1745 mutex_unlock(&mb->mib_lock); 1746 } 1747 1748 static void rtl8365mb_get_strings(struct dsa_switch *ds, int port, u32 stringset, u8 *data) 1749 { 1750 int i; 1751 1752 if (stringset != ETH_SS_STATS) 1753 return; 1754 1755 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1756 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1757 ethtool_puts(&data, mib->name); 1758 } 1759 } 1760 1761 static int rtl8365mb_get_sset_count(struct dsa_switch *ds, int port, int sset) 1762 { 1763 if (sset != ETH_SS_STATS) 1764 return -EOPNOTSUPP; 1765 1766 return RTL8365MB_MIB_END; 1767 } 1768 1769 static void rtl8365mb_get_phy_stats(struct dsa_switch *ds, int port, 1770 struct ethtool_eth_phy_stats *phy_stats) 1771 { 1772 struct realtek_priv *priv = ds->priv; 1773 struct rtl8365mb_mib_counter *mib; 1774 struct rtl8365mb *mb; 1775 1776 mb = priv->chip_data; 1777 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3StatsSymbolErrors]; 1778 1779 mutex_lock(&mb->mib_lock); 1780 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1781 &phy_stats->SymbolErrorDuringCarrier); 1782 mutex_unlock(&mb->mib_lock); 1783 } 1784 1785 static void rtl8365mb_get_mac_stats(struct dsa_switch *ds, int port, 1786 struct ethtool_eth_mac_stats *mac_stats) 1787 { 1788 u64 cnt[RTL8365MB_MIB_END] = { 1789 [RTL8365MB_MIB_ifOutOctets] = 1, 1790 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1791 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1792 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1793 [RTL8365MB_MIB_dot3OutPauseFrames] = 1, 1794 [RTL8365MB_MIB_ifOutDiscards] = 1, 1795 [RTL8365MB_MIB_ifInOctets] = 1, 1796 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1797 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1798 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1799 [RTL8365MB_MIB_dot3InPauseFrames] = 1, 1800 [RTL8365MB_MIB_dot3StatsSingleCollisionFrames] = 1, 1801 [RTL8365MB_MIB_dot3StatsMultipleCollisionFrames] = 1, 1802 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1803 [RTL8365MB_MIB_dot3StatsDeferredTransmissions] = 1, 1804 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1805 [RTL8365MB_MIB_dot3StatsExcessiveCollisions] = 1, 1806 1807 }; 1808 struct realtek_priv *priv = ds->priv; 1809 struct rtl8365mb *mb; 1810 int ret; 1811 int i; 1812 1813 mb = priv->chip_data; 1814 1815 mutex_lock(&mb->mib_lock); 1816 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1817 struct rtl8365mb_mib_counter *mib = &rtl8365mb_mib_counters[i]; 1818 1819 /* Only fetch required MIB counters (marked = 1 above) */ 1820 if (!cnt[i]) 1821 continue; 1822 1823 ret = rtl8365mb_mib_counter_read(priv, port, mib->offset, 1824 mib->length, &cnt[i]); 1825 if (ret) 1826 break; 1827 } 1828 mutex_unlock(&mb->mib_lock); 1829 1830 /* The RTL8365MB-VC exposes MIB objects, which we have to translate into 1831 * IEEE 802.3 Managed Objects. This is not always completely faithful, 1832 * but we try out best. See RFC 3635 for a detailed treatment of the 1833 * subject. 1834 */ 1835 1836 mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1837 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1838 cnt[RTL8365MB_MIB_ifOutBroadcastPkts] + 1839 cnt[RTL8365MB_MIB_dot3OutPauseFrames] - 1840 cnt[RTL8365MB_MIB_ifOutDiscards]; 1841 mac_stats->SingleCollisionFrames = 1842 cnt[RTL8365MB_MIB_dot3StatsSingleCollisionFrames]; 1843 mac_stats->MultipleCollisionFrames = 1844 cnt[RTL8365MB_MIB_dot3StatsMultipleCollisionFrames]; 1845 mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1846 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1847 cnt[RTL8365MB_MIB_ifInBroadcastPkts] + 1848 cnt[RTL8365MB_MIB_dot3InPauseFrames]; 1849 mac_stats->FrameCheckSequenceErrors = 1850 cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1851 mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] - 1852 18 * mac_stats->FramesTransmittedOK; 1853 mac_stats->FramesWithDeferredXmissions = 1854 cnt[RTL8365MB_MIB_dot3StatsDeferredTransmissions]; 1855 mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1856 mac_stats->FramesAbortedDueToXSColls = 1857 cnt[RTL8365MB_MIB_dot3StatsExcessiveCollisions]; 1858 mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] - 1859 18 * mac_stats->FramesReceivedOK; 1860 mac_stats->MulticastFramesXmittedOK = 1861 cnt[RTL8365MB_MIB_ifOutMulticastPkts]; 1862 mac_stats->BroadcastFramesXmittedOK = 1863 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1864 mac_stats->MulticastFramesReceivedOK = 1865 cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1866 mac_stats->BroadcastFramesReceivedOK = 1867 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1868 } 1869 1870 static void rtl8365mb_get_ctrl_stats(struct dsa_switch *ds, int port, 1871 struct ethtool_eth_ctrl_stats *ctrl_stats) 1872 { 1873 struct realtek_priv *priv = ds->priv; 1874 struct rtl8365mb_mib_counter *mib; 1875 struct rtl8365mb *mb; 1876 1877 mb = priv->chip_data; 1878 mib = &rtl8365mb_mib_counters[RTL8365MB_MIB_dot3ControlInUnknownOpcodes]; 1879 1880 mutex_lock(&mb->mib_lock); 1881 rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length, 1882 &ctrl_stats->UnsupportedOpcodesReceived); 1883 mutex_unlock(&mb->mib_lock); 1884 } 1885 1886 static void rtl8365mb_stats_update(struct realtek_priv *priv, int port) 1887 { 1888 u64 cnt[RTL8365MB_MIB_END] = { 1889 [RTL8365MB_MIB_ifOutOctets] = 1, 1890 [RTL8365MB_MIB_ifOutUcastPkts] = 1, 1891 [RTL8365MB_MIB_ifOutMulticastPkts] = 1, 1892 [RTL8365MB_MIB_ifOutBroadcastPkts] = 1, 1893 [RTL8365MB_MIB_ifOutDiscards] = 1, 1894 [RTL8365MB_MIB_ifInOctets] = 1, 1895 [RTL8365MB_MIB_ifInUcastPkts] = 1, 1896 [RTL8365MB_MIB_ifInMulticastPkts] = 1, 1897 [RTL8365MB_MIB_ifInBroadcastPkts] = 1, 1898 [RTL8365MB_MIB_etherStatsDropEvents] = 1, 1899 [RTL8365MB_MIB_etherStatsCollisions] = 1, 1900 [RTL8365MB_MIB_etherStatsFragments] = 1, 1901 [RTL8365MB_MIB_etherStatsJabbers] = 1, 1902 [RTL8365MB_MIB_dot3StatsFCSErrors] = 1, 1903 [RTL8365MB_MIB_dot3StatsLateCollisions] = 1, 1904 }; 1905 struct rtl8365mb *mb = priv->chip_data; 1906 struct rtnl_link_stats64 *stats; 1907 int ret; 1908 int i; 1909 1910 stats = &mb->ports[port].stats; 1911 1912 mutex_lock(&mb->mib_lock); 1913 for (i = 0; i < RTL8365MB_MIB_END; i++) { 1914 struct rtl8365mb_mib_counter *c = &rtl8365mb_mib_counters[i]; 1915 1916 /* Only fetch required MIB counters (marked = 1 above) */ 1917 if (!cnt[i]) 1918 continue; 1919 1920 ret = rtl8365mb_mib_counter_read(priv, port, c->offset, 1921 c->length, &cnt[i]); 1922 if (ret) 1923 break; 1924 } 1925 mutex_unlock(&mb->mib_lock); 1926 1927 /* Don't update statistics if there was an error reading the counters */ 1928 if (ret) 1929 return; 1930 1931 spin_lock(&mb->ports[port].stats_lock); 1932 1933 stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] + 1934 cnt[RTL8365MB_MIB_ifInMulticastPkts] + 1935 cnt[RTL8365MB_MIB_ifInBroadcastPkts]; 1936 1937 stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] + 1938 cnt[RTL8365MB_MIB_ifOutMulticastPkts] + 1939 cnt[RTL8365MB_MIB_ifOutBroadcastPkts]; 1940 1941 /* if{In,Out}Octets includes FCS - remove it */ 1942 stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets; 1943 stats->tx_bytes = 1944 cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets; 1945 1946 stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents]; 1947 stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards]; 1948 1949 stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts]; 1950 stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions]; 1951 1952 stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] + 1953 cnt[RTL8365MB_MIB_etherStatsJabbers]; 1954 stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors]; 1955 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors; 1956 1957 stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards]; 1958 stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions]; 1959 stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors; 1960 1961 spin_unlock(&mb->ports[port].stats_lock); 1962 } 1963 1964 static void rtl8365mb_stats_poll(struct work_struct *work) 1965 { 1966 struct rtl8365mb_port *p = container_of(to_delayed_work(work), 1967 struct rtl8365mb_port, 1968 mib_work); 1969 struct realtek_priv *priv = p->priv; 1970 1971 rtl8365mb_stats_update(priv, p->index); 1972 1973 schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES); 1974 } 1975 1976 static void rtl8365mb_get_stats64(struct dsa_switch *ds, int port, 1977 struct rtnl_link_stats64 *s) 1978 { 1979 struct realtek_priv *priv = ds->priv; 1980 struct rtl8365mb_port *p; 1981 struct rtl8365mb *mb; 1982 1983 mb = priv->chip_data; 1984 p = &mb->ports[port]; 1985 1986 spin_lock(&p->stats_lock); 1987 memcpy(s, &p->stats, sizeof(*s)); 1988 spin_unlock(&p->stats_lock); 1989 } 1990 1991 static void rtl8365mb_stats_setup(struct realtek_priv *priv) 1992 { 1993 struct rtl8365mb *mb = priv->chip_data; 1994 struct dsa_switch *ds = &priv->ds; 1995 struct dsa_port *dp; 1996 1997 /* Per-chip global mutex to protect MIB counter access, since doing 1998 * so requires accessing a series of registers in a particular order. 1999 */ 2000 mutex_init(&mb->mib_lock); 2001 2002 dsa_switch_for_each_available_port(dp, ds) { 2003 struct rtl8365mb_port *p = &mb->ports[dp->index]; 2004 2005 /* Per-port spinlock to protect the stats64 data */ 2006 spin_lock_init(&p->stats_lock); 2007 2008 /* This work polls the MIB counters and keeps the stats64 data 2009 * up-to-date. 2010 */ 2011 INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll); 2012 } 2013 } 2014 2015 static void rtl8365mb_stats_teardown(struct realtek_priv *priv) 2016 { 2017 struct rtl8365mb *mb = priv->chip_data; 2018 struct dsa_switch *ds = &priv->ds; 2019 struct dsa_port *dp; 2020 2021 dsa_switch_for_each_available_port(dp, ds) { 2022 struct rtl8365mb_port *p = &mb->ports[dp->index]; 2023 2024 cancel_delayed_work_sync(&p->mib_work); 2025 } 2026 } 2027 2028 static int rtl8365mb_get_and_clear_status_reg(struct realtek_priv *priv, u32 reg, 2029 u32 *val) 2030 { 2031 int ret; 2032 2033 ret = regmap_read(priv->map, reg, val); 2034 if (ret) 2035 return ret; 2036 2037 return regmap_write(priv->map, reg, *val); 2038 } 2039 2040 static irqreturn_t rtl8365mb_irq(int irq, void *data) 2041 { 2042 struct realtek_priv *priv = data; 2043 unsigned long line_changes = 0; 2044 u32 stat; 2045 int line; 2046 int ret; 2047 2048 ret = rtl8365mb_get_and_clear_status_reg(priv, RTL8365MB_INTR_STATUS_REG, 2049 &stat); 2050 if (ret) 2051 goto out_error; 2052 2053 if (stat & RTL8365MB_INTR_LINK_CHANGE_MASK) { 2054 u32 linkdown_ind; 2055 u32 linkup_ind; 2056 u32 val; 2057 2058 ret = rtl8365mb_get_and_clear_status_reg( 2059 priv, RTL8365MB_PORT_LINKUP_IND_REG, &val); 2060 if (ret) 2061 goto out_error; 2062 2063 linkup_ind = FIELD_GET(RTL8365MB_PORT_LINKUP_IND_MASK, val); 2064 2065 ret = rtl8365mb_get_and_clear_status_reg( 2066 priv, RTL8365MB_PORT_LINKDOWN_IND_REG, &val); 2067 if (ret) 2068 goto out_error; 2069 2070 linkdown_ind = FIELD_GET(RTL8365MB_PORT_LINKDOWN_IND_MASK, val); 2071 2072 line_changes = linkup_ind | linkdown_ind; 2073 } 2074 2075 if (!line_changes) 2076 goto out_none; 2077 2078 for_each_set_bit(line, &line_changes, priv->num_ports) { 2079 int child_irq = irq_find_mapping(priv->irqdomain, line); 2080 2081 if (!child_irq) 2082 continue; 2083 2084 handle_nested_irq(child_irq); 2085 } 2086 2087 return IRQ_HANDLED; 2088 2089 out_error: 2090 dev_err(priv->dev, "failed to read interrupt status: %pe\n", 2091 ERR_PTR(ret)); 2092 2093 out_none: 2094 return IRQ_NONE; 2095 } 2096 2097 static struct irq_chip rtl8365mb_irq_chip = { 2098 .name = "rtl8365mb", 2099 /* The hardware doesn't support masking IRQs on a per-port basis */ 2100 }; 2101 2102 static int rtl8365mb_irq_map(struct irq_domain *domain, unsigned int irq, 2103 irq_hw_number_t hwirq) 2104 { 2105 struct realtek_priv *priv = domain->host_data; 2106 struct rtl8365mb *mb = priv->chip_data; 2107 2108 irq_set_chip_data(irq, priv); 2109 irq_set_chip_and_handler(irq, &rtl8365mb_irq_chip, handle_simple_irq); 2110 irq_set_nested_thread(irq, 1); 2111 irq_set_noprobe(irq); 2112 irq_set_parent(irq, mb->irq); 2113 2114 return 0; 2115 } 2116 2117 static void rtl8365mb_irq_unmap(struct irq_domain *d, unsigned int irq) 2118 { 2119 irq_set_nested_thread(irq, 0); 2120 irq_set_chip_and_handler(irq, NULL, NULL); 2121 irq_set_chip_data(irq, NULL); 2122 } 2123 2124 static const struct irq_domain_ops rtl8365mb_irqdomain_ops = { 2125 .map = rtl8365mb_irq_map, 2126 .unmap = rtl8365mb_irq_unmap, 2127 .xlate = irq_domain_xlate_onecell, 2128 }; 2129 2130 static int rtl8365mb_set_irq_enable(struct realtek_priv *priv, bool enable) 2131 { 2132 return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG, 2133 RTL8365MB_INTR_LINK_CHANGE_MASK, 2134 FIELD_PREP(RTL8365MB_INTR_LINK_CHANGE_MASK, 2135 enable ? 1 : 0)); 2136 } 2137 2138 static int rtl8365mb_irq_enable(struct realtek_priv *priv) 2139 { 2140 return rtl8365mb_set_irq_enable(priv, true); 2141 } 2142 2143 static int rtl8365mb_irq_disable(struct realtek_priv *priv) 2144 { 2145 return rtl8365mb_set_irq_enable(priv, false); 2146 } 2147 2148 static int rtl8365mb_irq_setup(struct realtek_priv *priv) 2149 { 2150 struct rtl8365mb *mb = priv->chip_data; 2151 struct dsa_switch *ds = &priv->ds; 2152 struct device_node *intc; 2153 struct dsa_port *dp; 2154 u32 irq_trig; 2155 int virq; 2156 int irq; 2157 u32 val; 2158 int ret; 2159 2160 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); 2161 if (!intc) { 2162 dev_err(priv->dev, "missing child interrupt-controller node\n"); 2163 return -EINVAL; 2164 } 2165 2166 /* rtl8365mb IRQs cascade off this one */ 2167 irq = of_irq_get(intc, 0); 2168 if (irq <= 0) { 2169 if (!irq) { 2170 dev_err(priv->dev, "failed to map IRQ\n"); 2171 ret = -EINVAL; 2172 } else { 2173 ret = dev_err_probe(priv->dev, irq, 2174 "failed to get parent irq\n"); 2175 } 2176 goto out_put_node; 2177 } 2178 2179 /* Store the irq so that we know to map and free it during teardown */ 2180 mb->irq = irq; 2181 2182 priv->irqdomain = irq_domain_create_linear(of_fwnode_handle(intc), priv->num_ports, 2183 &rtl8365mb_irqdomain_ops, priv); 2184 if (!priv->irqdomain) { 2185 dev_err(priv->dev, "failed to add irq domain\n"); 2186 ret = -ENOMEM; 2187 goto out_put_node; 2188 } 2189 2190 dsa_switch_for_each_available_port(dp, ds) { 2191 virq = irq_create_mapping(priv->irqdomain, dp->index); 2192 if (!virq) { 2193 dev_err(priv->dev, 2194 "failed to create irq domain mapping\n"); 2195 ret = -EINVAL; 2196 goto out_remove_irqdomain; 2197 } 2198 2199 irq_set_parent(virq, irq); 2200 } 2201 2202 /* Configure chip interrupt signal polarity */ 2203 irq_trig = irq_get_trigger_type(irq); 2204 switch (irq_trig) { 2205 case IRQF_TRIGGER_RISING: 2206 case IRQF_TRIGGER_HIGH: 2207 val = RTL8365MB_INTR_POLARITY_HIGH; 2208 break; 2209 case IRQF_TRIGGER_FALLING: 2210 case IRQF_TRIGGER_LOW: 2211 val = RTL8365MB_INTR_POLARITY_LOW; 2212 break; 2213 default: 2214 dev_err(priv->dev, "unsupported irq trigger type %u\n", 2215 irq_trig); 2216 ret = -EINVAL; 2217 goto out_remove_irqdomain; 2218 } 2219 2220 ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG, 2221 RTL8365MB_INTR_POLARITY_MASK, 2222 FIELD_PREP(RTL8365MB_INTR_POLARITY_MASK, val)); 2223 if (ret) 2224 goto out_remove_irqdomain; 2225 2226 /* Disable the interrupt in case the chip has it enabled on reset */ 2227 ret = rtl8365mb_irq_disable(priv); 2228 if (ret) 2229 goto out_remove_irqdomain; 2230 2231 /* Clear the interrupt status register */ 2232 ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG, 2233 RTL8365MB_INTR_ALL_MASK); 2234 if (ret) 2235 goto out_remove_irqdomain; 2236 2237 ret = request_threaded_irq(irq, NULL, rtl8365mb_irq, IRQF_ONESHOT, 2238 "rtl8365mb", priv); 2239 if (ret) { 2240 dev_err(priv->dev, "failed to request irq: %pe\n", 2241 ERR_PTR(ret)); 2242 goto out_remove_irqdomain; 2243 } 2244 2245 ret = rtl8365mb_irq_enable(priv); 2246 if (ret) 2247 goto out_free_irq; 2248 2249 of_node_put(intc); 2250 2251 return 0; 2252 2253 out_free_irq: 2254 free_irq(mb->irq, priv); 2255 2256 out_remove_irqdomain: 2257 dsa_switch_for_each_port(dp, ds) { 2258 virq = irq_find_mapping(priv->irqdomain, dp->index); 2259 2260 if (virq) 2261 irq_dispose_mapping(virq); 2262 } 2263 2264 irq_domain_remove(priv->irqdomain); 2265 priv->irqdomain = NULL; 2266 2267 out_put_node: 2268 mb->irq = 0; 2269 of_node_put(intc); 2270 2271 return ret; 2272 } 2273 2274 static void rtl8365mb_irq_teardown(struct realtek_priv *priv) 2275 { 2276 struct rtl8365mb *mb = priv->chip_data; 2277 struct dsa_switch *ds = &priv->ds; 2278 struct dsa_port *dp; 2279 int virq; 2280 2281 if (mb->irq) { 2282 free_irq(mb->irq, priv); 2283 mb->irq = 0; 2284 } 2285 2286 if (priv->irqdomain) { 2287 /* Unused ports with a linked PHY still have an active IRQ 2288 * mapping that must be disposed of during teardown. Loop 2289 * through all ports. 2290 */ 2291 dsa_switch_for_each_port(dp, ds) { 2292 virq = irq_find_mapping(priv->irqdomain, dp->index); 2293 2294 if (virq) 2295 irq_dispose_mapping(virq); 2296 } 2297 2298 irq_domain_remove(priv->irqdomain); 2299 priv->irqdomain = NULL; 2300 } 2301 } 2302 2303 static int rtl8365mb_cpu_config(struct realtek_priv *priv) 2304 { 2305 struct rtl8365mb *mb = priv->chip_data; 2306 struct rtl8365mb_cpu *cpu = &mb->cpu; 2307 u32 val; 2308 int ret; 2309 2310 ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG, 2311 RTL8365MB_CPU_PORT_MASK_MASK, 2312 FIELD_PREP(RTL8365MB_CPU_PORT_MASK_MASK, 2313 cpu->mask)); 2314 if (ret) 2315 return ret; 2316 2317 val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) | 2318 FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) | 2319 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) | 2320 FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) | 2321 FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) | 2322 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) | 2323 FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_EXT_MASK, 2324 cpu->trap_port >> 3 & 0x1); 2325 ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val); 2326 if (ret) 2327 return ret; 2328 2329 return 0; 2330 } 2331 2332 static int rtl8365mb_change_tag_protocol(struct dsa_switch *ds, 2333 enum dsa_tag_protocol proto) 2334 { 2335 struct realtek_priv *priv = ds->priv; 2336 struct rtl8365mb_cpu *cpu; 2337 struct rtl8365mb *mb; 2338 2339 mb = priv->chip_data; 2340 cpu = &mb->cpu; 2341 2342 switch (proto) { 2343 case DSA_TAG_PROTO_RTL8_4: 2344 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 2345 cpu->position = RTL8365MB_CPU_POS_AFTER_SA; 2346 break; 2347 case DSA_TAG_PROTO_RTL8_4T: 2348 cpu->format = RTL8365MB_CPU_FORMAT_8BYTES; 2349 cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC; 2350 break; 2351 /* The switch also supports a 4-byte format, similar to rtl4a but with 2352 * the same 0x04 8-bit version and probably 8-bit port source/dest. 2353 * There is no public doc about it. Not supported yet and it will probably 2354 * never be. 2355 */ 2356 default: 2357 return -EPROTONOSUPPORT; 2358 } 2359 2360 return rtl8365mb_cpu_config(priv); 2361 } 2362 2363 static int rtl8365mb_switch_init(struct realtek_priv *priv) 2364 { 2365 struct rtl8365mb *mb = priv->chip_data; 2366 const struct rtl8365mb_chip_info *ci; 2367 int ret; 2368 int i; 2369 2370 ci = mb->chip_info; 2371 2372 /* Do any chip-specific init jam before getting to the common stuff */ 2373 if (ci->jam_table) { 2374 for (i = 0; i < ci->jam_size; i++) { 2375 ret = regmap_write(priv->map, ci->jam_table[i].reg, 2376 ci->jam_table[i].val); 2377 if (ret) 2378 return ret; 2379 } 2380 } 2381 2382 /* Common init jam */ 2383 for (i = 0; i < ARRAY_SIZE(rtl8365mb_init_jam_common); i++) { 2384 ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg, 2385 rtl8365mb_init_jam_common[i].val); 2386 if (ret) 2387 return ret; 2388 } 2389 2390 return 0; 2391 } 2392 2393 static int rtl8365mb_reset_chip(struct realtek_priv *priv) 2394 { 2395 u32 val; 2396 2397 priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG, 2398 FIELD_PREP(RTL8365MB_CHIP_RESET_HW_MASK, 1)); 2399 2400 /* Realtek documentation says the chip needs 1 second to reset. Sleep 2401 * for 100 ms before accessing any registers to prevent ACK timeouts. 2402 */ 2403 msleep(100); 2404 return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val, 2405 !(val & RTL8365MB_CHIP_RESET_HW_MASK), 2406 20000, 1e6); 2407 } 2408 2409 static int rtl8365mb_setup(struct dsa_switch *ds) 2410 { 2411 struct realtek_priv *priv = ds->priv; 2412 struct rtl8365mb_cpu *cpu; 2413 u32 downports_mask = 0; 2414 u32 upports_mask = 0; 2415 struct rtl8365mb *mb; 2416 struct dsa_port *dp; 2417 int ret; 2418 2419 mb = priv->chip_data; 2420 cpu = &mb->cpu; 2421 2422 ret = rtl8365mb_reset_chip(priv); 2423 if (ret) { 2424 dev_err(priv->dev, "failed to reset chip: %pe\n", 2425 ERR_PTR(ret)); 2426 goto out_error; 2427 } 2428 2429 /* Configure switch to vendor-defined initial state */ 2430 ret = rtl8365mb_switch_init(priv); 2431 if (ret) { 2432 dev_err(priv->dev, "failed to initialize switch: %pe\n", 2433 ERR_PTR(ret)); 2434 goto out_error; 2435 } 2436 2437 /* Set up cascading IRQs */ 2438 ret = rtl8365mb_irq_setup(priv); 2439 if (ret == -EPROBE_DEFER) 2440 return ret; 2441 else if (ret) 2442 dev_info(priv->dev, "no interrupt support\n"); 2443 2444 dsa_switch_for_each_port(dp, ds) { 2445 /* Cascading (DSA links) is not supported yet. 2446 * Historically, the driver has always been broken 2447 * without a dedicated CPU port because CPU tagging 2448 * would be disabled, rendering the switch entirely 2449 * non-functional for DSA operations. 2450 */ 2451 if (dsa_port_is_dsa(dp)) { 2452 dev_err(priv->dev, "Cascading (DSA link) not supported\n"); 2453 ret = -EOPNOTSUPP; 2454 goto out_teardown_irq; 2455 } 2456 } 2457 2458 /* Start with all ports blocked, including unused ports */ 2459 dsa_switch_for_each_port(dp, ds) { 2460 struct rtl8365mb_port *p = &mb->ports[dp->index]; 2461 2462 /* Set the initial STP state of all ports to DISABLED, otherwise 2463 * ports will still forward frames to the CPU despite being 2464 * administratively down by default. 2465 */ 2466 rtl8365mb_port_stp_state_set(ds, dp->index, BR_STATE_DISABLED); 2467 2468 /* Start with all port completely isolated */ 2469 ret = rtl8365mb_port_set_isolation(priv, dp->index, 0); 2470 if (ret) 2471 goto out_teardown_irq; 2472 2473 /* Set the default EFID 0 for standalone mode */ 2474 ret = rtl8365mb_port_set_efid(priv, dp->index, 0); 2475 if (ret) 2476 goto out_teardown_irq; 2477 2478 /* Disable learning */ 2479 ret = rtl8365mb_port_set_learning(priv, dp->index, false); 2480 if (ret) 2481 goto out_teardown_irq; 2482 2483 /* Enable all types of flooding */ 2484 ret = rtl83xx_setup_port_flood_control(priv, dp->index); 2485 if (ret) 2486 goto out_teardown_irq; 2487 2488 /* Set up per-port private data */ 2489 p->priv = priv; 2490 p->index = dp->index; 2491 2492 /* Collect CPU ports. If we support cascade switches, it should 2493 * also include the upstream DSA ports. 2494 */ 2495 if (!dsa_port_is_cpu(dp)) 2496 continue; 2497 2498 upports_mask |= BIT(dp->index); 2499 } 2500 2501 /* Configure user ports */ 2502 dsa_switch_for_each_port(dp, ds) { 2503 if (!dsa_port_is_user(dp)) 2504 continue; 2505 2506 /* Forward only to the CPU */ 2507 ret = rtl8365mb_port_set_isolation(priv, dp->index, 2508 upports_mask); 2509 if (ret) 2510 goto out_teardown_irq; 2511 2512 /* If we support cascade switches, it should also include the 2513 * downstream DSA ports. 2514 */ 2515 downports_mask |= BIT(dp->index); 2516 } 2517 2518 /* Configure CPU tagging */ 2519 /* If we support cascade switches, it should also include the upstream 2520 * DSA ports. 2521 */ 2522 dsa_switch_for_each_cpu_port(dp, ds) { 2523 /* Use the first CPU port as trap_port */ 2524 if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS) 2525 cpu->trap_port = dp->index; 2526 2527 /* Forward to all user ports */ 2528 ret = rtl8365mb_port_set_isolation(priv, dp->index, 2529 downports_mask); 2530 if (ret) 2531 goto out_teardown_irq; 2532 } 2533 2534 cpu->mask = upports_mask; 2535 cpu->enable = cpu->mask > 0; 2536 2537 if (!cpu->enable) { 2538 dev_err(priv->dev, "no CPU port defined\n"); 2539 ret = -EINVAL; 2540 goto out_teardown_irq; 2541 } 2542 2543 ret = rtl8365mb_cpu_config(priv); 2544 if (ret) 2545 goto out_teardown_irq; 2546 2547 ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN); 2548 if (ret) 2549 goto out_teardown_irq; 2550 2551 ds->assisted_learning_on_cpu_port = true; 2552 ds->fdb_isolation = true; 2553 /* The EFID is 3 bits, but EFID 0 is reserved for standalone ports */ 2554 ds->max_num_bridges = FIELD_MAX(RTL8365MB_EFID_MASK); 2555 2556 ds->configure_vlan_while_not_filtering = true; 2557 2558 /* Set up VLAN */ 2559 ret = rtl8365mb_vlan_setup(ds); 2560 if (ret) 2561 goto out_teardown_irq; 2562 2563 ret = rtl83xx_setup_user_mdio(ds); 2564 if (ret) { 2565 dev_err(priv->dev, "could not set up MDIO bus\n"); 2566 goto out_teardown_irq; 2567 } 2568 2569 /* Start statistics counter polling */ 2570 rtl8365mb_stats_setup(priv); 2571 2572 return 0; 2573 2574 out_teardown_irq: 2575 rtl8365mb_irq_teardown(priv); 2576 2577 out_error: 2578 return ret; 2579 } 2580 2581 static void rtl8365mb_teardown(struct dsa_switch *ds) 2582 { 2583 struct realtek_priv *priv = ds->priv; 2584 2585 rtl8365mb_stats_teardown(priv); 2586 rtl8365mb_irq_teardown(priv); 2587 } 2588 2589 static int rtl8365mb_get_chip_id_and_ver(struct regmap *map, u32 *id, u32 *ver) 2590 { 2591 int ret; 2592 2593 /* For some reason we have to write a magic value to an arbitrary 2594 * register whenever accessing the chip ID/version registers. 2595 */ 2596 ret = regmap_write(map, RTL8365MB_MAGIC_REG, RTL8365MB_MAGIC_VALUE); 2597 if (ret) 2598 return ret; 2599 2600 ret = regmap_read(map, RTL8365MB_CHIP_ID_REG, id); 2601 if (ret) 2602 return ret; 2603 2604 ret = regmap_read(map, RTL8365MB_CHIP_VER_REG, ver); 2605 if (ret) 2606 return ret; 2607 2608 /* Reset magic register */ 2609 ret = regmap_write(map, RTL8365MB_MAGIC_REG, 0); 2610 if (ret) 2611 return ret; 2612 2613 return 0; 2614 } 2615 2616 static int rtl8365mb_detect(struct realtek_priv *priv) 2617 { 2618 struct rtl8365mb *mb = priv->chip_data; 2619 u32 chip_id; 2620 u32 chip_ver; 2621 int ret; 2622 int i; 2623 2624 ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver); 2625 if (ret) { 2626 dev_err(priv->dev, "failed to read chip id and version: %pe\n", 2627 ERR_PTR(ret)); 2628 return ret; 2629 } 2630 2631 for (i = 0; i < ARRAY_SIZE(rtl8365mb_chip_infos); i++) { 2632 const struct rtl8365mb_chip_info *ci = &rtl8365mb_chip_infos[i]; 2633 2634 if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) { 2635 mb->chip_info = ci; 2636 break; 2637 } 2638 } 2639 2640 if (!mb->chip_info) { 2641 dev_err(priv->dev, 2642 "unrecognized switch (id=0x%04x, ver=0x%04x)", chip_id, 2643 chip_ver); 2644 return -ENODEV; 2645 } 2646 2647 dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name); 2648 2649 priv->num_ports = RTL8365MB_MAX_NUM_PORTS; 2650 mb->priv = priv; 2651 mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS; 2652 mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL; 2653 mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA; 2654 mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES; 2655 mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES; 2656 2657 return 0; 2658 } 2659 2660 static const struct phylink_mac_ops rtl8365mb_phylink_mac_ops = { 2661 .mac_config = rtl8365mb_phylink_mac_config, 2662 .mac_link_down = rtl8365mb_phylink_mac_link_down, 2663 .mac_link_up = rtl8365mb_phylink_mac_link_up, 2664 }; 2665 2666 static const struct dsa_switch_ops rtl8365mb_switch_ops = { 2667 .get_tag_protocol = rtl8365mb_get_tag_protocol, 2668 .change_tag_protocol = rtl8365mb_change_tag_protocol, 2669 .setup = rtl8365mb_setup, 2670 .teardown = rtl8365mb_teardown, 2671 .phylink_get_caps = rtl8365mb_phylink_get_caps, 2672 .port_bridge_join = rtl83xx_port_bridge_join, 2673 .port_bridge_leave = rtl83xx_port_bridge_leave, 2674 .port_pre_bridge_flags = rtl8365mb_port_pre_bridge_flags, 2675 .port_bridge_flags = rtl83xx_port_bridge_flags, 2676 .port_stp_state_set = rtl8365mb_port_stp_state_set, 2677 .port_fast_age = rtl83xx_port_fast_age, 2678 .port_fdb_add = rtl83xx_port_fdb_add, 2679 .port_fdb_del = rtl83xx_port_fdb_del, 2680 .port_fdb_dump = rtl83xx_port_fdb_dump, 2681 .port_mdb_add = rtl83xx_port_mdb_add, 2682 .port_mdb_del = rtl83xx_port_mdb_del, 2683 .port_vlan_add = rtl8365mb_port_vlan_add, 2684 .port_vlan_del = rtl8365mb_port_vlan_del, 2685 .port_vlan_filtering = rtl8365mb_port_vlan_filtering, 2686 .get_strings = rtl8365mb_get_strings, 2687 .get_ethtool_stats = rtl8365mb_get_ethtool_stats, 2688 .get_sset_count = rtl8365mb_get_sset_count, 2689 .get_eth_phy_stats = rtl8365mb_get_phy_stats, 2690 .get_eth_mac_stats = rtl8365mb_get_mac_stats, 2691 .get_eth_ctrl_stats = rtl8365mb_get_ctrl_stats, 2692 .get_stats64 = rtl8365mb_get_stats64, 2693 .port_change_mtu = rtl8365mb_port_change_mtu, 2694 .port_max_mtu = rtl8365mb_port_max_mtu, 2695 .port_hsr_join = dsa_port_simple_hsr_join, 2696 .port_hsr_leave = dsa_port_simple_hsr_leave, 2697 }; 2698 2699 static const struct realtek_ops rtl8365mb_ops = { 2700 .detect = rtl8365mb_detect, 2701 .port_add_isolation = rtl8365mb_port_add_isolation, 2702 .port_remove_isolation = rtl8365mb_port_remove_isolation, 2703 .port_set_efid = rtl8365mb_port_set_efid, 2704 .port_set_learning = rtl8365mb_port_set_learning, 2705 .port_set_ucast_flood = rtl8365mb_port_set_ucast_flood, 2706 .port_set_mcast_flood = rtl8365mb_port_set_mcast_flood, 2707 .port_set_bcast_flood = rtl8365mb_port_set_bcast_flood, 2708 .l2_add_uc = rtl8365mb_l2_add_uc, 2709 .l2_del_uc = rtl8365mb_l2_del_uc, 2710 .l2_get_next_uc = rtl8365mb_l2_get_next_uc, 2711 .l2_add_mc = rtl8365mb_l2_add_mc, 2712 .l2_del_mc = rtl8365mb_l2_del_mc, 2713 .l2_flush = rtl8365mb_l2_flush, 2714 .phy_read = rtl8365mb_phy_read, 2715 .phy_write = rtl8365mb_phy_write, 2716 }; 2717 2718 const struct realtek_variant rtl8365mb_variant = { 2719 .ds_ops = &rtl8365mb_switch_ops, 2720 .ops = &rtl8365mb_ops, 2721 .phylink_mac_ops = &rtl8365mb_phylink_mac_ops, 2722 .clk_delay = 10, 2723 .cmd_read = 0xb9, 2724 .cmd_write = 0xb8, 2725 .chip_data_sz = sizeof(struct rtl8365mb), 2726 }; 2727 2728 static const struct of_device_id rtl8365mb_of_match[] = { 2729 { .compatible = "realtek,rtl8365mb", .data = &rtl8365mb_variant, }, 2730 { /* sentinel */ }, 2731 }; 2732 MODULE_DEVICE_TABLE(of, rtl8365mb_of_match); 2733 2734 static struct platform_driver rtl8365mb_smi_driver = { 2735 .driver = { 2736 .name = "rtl8365mb-smi", 2737 .of_match_table = rtl8365mb_of_match, 2738 }, 2739 .probe = realtek_smi_probe, 2740 .remove = realtek_smi_remove, 2741 .shutdown = realtek_smi_shutdown, 2742 }; 2743 2744 static struct mdio_driver rtl8365mb_mdio_driver = { 2745 .mdiodrv.driver = { 2746 .name = "rtl8365mb-mdio", 2747 .of_match_table = rtl8365mb_of_match, 2748 }, 2749 .probe = realtek_mdio_probe, 2750 .remove = realtek_mdio_remove, 2751 .shutdown = realtek_mdio_shutdown, 2752 }; 2753 2754 static int rtl8365mb_init(void) 2755 { 2756 int ret; 2757 2758 ret = realtek_mdio_driver_register(&rtl8365mb_mdio_driver); 2759 if (ret) 2760 return ret; 2761 2762 ret = realtek_smi_driver_register(&rtl8365mb_smi_driver); 2763 if (ret) { 2764 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 2765 return ret; 2766 } 2767 2768 return 0; 2769 } 2770 module_init(rtl8365mb_init); 2771 2772 static void __exit rtl8365mb_exit(void) 2773 { 2774 realtek_smi_driver_unregister(&rtl8365mb_smi_driver); 2775 realtek_mdio_driver_unregister(&rtl8365mb_mdio_driver); 2776 } 2777 module_exit(rtl8365mb_exit); 2778 2779 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>"); 2780 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch"); 2781 MODULE_LICENSE("GPL"); 2782 MODULE_IMPORT_NS("REALTEK_DSA"); 2783