1*23794becSDaniel Golle /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*23794becSDaniel Golle 3*23794becSDaniel Golle #ifndef __MXL862XX_API_H 4*23794becSDaniel Golle #define __MXL862XX_API_H 5*23794becSDaniel Golle 6*23794becSDaniel Golle #include <linux/if_ether.h> 7*23794becSDaniel Golle 8*23794becSDaniel Golle /** 9*23794becSDaniel Golle * struct mdio_relay_data - relayed access to the switch internal MDIO bus 10*23794becSDaniel Golle * @data: data to be read or written 11*23794becSDaniel Golle * @phy: PHY index 12*23794becSDaniel Golle * @mmd: MMD device 13*23794becSDaniel Golle * @reg: register index 14*23794becSDaniel Golle */ 15*23794becSDaniel Golle struct mdio_relay_data { 16*23794becSDaniel Golle __le16 data; 17*23794becSDaniel Golle u8 phy; 18*23794becSDaniel Golle u8 mmd; 19*23794becSDaniel Golle __le16 reg; 20*23794becSDaniel Golle } __packed; 21*23794becSDaniel Golle 22*23794becSDaniel Golle /** 23*23794becSDaniel Golle * struct mxl862xx_register_mod - Register access parameter to directly 24*23794becSDaniel Golle * modify internal registers 25*23794becSDaniel Golle * @addr: Register address offset for modification 26*23794becSDaniel Golle * @data: Value to write to the register address 27*23794becSDaniel Golle * @mask: Mask of bits to be modified (1 to modify, 0 to ignore) 28*23794becSDaniel Golle * 29*23794becSDaniel Golle * Used for direct register modification operations. 30*23794becSDaniel Golle */ 31*23794becSDaniel Golle struct mxl862xx_register_mod { 32*23794becSDaniel Golle __le16 addr; 33*23794becSDaniel Golle __le16 data; 34*23794becSDaniel Golle __le16 mask; 35*23794becSDaniel Golle } __packed; 36*23794becSDaniel Golle 37*23794becSDaniel Golle /** 38*23794becSDaniel Golle * enum mxl862xx_mac_clear_type - MAC table clear type 39*23794becSDaniel Golle * @MXL862XX_MAC_CLEAR_PHY_PORT: clear dynamic entries based on port_id 40*23794becSDaniel Golle * @MXL862XX_MAC_CLEAR_DYNAMIC: clear all dynamic entries 41*23794becSDaniel Golle */ 42*23794becSDaniel Golle enum mxl862xx_mac_clear_type { 43*23794becSDaniel Golle MXL862XX_MAC_CLEAR_PHY_PORT = 0, 44*23794becSDaniel Golle MXL862XX_MAC_CLEAR_DYNAMIC, 45*23794becSDaniel Golle }; 46*23794becSDaniel Golle 47*23794becSDaniel Golle /** 48*23794becSDaniel Golle * struct mxl862xx_mac_table_clear - MAC table clear 49*23794becSDaniel Golle * @type: see &enum mxl862xx_mac_clear_type 50*23794becSDaniel Golle * @port_id: physical port id 51*23794becSDaniel Golle */ 52*23794becSDaniel Golle struct mxl862xx_mac_table_clear { 53*23794becSDaniel Golle u8 type; 54*23794becSDaniel Golle u8 port_id; 55*23794becSDaniel Golle } __packed; 56*23794becSDaniel Golle 57*23794becSDaniel Golle /** 58*23794becSDaniel Golle * enum mxl862xx_age_timer - Aging Timer Value. 59*23794becSDaniel Golle * @MXL862XX_AGETIMER_1_SEC: 1 second aging time 60*23794becSDaniel Golle * @MXL862XX_AGETIMER_10_SEC: 10 seconds aging time 61*23794becSDaniel Golle * @MXL862XX_AGETIMER_300_SEC: 300 seconds aging time 62*23794becSDaniel Golle * @MXL862XX_AGETIMER_1_HOUR: 1 hour aging time 63*23794becSDaniel Golle * @MXL862XX_AGETIMER_1_DAY: 24 hours aging time 64*23794becSDaniel Golle * @MXL862XX_AGETIMER_CUSTOM: Custom aging time in seconds 65*23794becSDaniel Golle */ 66*23794becSDaniel Golle enum mxl862xx_age_timer { 67*23794becSDaniel Golle MXL862XX_AGETIMER_1_SEC = 1, 68*23794becSDaniel Golle MXL862XX_AGETIMER_10_SEC, 69*23794becSDaniel Golle MXL862XX_AGETIMER_300_SEC, 70*23794becSDaniel Golle MXL862XX_AGETIMER_1_HOUR, 71*23794becSDaniel Golle MXL862XX_AGETIMER_1_DAY, 72*23794becSDaniel Golle MXL862XX_AGETIMER_CUSTOM, 73*23794becSDaniel Golle }; 74*23794becSDaniel Golle 75*23794becSDaniel Golle /** 76*23794becSDaniel Golle * struct mxl862xx_bridge_alloc - Bridge Allocation 77*23794becSDaniel Golle * @bridge_id: If the bridge allocation is successful, a valid ID will be 78*23794becSDaniel Golle * returned in this field. Otherwise, INVALID_HANDLE is 79*23794becSDaniel Golle * returned. For bridge free, this field should contain a 80*23794becSDaniel Golle * valid ID returned by the bridge allocation. ID 0 is not 81*23794becSDaniel Golle * used for historic reasons. 82*23794becSDaniel Golle * 83*23794becSDaniel Golle * Used by MXL862XX_BRIDGE_ALLOC and MXL862XX_BRIDGE_FREE. 84*23794becSDaniel Golle */ 85*23794becSDaniel Golle struct mxl862xx_bridge_alloc { 86*23794becSDaniel Golle __le16 bridge_id; 87*23794becSDaniel Golle }; 88*23794becSDaniel Golle 89*23794becSDaniel Golle /** 90*23794becSDaniel Golle * enum mxl862xx_bridge_config_mask - Bridge configuration mask 91*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT: 92*23794becSDaniel Golle * Mask for mac_learning_limit_enable and mac_learning_limit. 93*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT: 94*23794becSDaniel Golle * Mask for mac_learning_count 95*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT: 96*23794becSDaniel Golle * Mask for learning_discard_event 97*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER: 98*23794becSDaniel Golle * Mask for sub_metering_enable and traffic_sub_meter_id 99*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE: 100*23794becSDaniel Golle * Mask for forward_broadcast, forward_unknown_multicast_ip, 101*23794becSDaniel Golle * forward_unknown_multicast_non_ip and forward_unknown_unicast. 102*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_ALL: Enable all 103*23794becSDaniel Golle * @MXL862XX_BRIDGE_CONFIG_MASK_FORCE: Bypass any check for debug purpose 104*23794becSDaniel Golle */ 105*23794becSDaniel Golle enum mxl862xx_bridge_config_mask { 106*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(0), 107*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(1), 108*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT = BIT(2), 109*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER = BIT(3), 110*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE = BIT(4), 111*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_ALL = 0x7FFFFFFF, 112*23794becSDaniel Golle MXL862XX_BRIDGE_CONFIG_MASK_FORCE = BIT(31) 113*23794becSDaniel Golle }; 114*23794becSDaniel Golle 115*23794becSDaniel Golle /** 116*23794becSDaniel Golle * enum mxl862xx_bridge_port_egress_meter - Meters for egress traffic type 117*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST: 118*23794becSDaniel Golle * Index of broadcast traffic meter 119*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST: 120*23794becSDaniel Golle * Index of known multicast traffic meter 121*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP: 122*23794becSDaniel Golle * Index of unknown multicast IP traffic meter 123*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP: 124*23794becSDaniel Golle * Index of unknown multicast non-IP traffic meter 125*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC: 126*23794becSDaniel Golle * Index of unknown unicast traffic meter 127*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS: 128*23794becSDaniel Golle * Index of traffic meter for other types 129*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX: Number of index 130*23794becSDaniel Golle */ 131*23794becSDaniel Golle enum mxl862xx_bridge_port_egress_meter { 132*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST = 0, 133*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST, 134*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP, 135*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP, 136*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC, 137*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS, 138*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX, 139*23794becSDaniel Golle }; 140*23794becSDaniel Golle 141*23794becSDaniel Golle /** 142*23794becSDaniel Golle * enum mxl862xx_bridge_forward_mode - Bridge forwarding type of packet 143*23794becSDaniel Golle * @MXL862XX_BRIDGE_FORWARD_FLOOD: Packet is flooded to port members of 144*23794becSDaniel Golle * ingress bridge port 145*23794becSDaniel Golle * @MXL862XX_BRIDGE_FORWARD_DISCARD: Packet is discarded 146*23794becSDaniel Golle */ 147*23794becSDaniel Golle enum mxl862xx_bridge_forward_mode { 148*23794becSDaniel Golle MXL862XX_BRIDGE_FORWARD_FLOOD = 0, 149*23794becSDaniel Golle MXL862XX_BRIDGE_FORWARD_DISCARD, 150*23794becSDaniel Golle }; 151*23794becSDaniel Golle 152*23794becSDaniel Golle /** 153*23794becSDaniel Golle * struct mxl862xx_bridge_config - Bridge Configuration 154*23794becSDaniel Golle * @bridge_id: Bridge ID (FID) 155*23794becSDaniel Golle * @mask: See &enum mxl862xx_bridge_config_mask 156*23794becSDaniel Golle * @mac_learning_limit_enable: Enable MAC learning limitation 157*23794becSDaniel Golle * @mac_learning_limit: Max number of MAC addresses that can be learned in 158*23794becSDaniel Golle * this bridge (all bridge ports) 159*23794becSDaniel Golle * @mac_learning_count: Number of MAC addresses learned from this bridge 160*23794becSDaniel Golle * @learning_discard_event: Number of learning discard events due to 161*23794becSDaniel Golle * hardware resource not available 162*23794becSDaniel Golle * @sub_metering_enable: Traffic metering on type of traffic (such as 163*23794becSDaniel Golle * broadcast, multicast, unknown unicast, etc) applies 164*23794becSDaniel Golle * @traffic_sub_meter_id: Meter for bridge process with specific type (such 165*23794becSDaniel Golle * as broadcast, multicast, unknown unicast, etc) 166*23794becSDaniel Golle * @forward_broadcast: Forwarding mode of broadcast traffic. See 167*23794becSDaniel Golle * &enum mxl862xx_bridge_forward_mode 168*23794becSDaniel Golle * @forward_unknown_multicast_ip: Forwarding mode of unknown multicast IP 169*23794becSDaniel Golle * traffic. 170*23794becSDaniel Golle * See &enum mxl862xx_bridge_forward_mode 171*23794becSDaniel Golle * @forward_unknown_multicast_non_ip: Forwarding mode of unknown multicast 172*23794becSDaniel Golle * non-IP traffic. 173*23794becSDaniel Golle * See &enum mxl862xx_bridge_forward_mode 174*23794becSDaniel Golle * @forward_unknown_unicast: Forwarding mode of unknown unicast traffic. See 175*23794becSDaniel Golle * &enum mxl862xx_bridge_forward_mode 176*23794becSDaniel Golle */ 177*23794becSDaniel Golle struct mxl862xx_bridge_config { 178*23794becSDaniel Golle __le16 bridge_id; 179*23794becSDaniel Golle __le32 mask; /* enum mxl862xx_bridge_config_mask */ 180*23794becSDaniel Golle u8 mac_learning_limit_enable; 181*23794becSDaniel Golle __le16 mac_learning_limit; 182*23794becSDaniel Golle __le16 mac_learning_count; 183*23794becSDaniel Golle __le32 learning_discard_event; 184*23794becSDaniel Golle u8 sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 185*23794becSDaniel Golle __le16 traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 186*23794becSDaniel Golle __le32 forward_broadcast; /* enum mxl862xx_bridge_forward_mode */ 187*23794becSDaniel Golle __le32 forward_unknown_multicast_ip; /* enum mxl862xx_bridge_forward_mode */ 188*23794becSDaniel Golle __le32 forward_unknown_multicast_non_ip; /* enum mxl862xx_bridge_forward_mode */ 189*23794becSDaniel Golle __le32 forward_unknown_unicast; /* enum mxl862xx_bridge_forward_mode */ 190*23794becSDaniel Golle } __packed; 191*23794becSDaniel Golle 192*23794becSDaniel Golle /** 193*23794becSDaniel Golle * struct mxl862xx_bridge_port_alloc - Bridge Port Allocation 194*23794becSDaniel Golle * @bridge_port_id: If the bridge port allocation is successful, a valid ID 195*23794becSDaniel Golle * will be returned in this field. Otherwise, INVALID_HANDLE 196*23794becSDaniel Golle * is returned. For bridge port free, this field should 197*23794becSDaniel Golle * contain a valid ID returned by the bridge port allocation. 198*23794becSDaniel Golle * 199*23794becSDaniel Golle * Used by MXL862XX_BRIDGE_PORT_ALLOC and MXL862XX_BRIDGE_PORT_FREE. 200*23794becSDaniel Golle */ 201*23794becSDaniel Golle struct mxl862xx_bridge_port_alloc { 202*23794becSDaniel Golle __le16 bridge_port_id; 203*23794becSDaniel Golle }; 204*23794becSDaniel Golle 205*23794becSDaniel Golle /** 206*23794becSDaniel Golle * enum mxl862xx_bridge_port_config_mask - Bridge Port configuration mask 207*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID: 208*23794becSDaniel Golle * Mask for bridge_id 209*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN: 210*23794becSDaniel Golle * Mask for ingress_extended_vlan_enable, 211*23794becSDaniel Golle * ingress_extended_vlan_block_id and ingress_extended_vlan_block_size 212*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN: 213*23794becSDaniel Golle * Mask for egress_extended_vlan_enable, egress_extended_vlan_block_id 214*23794becSDaniel Golle * and egress_extended_vlan_block_size 215*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING: 216*23794becSDaniel Golle * Mask for ingress_marking_mode 217*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING: 218*23794becSDaniel Golle * Mask for egress_remarking_mode 219*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER: 220*23794becSDaniel Golle * Mask for ingress_metering_enable and ingress_traffic_meter_id 221*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER: 222*23794becSDaniel Golle * Mask for egress_sub_metering_enable and egress_traffic_sub_meter_id 223*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING: 224*23794becSDaniel Golle * Mask for dest_logical_port_id, pmapper_enable, dest_sub_if_id_group, 225*23794becSDaniel Golle * pmapper_mapping_mode, pmapper_id_valid and pmapper 226*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP: 227*23794becSDaniel Golle * Mask for bridge_port_map 228*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP: 229*23794becSDaniel Golle * Mask for mc_dest_ip_lookup_disable 230*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP: 231*23794becSDaniel Golle * Mask for mc_src_ip_lookup_enable 232*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP: 233*23794becSDaniel Golle * Mask for dest_mac_lookup_disable 234*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING: 235*23794becSDaniel Golle * Mask for src_mac_learning_disable 236*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING: 237*23794becSDaniel Golle * Mask for mac_spoofing_detect_enable 238*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK: 239*23794becSDaniel Golle * Mask for port_lock_enable 240*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT: 241*23794becSDaniel Golle * Mask for mac_learning_limit_enable and mac_learning_limit 242*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT: 243*23794becSDaniel Golle * Mask for mac_learning_count 244*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER: 245*23794becSDaniel Golle * Mask for ingress_vlan_filter_enable, ingress_vlan_filter_block_id 246*23794becSDaniel Golle * and ingress_vlan_filter_block_size 247*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1: 248*23794becSDaniel Golle * Mask for bypass_egress_vlan_filter1, egress_vlan_filter1enable, 249*23794becSDaniel Golle * egress_vlan_filter1block_id and egress_vlan_filter1block_size 250*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2: 251*23794becSDaniel Golle * Mask for egress_vlan_filter2enable, egress_vlan_filter2block_id and 252*23794becSDaniel Golle * egress_vlan_filter2block_size 253*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING: 254*23794becSDaniel Golle * Mask for vlan_tag_selection, vlan_src_mac_priority_enable, 255*23794becSDaniel Golle * vlan_src_mac_dei_enable, vlan_src_mac_vid_enable, 256*23794becSDaniel Golle * vlan_dst_mac_priority_enable, vlan_dst_mac_dei_enable and 257*23794becSDaniel Golle * vlan_dst_mac_vid_enable 258*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP: 259*23794becSDaniel Golle * Mask for vlan_multicast_priority_enable, 260*23794becSDaniel Golle * vlan_multicast_dei_enable and vlan_multicast_vid_enable 261*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER: 262*23794becSDaniel Golle * Mask for loop_violation_count 263*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL: Enable all 264*23794becSDaniel Golle * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE: Bypass any check for debug purpose 265*23794becSDaniel Golle */ 266*23794becSDaniel Golle enum mxl862xx_bridge_port_config_mask { 267*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID = BIT(0), 268*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN = BIT(1), 269*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN = BIT(2), 270*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING = BIT(3), 271*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING = BIT(4), 272*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER = BIT(5), 273*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER = BIT(6), 274*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING = BIT(7), 275*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP = BIT(8), 276*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP = BIT(9), 277*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP = BIT(10), 278*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP = BIT(11), 279*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING = BIT(12), 280*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING = BIT(13), 281*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK = BIT(14), 282*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(15), 283*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(16), 284*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER = BIT(17), 285*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1 = BIT(18), 286*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2 = BIT(19), 287*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING = BIT(20), 288*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP = BIT(21), 289*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER = BIT(22), 290*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL = 0x7FFFFFFF, 291*23794becSDaniel Golle MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE = BIT(31) 292*23794becSDaniel Golle }; 293*23794becSDaniel Golle 294*23794becSDaniel Golle /** 295*23794becSDaniel Golle * enum mxl862xx_color_marking_mode - Color Marking Mode 296*23794becSDaniel Golle * @MXL862XX_MARKING_ALL_GREEN: mark packets (except critical) to green 297*23794becSDaniel Golle * @MXL862XX_MARKING_INTERNAL_MARKING: do not change color and priority 298*23794becSDaniel Golle * @MXL862XX_MARKING_DEI: DEI mark mode 299*23794becSDaniel Golle * @MXL862XX_MARKING_PCP_8P0D: PCP 8P0D mark mode 300*23794becSDaniel Golle * @MXL862XX_MARKING_PCP_7P1D: PCP 7P1D mark mode 301*23794becSDaniel Golle * @MXL862XX_MARKING_PCP_6P2D: PCP 6P2D mark mode 302*23794becSDaniel Golle * @MXL862XX_MARKING_PCP_5P3D: PCP 5P3D mark mode 303*23794becSDaniel Golle * @MXL862XX_MARKING_DSCP_AF: DSCP AF class 304*23794becSDaniel Golle */ 305*23794becSDaniel Golle enum mxl862xx_color_marking_mode { 306*23794becSDaniel Golle MXL862XX_MARKING_ALL_GREEN = 0, 307*23794becSDaniel Golle MXL862XX_MARKING_INTERNAL_MARKING, 308*23794becSDaniel Golle MXL862XX_MARKING_DEI, 309*23794becSDaniel Golle MXL862XX_MARKING_PCP_8P0D, 310*23794becSDaniel Golle MXL862XX_MARKING_PCP_7P1D, 311*23794becSDaniel Golle MXL862XX_MARKING_PCP_6P2D, 312*23794becSDaniel Golle MXL862XX_MARKING_PCP_5P3D, 313*23794becSDaniel Golle MXL862XX_MARKING_DSCP_AF, 314*23794becSDaniel Golle }; 315*23794becSDaniel Golle 316*23794becSDaniel Golle /** 317*23794becSDaniel Golle * enum mxl862xx_color_remarking_mode - Color Remarking Mode 318*23794becSDaniel Golle * @MXL862XX_REMARKING_NONE: values from last process stage 319*23794becSDaniel Golle * @MXL862XX_REMARKING_DEI: DEI mark mode 320*23794becSDaniel Golle * @MXL862XX_REMARKING_PCP_8P0D: PCP 8P0D mark mode 321*23794becSDaniel Golle * @MXL862XX_REMARKING_PCP_7P1D: PCP 7P1D mark mode 322*23794becSDaniel Golle * @MXL862XX_REMARKING_PCP_6P2D: PCP 6P2D mark mode 323*23794becSDaniel Golle * @MXL862XX_REMARKING_PCP_5P3D: PCP 5P3D mark mode 324*23794becSDaniel Golle * @MXL862XX_REMARKING_DSCP_AF: DSCP AF class 325*23794becSDaniel Golle */ 326*23794becSDaniel Golle enum mxl862xx_color_remarking_mode { 327*23794becSDaniel Golle MXL862XX_REMARKING_NONE = 0, 328*23794becSDaniel Golle MXL862XX_REMARKING_DEI = 2, 329*23794becSDaniel Golle MXL862XX_REMARKING_PCP_8P0D, 330*23794becSDaniel Golle MXL862XX_REMARKING_PCP_7P1D, 331*23794becSDaniel Golle MXL862XX_REMARKING_PCP_6P2D, 332*23794becSDaniel Golle MXL862XX_REMARKING_PCP_5P3D, 333*23794becSDaniel Golle MXL862XX_REMARKING_DSCP_AF, 334*23794becSDaniel Golle }; 335*23794becSDaniel Golle 336*23794becSDaniel Golle /** 337*23794becSDaniel Golle * enum mxl862xx_pmapper_mapping_mode - P-mapper Mapping Mode 338*23794becSDaniel Golle * @MXL862XX_PMAPPER_MAPPING_PCP: Use PCP for VLAN tagged packets to derive 339*23794becSDaniel Golle * sub interface ID group 340*23794becSDaniel Golle * @MXL862XX_PMAPPER_MAPPING_LAG: Use LAG Index for Pmapper access 341*23794becSDaniel Golle * regardless of IP and VLAN packet 342*23794becSDaniel Golle * @MXL862XX_PMAPPER_MAPPING_DSCP: Use DSCP for VLAN tagged IP packets to 343*23794becSDaniel Golle * derive sub interface ID group 344*23794becSDaniel Golle */ 345*23794becSDaniel Golle enum mxl862xx_pmapper_mapping_mode { 346*23794becSDaniel Golle MXL862XX_PMAPPER_MAPPING_PCP = 0, 347*23794becSDaniel Golle MXL862XX_PMAPPER_MAPPING_LAG, 348*23794becSDaniel Golle MXL862XX_PMAPPER_MAPPING_DSCP, 349*23794becSDaniel Golle }; 350*23794becSDaniel Golle 351*23794becSDaniel Golle /** 352*23794becSDaniel Golle * struct mxl862xx_pmapper - P-mapper Configuration 353*23794becSDaniel Golle * @pmapper_id: Index of P-mapper (0-31) 354*23794becSDaniel Golle * @dest_sub_if_id_group: Sub interface ID group. Entry 0 is for non-IP and 355*23794becSDaniel Golle * non-VLAN tagged packets. 356*23794becSDaniel Golle * Entries 1-8 are PCP mapping entries for VLAN tagged 357*23794becSDaniel Golle * packets. 358*23794becSDaniel Golle * Entries 9-72 are DSCP or LAG mapping entries. 359*23794becSDaniel Golle * 360*23794becSDaniel Golle * Used by CTP port config and bridge port config. In case of LAG, it is 361*23794becSDaniel Golle * user's responsibility to provide the mapped entries in given P-mapper 362*23794becSDaniel Golle * table. In other modes the entries are auto mapped from input packet. 363*23794becSDaniel Golle */ 364*23794becSDaniel Golle struct mxl862xx_pmapper { 365*23794becSDaniel Golle __le16 pmapper_id; 366*23794becSDaniel Golle u8 dest_sub_if_id_group[73]; 367*23794becSDaniel Golle } __packed; 368*23794becSDaniel Golle 369*23794becSDaniel Golle /** 370*23794becSDaniel Golle * struct mxl862xx_bridge_port_config - Bridge Port Configuration 371*23794becSDaniel Golle * @bridge_port_id: Bridge Port ID allocated by bridge port allocation 372*23794becSDaniel Golle * @mask: See &enum mxl862xx_bridge_port_config_mask 373*23794becSDaniel Golle * @bridge_id: Bridge ID (FID) to which this bridge port is associated 374*23794becSDaniel Golle * @ingress_extended_vlan_enable: Enable extended VLAN processing for 375*23794becSDaniel Golle * ingress traffic 376*23794becSDaniel Golle * @ingress_extended_vlan_block_id: Extended VLAN block allocated for 377*23794becSDaniel Golle * ingress traffic 378*23794becSDaniel Golle * @ingress_extended_vlan_block_size: Extended VLAN block size for ingress 379*23794becSDaniel Golle * traffic 380*23794becSDaniel Golle * @egress_extended_vlan_enable: Enable extended VLAN processing for egress 381*23794becSDaniel Golle * traffic 382*23794becSDaniel Golle * @egress_extended_vlan_block_id: Extended VLAN block allocated for egress 383*23794becSDaniel Golle * traffic 384*23794becSDaniel Golle * @egress_extended_vlan_block_size: Extended VLAN block size for egress 385*23794becSDaniel Golle * traffic 386*23794becSDaniel Golle * @ingress_marking_mode: Ingress color marking mode. See 387*23794becSDaniel Golle * &enum mxl862xx_color_marking_mode 388*23794becSDaniel Golle * @egress_remarking_mode: Color remarking for egress traffic. See 389*23794becSDaniel Golle * &enum mxl862xx_color_remarking_mode 390*23794becSDaniel Golle * @ingress_metering_enable: Traffic metering on ingress traffic applies 391*23794becSDaniel Golle * @ingress_traffic_meter_id: Meter for ingress Bridge Port process 392*23794becSDaniel Golle * @egress_sub_metering_enable: Traffic metering on various types of egress 393*23794becSDaniel Golle * traffic 394*23794becSDaniel Golle * @egress_traffic_sub_meter_id: Meter for egress Bridge Port process with 395*23794becSDaniel Golle * specific type 396*23794becSDaniel Golle * @dest_logical_port_id: Destination logical port 397*23794becSDaniel Golle * @pmapper_enable: Enable P-mapper 398*23794becSDaniel Golle * @dest_sub_if_id_group: Destination sub interface ID group when 399*23794becSDaniel Golle * pmapper_enable is false 400*23794becSDaniel Golle * @pmapper_mapping_mode: P-mapper mapping mode. See 401*23794becSDaniel Golle * &enum mxl862xx_pmapper_mapping_mode 402*23794becSDaniel Golle * @pmapper_id_valid: When true, P-mapper is re-used; when false, 403*23794becSDaniel Golle * allocation is handled by API 404*23794becSDaniel Golle * @pmapper: P-mapper configuration used when pmapper_enable is true 405*23794becSDaniel Golle * @bridge_port_map: Port map defining broadcast domain. Each bit 406*23794becSDaniel Golle * represents one bridge port. Bridge port ID is 407*23794becSDaniel Golle * index * 16 + bit offset. 408*23794becSDaniel Golle * @mc_dest_ip_lookup_disable: Disable multicast IP destination table 409*23794becSDaniel Golle * lookup 410*23794becSDaniel Golle * @mc_src_ip_lookup_enable: Enable multicast IP source table lookup 411*23794becSDaniel Golle * @dest_mac_lookup_disable: Disable destination MAC lookup; packet treated 412*23794becSDaniel Golle * as unknown 413*23794becSDaniel Golle * @src_mac_learning_disable: Disable source MAC address learning 414*23794becSDaniel Golle * @mac_spoofing_detect_enable: Enable MAC spoofing detection 415*23794becSDaniel Golle * @port_lock_enable: Enable port locking 416*23794becSDaniel Golle * @mac_learning_limit_enable: Enable MAC learning limitation 417*23794becSDaniel Golle * @mac_learning_limit: Maximum number of MAC addresses that can be learned 418*23794becSDaniel Golle * from this bridge port 419*23794becSDaniel Golle * @loop_violation_count: Number of loop violation events from this bridge 420*23794becSDaniel Golle * port 421*23794becSDaniel Golle * @mac_learning_count: Number of MAC addresses learned from this bridge 422*23794becSDaniel Golle * port 423*23794becSDaniel Golle * @ingress_vlan_filter_enable: Enable ingress VLAN filter 424*23794becSDaniel Golle * @ingress_vlan_filter_block_id: VLAN filter block of ingress traffic 425*23794becSDaniel Golle * @ingress_vlan_filter_block_size: VLAN filter block size for ingress 426*23794becSDaniel Golle * traffic 427*23794becSDaniel Golle * @bypass_egress_vlan_filter1: For ingress traffic, bypass VLAN filter 1 428*23794becSDaniel Golle * at egress bridge port processing 429*23794becSDaniel Golle * @egress_vlan_filter1enable: Enable egress VLAN filter 1 430*23794becSDaniel Golle * @egress_vlan_filter1block_id: VLAN filter block 1 of egress traffic 431*23794becSDaniel Golle * @egress_vlan_filter1block_size: VLAN filter block 1 size 432*23794becSDaniel Golle * @egress_vlan_filter2enable: Enable egress VLAN filter 2 433*23794becSDaniel Golle * @egress_vlan_filter2block_id: VLAN filter block 2 of egress traffic 434*23794becSDaniel Golle * @egress_vlan_filter2block_size: VLAN filter block 2 size 435*23794becSDaniel Golle * @vlan_tag_selection: VLAN tag selection for MAC address/multicast 436*23794becSDaniel Golle * learning, lookup and filtering. 437*23794becSDaniel Golle * 0 - Intermediate outer VLAN tag is used. 438*23794becSDaniel Golle * 1 - Original outer VLAN tag is used. 439*23794becSDaniel Golle * @vlan_src_mac_priority_enable: Enable VLAN Priority field for source MAC 440*23794becSDaniel Golle * learning and filtering 441*23794becSDaniel Golle * @vlan_src_mac_dei_enable: Enable VLAN DEI/CFI field for source MAC 442*23794becSDaniel Golle * learning and filtering 443*23794becSDaniel Golle * @vlan_src_mac_vid_enable: Enable VLAN ID field for source MAC learning 444*23794becSDaniel Golle * and filtering 445*23794becSDaniel Golle * @vlan_dst_mac_priority_enable: Enable VLAN Priority field for destination 446*23794becSDaniel Golle * MAC lookup and filtering 447*23794becSDaniel Golle * @vlan_dst_mac_dei_enable: Enable VLAN CFI/DEI field for destination MAC 448*23794becSDaniel Golle * lookup and filtering 449*23794becSDaniel Golle * @vlan_dst_mac_vid_enable: Enable VLAN ID field for destination MAC lookup 450*23794becSDaniel Golle * and filtering 451*23794becSDaniel Golle * @vlan_multicast_priority_enable: Enable VLAN Priority field for IP 452*23794becSDaniel Golle * multicast lookup 453*23794becSDaniel Golle * @vlan_multicast_dei_enable: Enable VLAN CFI/DEI field for IP multicast 454*23794becSDaniel Golle * lookup 455*23794becSDaniel Golle * @vlan_multicast_vid_enable: Enable VLAN ID field for IP multicast lookup 456*23794becSDaniel Golle */ 457*23794becSDaniel Golle struct mxl862xx_bridge_port_config { 458*23794becSDaniel Golle __le16 bridge_port_id; 459*23794becSDaniel Golle __le32 mask; /* enum mxl862xx_bridge_port_config_mask */ 460*23794becSDaniel Golle __le16 bridge_id; 461*23794becSDaniel Golle u8 ingress_extended_vlan_enable; 462*23794becSDaniel Golle __le16 ingress_extended_vlan_block_id; 463*23794becSDaniel Golle __le16 ingress_extended_vlan_block_size; 464*23794becSDaniel Golle u8 egress_extended_vlan_enable; 465*23794becSDaniel Golle __le16 egress_extended_vlan_block_id; 466*23794becSDaniel Golle __le16 egress_extended_vlan_block_size; 467*23794becSDaniel Golle __le32 ingress_marking_mode; /* enum mxl862xx_color_marking_mode */ 468*23794becSDaniel Golle __le32 egress_remarking_mode; /* enum mxl862xx_color_remarking_mode */ 469*23794becSDaniel Golle u8 ingress_metering_enable; 470*23794becSDaniel Golle __le16 ingress_traffic_meter_id; 471*23794becSDaniel Golle u8 egress_sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 472*23794becSDaniel Golle __le16 egress_traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 473*23794becSDaniel Golle u8 dest_logical_port_id; 474*23794becSDaniel Golle u8 pmapper_enable; 475*23794becSDaniel Golle __le16 dest_sub_if_id_group; 476*23794becSDaniel Golle __le32 pmapper_mapping_mode; /* enum mxl862xx_pmapper_mapping_mode */ 477*23794becSDaniel Golle u8 pmapper_id_valid; 478*23794becSDaniel Golle struct mxl862xx_pmapper pmapper; 479*23794becSDaniel Golle __le16 bridge_port_map[8]; 480*23794becSDaniel Golle u8 mc_dest_ip_lookup_disable; 481*23794becSDaniel Golle u8 mc_src_ip_lookup_enable; 482*23794becSDaniel Golle u8 dest_mac_lookup_disable; 483*23794becSDaniel Golle u8 src_mac_learning_disable; 484*23794becSDaniel Golle u8 mac_spoofing_detect_enable; 485*23794becSDaniel Golle u8 port_lock_enable; 486*23794becSDaniel Golle u8 mac_learning_limit_enable; 487*23794becSDaniel Golle __le16 mac_learning_limit; 488*23794becSDaniel Golle __le16 loop_violation_count; 489*23794becSDaniel Golle __le16 mac_learning_count; 490*23794becSDaniel Golle u8 ingress_vlan_filter_enable; 491*23794becSDaniel Golle __le16 ingress_vlan_filter_block_id; 492*23794becSDaniel Golle __le16 ingress_vlan_filter_block_size; 493*23794becSDaniel Golle u8 bypass_egress_vlan_filter1; 494*23794becSDaniel Golle u8 egress_vlan_filter1enable; 495*23794becSDaniel Golle __le16 egress_vlan_filter1block_id; 496*23794becSDaniel Golle __le16 egress_vlan_filter1block_size; 497*23794becSDaniel Golle u8 egress_vlan_filter2enable; 498*23794becSDaniel Golle __le16 egress_vlan_filter2block_id; 499*23794becSDaniel Golle __le16 egress_vlan_filter2block_size; 500*23794becSDaniel Golle u8 vlan_tag_selection; 501*23794becSDaniel Golle u8 vlan_src_mac_priority_enable; 502*23794becSDaniel Golle u8 vlan_src_mac_dei_enable; 503*23794becSDaniel Golle u8 vlan_src_mac_vid_enable; 504*23794becSDaniel Golle u8 vlan_dst_mac_priority_enable; 505*23794becSDaniel Golle u8 vlan_dst_mac_dei_enable; 506*23794becSDaniel Golle u8 vlan_dst_mac_vid_enable; 507*23794becSDaniel Golle u8 vlan_multicast_priority_enable; 508*23794becSDaniel Golle u8 vlan_multicast_dei_enable; 509*23794becSDaniel Golle u8 vlan_multicast_vid_enable; 510*23794becSDaniel Golle } __packed; 511*23794becSDaniel Golle 512*23794becSDaniel Golle /** 513*23794becSDaniel Golle * struct mxl862xx_cfg - Global Switch configuration Attributes 514*23794becSDaniel Golle * @mac_table_age_timer: See &enum mxl862xx_age_timer 515*23794becSDaniel Golle * @age_timer: Custom MAC table aging timer in seconds 516*23794becSDaniel Golle * @max_packet_len: Maximum Ethernet packet length 517*23794becSDaniel Golle * @learning_limit_action: Automatic MAC address table learning limitation 518*23794becSDaniel Golle * consecutive action 519*23794becSDaniel Golle * @mac_locking_action: Accept or discard MAC port locking violation 520*23794becSDaniel Golle * packets 521*23794becSDaniel Golle * @mac_spoofing_action: Accept or discard MAC spoofing and port MAC locking 522*23794becSDaniel Golle * violation packets 523*23794becSDaniel Golle * @pause_mac_mode_src: Pause frame MAC source address mode 524*23794becSDaniel Golle * @pause_mac_src: Pause frame MAC source address 525*23794becSDaniel Golle */ 526*23794becSDaniel Golle struct mxl862xx_cfg { 527*23794becSDaniel Golle __le32 mac_table_age_timer; /* enum mxl862xx_age_timer */ 528*23794becSDaniel Golle __le32 age_timer; 529*23794becSDaniel Golle __le16 max_packet_len; 530*23794becSDaniel Golle u8 learning_limit_action; 531*23794becSDaniel Golle u8 mac_locking_action; 532*23794becSDaniel Golle u8 mac_spoofing_action; 533*23794becSDaniel Golle u8 pause_mac_mode_src; 534*23794becSDaniel Golle u8 pause_mac_src[ETH_ALEN]; 535*23794becSDaniel Golle } __packed; 536*23794becSDaniel Golle 537*23794becSDaniel Golle /** 538*23794becSDaniel Golle * enum mxl862xx_ss_sp_tag_mask - Special tag valid field indicator bits 539*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_MASK_RX: valid RX special tag mode 540*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_MASK_TX: valid TX special tag mode 541*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_MASK_RX_PEN: valid RX special tag info over preamble 542*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_MASK_TX_PEN: valid TX special tag info over preamble 543*23794becSDaniel Golle */ 544*23794becSDaniel Golle enum mxl862xx_ss_sp_tag_mask { 545*23794becSDaniel Golle MXL862XX_SS_SP_TAG_MASK_RX = BIT(0), 546*23794becSDaniel Golle MXL862XX_SS_SP_TAG_MASK_TX = BIT(1), 547*23794becSDaniel Golle MXL862XX_SS_SP_TAG_MASK_RX_PEN = BIT(2), 548*23794becSDaniel Golle MXL862XX_SS_SP_TAG_MASK_TX_PEN = BIT(3), 549*23794becSDaniel Golle }; 550*23794becSDaniel Golle 551*23794becSDaniel Golle /** 552*23794becSDaniel Golle * enum mxl862xx_ss_sp_tag_rx - RX special tag mode 553*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT: packet does NOT have special 554*23794becSDaniel Golle * tag and special tag is NOT inserted 555*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT: packet does NOT have special tag 556*23794becSDaniel Golle * and special tag is inserted 557*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT: packet has special tag and special 558*23794becSDaniel Golle * tag is NOT inserted 559*23794becSDaniel Golle */ 560*23794becSDaniel Golle enum mxl862xx_ss_sp_tag_rx { 561*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT = 0, 562*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT = 1, 563*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT = 2, 564*23794becSDaniel Golle }; 565*23794becSDaniel Golle 566*23794becSDaniel Golle /** 567*23794becSDaniel Golle * enum mxl862xx_ss_sp_tag_tx - TX special tag mode 568*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE: packet does NOT have special 569*23794becSDaniel Golle * tag and special tag is NOT removed 570*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_TX_TAG_REPLACE: packet has special tag and special 571*23794becSDaniel Golle * tag is replaced 572*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE: packet has special tag and special 573*23794becSDaniel Golle * tag is NOT removed 574*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_TX_TAG_REMOVE: packet has special tag and special 575*23794becSDaniel Golle * tag is removed 576*23794becSDaniel Golle */ 577*23794becSDaniel Golle enum mxl862xx_ss_sp_tag_tx { 578*23794becSDaniel Golle MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE = 0, 579*23794becSDaniel Golle MXL862XX_SS_SP_TAG_TX_TAG_REPLACE = 1, 580*23794becSDaniel Golle MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE = 2, 581*23794becSDaniel Golle MXL862XX_SS_SP_TAG_TX_TAG_REMOVE = 3, 582*23794becSDaniel Golle }; 583*23794becSDaniel Golle 584*23794becSDaniel Golle /** 585*23794becSDaniel Golle * enum mxl862xx_ss_sp_tag_rx_pen - RX special tag info over preamble 586*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_PEN_ALL_0: special tag info inserted from byte 2 587*23794becSDaniel Golle * to 7 are all 0 588*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16: special tag byte 5 is 16, other 589*23794becSDaniel Golle * bytes from 2 to 7 are 0 590*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE: special tag byte 5 is 591*23794becSDaniel Golle * from preamble field, others 592*23794becSDaniel Golle * are 0 593*23794becSDaniel Golle * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE: special tag byte 2 594*23794becSDaniel Golle * to 7 are from preamble 595*23794becSDaniel Golle * field 596*23794becSDaniel Golle */ 597*23794becSDaniel Golle enum mxl862xx_ss_sp_tag_rx_pen { 598*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_PEN_ALL_0 = 0, 599*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16 = 1, 600*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE = 2, 601*23794becSDaniel Golle MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE = 3, 602*23794becSDaniel Golle }; 603*23794becSDaniel Golle 604*23794becSDaniel Golle /** 605*23794becSDaniel Golle * struct mxl862xx_ss_sp_tag - Special tag port settings 606*23794becSDaniel Golle * @pid: port ID (1~16) 607*23794becSDaniel Golle * @mask: See &enum mxl862xx_ss_sp_tag_mask 608*23794becSDaniel Golle * @rx: See &enum mxl862xx_ss_sp_tag_rx 609*23794becSDaniel Golle * @tx: See &enum mxl862xx_ss_sp_tag_tx 610*23794becSDaniel Golle * @rx_pen: See &enum mxl862xx_ss_sp_tag_rx_pen 611*23794becSDaniel Golle * @tx_pen: TX special tag info over preamble 612*23794becSDaniel Golle * 0 - disabled 613*23794becSDaniel Golle * 1 - enabled 614*23794becSDaniel Golle */ 615*23794becSDaniel Golle struct mxl862xx_ss_sp_tag { 616*23794becSDaniel Golle u8 pid; 617*23794becSDaniel Golle u8 mask; /* enum mxl862xx_ss_sp_tag_mask */ 618*23794becSDaniel Golle u8 rx; /* enum mxl862xx_ss_sp_tag_rx */ 619*23794becSDaniel Golle u8 tx; /* enum mxl862xx_ss_sp_tag_tx */ 620*23794becSDaniel Golle u8 rx_pen; /* enum mxl862xx_ss_sp_tag_rx_pen */ 621*23794becSDaniel Golle u8 tx_pen; /* boolean */ 622*23794becSDaniel Golle } __packed; 623*23794becSDaniel Golle 624*23794becSDaniel Golle /** 625*23794becSDaniel Golle * enum mxl862xx_logical_port_mode - Logical port mode 626*23794becSDaniel Golle * @MXL862XX_LOGICAL_PORT_8BIT_WLAN: WLAN with 8-bit station ID 627*23794becSDaniel Golle * @MXL862XX_LOGICAL_PORT_9BIT_WLAN: WLAN with 9-bit station ID 628*23794becSDaniel Golle * @MXL862XX_LOGICAL_PORT_ETHERNET: Ethernet port 629*23794becSDaniel Golle * @MXL862XX_LOGICAL_PORT_OTHER: Others 630*23794becSDaniel Golle */ 631*23794becSDaniel Golle enum mxl862xx_logical_port_mode { 632*23794becSDaniel Golle MXL862XX_LOGICAL_PORT_8BIT_WLAN = 0, 633*23794becSDaniel Golle MXL862XX_LOGICAL_PORT_9BIT_WLAN, 634*23794becSDaniel Golle MXL862XX_LOGICAL_PORT_ETHERNET, 635*23794becSDaniel Golle MXL862XX_LOGICAL_PORT_OTHER = 0xFF, 636*23794becSDaniel Golle }; 637*23794becSDaniel Golle 638*23794becSDaniel Golle /** 639*23794becSDaniel Golle * struct mxl862xx_ctp_port_assignment - CTP Port Assignment/association 640*23794becSDaniel Golle * with logical port 641*23794becSDaniel Golle * @logical_port_id: Logical Port Id. The valid range is hardware dependent 642*23794becSDaniel Golle * @first_ctp_port_id: First CTP (Connectivity Termination Port) ID mapped 643*23794becSDaniel Golle * to above logical port ID 644*23794becSDaniel Golle * @number_of_ctp_port: Total number of CTP Ports mapped above logical port 645*23794becSDaniel Golle * ID 646*23794becSDaniel Golle * @mode: Logical port mode to define sub interface ID format. See 647*23794becSDaniel Golle * &enum mxl862xx_logical_port_mode 648*23794becSDaniel Golle * @bridge_port_id: Bridge Port ID (not FID). For allocation, each CTP 649*23794becSDaniel Golle * allocated is mapped to the Bridge Port given by this field. 650*23794becSDaniel Golle * The Bridge Port will be configured to use first CTP as 651*23794becSDaniel Golle * egress CTP. 652*23794becSDaniel Golle */ 653*23794becSDaniel Golle struct mxl862xx_ctp_port_assignment { 654*23794becSDaniel Golle u8 logical_port_id; 655*23794becSDaniel Golle __le16 first_ctp_port_id; 656*23794becSDaniel Golle __le16 number_of_ctp_port; 657*23794becSDaniel Golle __le32 mode; /* enum mxl862xx_logical_port_mode */ 658*23794becSDaniel Golle __le16 bridge_port_id; 659*23794becSDaniel Golle } __packed; 660*23794becSDaniel Golle 661*23794becSDaniel Golle /** 662*23794becSDaniel Golle * struct mxl862xx_sys_fw_image_version - Firmware version information 663*23794becSDaniel Golle * @iv_major: firmware major version 664*23794becSDaniel Golle * @iv_minor: firmware minor version 665*23794becSDaniel Golle * @iv_revision: firmware revision 666*23794becSDaniel Golle * @iv_build_num: firmware build number 667*23794becSDaniel Golle */ 668*23794becSDaniel Golle struct mxl862xx_sys_fw_image_version { 669*23794becSDaniel Golle u8 iv_major; 670*23794becSDaniel Golle u8 iv_minor; 671*23794becSDaniel Golle __le16 iv_revision; 672*23794becSDaniel Golle __le32 iv_build_num; 673*23794becSDaniel Golle } __packed; 674*23794becSDaniel Golle 675*23794becSDaniel Golle #endif /* __MXL862XX_API_H */ 676