1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __MXL862XX_API_H 4 #define __MXL862XX_API_H 5 6 #include <linux/if_ether.h> 7 8 /** 9 * struct mdio_relay_data - relayed access to the switch internal MDIO bus 10 * @data: data to be read or written 11 * @phy: PHY index 12 * @mmd: MMD device 13 * @reg: register index 14 */ 15 struct mdio_relay_data { 16 __le16 data; 17 u8 phy; 18 u8 mmd; 19 __le16 reg; 20 } __packed; 21 22 /** 23 * struct mxl862xx_register_mod - Register access parameter to directly 24 * modify internal registers 25 * @addr: Register address offset for modification 26 * @data: Value to write to the register address 27 * @mask: Mask of bits to be modified (1 to modify, 0 to ignore) 28 * 29 * Used for direct register modification operations. 30 */ 31 struct mxl862xx_register_mod { 32 __le16 addr; 33 __le16 data; 34 __le16 mask; 35 } __packed; 36 37 /** 38 * enum mxl862xx_mac_clear_type - MAC table clear type 39 * @MXL862XX_MAC_CLEAR_PHY_PORT: clear dynamic entries based on port_id 40 * @MXL862XX_MAC_CLEAR_DYNAMIC: clear all dynamic entries 41 */ 42 enum mxl862xx_mac_clear_type { 43 MXL862XX_MAC_CLEAR_PHY_PORT = 0, 44 MXL862XX_MAC_CLEAR_DYNAMIC, 45 }; 46 47 /** 48 * struct mxl862xx_mac_table_clear - MAC table clear 49 * @type: see &enum mxl862xx_mac_clear_type 50 * @port_id: physical port id 51 */ 52 struct mxl862xx_mac_table_clear { 53 u8 type; 54 u8 port_id; 55 } __packed; 56 57 /** 58 * enum mxl862xx_age_timer - Aging Timer Value. 59 * @MXL862XX_AGETIMER_1_SEC: 1 second aging time 60 * @MXL862XX_AGETIMER_10_SEC: 10 seconds aging time 61 * @MXL862XX_AGETIMER_300_SEC: 300 seconds aging time 62 * @MXL862XX_AGETIMER_1_HOUR: 1 hour aging time 63 * @MXL862XX_AGETIMER_1_DAY: 24 hours aging time 64 * @MXL862XX_AGETIMER_CUSTOM: Custom aging time in seconds 65 */ 66 enum mxl862xx_age_timer { 67 MXL862XX_AGETIMER_1_SEC = 1, 68 MXL862XX_AGETIMER_10_SEC, 69 MXL862XX_AGETIMER_300_SEC, 70 MXL862XX_AGETIMER_1_HOUR, 71 MXL862XX_AGETIMER_1_DAY, 72 MXL862XX_AGETIMER_CUSTOM, 73 }; 74 75 /** 76 * struct mxl862xx_bridge_alloc - Bridge Allocation 77 * @bridge_id: If the bridge allocation is successful, a valid ID will be 78 * returned in this field. Otherwise, INVALID_HANDLE is 79 * returned. For bridge free, this field should contain a 80 * valid ID returned by the bridge allocation. ID 0 is not 81 * used for historic reasons. 82 * 83 * Used by MXL862XX_BRIDGE_ALLOC and MXL862XX_BRIDGE_FREE. 84 */ 85 struct mxl862xx_bridge_alloc { 86 __le16 bridge_id; 87 }; 88 89 /** 90 * enum mxl862xx_bridge_config_mask - Bridge configuration mask 91 * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT: 92 * Mask for mac_learning_limit_enable and mac_learning_limit. 93 * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT: 94 * Mask for mac_learning_count 95 * @MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT: 96 * Mask for learning_discard_event 97 * @MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER: 98 * Mask for sub_metering_enable and traffic_sub_meter_id 99 * @MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE: 100 * Mask for forward_broadcast, forward_unknown_multicast_ip, 101 * forward_unknown_multicast_non_ip and forward_unknown_unicast. 102 * @MXL862XX_BRIDGE_CONFIG_MASK_ALL: Enable all 103 * @MXL862XX_BRIDGE_CONFIG_MASK_FORCE: Bypass any check for debug purpose 104 */ 105 enum mxl862xx_bridge_config_mask { 106 MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(0), 107 MXL862XX_BRIDGE_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(1), 108 MXL862XX_BRIDGE_CONFIG_MASK_MAC_DISCARD_COUNT = BIT(2), 109 MXL862XX_BRIDGE_CONFIG_MASK_SUB_METER = BIT(3), 110 MXL862XX_BRIDGE_CONFIG_MASK_FORWARDING_MODE = BIT(4), 111 MXL862XX_BRIDGE_CONFIG_MASK_ALL = 0x7FFFFFFF, 112 MXL862XX_BRIDGE_CONFIG_MASK_FORCE = BIT(31) 113 }; 114 115 /** 116 * enum mxl862xx_bridge_port_egress_meter - Meters for egress traffic type 117 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST: 118 * Index of broadcast traffic meter 119 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST: 120 * Index of known multicast traffic meter 121 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP: 122 * Index of unknown multicast IP traffic meter 123 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP: 124 * Index of unknown multicast non-IP traffic meter 125 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC: 126 * Index of unknown unicast traffic meter 127 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS: 128 * Index of traffic meter for other types 129 * @MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX: Number of index 130 */ 131 enum mxl862xx_bridge_port_egress_meter { 132 MXL862XX_BRIDGE_PORT_EGRESS_METER_BROADCAST = 0, 133 MXL862XX_BRIDGE_PORT_EGRESS_METER_MULTICAST, 134 MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_IP, 135 MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_MC_NON_IP, 136 MXL862XX_BRIDGE_PORT_EGRESS_METER_UNKNOWN_UC, 137 MXL862XX_BRIDGE_PORT_EGRESS_METER_OTHERS, 138 MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX, 139 }; 140 141 /** 142 * enum mxl862xx_bridge_forward_mode - Bridge forwarding type of packet 143 * @MXL862XX_BRIDGE_FORWARD_FLOOD: Packet is flooded to port members of 144 * ingress bridge port 145 * @MXL862XX_BRIDGE_FORWARD_DISCARD: Packet is discarded 146 */ 147 enum mxl862xx_bridge_forward_mode { 148 MXL862XX_BRIDGE_FORWARD_FLOOD = 0, 149 MXL862XX_BRIDGE_FORWARD_DISCARD, 150 }; 151 152 /** 153 * struct mxl862xx_bridge_config - Bridge Configuration 154 * @bridge_id: Bridge ID (FID) 155 * @mask: See &enum mxl862xx_bridge_config_mask 156 * @mac_learning_limit_enable: Enable MAC learning limitation 157 * @mac_learning_limit: Max number of MAC addresses that can be learned in 158 * this bridge (all bridge ports) 159 * @mac_learning_count: Number of MAC addresses learned from this bridge 160 * @learning_discard_event: Number of learning discard events due to 161 * hardware resource not available 162 * @sub_metering_enable: Traffic metering on type of traffic (such as 163 * broadcast, multicast, unknown unicast, etc) applies 164 * @traffic_sub_meter_id: Meter for bridge process with specific type (such 165 * as broadcast, multicast, unknown unicast, etc) 166 * @forward_broadcast: Forwarding mode of broadcast traffic. See 167 * &enum mxl862xx_bridge_forward_mode 168 * @forward_unknown_multicast_ip: Forwarding mode of unknown multicast IP 169 * traffic. 170 * See &enum mxl862xx_bridge_forward_mode 171 * @forward_unknown_multicast_non_ip: Forwarding mode of unknown multicast 172 * non-IP traffic. 173 * See &enum mxl862xx_bridge_forward_mode 174 * @forward_unknown_unicast: Forwarding mode of unknown unicast traffic. See 175 * &enum mxl862xx_bridge_forward_mode 176 */ 177 struct mxl862xx_bridge_config { 178 __le16 bridge_id; 179 __le32 mask; /* enum mxl862xx_bridge_config_mask */ 180 u8 mac_learning_limit_enable; 181 __le16 mac_learning_limit; 182 __le16 mac_learning_count; 183 __le32 learning_discard_event; 184 u8 sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 185 __le16 traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 186 __le32 forward_broadcast; /* enum mxl862xx_bridge_forward_mode */ 187 __le32 forward_unknown_multicast_ip; /* enum mxl862xx_bridge_forward_mode */ 188 __le32 forward_unknown_multicast_non_ip; /* enum mxl862xx_bridge_forward_mode */ 189 __le32 forward_unknown_unicast; /* enum mxl862xx_bridge_forward_mode */ 190 } __packed; 191 192 /** 193 * struct mxl862xx_bridge_port_alloc - Bridge Port Allocation 194 * @bridge_port_id: If the bridge port allocation is successful, a valid ID 195 * will be returned in this field. Otherwise, INVALID_HANDLE 196 * is returned. For bridge port free, this field should 197 * contain a valid ID returned by the bridge port allocation. 198 * 199 * Used by MXL862XX_BRIDGE_PORT_ALLOC and MXL862XX_BRIDGE_PORT_FREE. 200 */ 201 struct mxl862xx_bridge_port_alloc { 202 __le16 bridge_port_id; 203 }; 204 205 /** 206 * enum mxl862xx_bridge_port_config_mask - Bridge Port configuration mask 207 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID: 208 * Mask for bridge_id 209 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN: 210 * Mask for ingress_extended_vlan_enable, 211 * ingress_extended_vlan_block_id and ingress_extended_vlan_block_size 212 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN: 213 * Mask for egress_extended_vlan_enable, egress_extended_vlan_block_id 214 * and egress_extended_vlan_block_size 215 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING: 216 * Mask for ingress_marking_mode 217 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING: 218 * Mask for egress_remarking_mode 219 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER: 220 * Mask for ingress_metering_enable and ingress_traffic_meter_id 221 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER: 222 * Mask for egress_sub_metering_enable and egress_traffic_sub_meter_id 223 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING: 224 * Mask for dest_logical_port_id, pmapper_enable, dest_sub_if_id_group, 225 * pmapper_mapping_mode, pmapper_id_valid and pmapper 226 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP: 227 * Mask for bridge_port_map 228 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP: 229 * Mask for mc_dest_ip_lookup_disable 230 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP: 231 * Mask for mc_src_ip_lookup_enable 232 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP: 233 * Mask for dest_mac_lookup_disable 234 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING: 235 * Mask for src_mac_learning_disable 236 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING: 237 * Mask for mac_spoofing_detect_enable 238 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK: 239 * Mask for port_lock_enable 240 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT: 241 * Mask for mac_learning_limit_enable and mac_learning_limit 242 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT: 243 * Mask for mac_learning_count 244 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER: 245 * Mask for ingress_vlan_filter_enable, ingress_vlan_filter_block_id 246 * and ingress_vlan_filter_block_size 247 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1: 248 * Mask for bypass_egress_vlan_filter1, egress_vlan_filter1enable, 249 * egress_vlan_filter1block_id and egress_vlan_filter1block_size 250 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2: 251 * Mask for egress_vlan_filter2enable, egress_vlan_filter2block_id and 252 * egress_vlan_filter2block_size 253 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING: 254 * Mask for vlan_tag_selection, vlan_src_mac_priority_enable, 255 * vlan_src_mac_dei_enable, vlan_src_mac_vid_enable, 256 * vlan_dst_mac_priority_enable, vlan_dst_mac_dei_enable and 257 * vlan_dst_mac_vid_enable 258 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP: 259 * Mask for vlan_multicast_priority_enable, 260 * vlan_multicast_dei_enable and vlan_multicast_vid_enable 261 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER: 262 * Mask for loop_violation_count 263 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL: Enable all 264 * @MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE: Bypass any check for debug purpose 265 */ 266 enum mxl862xx_bridge_port_config_mask { 267 MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_ID = BIT(0), 268 MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN = BIT(1), 269 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN = BIT(2), 270 MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_MARKING = BIT(3), 271 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_REMARKING = BIT(4), 272 MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_METER = BIT(5), 273 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_SUB_METER = BIT(6), 274 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_CTP_MAPPING = BIT(7), 275 MXL862XX_BRIDGE_PORT_CONFIG_MASK_BRIDGE_PORT_MAP = BIT(8), 276 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_IP_LOOKUP = BIT(9), 277 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_IP_LOOKUP = BIT(10), 278 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_DEST_MAC_LOOKUP = BIT(11), 279 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MC_SRC_MAC_LEARNING = BIT(12), 280 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_SPOOFING = BIT(13), 281 MXL862XX_BRIDGE_PORT_CONFIG_MASK_PORT_LOCK = BIT(14), 282 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNING_LIMIT = BIT(15), 283 MXL862XX_BRIDGE_PORT_CONFIG_MASK_MAC_LEARNED_COUNT = BIT(16), 284 MXL862XX_BRIDGE_PORT_CONFIG_MASK_INGRESS_VLAN_FILTER = BIT(17), 285 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER1 = BIT(18), 286 MXL862XX_BRIDGE_PORT_CONFIG_MASK_EGRESS_VLAN_FILTER2 = BIT(19), 287 MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MAC_LEARNING = BIT(20), 288 MXL862XX_BRIDGE_PORT_CONFIG_MASK_VLAN_BASED_MULTICAST_LOOKUP = BIT(21), 289 MXL862XX_BRIDGE_PORT_CONFIG_MASK_LOOP_VIOLATION_COUNTER = BIT(22), 290 MXL862XX_BRIDGE_PORT_CONFIG_MASK_ALL = 0x7FFFFFFF, 291 MXL862XX_BRIDGE_PORT_CONFIG_MASK_FORCE = BIT(31) 292 }; 293 294 /** 295 * enum mxl862xx_color_marking_mode - Color Marking Mode 296 * @MXL862XX_MARKING_ALL_GREEN: mark packets (except critical) to green 297 * @MXL862XX_MARKING_INTERNAL_MARKING: do not change color and priority 298 * @MXL862XX_MARKING_DEI: DEI mark mode 299 * @MXL862XX_MARKING_PCP_8P0D: PCP 8P0D mark mode 300 * @MXL862XX_MARKING_PCP_7P1D: PCP 7P1D mark mode 301 * @MXL862XX_MARKING_PCP_6P2D: PCP 6P2D mark mode 302 * @MXL862XX_MARKING_PCP_5P3D: PCP 5P3D mark mode 303 * @MXL862XX_MARKING_DSCP_AF: DSCP AF class 304 */ 305 enum mxl862xx_color_marking_mode { 306 MXL862XX_MARKING_ALL_GREEN = 0, 307 MXL862XX_MARKING_INTERNAL_MARKING, 308 MXL862XX_MARKING_DEI, 309 MXL862XX_MARKING_PCP_8P0D, 310 MXL862XX_MARKING_PCP_7P1D, 311 MXL862XX_MARKING_PCP_6P2D, 312 MXL862XX_MARKING_PCP_5P3D, 313 MXL862XX_MARKING_DSCP_AF, 314 }; 315 316 /** 317 * enum mxl862xx_color_remarking_mode - Color Remarking Mode 318 * @MXL862XX_REMARKING_NONE: values from last process stage 319 * @MXL862XX_REMARKING_DEI: DEI mark mode 320 * @MXL862XX_REMARKING_PCP_8P0D: PCP 8P0D mark mode 321 * @MXL862XX_REMARKING_PCP_7P1D: PCP 7P1D mark mode 322 * @MXL862XX_REMARKING_PCP_6P2D: PCP 6P2D mark mode 323 * @MXL862XX_REMARKING_PCP_5P3D: PCP 5P3D mark mode 324 * @MXL862XX_REMARKING_DSCP_AF: DSCP AF class 325 */ 326 enum mxl862xx_color_remarking_mode { 327 MXL862XX_REMARKING_NONE = 0, 328 MXL862XX_REMARKING_DEI = 2, 329 MXL862XX_REMARKING_PCP_8P0D, 330 MXL862XX_REMARKING_PCP_7P1D, 331 MXL862XX_REMARKING_PCP_6P2D, 332 MXL862XX_REMARKING_PCP_5P3D, 333 MXL862XX_REMARKING_DSCP_AF, 334 }; 335 336 /** 337 * enum mxl862xx_pmapper_mapping_mode - P-mapper Mapping Mode 338 * @MXL862XX_PMAPPER_MAPPING_PCP: Use PCP for VLAN tagged packets to derive 339 * sub interface ID group 340 * @MXL862XX_PMAPPER_MAPPING_LAG: Use LAG Index for Pmapper access 341 * regardless of IP and VLAN packet 342 * @MXL862XX_PMAPPER_MAPPING_DSCP: Use DSCP for VLAN tagged IP packets to 343 * derive sub interface ID group 344 */ 345 enum mxl862xx_pmapper_mapping_mode { 346 MXL862XX_PMAPPER_MAPPING_PCP = 0, 347 MXL862XX_PMAPPER_MAPPING_LAG, 348 MXL862XX_PMAPPER_MAPPING_DSCP, 349 }; 350 351 /** 352 * struct mxl862xx_pmapper - P-mapper Configuration 353 * @pmapper_id: Index of P-mapper (0-31) 354 * @dest_sub_if_id_group: Sub interface ID group. Entry 0 is for non-IP and 355 * non-VLAN tagged packets. 356 * Entries 1-8 are PCP mapping entries for VLAN tagged 357 * packets. 358 * Entries 9-72 are DSCP or LAG mapping entries. 359 * 360 * Used by CTP port config and bridge port config. In case of LAG, it is 361 * user's responsibility to provide the mapped entries in given P-mapper 362 * table. In other modes the entries are auto mapped from input packet. 363 */ 364 struct mxl862xx_pmapper { 365 __le16 pmapper_id; 366 u8 dest_sub_if_id_group[73]; 367 } __packed; 368 369 /** 370 * struct mxl862xx_bridge_port_config - Bridge Port Configuration 371 * @bridge_port_id: Bridge Port ID allocated by bridge port allocation 372 * @mask: See &enum mxl862xx_bridge_port_config_mask 373 * @bridge_id: Bridge ID (FID) to which this bridge port is associated 374 * @ingress_extended_vlan_enable: Enable extended VLAN processing for 375 * ingress traffic 376 * @ingress_extended_vlan_block_id: Extended VLAN block allocated for 377 * ingress traffic 378 * @ingress_extended_vlan_block_size: Extended VLAN block size for ingress 379 * traffic 380 * @egress_extended_vlan_enable: Enable extended VLAN processing for egress 381 * traffic 382 * @egress_extended_vlan_block_id: Extended VLAN block allocated for egress 383 * traffic 384 * @egress_extended_vlan_block_size: Extended VLAN block size for egress 385 * traffic 386 * @ingress_marking_mode: Ingress color marking mode. See 387 * &enum mxl862xx_color_marking_mode 388 * @egress_remarking_mode: Color remarking for egress traffic. See 389 * &enum mxl862xx_color_remarking_mode 390 * @ingress_metering_enable: Traffic metering on ingress traffic applies 391 * @ingress_traffic_meter_id: Meter for ingress Bridge Port process 392 * @egress_sub_metering_enable: Traffic metering on various types of egress 393 * traffic 394 * @egress_traffic_sub_meter_id: Meter for egress Bridge Port process with 395 * specific type 396 * @dest_logical_port_id: Destination logical port 397 * @pmapper_enable: Enable P-mapper 398 * @dest_sub_if_id_group: Destination sub interface ID group when 399 * pmapper_enable is false 400 * @pmapper_mapping_mode: P-mapper mapping mode. See 401 * &enum mxl862xx_pmapper_mapping_mode 402 * @pmapper_id_valid: When true, P-mapper is re-used; when false, 403 * allocation is handled by API 404 * @pmapper: P-mapper configuration used when pmapper_enable is true 405 * @bridge_port_map: Port map defining broadcast domain. Each bit 406 * represents one bridge port. Bridge port ID is 407 * index * 16 + bit offset. 408 * @mc_dest_ip_lookup_disable: Disable multicast IP destination table 409 * lookup 410 * @mc_src_ip_lookup_enable: Enable multicast IP source table lookup 411 * @dest_mac_lookup_disable: Disable destination MAC lookup; packet treated 412 * as unknown 413 * @src_mac_learning_disable: Disable source MAC address learning 414 * @mac_spoofing_detect_enable: Enable MAC spoofing detection 415 * @port_lock_enable: Enable port locking 416 * @mac_learning_limit_enable: Enable MAC learning limitation 417 * @mac_learning_limit: Maximum number of MAC addresses that can be learned 418 * from this bridge port 419 * @loop_violation_count: Number of loop violation events from this bridge 420 * port 421 * @mac_learning_count: Number of MAC addresses learned from this bridge 422 * port 423 * @ingress_vlan_filter_enable: Enable ingress VLAN filter 424 * @ingress_vlan_filter_block_id: VLAN filter block of ingress traffic 425 * @ingress_vlan_filter_block_size: VLAN filter block size for ingress 426 * traffic 427 * @bypass_egress_vlan_filter1: For ingress traffic, bypass VLAN filter 1 428 * at egress bridge port processing 429 * @egress_vlan_filter1enable: Enable egress VLAN filter 1 430 * @egress_vlan_filter1block_id: VLAN filter block 1 of egress traffic 431 * @egress_vlan_filter1block_size: VLAN filter block 1 size 432 * @egress_vlan_filter2enable: Enable egress VLAN filter 2 433 * @egress_vlan_filter2block_id: VLAN filter block 2 of egress traffic 434 * @egress_vlan_filter2block_size: VLAN filter block 2 size 435 * @vlan_tag_selection: VLAN tag selection for MAC address/multicast 436 * learning, lookup and filtering. 437 * 0 - Intermediate outer VLAN tag is used. 438 * 1 - Original outer VLAN tag is used. 439 * @vlan_src_mac_priority_enable: Enable VLAN Priority field for source MAC 440 * learning and filtering 441 * @vlan_src_mac_dei_enable: Enable VLAN DEI/CFI field for source MAC 442 * learning and filtering 443 * @vlan_src_mac_vid_enable: Enable VLAN ID field for source MAC learning 444 * and filtering 445 * @vlan_dst_mac_priority_enable: Enable VLAN Priority field for destination 446 * MAC lookup and filtering 447 * @vlan_dst_mac_dei_enable: Enable VLAN CFI/DEI field for destination MAC 448 * lookup and filtering 449 * @vlan_dst_mac_vid_enable: Enable VLAN ID field for destination MAC lookup 450 * and filtering 451 * @vlan_multicast_priority_enable: Enable VLAN Priority field for IP 452 * multicast lookup 453 * @vlan_multicast_dei_enable: Enable VLAN CFI/DEI field for IP multicast 454 * lookup 455 * @vlan_multicast_vid_enable: Enable VLAN ID field for IP multicast lookup 456 */ 457 struct mxl862xx_bridge_port_config { 458 __le16 bridge_port_id; 459 __le32 mask; /* enum mxl862xx_bridge_port_config_mask */ 460 __le16 bridge_id; 461 u8 ingress_extended_vlan_enable; 462 __le16 ingress_extended_vlan_block_id; 463 __le16 ingress_extended_vlan_block_size; 464 u8 egress_extended_vlan_enable; 465 __le16 egress_extended_vlan_block_id; 466 __le16 egress_extended_vlan_block_size; 467 __le32 ingress_marking_mode; /* enum mxl862xx_color_marking_mode */ 468 __le32 egress_remarking_mode; /* enum mxl862xx_color_remarking_mode */ 469 u8 ingress_metering_enable; 470 __le16 ingress_traffic_meter_id; 471 u8 egress_sub_metering_enable[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 472 __le16 egress_traffic_sub_meter_id[MXL862XX_BRIDGE_PORT_EGRESS_METER_MAX]; 473 u8 dest_logical_port_id; 474 u8 pmapper_enable; 475 __le16 dest_sub_if_id_group; 476 __le32 pmapper_mapping_mode; /* enum mxl862xx_pmapper_mapping_mode */ 477 u8 pmapper_id_valid; 478 struct mxl862xx_pmapper pmapper; 479 __le16 bridge_port_map[8]; 480 u8 mc_dest_ip_lookup_disable; 481 u8 mc_src_ip_lookup_enable; 482 u8 dest_mac_lookup_disable; 483 u8 src_mac_learning_disable; 484 u8 mac_spoofing_detect_enable; 485 u8 port_lock_enable; 486 u8 mac_learning_limit_enable; 487 __le16 mac_learning_limit; 488 __le16 loop_violation_count; 489 __le16 mac_learning_count; 490 u8 ingress_vlan_filter_enable; 491 __le16 ingress_vlan_filter_block_id; 492 __le16 ingress_vlan_filter_block_size; 493 u8 bypass_egress_vlan_filter1; 494 u8 egress_vlan_filter1enable; 495 __le16 egress_vlan_filter1block_id; 496 __le16 egress_vlan_filter1block_size; 497 u8 egress_vlan_filter2enable; 498 __le16 egress_vlan_filter2block_id; 499 __le16 egress_vlan_filter2block_size; 500 u8 vlan_tag_selection; 501 u8 vlan_src_mac_priority_enable; 502 u8 vlan_src_mac_dei_enable; 503 u8 vlan_src_mac_vid_enable; 504 u8 vlan_dst_mac_priority_enable; 505 u8 vlan_dst_mac_dei_enable; 506 u8 vlan_dst_mac_vid_enable; 507 u8 vlan_multicast_priority_enable; 508 u8 vlan_multicast_dei_enable; 509 u8 vlan_multicast_vid_enable; 510 } __packed; 511 512 /** 513 * struct mxl862xx_cfg - Global Switch configuration Attributes 514 * @mac_table_age_timer: See &enum mxl862xx_age_timer 515 * @age_timer: Custom MAC table aging timer in seconds 516 * @max_packet_len: Maximum Ethernet packet length 517 * @learning_limit_action: Automatic MAC address table learning limitation 518 * consecutive action 519 * @mac_locking_action: Accept or discard MAC port locking violation 520 * packets 521 * @mac_spoofing_action: Accept or discard MAC spoofing and port MAC locking 522 * violation packets 523 * @pause_mac_mode_src: Pause frame MAC source address mode 524 * @pause_mac_src: Pause frame MAC source address 525 */ 526 struct mxl862xx_cfg { 527 __le32 mac_table_age_timer; /* enum mxl862xx_age_timer */ 528 __le32 age_timer; 529 __le16 max_packet_len; 530 u8 learning_limit_action; 531 u8 mac_locking_action; 532 u8 mac_spoofing_action; 533 u8 pause_mac_mode_src; 534 u8 pause_mac_src[ETH_ALEN]; 535 } __packed; 536 537 /** 538 * enum mxl862xx_ss_sp_tag_mask - Special tag valid field indicator bits 539 * @MXL862XX_SS_SP_TAG_MASK_RX: valid RX special tag mode 540 * @MXL862XX_SS_SP_TAG_MASK_TX: valid TX special tag mode 541 * @MXL862XX_SS_SP_TAG_MASK_RX_PEN: valid RX special tag info over preamble 542 * @MXL862XX_SS_SP_TAG_MASK_TX_PEN: valid TX special tag info over preamble 543 */ 544 enum mxl862xx_ss_sp_tag_mask { 545 MXL862XX_SS_SP_TAG_MASK_RX = BIT(0), 546 MXL862XX_SS_SP_TAG_MASK_TX = BIT(1), 547 MXL862XX_SS_SP_TAG_MASK_RX_PEN = BIT(2), 548 MXL862XX_SS_SP_TAG_MASK_TX_PEN = BIT(3), 549 }; 550 551 /** 552 * enum mxl862xx_ss_sp_tag_rx - RX special tag mode 553 * @MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT: packet does NOT have special 554 * tag and special tag is NOT inserted 555 * @MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT: packet does NOT have special tag 556 * and special tag is inserted 557 * @MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT: packet has special tag and special 558 * tag is NOT inserted 559 */ 560 enum mxl862xx_ss_sp_tag_rx { 561 MXL862XX_SS_SP_TAG_RX_NO_TAG_NO_INSERT = 0, 562 MXL862XX_SS_SP_TAG_RX_NO_TAG_INSERT = 1, 563 MXL862XX_SS_SP_TAG_RX_TAG_NO_INSERT = 2, 564 }; 565 566 /** 567 * enum mxl862xx_ss_sp_tag_tx - TX special tag mode 568 * @MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE: packet does NOT have special 569 * tag and special tag is NOT removed 570 * @MXL862XX_SS_SP_TAG_TX_TAG_REPLACE: packet has special tag and special 571 * tag is replaced 572 * @MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE: packet has special tag and special 573 * tag is NOT removed 574 * @MXL862XX_SS_SP_TAG_TX_TAG_REMOVE: packet has special tag and special 575 * tag is removed 576 */ 577 enum mxl862xx_ss_sp_tag_tx { 578 MXL862XX_SS_SP_TAG_TX_NO_TAG_NO_REMOVE = 0, 579 MXL862XX_SS_SP_TAG_TX_TAG_REPLACE = 1, 580 MXL862XX_SS_SP_TAG_TX_TAG_NO_REMOVE = 2, 581 MXL862XX_SS_SP_TAG_TX_TAG_REMOVE = 3, 582 }; 583 584 /** 585 * enum mxl862xx_ss_sp_tag_rx_pen - RX special tag info over preamble 586 * @MXL862XX_SS_SP_TAG_RX_PEN_ALL_0: special tag info inserted from byte 2 587 * to 7 are all 0 588 * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16: special tag byte 5 is 16, other 589 * bytes from 2 to 7 are 0 590 * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE: special tag byte 5 is 591 * from preamble field, others 592 * are 0 593 * @MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE: special tag byte 2 594 * to 7 are from preamble 595 * field 596 */ 597 enum mxl862xx_ss_sp_tag_rx_pen { 598 MXL862XX_SS_SP_TAG_RX_PEN_ALL_0 = 0, 599 MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_IS_16 = 1, 600 MXL862XX_SS_SP_TAG_RX_PEN_BYTE_5_FROM_PREAMBLE = 2, 601 MXL862XX_SS_SP_TAG_RX_PEN_BYTE_2_TO_7_FROM_PREAMBLE = 3, 602 }; 603 604 /** 605 * struct mxl862xx_ss_sp_tag - Special tag port settings 606 * @pid: port ID (1~16) 607 * @mask: See &enum mxl862xx_ss_sp_tag_mask 608 * @rx: See &enum mxl862xx_ss_sp_tag_rx 609 * @tx: See &enum mxl862xx_ss_sp_tag_tx 610 * @rx_pen: See &enum mxl862xx_ss_sp_tag_rx_pen 611 * @tx_pen: TX special tag info over preamble 612 * 0 - disabled 613 * 1 - enabled 614 */ 615 struct mxl862xx_ss_sp_tag { 616 u8 pid; 617 u8 mask; /* enum mxl862xx_ss_sp_tag_mask */ 618 u8 rx; /* enum mxl862xx_ss_sp_tag_rx */ 619 u8 tx; /* enum mxl862xx_ss_sp_tag_tx */ 620 u8 rx_pen; /* enum mxl862xx_ss_sp_tag_rx_pen */ 621 u8 tx_pen; /* boolean */ 622 } __packed; 623 624 /** 625 * enum mxl862xx_logical_port_mode - Logical port mode 626 * @MXL862XX_LOGICAL_PORT_8BIT_WLAN: WLAN with 8-bit station ID 627 * @MXL862XX_LOGICAL_PORT_9BIT_WLAN: WLAN with 9-bit station ID 628 * @MXL862XX_LOGICAL_PORT_ETHERNET: Ethernet port 629 * @MXL862XX_LOGICAL_PORT_OTHER: Others 630 */ 631 enum mxl862xx_logical_port_mode { 632 MXL862XX_LOGICAL_PORT_8BIT_WLAN = 0, 633 MXL862XX_LOGICAL_PORT_9BIT_WLAN, 634 MXL862XX_LOGICAL_PORT_ETHERNET, 635 MXL862XX_LOGICAL_PORT_OTHER = 0xFF, 636 }; 637 638 /** 639 * struct mxl862xx_ctp_port_assignment - CTP Port Assignment/association 640 * with logical port 641 * @logical_port_id: Logical Port Id. The valid range is hardware dependent 642 * @first_ctp_port_id: First CTP (Connectivity Termination Port) ID mapped 643 * to above logical port ID 644 * @number_of_ctp_port: Total number of CTP Ports mapped above logical port 645 * ID 646 * @mode: Logical port mode to define sub interface ID format. See 647 * &enum mxl862xx_logical_port_mode 648 * @bridge_port_id: Bridge Port ID (not FID). For allocation, each CTP 649 * allocated is mapped to the Bridge Port given by this field. 650 * The Bridge Port will be configured to use first CTP as 651 * egress CTP. 652 */ 653 struct mxl862xx_ctp_port_assignment { 654 u8 logical_port_id; 655 __le16 first_ctp_port_id; 656 __le16 number_of_ctp_port; 657 __le32 mode; /* enum mxl862xx_logical_port_mode */ 658 __le16 bridge_port_id; 659 } __packed; 660 661 /** 662 * struct mxl862xx_sys_fw_image_version - Firmware version information 663 * @iv_major: firmware major version 664 * @iv_minor: firmware minor version 665 * @iv_revision: firmware revision 666 * @iv_build_num: firmware build number 667 */ 668 struct mxl862xx_sys_fw_image_version { 669 u8 iv_major; 670 u8 iv_minor; 671 __le16 iv_revision; 672 __le32 iv_build_num; 673 } __packed; 674 675 #endif /* __MXL862XX_API_H */ 676