1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2026 David Yang 4 */ 5 6 #ifndef _YT_TC_H 7 #define _YT_TC_H 8 9 #include <net/dsa.h> 10 #include <net/pkt_cls.h> 11 12 #define YT921X_ACLn_ACT(n) (0x1c0000 + 0x10 * (n)) 13 #define YT921X_ACL_ACTc_STAG_M GENMASK(26, 25) 14 #define YT921X_ACL_ACTc_STAG(x) FIELD_PREP(YT921X_ACL_ACTc_STAG_M, (x)) 15 #define YT921X_ACL_ACTc_STAG_DONTCARE YT921X_ACL_ACTc_STAG(0) 16 #define YT921X_ACL_ACTc_STAG_UNTAG YT921X_ACL_ACTc_STAG(1) 17 #define YT921X_ACL_ACTc_STAG_TAG YT921X_ACL_ACTc_STAG(2) 18 #define YT921X_ACL_ACTc_STAG_KEEP YT921X_ACL_ACTc_STAG(3) 19 #define YT921X_ACL_ACTc_CTAG_M GENMASK(24, 23) 20 #define YT921X_ACL_ACTc_CTAG(x) FIELD_PREP(YT921X_ACL_ACTc_CTAG_M, (x)) 21 #define YT921X_ACL_ACTc_CTAG_DONTCARE YT921X_ACL_ACTc_CTAG(0) 22 #define YT921X_ACL_ACTc_CTAG_UNTAG YT921X_ACL_ACTc_CTAG(1) 23 #define YT921X_ACL_ACTc_CTAG_TAG YT921X_ACL_ACTc_CTAG(2) 24 #define YT921X_ACL_ACTc_CTAG_KEEP YT921X_ACL_ACTc_CTAG(3) 25 #define YT921X_ACL_ACTc_FWD_M GENMASK(22, 21) 26 #define YT921X_ACL_ACTc_FWD(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_M, (x)) 27 #define YT921X_ACL_ACTc_FWD_FWD YT921X_ACL_ACTc_FWD(0) 28 #define YT921X_ACL_ACTc_FWD_COPY YT921X_ACL_ACTc_FWD(1) 29 #define YT921X_ACL_ACTc_FWD_REDIR YT921X_ACL_ACTc_FWD(2) 30 #define YT921X_ACL_ACTc_FWD_TRAP YT921X_ACL_ACTc_FWD(3) 31 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M GENMASK(20, 10) 32 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTS(x) FIELD_PREP(YT921X_ACL_ACTc_FWD_REDIR_DPORTS_M, (x)) 33 #define YT921X_ACL_ACTc_FWD_REDIR_DPORTn(port) BIT((port) + 10) 34 #define YT921X_ACL_ACTc_FWD_EN BIT(9) 35 #define YT921X_ACL_ACTc_SDEI BIT(8) 36 #define YT921X_ACL_ACTc_SDEI_REPLACE BIT(7) 37 #define YT921X_ACL_ACTc_SPRI_M GENMASK(6, 4) 38 #define YT921X_ACL_ACTc_SPRI(x) FIELD_PREP(YT921X_ACL_ACTc_SPRI_M, (x)) 39 #define YT921X_ACL_ACTc_SPRI_REPLACE BIT(3) 40 #define YT921X_ACL_ACTbc_SVID_M GENMASK_ULL(34, 23) 41 #define YT921X_ACL_ACTbc_SVID(x) FIELD_PREP(YT921X_ACL_ACTbc_SVID_M, (x)) 42 #define YT921X_ACL_ACTb_SVID_REPLACE BIT(22) 43 #define YT921X_ACL_ACTb_CDEI BIT(21) 44 #define YT921X_ACL_ACTb_CDEI_REPLACE BIT(20) 45 #define YT921X_ACL_ACTb_CPRI_M GENMASK(19, 17) 46 #define YT921X_ACL_ACTb_CPRI(x) FIELD_PREP(YT921X_ACL_ACTb_CPRI_M, (x)) 47 #define YT921X_ACL_ACTb_CPRI_REPLACE BIT(16) 48 #define YT921X_ACL_ACTb_CVID_M GENMASK(15, 4) 49 #define YT921X_ACL_ACTb_CVID(x) FIELD_PREP(YT921X_ACL_ACTb_CVID_M, (x)) 50 #define YT921X_ACL_ACTb_CVID_REPLACE BIT(3) 51 #define YT921X_ACL_ACTb_PRIO_M GENMASK(2, 0) 52 #define YT921X_ACL_ACTb_PRIO(x) FIELD_PREP(YT921X_ACL_ACTb_PRIO_M, (x)) 53 #define YT921X_ACL_ACTa_PRIO_EN BIT(31) 54 #define YT921X_ACL_ACTa_COLOR_M GENMASK(30, 29) 55 #define YT921X_ACL_ACTa_COLOR(x) FIELD_PREP(YT921X_ACL_ACTa_COLOR_M, (x)) 56 #define YT921X_ACL_ACTa_COLOR_GREEN YT921X_ACL_ACTa_COLOR(0) 57 #define YT921X_ACL_ACTa_COLOR_YELLOW YT921X_ACL_ACTa_COLOR(1) 58 #define YT921X_ACL_ACTa_COLOR_RED YT921X_ACL_ACTa_COLOR(2) 59 #define YT921X_ACL_ACTa_COLOR_EN BIT(28) 60 #define YT921X_ACL_ACTa_DSCP_M GENMASK(27, 22) 61 #define YT921X_ACL_ACTa_DSCP(x) FIELD_PREP(YT921X_ACL_ACTa_DSCP_M, (x)) 62 #define YT921X_ACL_ACTa_DSCP_REPLACE BIT(21) 63 #define YT921X_ACL_ACTa_METER_ID_M GENMASK(20, 15) 64 #define YT921X_ACL_ACTa_METER_ID(x) FIELD_PREP(YT921X_ACL_ACTa_METER_ID_M, (x)) 65 #define YT921X_ACL_ACTa_METER_EN BIT(14) 66 #define YT921X_ACL_ACTa_MIRROR_EN BIT(13) 67 #define YT921X_ACL_ACTa_FLOWSTAT_EN BIT(12) 68 #define YT921X_ACL_ACTa_FLOWSTAT_ID_M GENMASK(11, 6) 69 #define YT921X_ACL_ACTa_FLOWSTAT_ID(x) FIELD_PREP(YT921X_ACL_ACTa_FLOWSTAT_ID_M, (x)) 70 #define YT921X_ACL_ACTa_GPIO_EN BIT(5) 71 #define YT921X_ACL_ACTa_GPIO_PIN_M GENMASK(4, 1) 72 #define YT921X_ACL_ACTa_GPIO_PIN(x) FIELD_PREP(YT921X_ACL_ACTa_GPIO_PIN_M, (x)) 73 #define YT921X_ACL_ACTa_INTR_EN BIT(0) 74 #define YT921X_ACL_BLK_KEEP 0x201000 75 #define YT921X_ACL_BLK_KEEP_GRPIDn_M(bin) (7 << (4 * (bin) + 1)) 76 #define YT921X_ACL_BLK_KEEP_GRPIDn(bin, x) ((x) << (4 * (bin) + 1)) 77 #define YT921X_ACL_BLK_KEEP_KEEPn(bin) BIT(4 * (bin)) 78 #define YT921X_ACL_PORT 0x202000 79 #define YT921X_ACL_PORT_PORTS_M GENMASK(10, 0) 80 #define YT921X_ACL_PORT_PORTS(x) FIELD_PREP(YT921X_ACL_PORT_PORTS_M, (x)) 81 #define YT921X_ACL_PORT_PORTn(port) BIT(port) 82 #define YT921X_ACL_BLK_CMD 0x202004 83 #define YT921X_ACL_BLK_CMD_BLKID_M GENMASK(6, 1) 84 #define YT921X_ACL_BLK_CMD_BLKID(x) FIELD_PREP(YT921X_ACL_BLK_CMD_BLKID_M, (x)) 85 #define YT921X_ACL_BLK_CMD_MODIFY BIT(0) 86 #define YT921X_ACLn_ENTRY(blk) (0x203000 + 4 * (blk)) 87 #define YT921X_ACL_ENTRY_GRPIDm_M(bin) (7 << (4 * (bin) + 1)) 88 #define YT921X_ACL_ENTRY_GRPIDm(bin, x) ((x) << (4 * (bin) + 1)) 89 #define YT921X_ACL_ENTRY_ENm(bin) BIT(4 * (bin)) 90 #define YT921X_ACLn_KEYm(blk, bin) (0x204000 + 0x200 * (bin) + 8 * (blk)) 91 #define YT921X_ACL_KEYb_ORD_M GENMASK(29, 21) 92 #define YT921X_ACL_KEYb_ORD(x) FIELD_PREP(YT921X_ACL_KEYb_ORD_M, (x)) 93 #define YT921X_ACL_KEYb_SPORTS_M GENMASK(20, 10) 94 #define YT921X_ACL_KEYb_SPORTS(x) FIELD_PREP(YT921X_ACL_KEYb_SPORTS_M, (x)) 95 #define YT921X_ACL_KEYb_SPORTn(port) BIT((port) + 10) 96 #define YT921X_ACL_KEYb_REVERSE BIT(9) /* reverse match */ 97 #define YT921X_ACL_KEYb_TYPE_M GENMASK(8, 4) 98 #define YT921X_ACL_KEYb_TYPE(x) FIELD_PREP(YT921X_ACL_KEYb_TYPE_M, (x)) 99 /* KEY_* fields need no masks */ 100 #define YT921X_ACLn_MASKm(blk, bin) (0x205000 + 0x200 * (bin) + 8 * (blk)) 101 102 enum yt921x_acl_type { 103 YT921X_ACL_TYPE_NA, 104 YT921X_ACL_TYPE_MAC_DA0, 105 YT921X_ACL_TYPE_MAC_SA0, 106 YT921X_ACL_TYPE_MAC_DA1_SA1, 107 YT921X_ACL_TYPE_VLAN, 108 YT921X_ACL_TYPE_VTAG, 109 YT921X_ACL_TYPE_IPV4_DA, 110 YT921X_ACL_TYPE_IPV4_SA, 111 YT921X_ACL_TYPE_IPV6_DA0, 112 YT921X_ACL_TYPE_IPV6_DA1, 113 YT921X_ACL_TYPE_IPV6_DA2, 114 YT921X_ACL_TYPE_IPV6_DA3, 115 YT921X_ACL_TYPE_IPV6_SA0, 116 YT921X_ACL_TYPE_IPV6_SA1, 117 YT921X_ACL_TYPE_IPV6_SA2, 118 YT921X_ACL_TYPE_IPV6_SA3, 119 YT921X_ACL_TYPE_MISC, 120 YT921X_ACL_TYPE_L4, 121 /* Each User Defined Filter entry contains 2 UDF windows (UDF_CTRL 2i 122 * and 2i+1) 123 */ 124 YT921X_ACL_TYPE_UDF0, 125 YT921X_ACL_TYPE_UDF1, 126 YT921X_ACL_TYPE_UDF2, 127 YT921X_ACL_TYPE_UDF3, 128 YT921X_ACL_TYPE_UDF4, 129 YT921X_ACL_TYPE_UDF5, 130 YT921X_ACL_TYPE_UDF6, 131 YT921X_ACL_TYPE_UDF7, 132 YT921X_ACL_TYPE_ETHERTYPE, 133 YT921X_ACL_TYPE_NUM 134 }; 135 136 /* Range: turn KEY:MASK into MIN:MAX */ 137 138 #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M GENMASK(3, 0) 139 #define YT921X_ACL_BINb_MAC_xA0_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_xA0_L3_TYPE_M, (x)) 140 #define YT921X_ACL_BINa_MAC_xA0_MAC_xA0_M GENMASK(31, 0) 141 142 #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M GENMASK(2, 0) 143 #define YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MAC_DA1_SA1_L2_TYPE_M, (x)) 144 #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_DA1_M GENMASK(31, 16) 145 #define YT921X_ACL_BINa_MAC_DA1_SA1_MAC_SA1_M GENMASK(15, 0) 146 147 #define YT921X_ACL_KEYb_VLAN_SVID_RANGE_EN BIT(31) 148 #define YT921X_ACL_KEYb_VLAN_CVID_RANGE_EN BIT(30) 149 #define YT921X_ACL_BINb_VLAN_CDEI BIT(3) 150 #define YT921X_ACL_BINb_VLAN_CPRI_M GENMASK(2, 0) 151 #define YT921X_ACL_BINb_VLAN_CPRI(x) FIELD_PREP(YT921X_ACL_BINb_VLAN_CPRI_M, (x)) 152 #define YT921X_ACL_BINa_VLAN_CTAG_FMT_M GENMASK(31, 30) 153 #define YT921X_ACL_BINa_VLAN_CTAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CTAG_FMT_M, (x)) 154 #define YT921X_ACL_BINa_VLAN_SDEI BIT(29) 155 #define YT921X_ACL_BINa_VLAN_SPRI_M GENMASK(28, 26) 156 #define YT921X_ACL_BINa_VLAN_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SPRI_M, (x)) 157 #define YT921X_ACL_BINa_VLAN_STAG_FMT_M GENMASK(25, 24) 158 #define YT921X_ACL_BINa_VLAN_STAG_FMT(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_STAG_FMT_M, (x)) 159 #define YT921X_ACL_BINa_VLAN_SVID_M GENMASK(23, 12) 160 #define YT921X_ACL_BINa_VLAN_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_SVID_M, (x)) 161 #define YT921X_ACL_BINa_VLAN_CVID_M GENMASK(11, 0) 162 #define YT921X_ACL_BINa_VLAN_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VLAN_CVID_M, (x)) 163 164 #define YT921X_ACL_KEYb_VTAG_SVID_RANGE_EN BIT(31) 165 #define YT921X_ACL_KEYb_VTAG_CVID_RANGE_EN BIT(30) 166 #define YT921X_ACL_BINa_VTAG_CDEI BIT(31) 167 #define YT921X_ACL_BINa_VTAG_CPRI_M GENMASK(30, 28) 168 #define YT921X_ACL_BINa_VTAG_CPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CPRI_M, (x)) 169 #define YT921X_ACL_BINa_VTAG_SDEI BIT(27) 170 #define YT921X_ACL_BINa_VTAG_SPRI_M GENMASK(26, 24) 171 #define YT921X_ACL_BINa_VTAG_SPRI(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SPRI_M, (x)) 172 #define YT921X_ACL_BINa_VTAG_SVID_M GENMASK(23, 12) 173 #define YT921X_ACL_BINa_VTAG_SVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_SVID_M, (x)) 174 #define YT921X_ACL_BINa_VTAG_CVID_M GENMASK(11, 0) 175 #define YT921X_ACL_BINa_VTAG_CVID(x) FIELD_PREP(YT921X_ACL_BINa_VTAG_CVID_M, (x)) 176 177 #define YT921X_ACL_KEYb_IPV4_ADDR_RANGE_EN BIT(30) 178 #define YT921X_ACL_BINb_IPV4_FRAG BIT(3) 179 #define YT921X_ACL_BINb_IPV4_L4_TYPE_M GENMASK(2, 0) 180 #define YT921X_ACL_BINb_IPV4_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV4_L4_TYPE_M, (x)) 181 #define YT921X_ACL_BINa_IPV4_ADDR_M GENMASK(31, 0) 182 183 #define YT921X_ACL_BINb_IPV6_L4_TYPE_M GENMASK(2, 0) 184 #define YT921X_ACL_BINb_IPV6_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_IPV6_L4_TYPE_M, (x)) 185 #define YT921X_ACL_BINa_IPV6_ADDRx_M GENMASK(31, 0) 186 187 #define YT921X_ACL_BINb_IPV6_xA1_IP_OPTION BIT(3) 188 189 #define YT921X_ACL_BINb_IPV6_xA2_FIRST_FRAG BIT(3) 190 191 #define YT921X_ACL_KEYb_IPV6_xA3_ADDR_RANGE_EN BIT(30) 192 #define YT921X_ACL_BINb_IPV6_xA3_FRAG BIT(3) 193 194 #define YT921X_ACL_BINb_MISC_FRAG BIT(3) 195 #define YT921X_ACL_BINb_MISC_L4_TYPE_M GENMASK(2, 0) 196 #define YT921X_ACL_BINb_MISC_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_MISC_L4_TYPE_M, (x)) 197 #define YT921X_ACL_BINa_MISC_PPPOE_FLAG BIT(30) 198 #define YT921X_ACL_BINa_MISC_FIRST_FRAG BIT(29) 199 #define YT921X_ACL_BINa_MISC_IP_OPTION BIT(28) 200 #define YT921X_ACL_BINa_MISC_TCP_FLAGS_M GENMASK(27, 20) 201 #define YT921X_ACL_BINa_MISC_TCP_FLAGS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TCP_FLAGS_M, (x)) 202 #define YT921X_ACL_BINa_MISC_IP_PROTO_M GENMASK(19, 12) 203 #define YT921X_ACL_BINa_MISC_IP_PROTO(x) FIELD_PREP(YT921X_ACL_BINa_MISC_IP_PROTO_M, (x)) 204 #define YT921X_ACL_BINa_MISC_TOS_M GENMASK(11, 4) 205 #define YT921X_ACL_BINa_MISC_TOS(x) FIELD_PREP(YT921X_ACL_BINa_MISC_TOS_M, (x)) 206 #define YT921X_ACL_BINa_MISC_L3_TYPE_M GENMASK(3, 0) 207 #define YT921X_ACL_BINa_MISC_L3_TYPE(x) FIELD_PREP(YT921X_ACL_BINa_MISC_L3_TYPE_M, (x)) 208 209 #define YT921X_ACL_KEYb_L4_DPORT_RANGE_EN BIT(31) 210 #define YT921X_ACL_KEYb_L4_SPORT_RANGE_EN BIT(30) 211 #define YT921X_ACL_BINb_L4_FRAG BIT(3) 212 #define YT921X_ACL_BINb_L4_TYPE_M GENMASK(2, 0) 213 #define YT921X_ACL_BINb_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_L4_TYPE_M, (x)) 214 #define YT921X_ACL_BINa_L4_DPORT_M GENMASK(31, 16) 215 #define YT921X_ACL_BINa_L4_SPORT_M GENMASK(15, 0) 216 217 #define YT921X_ACL_BINb_UDF_IS_IGMP BIT(0) 218 #define YT921X_ACL_BINa_UDF_UDF0_M GENMASK(31, 16) 219 #define YT921X_ACL_BINa_UDF_UDF0(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF0_M, (x)) 220 #define YT921X_ACL_BINa_UDF_UDF1_M GENMASK(15, 0) 221 #define YT921X_ACL_BINa_UDF_UDF1(x) FIELD_PREP(YT921X_ACL_BINa_UDF_UDF1_M, (x)) 222 223 #define YT921X_ACL_KEYb_ETHERTYPE_ETHERTYPE_RANGE_EN BIT(30) 224 #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M GENMASK(2, 0) 225 #define YT921X_ACL_BINb_ETHERTYPE_L4_TYPE(x) FIELD_PREP(YT921X_ACL_BINb_ETHERTYPE_L4_TYPE_M, (x)) 226 #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M GENMASK(15, 0) 227 #define YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE(x) FIELD_PREP(YT921X_ACL_BINa_ETHERTYPE_ETHERTYPE_M, (x)) 228 229 enum yt921x_l2_type { 230 YT921X_L2_TYPE_ETH, 231 YT921X_L2_TYPE_ETHV2, 232 YT921X_L2_TYPE_ETHSAP, 233 YT921X_L2_TYPE_ETHSNAP, 234 }; 235 236 enum yt921x_l3_type { 237 YT921X_L3_TYPE_OTHER, 238 YT921X_L3_TYPE_IPV4, 239 YT921X_L3_TYPE_IPV6, 240 YT921X_L3_TYPE_ARP, 241 YT921X_L3_TYPE_LLDP, 242 YT921X_L3_TYPE_PAE, 243 YT921X_L3_TYPE_ERP, 244 YT921X_L3_TYPE_SLOW_PROTOCOL, 245 }; 246 247 enum yt921x_l4_type { 248 YT921X_L4_TYPE_OTHER, 249 YT921X_L4_TYPE_TCP, 250 YT921X_L4_TYPE_UDP, 251 YT921X_L4_TYPE_UDPLITE, 252 YT921X_L4_TYPE_ICMP, 253 YT921X_L4_TYPE_IGMP, 254 YT921X_L4_TYPE_MLD, 255 YT921X_L4_TYPE_ND, 256 }; 257 258 #define YT921X_UDFn_CTRL(x) (0x210094 + 4 * (x)) 259 #define YT921X_UDF_CTRL_UDF_TYPE_M GENMASK(8, 7) 260 #define YT921X_UDF_CTRL_UDF_TYPE(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_TYPE_M, (x)) 261 #define YT921X_UDF_CTRL_UDF_OFFSET_M GENMASK(6, 0) 262 #define YT921X_UDF_CTRL_UDF_OFFSET(x) FIELD_PREP(YT921X_UDF_CTRL_UDF_OFFSET_M, (x)) 263 264 enum yt921x_udf_type { 265 YT921X_UDF_TYPE_L2, 266 YT921X_UDF_TYPE_L3, 267 YT921X_UDF_TYPE_L4, 268 }; 269 270 #define YT921X_PORTn_RATE(port) (0x220000 + 4 * (port)) 271 #define YT921X_PORT_RATE_GAP_VALUE GENMASK(4, 0) /* default 20 */ 272 #define YT921X_METER_SLOT 0x220104 273 #define YT921X_METER_SLOT_SLOT_M GENMASK(11, 0) 274 #define YT921X_PORTn_METER(port) (0x220108 + 4 * (port)) 275 #define YT921X_PORT_METER_EN BIT(4) 276 #define YT921X_PORT_METER_ID_M GENMASK(3, 0) 277 #define YT921X_PORT_METER_ID(x) FIELD_PREP(YT921X_PORT_METER_ID_M, (x)) 278 #define YT921X_METERn_CTRL(x) (0x220800 + 0x10 * (x)) 279 #define YT921X_METER_CTRLc_METER_EN BIT(14) 280 #define YT921X_METER_CTRLc_TOKEN_OVERFLOW_EN BIT(13) /* RFC4115: yellow use unused green bw */ 281 #define YT921X_METER_CTRLc_DROP_M GENMASK(12, 11) 282 #define YT921X_METER_CTRLc_DROP(x) FIELD_PREP(YT921X_METER_CTRLc_DROP_M, (x)) 283 #define YT921X_METER_CTRLc_DROP_GYR YT921X_METER_CTRLc_DROP(0) 284 #define YT921X_METER_CTRLc_DROP_YR YT921X_METER_CTRLc_DROP(1) 285 #define YT921X_METER_CTRLc_DROP_R YT921X_METER_CTRLc_DROP(2) 286 #define YT921X_METER_CTRLc_DROP_NONE YT921X_METER_CTRLc_DROP(3) 287 #define YT921X_METER_CTRLc_COLOR_BLIND BIT(10) 288 #define YT921X_METER_CTRLc_UNIT_M GENMASK(9, 7) 289 #define YT921X_METER_CTRLc_UNIT(x) FIELD_PREP(YT921X_METER_CTRLc_UNIT_M, (x)) 290 #define YT921X_METER_CTRLc_BYTE_MODE_INCLUDE_GAP BIT(6) /* +GAP_VALUE bytes each packet */ 291 #define YT921X_METER_CTRLc_PKT_MODE BIT(5) /* 0: byte rate mode */ 292 #define YT921X_METER_CTRLc_RFC2698 BIT(4) /* 0: RFC4115 */ 293 #define YT921X_METER_CTRLbc_CBS_M GENMASK_ULL(35, 20) 294 #define YT921X_METER_CTRLbc_CBS(x) FIELD_PREP(YT921X_METER_CTRLbc_CBS_M, (x)) 295 #define YT921X_METER_CTRLb_CIR_M GENMASK(19, 2) 296 #define YT921X_METER_CTRLb_CIR(x) FIELD_PREP(YT921X_METER_CTRLb_CIR_M, (x)) 297 #define YT921X_METER_CTRLab_EBS_M GENMASK_ULL(33, 18) 298 #define YT921X_METER_CTRLab_EBS(x) FIELD_PREP(YT921X_METER_CTRLab_EBS_M, (x)) 299 #define YT921X_METER_CTRLa_EIR_M GENMASK(17, 0) 300 #define YT921X_METER_CTRLa_EIR(x) FIELD_PREP(YT921X_METER_CTRLa_EIR_M, (x)) 301 #define YT921X_METERn_STAT(x) (0x221000 + 8 * (x)) 302 303 #define YT921X_MIRROR 0x300300 304 #define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) 305 #define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_M, (x)) 306 #define YT921X_MIRROR_IGR_PORTn(port) BIT((port) + 16) 307 #define YT921X_MIRROR_EGR_PORTS_M GENMASK(14, 4) 308 #define YT921X_MIRROR_EGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_EGR_PORTS_M, (x)) 309 #define YT921X_MIRROR_EGR_PORTn(port) BIT((port) + 4) 310 #define YT921X_MIRROR_PORT_M GENMASK(3, 0) 311 #define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) 312 313 #define YT921X_PORT_SHAPE_SLOT 0x34000c 314 #define YT921X_PORT_SHAPE_SLOT_SLOT_M GENMASK(11, 0) 315 #define YT921X_PORTn_SHAPE_CTRL(port) (0x354000 + 8 * (port)) 316 #define YT921X_PORT_SHAPE_CTRLb_EN BIT(4) 317 #define YT921X_PORT_SHAPE_CTRLb_PKT_MODE BIT(3) /* 0: byte rate mode */ 318 #define YT921X_PORT_SHAPE_CTRLb_UNIT_M GENMASK(2, 0) 319 #define YT921X_PORT_SHAPE_CTRLb_UNIT(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLb_UNIT_M, (x)) 320 #define YT921X_PORT_SHAPE_CTRLa_CBS_M GENMASK(31, 18) 321 #define YT921X_PORT_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CBS_M, (x)) 322 #define YT921X_PORT_SHAPE_CTRLa_CIR_M GENMASK(17, 0) 323 #define YT921X_PORT_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CIR_M, (x)) 324 #define YT921X_PORTn_SHAPE_STAT(port) (0x356000 + 4 * (port)) 325 326 #define YT921X_TOKEN_BYTE_C 1 /* 1 token = 2^1 byte */ 327 #define YT921X_TOKEN_PKT_C -6 /* 1 token = 2^-6 packets */ 328 #define YT921X_TOKEN_RATE_C -15 329 #define YT921X_METER_SLOT_MIN 80 330 #define YT921X_METER_UNIT_MAX ((1 << 3) - 1) 331 #define YT921X_METER_CIR_MAX ((1 << 18) - 1) 332 #define YT921X_METER_CBS_MAX ((1 << 16) - 1) 333 #define YT921X_PORT_SHAPE_SLOT_MIN 80 334 #define YT921X_SHAPE_UNIT_MAX ((1 << 3) - 1) 335 #define YT921X_SHAPE_CIR_MAX ((1 << 18) - 1) 336 #define YT921X_SHAPE_CBS_MAX ((1 << 14) - 1) 337 338 #define YT921X_ACL_ENT_PER_BLK 8 339 #define YT921X_ACL_NUM 384 340 #define YT921X_ACL_ORD_NUM 512 341 342 struct yt921x_acl_entry { 343 u32 key[2]; 344 u32 mask[2]; 345 }; 346 347 struct yt921x_acl_rule { 348 unsigned long tag; 349 enum tc_setup_type type; 350 351 u32 action[3]; 352 bool sw_assisted; 353 354 u8 mask; 355 struct yt921x_acl_entry entries[YT921X_ACL_ENT_PER_BLK]; 356 }; 357 358 struct yt921x_acl_blk { 359 struct yt921x_acl_rule *rules[YT921X_ACL_ENT_PER_BLK]; 360 }; 361 362 void yt921x_dsa_port_policer_del(struct dsa_switch *ds, int port); 363 int 364 yt921x_dsa_port_policer_add(struct dsa_switch *ds, int port, 365 const struct flow_action_police *police, 366 struct netlink_ext_ack *extack); 367 int 368 yt921x_dsa_port_setup_tc(struct dsa_switch *ds, int port, 369 enum tc_setup_type type, void *type_data); 370 int 371 yt921x_dsa_cls_flower_del(struct dsa_switch *ds, int port, 372 struct flow_cls_offload *cls, bool ingress); 373 int 374 yt921x_dsa_cls_flower_add(struct dsa_switch *ds, int port, 375 struct flow_cls_offload *cls, bool ingress); 376 void 377 yt921x_dsa_port_mirror_del(struct dsa_switch *ds, int port, 378 struct dsa_mall_mirror_tc_entry *mirror); 379 int 380 yt921x_dsa_port_mirror_add(struct dsa_switch *ds, int port, 381 struct dsa_mall_mirror_tc_entry *mirror, 382 bool ingress, struct netlink_ext_ack *extack); 383 384 int yt921x_chip_setup_tc(struct yt921x_priv *priv); 385 int yt921x_chip_setup_acl(struct yt921x_priv *priv); 386 387 #endif 388