1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2025 David Yang 4 */ 5 6 #ifndef __YT921X_H 7 #define __YT921X_H 8 9 #include <net/dsa.h> 10 11 #define YT921X_SMI_SWITCHID_M GENMASK(3, 2) 12 #define YT921X_SMI_SWITCHID(x) FIELD_PREP(YT921X_SMI_SWITCHID_M, (x)) 13 #define YT921X_SMI_AD BIT(1) 14 #define YT921X_SMI_ADDR 0 15 #define YT921X_SMI_DATA YT921X_SMI_AD 16 #define YT921X_SMI_RW BIT(0) 17 #define YT921X_SMI_WRITE 0 18 #define YT921X_SMI_READ YT921X_SMI_RW 19 20 #define YT921X_SWITCHID_NUM 4 21 22 #define YT921X_RST 0x80000 23 #define YT921X_RST_HW BIT(31) 24 #define YT921X_RST_SW BIT(1) 25 #define YT921X_FUNC 0x80004 26 #define YT921X_FUNC_METER BIT(4) 27 #define YT921X_FUNC_ACL BIT(2) 28 #define YT921X_FUNC_MIB BIT(1) 29 #define YT921X_CHIP_ID 0x80008 30 #define YT921X_CHIP_ID_MAJOR GENMASK(31, 16) 31 #define YT921X_EXT_CPU_PORT 0x8000c 32 #define YT921X_EXT_CPU_PORT_TAG_EN BIT(15) 33 #define YT921X_EXT_CPU_PORT_PORT_EN BIT(14) 34 #define YT921X_EXT_CPU_PORT_PORT_M GENMASK(3, 0) 35 #define YT921X_EXT_CPU_PORT_PORT(x) FIELD_PREP(YT921X_EXT_CPU_PORT_PORT_M, (x)) 36 #define YT921X_CPU_TAG_TPID 0x80010 37 #define YT921X_CPU_TAG_TPID_TPID_M GENMASK(15, 0) 38 /* Same as ETH_P_YT921X, but this represents the true HW default, while the 39 * former is a local convention chosen by us. 40 */ 41 #define YT921X_CPU_TAG_TPID_TPID_DEFAULT 0x9988 42 #define YT921X_PVID_SEL 0x80014 43 #define YT921X_PVID_SEL_SVID_PORTn(port) BIT(port) 44 #define YT921X_SERDES_CTRL 0x80028 45 #define YT921X_SERDES_CTRL_TEST BIT(6) 46 #define YT921X_SERDES_CTRL_PORTn(port) BIT((port) - 8) 47 #define YT921X_IO_LEVEL 0x80030 48 #define YT9215_IO_LEVEL_NORMAL_M GENMASK(5, 4) 49 #define YT9215_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9215_IO_LEVEL_NORMAL_M, (x)) 50 #define YT9215_IO_LEVEL_NORMAL_3V3 YT9215_IO_LEVEL_NORMAL(0) 51 #define YT9215_IO_LEVEL_NORMAL_1V8 YT9215_IO_LEVEL_NORMAL(3) 52 #define YT9215_IO_LEVEL_RGMII1_M GENMASK(3, 2) 53 #define YT9215_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII1_M, (x)) 54 #define YT9215_IO_LEVEL_RGMII1_3V3 YT9215_IO_LEVEL_RGMII1(0) 55 #define YT9215_IO_LEVEL_RGMII1_2V5 YT9215_IO_LEVEL_RGMII1(1) 56 #define YT9215_IO_LEVEL_RGMII1_1V8 YT9215_IO_LEVEL_RGMII1(2) 57 #define YT9215_IO_LEVEL_RGMII0_M GENMASK(1, 0) 58 #define YT9215_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9215_IO_LEVEL_RGMII0_M, (x)) 59 #define YT9215_IO_LEVEL_RGMII0_3V3 YT9215_IO_LEVEL_RGMII0(0) 60 #define YT9215_IO_LEVEL_RGMII0_2V5 YT9215_IO_LEVEL_RGMII0(1) 61 #define YT9215_IO_LEVEL_RGMII0_1V8 YT9215_IO_LEVEL_RGMII0(2) 62 #define YT9218_IO_LEVEL_RGMII1_M GENMASK(5, 4) 63 #define YT9218_IO_LEVEL_RGMII1(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII1_M, (x)) 64 #define YT9218_IO_LEVEL_RGMII1_3V3 YT9218_IO_LEVEL_RGMII1(0) 65 #define YT9218_IO_LEVEL_RGMII1_2V5 YT9218_IO_LEVEL_RGMII1(1) 66 #define YT9218_IO_LEVEL_RGMII1_1V8 YT9218_IO_LEVEL_RGMII1(2) 67 #define YT9218_IO_LEVEL_RGMII0_M GENMASK(3, 2) 68 #define YT9218_IO_LEVEL_RGMII0(x) FIELD_PREP(YT9218_IO_LEVEL_RGMII0_M, (x)) 69 #define YT9218_IO_LEVEL_RGMII0_3V3 YT9218_IO_LEVEL_RGMII0(0) 70 #define YT9218_IO_LEVEL_RGMII0_2V5 YT9218_IO_LEVEL_RGMII0(1) 71 #define YT9218_IO_LEVEL_RGMII0_1V8 YT9218_IO_LEVEL_RGMII0(2) 72 #define YT9218_IO_LEVEL_NORMAL_M GENMASK(1, 0) 73 #define YT9218_IO_LEVEL_NORMAL(x) FIELD_PREP(YT9218_IO_LEVEL_NORMAL_M, (x)) 74 #define YT9218_IO_LEVEL_NORMAL_3V3 YT9218_IO_LEVEL_NORMAL(0) 75 #define YT9218_IO_LEVEL_NORMAL_1V8 YT9218_IO_LEVEL_NORMAL(3) 76 #define YT921X_MAC_ADDR_HI2 0x80080 77 #define YT921X_MAC_ADDR_LO4 0x80084 78 #define YT921X_SERDESn(port) (0x8008c + 4 * ((port) - 8)) 79 #define YT921X_SERDES_MODE_M GENMASK(9, 7) 80 #define YT921X_SERDES_MODE(x) FIELD_PREP(YT921X_SERDES_MODE_M, (x)) 81 #define YT921X_SERDES_MODE_SGMII YT921X_SERDES_MODE(0) 82 #define YT921X_SERDES_MODE_REVSGMII YT921X_SERDES_MODE(1) 83 #define YT921X_SERDES_MODE_1000BASEX YT921X_SERDES_MODE(2) 84 #define YT921X_SERDES_MODE_100BASEX YT921X_SERDES_MODE(3) 85 #define YT921X_SERDES_MODE_2500BASEX YT921X_SERDES_MODE(4) 86 #define YT921X_SERDES_RX_PAUSE BIT(6) 87 #define YT921X_SERDES_TX_PAUSE BIT(5) 88 #define YT921X_SERDES_LINK BIT(4) /* force link */ 89 #define YT921X_SERDES_DUPLEX_FULL BIT(3) 90 #define YT921X_SERDES_SPEED_M GENMASK(2, 0) 91 #define YT921X_SERDES_SPEED(x) FIELD_PREP(YT921X_SERDES_SPEED_M, (x)) 92 #define YT921X_PORTn_CTRL(port) (0x80100 + 4 * (port)) /* Bit 7-0 shared with PORT_STATUS */ 93 #define YT921X_PORT_CTRL_PAUSE_AN BIT(10) 94 #define YT921X_PORT_CTRL_LINK_AN BIT(9) 95 #define YT921X_PORT_CTRL_HALF_PAUSE BIT(8) /* Half-duplex back pressure mode */ 96 #define YT921X_PORTn_STATUS(port) (0x80200 + 4 * (port)) 97 #define YT921X_PORT_LINK BIT(8) 98 #define YT921X_PORT_DUPLEX_FULL BIT(7) 99 #define YT921X_PORT_RX_PAUSE BIT(6) 100 #define YT921X_PORT_TX_PAUSE BIT(5) 101 #define YT921X_PORT_RX_MAC_EN BIT(4) 102 #define YT921X_PORT_TX_MAC_EN BIT(3) 103 #define YT921X_PORT_SPEED_M GENMASK(2, 0) 104 #define YT921X_PORT_SPEED(x) FIELD_PREP(YT921X_PORT_SPEED_M, (x)) 105 #define YT921X_PON_STRAP_FUNC 0x80320 106 #define YT921X_PON_STRAP_VAL 0x80324 107 #define YT921X_PON_STRAP_CAP 0x80328 108 #define YT921X_PON_STRAP_EEE BIT(16) 109 #define YT921X_PON_STRAP_LOOP_DETECT BIT(7) 110 #define YT921X_MDIO_POLLINGn(port) (0x80364 + 4 * ((port) - 8)) 111 #define YT921X_MDIO_POLLING_DUPLEX_FULL BIT(4) 112 #define YT921X_MDIO_POLLING_LINK BIT(3) 113 #define YT921X_MDIO_POLLING_SPEED_M GENMASK(2, 0) 114 #define YT921X_MDIO_POLLING_SPEED(x) FIELD_PREP(YT921X_MDIO_POLLING_SPEED_M, (x)) 115 116 enum yt921x_speed { 117 YT921X_SPEED_10, 118 YT921X_SPEED_100, 119 YT921X_SPEED_1000, 120 YT921X_SPEED_10000, 121 YT921X_SPEED_2500, 122 YT921X_SPEED_INVALID 123 }; 124 125 #define YT921X_SENSOR 0x8036c 126 #define YT921X_SENSOR_TEMP BIT(18) 127 #define YT921X_TEMP 0x80374 128 #define YT921X_CHIP_MODE 0x80388 129 #define YT921X_CHIP_MODE_MODE GENMASK(1, 0) 130 #define YT921X_XMII_CTRL 0x80394 131 #define YT921X_XMII_CTRL_PORTn(port) BIT(9 - (port)) /* Yes, it's reversed */ 132 #define YT921X_XMIIn(port) (0x80400 + 8 * ((port) - 8)) 133 #define YT921X_XMII_MODE_M GENMASK(31, 29) 134 #define YT921X_XMII_MODE(x) FIELD_PREP(YT921X_XMII_MODE_M, (x)) 135 #define YT921X_XMII_MODE_MII YT921X_XMII_MODE(0) 136 #define YT921X_XMII_MODE_REVMII YT921X_XMII_MODE(1) 137 #define YT921X_XMII_MODE_RMII YT921X_XMII_MODE(2) 138 #define YT921X_XMII_MODE_REVRMII YT921X_XMII_MODE(3) 139 #define YT921X_XMII_MODE_RGMII YT921X_XMII_MODE(4) 140 #define YT921X_XMII_MODE_DISABLE YT921X_XMII_MODE(5) 141 #define YT921X_XMII_LINK BIT(19) /* force link */ 142 #define YT921X_XMII_EN BIT(18) 143 #define YT921X_XMII_SOFT_RST BIT(17) 144 #define YT921X_XMII_RGMII_TX_DELAY_150PS_M GENMASK(16, 13) 145 #define YT921X_XMII_RGMII_TX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_TX_DELAY_150PS_M, (x)) 146 #define YT921X_XMII_TX_CLK_IN BIT(11) 147 #define YT921X_XMII_RX_CLK_IN BIT(10) 148 #define YT921X_XMII_RGMII_TX_DELAY_2NS BIT(8) 149 #define YT921X_XMII_RGMII_TX_CLK_OUT BIT(7) 150 #define YT921X_XMII_RGMII_RX_DELAY_150PS_M GENMASK(6, 3) 151 #define YT921X_XMII_RGMII_RX_DELAY_150PS(x) FIELD_PREP(YT921X_XMII_RGMII_RX_DELAY_150PS_M, (x)) 152 #define YT921X_XMII_RMII_PHY_TX_CLK_OUT BIT(2) 153 #define YT921X_XMII_REVMII_TX_CLK_OUT BIT(1) 154 #define YT921X_XMII_REVMII_RX_CLK_OUT BIT(0) 155 156 #define YT921X_MACn_FRAME(port) (0x81008 + 0x1000 * (port)) 157 #define YT921X_MAC_FRAME_SIZE_M GENMASK(21, 8) 158 #define YT921X_MAC_FRAME_SIZE(x) FIELD_PREP(YT921X_MAC_FRAME_SIZE_M, (x)) 159 160 #define YT921X_EEEn_VAL(port) (0xa0000 + 0x40 * (port)) 161 #define YT921X_EEE_VAL_DATA BIT(1) 162 163 #define YT921X_EEE_CTRL 0xb0000 164 #define YT921X_EEE_CTRL_ENn(port) BIT(port) 165 166 #define YT921X_EDATA_CTRL 0xe0000 167 #define YT921X_EDATA_CTRL_ADDR_M GENMASK(15, 8) 168 #define YT921X_EDATA_CTRL_ADDR(x) FIELD_PREP(YT921X_EDATA_CTRL_ADDR_M, (x)) 169 #define YT921X_EDATA_CTRL_OP_M GENMASK(3, 0) 170 #define YT921X_EDATA_CTRL_OP(x) FIELD_PREP(YT921X_EDATA_CTRL_OP_M, (x)) 171 #define YT921X_EDATA_CTRL_READ YT921X_EDATA_CTRL_OP(5) 172 #define YT921X_EDATA_DATA 0xe0004 173 #define YT921X_EDATA_DATA_DATA_M GENMASK(31, 24) 174 #define YT921X_EDATA_DATA_STATUS_M GENMASK(3, 0) 175 #define YT921X_EDATA_DATA_STATUS(x) FIELD_PREP(YT921X_EDATA_DATA_STATUS_M, (x)) 176 #define YT921X_EDATA_DATA_IDLE YT921X_EDATA_DATA_STATUS(3) 177 #define YT921X_SYS_CLK 0xe0040 178 #define YT921X_SYS_CLK_SEL_M GENMASK(1, 0) /* unknown: 167M */ 179 #define YT9215_SYS_CLK_125M 0 180 #define YT9218_SYS_CLK_167M 0 181 #define YT921X_SYS_CLK_143M 1 182 183 #define YT921X_PORTn_EGR(port) (0x100000 + 4 * (port)) 184 #define YT921X_PORT_EGR_TPID_CTAG_M GENMASK(5, 4) 185 #define YT921X_PORT_EGR_TPID_CTAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_CTAG_M, (x)) 186 #define YT921X_PORT_EGR_TPID_STAG_M GENMASK(3, 2) 187 #define YT921X_PORT_EGR_TPID_STAG(x) FIELD_PREP(YT921X_PORT_EGR_TPID_STAG_M, (x)) 188 #define YT921X_TPID_EGRn(x) (0x100300 + 4 * (x)) /* [0, 3] */ 189 #define YT921X_TPID_EGR_TPID_M GENMASK(15, 0) 190 191 #define YT921X_IPM_DSCPn(n) (0x180000 + 4 * (n)) /* Internal Priority Map */ 192 #define YT921X_IPM_PCPn(map, dei, pcp) (0x180100 + 4 * (16 * (map) + 8 * (dei) + (pcp))) 193 #define YT921X_IPM_PRIO_M GENMASK(4, 2) 194 #define YT921X_IPM_PRIO(x) FIELD_PREP(YT921X_IPM_PRIO_M, (x)) 195 #define YT921X_IPM_COLOR_M GENMASK(1, 0) 196 #define YT921X_IPM_COLOR(x) FIELD_PREP(YT921X_IPM_COLOR_M, (x)) 197 #define YT921X_IPM_COLOR_GREEN YT921X_IPM_COLOR(0) 198 #define YT921X_IPM_COLOR_YELLOW YT921X_IPM_COLOR(1) 199 #define YT921X_IPM_COLOR_RED YT921X_IPM_COLOR(2) 200 #define YT921X_PORTn_QOS(port) (0x180180 + 4 * (port)) 201 #define YT921X_PORT_QOS_CVLAN_PRIO_MAP_ID BIT(5) 202 #define YT921X_PORT_QOS_SVLAN_PRIO_MAP_ID BIT(4) 203 #define YT921X_PORT_QOS_PRIO_M GENMASK(3, 1) 204 #define YT921X_PORT_QOS_PRIO(x) FIELD_PREP(YT921X_PORT_QOS_PRIO_M, (x)) 205 #define YT921X_PORT_QOS_PRIO_EN BIT(0) 206 #define YT921X_PORTn_PRIO_ORD(port) (0x180200 + 4 * (port)) 207 #define YT921X_PORT_PRIO_ORD_APPm_M(m) GENMASK(3 * (m) + 2, 3 * (m)) 208 #define YT921X_PORT_PRIO_ORD_APPm(m, x) ((x) << (3 * (m))) /* 0: disabled, except PORT_QOS_PRIO */ 209 210 enum yt921x_app_selector { 211 YT921X_APP_SEL_MAC_SA, 212 YT921X_APP_SEL_MAC_DA, 213 YT921X_APP_SEL_VID, 214 YT921X_APP_SEL_ACL, 215 YT921X_APP_SEL_DSCP, 216 YT921X_APP_SEL_CVLAN_PCP, 217 YT921X_APP_SEL_SVLAN_PCP, 218 /* The physical port, i.e. YT921X_PORT_QOS_PRIO */ 219 YT921X_APP_SEL_PORT, 220 YT921X_APP_SEL_NUM 221 }; 222 223 #define YT921X_VLAN_IGR_FILTER 0x180280 224 #define YT921X_VLAN_IGR_FILTER_PORTn_BYPASS_IGMP(port) BIT((port) + 11) 225 #define YT921X_VLAN_IGR_FILTER_PORTn(port) BIT(port) 226 #define YT921X_PORTn_ISOLATION(port) (0x180294 + 4 * (port)) 227 #define YT921X_PORT_ISOLATION_BLOCKn(port) BIT(port) 228 #define YT921X_STPn(n) (0x18038c + 4 * (n)) 229 #define YT921X_STP_PORTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 230 #define YT921X_STP_PORTn(port, x) ((x) << (2 * (port))) 231 #define YT921X_STP_PORTn_DISABLED(port) YT921X_STP_PORTn(port, 0) 232 #define YT921X_STP_PORTn_LEARNING(port) YT921X_STP_PORTn(port, 1) 233 #define YT921X_STP_PORTn_BLOCKING(port) YT921X_STP_PORTn(port, 2) 234 #define YT921X_STP_PORTn_FORWARD(port) YT921X_STP_PORTn(port, 3) 235 #define YT921X_PORTn_LEARN(port) (0x1803d0 + 4 * (port)) 236 #define YT921X_PORT_LEARN_VID_LEARN_MULTI_EN BIT(22) 237 #define YT921X_PORT_LEARN_VID_LEARN_MODE BIT(21) 238 #define YT921X_PORT_LEARN_VID_LEARN_EN BIT(20) 239 #define YT921X_PORT_LEARN_SUSPEND_COPY_EN BIT(19) 240 #define YT921X_PORT_LEARN_SUSPEND_DROP_EN BIT(18) 241 #define YT921X_PORT_LEARN_DIS BIT(17) 242 #define YT921X_PORT_LEARN_LIMIT_EN BIT(16) 243 #define YT921X_PORT_LEARN_LIMIT_M GENMASK(15, 8) 244 #define YT921X_PORT_LEARN_LIMIT(x) FIELD_PREP(YT921X_PORT_LEARN_LIMIT_M, (x)) 245 #define YT921X_PORT_LEARN_DROP_ON_EXCEEDED BIT(2) 246 #define YT921X_PORT_LEARN_MODE_M GENMASK(1, 0) 247 #define YT921X_PORT_LEARN_MODE(x) FIELD_PREP(YT921X_PORT_LEARN_MODE_M, (x)) 248 #define YT921X_PORT_LEARN_MODE_AUTO YT921X_PORT_LEARN_MODE(0) 249 #define YT921X_PORT_LEARN_MODE_AUTO_AND_COPY YT921X_PORT_LEARN_MODE(1) 250 #define YT921X_PORT_LEARN_MODE_CPU_CONTROL YT921X_PORT_LEARN_MODE(2) 251 #define YT921X_AGEING 0x180440 252 #define YT921X_AGEING_INTERVAL_M GENMASK(15, 0) 253 #define YT921X_FDB_IN0 0x180454 254 #define YT921X_FDB_IN1 0x180458 255 #define YT921X_FDB_IN2 0x18045c 256 #define YT921X_FDB_OP 0x180460 257 #define YT921X_FDB_OP_INDEX_M GENMASK(22, 11) 258 #define YT921X_FDB_OP_INDEX(x) FIELD_PREP(YT921X_FDB_OP_INDEX_M, (x)) 259 #define YT921X_FDB_OP_MODE_INDEX BIT(10) /* mac+fid / index */ 260 #define YT921X_FDB_OP_FLUSH_MCAST BIT(9) /* ucast / mcast */ 261 #define YT921X_FDB_OP_FLUSH_M GENMASK(8, 7) 262 #define YT921X_FDB_OP_FLUSH(x) FIELD_PREP(YT921X_FDB_OP_FLUSH_M, (x)) 263 #define YT921X_FDB_OP_FLUSH_ALL YT921X_FDB_OP_FLUSH(0) 264 #define YT921X_FDB_OP_FLUSH_PORT YT921X_FDB_OP_FLUSH(1) 265 #define YT921X_FDB_OP_FLUSH_PORT_VID YT921X_FDB_OP_FLUSH(2) 266 #define YT921X_FDB_OP_FLUSH_VID YT921X_FDB_OP_FLUSH(3) 267 #define YT921X_FDB_OP_FLUSH_STATIC BIT(6) 268 #define YT921X_FDB_OP_NEXT_TYPE_M GENMASK(5, 4) 269 #define YT921X_FDB_OP_NEXT_TYPE(x) FIELD_PREP(YT921X_FDB_OP_NEXT_TYPE_M, (x)) 270 #define YT921X_FDB_OP_NEXT_TYPE_UCAST_PORT YT921X_FDB_OP_NEXT_TYPE(0) 271 #define YT921X_FDB_OP_NEXT_TYPE_UCAST_VID YT921X_FDB_OP_NEXT_TYPE(1) 272 #define YT921X_FDB_OP_NEXT_TYPE_UCAST YT921X_FDB_OP_NEXT_TYPE(2) 273 #define YT921X_FDB_OP_NEXT_TYPE_MCAST YT921X_FDB_OP_NEXT_TYPE(3) 274 #define YT921X_FDB_OP_OP_M GENMASK(3, 1) 275 #define YT921X_FDB_OP_OP(x) FIELD_PREP(YT921X_FDB_OP_OP_M, (x)) 276 #define YT921X_FDB_OP_OP_ADD YT921X_FDB_OP_OP(0) 277 #define YT921X_FDB_OP_OP_DEL YT921X_FDB_OP_OP(1) 278 #define YT921X_FDB_OP_OP_GET_ONE YT921X_FDB_OP_OP(2) 279 #define YT921X_FDB_OP_OP_GET_NEXT YT921X_FDB_OP_OP(3) 280 #define YT921X_FDB_OP_OP_FLUSH YT921X_FDB_OP_OP(4) 281 #define YT921X_FDB_OP_START BIT(0) 282 #define YT921X_FDB_RESULT 0x180464 283 #define YT921X_FDB_RESULT_DONE BIT(15) 284 #define YT921X_FDB_RESULT_NOTFOUND BIT(14) 285 #define YT921X_FDB_RESULT_OVERWRITED BIT(13) 286 #define YT921X_FDB_RESULT_INDEX_M GENMASK(11, 0) 287 #define YT921X_FDB_RESULT_INDEX(x) FIELD_PREP(YT921X_FDB_RESULT_INDEX_M, (x)) 288 #define YT921X_FDB_OUT0 0x1804b0 289 #define YT921X_FDB_IO0_ADDR_HI4_M GENMASK(31, 0) 290 #define YT921X_FDB_OUT1 0x1804b4 291 #define YT921X_FDB_IO1_EGR_PRIO_EN BIT(31) 292 #define YT921X_FDB_IO1_STATUS_M GENMASK(30, 28) 293 #define YT921X_FDB_IO1_STATUS(x) FIELD_PREP(YT921X_FDB_IO1_STATUS_M, (x)) 294 #define YT921X_FDB_IO1_STATUS_INVALID YT921X_FDB_IO1_STATUS(0) 295 #define YT921X_FDB_IO1_STATUS_MIN_TIME YT921X_FDB_IO1_STATUS(1) 296 #define YT921X_FDB_IO1_STATUS_MOVE_AGING_MAX_TIME YT921X_FDB_IO1_STATUS(3) 297 #define YT921X_FDB_IO1_STATUS_MAX_TIME YT921X_FDB_IO1_STATUS(5) 298 #define YT921X_FDB_IO1_STATUS_PENDING YT921X_FDB_IO1_STATUS(6) 299 #define YT921X_FDB_IO1_STATUS_STATIC YT921X_FDB_IO1_STATUS(7) 300 #define YT921X_FDB_IO1_FID_M GENMASK(27, 16) /* filtering ID (VID) */ 301 #define YT921X_FDB_IO1_FID(x) FIELD_PREP(YT921X_FDB_IO1_FID_M, (x)) 302 #define YT921X_FDB_IO1_ADDR_LO2_M GENMASK(15, 0) 303 #define YT921X_FDB_OUT2 0x1804b8 304 #define YT921X_FDB_IO2_MOVE_AGING_STATUS_M GENMASK(31, 30) 305 #define YT921X_FDB_IO2_IGR_DROP BIT(29) 306 #define YT921X_FDB_IO2_EGR_PORTS_M GENMASK(28, 18) 307 #define YT921X_FDB_IO2_EGR_PORTS(x) FIELD_PREP(YT921X_FDB_IO2_EGR_PORTS_M, (x)) 308 #define YT921X_FDB_IO2_EGR_DROP BIT(17) 309 #define YT921X_FDB_IO2_COPY_TO_CPU BIT(16) 310 #define YT921X_FDB_IO2_IGR_PRIO_EN BIT(15) 311 #define YT921X_FDB_IO2_PRIO_M GENMASK(14, 12) 312 #define YT921X_FDB_IO2_PRIO(x) FIELD_PREP(YT921X_FDB_IO2_PRIO_M, (x)) 313 #define YT921X_FDB_IO2_NEW_VID_M GENMASK(11, 0) 314 #define YT921X_FDB_IO2_NEW_VID(x) FIELD_PREP(YT921X_FDB_IO2_NEW_VID_M, (x)) 315 #define YT921X_FILTER_UNK_UCAST 0x180508 316 #define YT921X_FILTER_UNK_MCAST 0x18050c 317 #define YT921X_FILTER_MCAST 0x180510 318 #define YT921X_FILTER_BCAST 0x180514 319 #define YT921X_FILTER_PORTS_M GENMASK(10, 0) 320 #define YT921X_FILTER_PORTS(x) FIELD_PREP(YT921X_FILTER_PORTS_M, (x)) 321 #define YT921X_FILTER_PORTn(port) BIT(port) 322 #define YT921X_VLAN_EGR_FILTER 0x180598 323 #define YT921X_VLAN_EGR_FILTER_PORTn(port) BIT(port) 324 #define YT921X_LAG_GROUPn(n) (0x1805a8 + 4 * (n)) 325 #define YT921X_LAG_GROUP_PORTS_M GENMASK(13, 3) 326 #define YT921X_LAG_GROUP_PORTS(x) FIELD_PREP(YT921X_LAG_GROUP_PORTS_M, (x)) 327 #define YT921X_LAG_GROUP_MEMBER_NUM_M GENMASK(2, 0) 328 #define YT921X_LAG_GROUP_MEMBER_NUM(x) FIELD_PREP(YT921X_LAG_GROUP_MEMBER_NUM_M, (x)) 329 #define YT921X_LAG_MEMBERnm(n, m) (0x1805b0 + 4 * (4 * (n) + (m))) 330 #define YT921X_LAG_MEMBER_PORT_M GENMASK(3, 0) 331 #define YT921X_LAG_MEMBER_PORT(x) FIELD_PREP(YT921X_LAG_MEMBER_PORT_M, (x)) 332 #define YT921X_CPU_COPY 0x180690 333 #define YT921X_CPU_COPY_FORCE_INT_PORT BIT(2) 334 #define YT921X_CPU_COPY_TO_INT_CPU BIT(1) 335 #define YT921X_CPU_COPY_TO_EXT_CPU BIT(0) 336 #define YT921X_ACL_PERMIT_UNMATCH 0x1806a0 337 #define YT921X_ACL_PERMIT_UNMATCH_PORTS_M GENMASK(10, 0) 338 #define YT921X_ACL_PERMIT_UNMATCH_PORTS(x) FIELD_PREP(YT921X_ACL_PERMIT_UNMATCH_PORTS_M, (x)) 339 #define YT921X_ACL_PERMIT_UNMATCH_PORTn(port) BIT(port) 340 #define YT921X_ACT_UNK_UCAST 0x180734 341 #define YT921X_ACT_UNK_MCAST 0x180738 342 #define YT921X_ACT_UNK_MCAST_BYPASS_DROP_RMA BIT(23) 343 #define YT921X_ACT_UNK_MCAST_BYPASS_DROP_IGMP BIT(22) 344 #define YT921X_ACT_UNK_ACTn_M(port) GENMASK(2 * (port) + 1, 2 * (port)) 345 #define YT921X_ACT_UNK_ACTn(port, x) ((x) << (2 * (port))) 346 #define YT921X_ACT_UNK_ACTn_FORWARD(port) YT921X_ACT_UNK_ACTn(port, 0) /* flood */ 347 #define YT921X_ACT_UNK_ACTn_TRAP(port) YT921X_ACT_UNK_ACTn(port, 1) /* steer to CPU */ 348 #define YT921X_ACT_UNK_ACTn_DROP(port) YT921X_ACT_UNK_ACTn(port, 2) /* discard */ 349 /* NEVER use this action; see comments in the tag driver */ 350 #define YT921X_ACT_UNK_ACTn_COPY(port) YT921X_ACT_UNK_ACTn(port, 3) /* flood and copy */ 351 #define YT921X_FDB_HW_FLUSH 0x180958 352 #define YT921X_FDB_HW_FLUSH_ON_LINKDOWN BIT(0) 353 354 #define YT921X_VLANn_CTRL(vlan) (0x188000 + 8 * (vlan)) 355 #define YT921X_VLAN_CTRLb_UNTAG_PORTS_M GENMASK(18, 8) 356 #define YT921X_VLAN_CTRLb_UNTAG_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLb_UNTAG_PORTS_M, (x)) 357 #define YT921X_VLAN_CTRLb_UNTAG_PORTn(port) BIT((port) + 8) 358 #define YT921X_VLAN_CTRLb_STP_ID_M GENMASK(7, 4) 359 #define YT921X_VLAN_CTRLb_STP_ID(x) FIELD_PREP(YT921X_VLAN_CTRLb_STP_ID_M, (x)) 360 #define YT921X_VLAN_CTRLb_SVLAN_EN BIT(3) 361 #define YT921X_VLAN_CTRLab_FID_M GENMASK_ULL(34, 23) 362 #define YT921X_VLAN_CTRLab_FID(x) FIELD_PREP(YT921X_VLAN_CTRLab_FID_M, (x)) 363 #define YT921X_VLAN_CTRLa_LEARN_DIS BIT(22) 364 #define YT921X_VLAN_CTRLa_PRIO_EN BIT(21) 365 #define YT921X_VLAN_CTRLa_PRIO_M GENMASK(20, 18) 366 #define YT921X_VLAN_CTRLa_PRIO(x) FIELD_PREP(YT921X_VLAN_CTRLa_PRIO_M, (x)) 367 #define YT921X_VLAN_CTRLa_PORTS_M GENMASK(17, 7) 368 #define YT921X_VLAN_CTRLa_PORTS(x) FIELD_PREP(YT921X_VLAN_CTRLa_PORTS_M, (x)) 369 #define YT921X_VLAN_CTRLa_PORTn(port) BIT((port) + 7) 370 #define YT921X_VLAN_CTRLa_BYPASS_1X_AC BIT(6) 371 #define YT921X_VLAN_CTRLa_METER_EN BIT(5) 372 #define YT921X_VLAN_CTRLa_METER_ID_M GENMASK(4, 0) 373 374 #define YT921X_TPID_IGRn(x) (0x210000 + 4 * (x)) /* [0, 3] */ 375 #define YT921X_TPID_IGR_TPID_M GENMASK(15, 0) 376 #define YT921X_PORTn_IGR_TPID(port) (0x210010 + 4 * (port)) 377 #define YT921X_PORT_IGR_TPIDn_STAG_M GENMASK(7, 4) 378 #define YT921X_PORT_IGR_TPIDn_STAG(x) BIT((x) + 4) 379 #define YT921X_PORT_IGR_TPIDn_CTAG_M GENMASK(3, 0) 380 #define YT921X_PORT_IGR_TPIDn_CTAG(x) BIT(x) 381 #define YT921X_LAG_HASH 0x210090 382 #define YT921X_LAG_HASH_L4_SPORT BIT(7) 383 #define YT921X_LAG_HASH_L4_DPORT BIT(6) 384 #define YT921X_LAG_HASH_IP_PROTO BIT(5) 385 #define YT921X_LAG_HASH_IP_SRC BIT(4) 386 #define YT921X_LAG_HASH_IP_DST BIT(3) 387 #define YT921X_LAG_HASH_MAC_SA BIT(2) 388 #define YT921X_LAG_HASH_MAC_DA BIT(1) 389 #define YT921X_LAG_HASH_SRC_PORT BIT(0) 390 391 #define YT921X_PORTn_VLAN_CTRL(port) (0x230010 + 4 * (port)) 392 #define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_EN BIT(31) 393 #define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_EN BIT(30) 394 #define YT921X_PORT_VLAN_CTRL_SVID_M GENMASK(29, 18) 395 #define YT921X_PORT_VLAN_CTRL_SVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_SVID_M, (x)) 396 #define YT921X_PORT_VLAN_CTRL_CVID_M GENMASK(17, 6) 397 #define YT921X_PORT_VLAN_CTRL_CVID(x) FIELD_PREP(YT921X_PORT_VLAN_CTRL_CVID_M, (x)) 398 #define YT921X_PORT_VLAN_CTRL_SVLAN_PRIO_M GENMASK(5, 3) 399 #define YT921X_PORT_VLAN_CTRL_CVLAN_PRIO_M GENMASK(2, 0) 400 #define YT921X_PORTn_VLAN_CTRL1(port) (0x230080 + 4 * (port)) 401 #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_EN BIT(8) 402 #define YT921X_PORT_VLAN_CTRL1_VLAN_RANGE_PROFILE_ID_M GENMASK(7, 4) 403 #define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_TAGGED BIT(3) 404 #define YT921X_PORT_VLAN_CTRL1_SVLAN_DROP_UNTAGGED BIT(2) 405 #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED BIT(1) 406 #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED BIT(0) 407 408 #define YT921X_EDATA_EXTMODE 0xfb 409 #define YT921X_EDATA_LEN 0x100 410 411 #define YT921X_FDB_NUM 4096 412 413 enum yt921x_fdb_entry_status { 414 YT921X_FDB_ENTRY_STATUS_INVALID = 0, 415 YT921X_FDB_ENTRY_STATUS_MIN_TIME = 1, 416 YT921X_FDB_ENTRY_STATUS_MOVE_AGING_MAX_TIME = 3, 417 YT921X_FDB_ENTRY_STATUS_MAX_TIME = 5, 418 YT921X_FDB_ENTRY_STATUS_PENDING = 6, 419 YT921X_FDB_ENTRY_STATUS_STATIC = 7, 420 }; 421 422 #define YT921X_MSTI_NUM 16 423 424 /* Custom meters only, not including dedicated port meters (11) */ 425 #define YT921X_METER_NUM 64 426 427 #define YT921X_LAG_NUM 2 428 #define YT921X_LAG_PORT_NUM 4 429 430 #define YT921X_PRIO_NUM 8 431 432 #define YT9215_MAJOR 0x9002 433 #define YT9218_MAJOR 0x9001 434 435 /* required for a hard reset */ 436 #define YT921X_RST_DELAY_US 10000 437 438 #define YT921X_FRAME_SIZE_MAX 0x2400 /* 9216 */ 439 440 #define YT921X_TAG_LEN 8 441 442 #define YT921X_ACL_BLK_NUM 48 443 #define YT921X_UDF_NUM 16 444 445 #define YT921X_LED_GROUP_NUM 3 446 #define YT921X_LED_PORT_NUM 10 447 448 /* 8 internal + 2 external + 1 mcu */ 449 #define YT921X_PORT_NUM 11 450 451 #define YT921X_NAME "yt921x" 452 453 struct yt921x_port { 454 unsigned char index; 455 456 /* SerDes in use */ 457 bool serdes:1; 458 /* Link from in-band status (PHYLINK_PCS_NEG_INBAND) */ 459 bool inband:1; 460 /* BR_HAIRPIN_MODE */ 461 bool hairpin:1; 462 /* BR_ISOLATED */ 463 bool isolated:1; 464 465 unsigned short acl_cnt; 466 467 #if IS_ENABLED(CONFIG_NET_DSA_YT921X_LEDS) 468 unsigned char led_duty; 469 unsigned short led_cycle; 470 471 unsigned char led_duty_mask; 472 unsigned char led_cycle_mask; 473 474 struct yt921x_led *leds[YT921X_LED_GROUP_NUM]; 475 #endif 476 477 struct yt921x_mib *mib; 478 struct phylink_pcs pcs; 479 }; 480 481 #define pcs_to_yt921x_port(_pcs) container_of((_pcs), struct yt921x_port, pcs) 482 483 struct yt921x_reg_ops { 484 int (*read)(void *context, u32 reg, u32 *valp); 485 int (*write)(void *context, u32 reg, u32 val); 486 }; 487 488 struct yt921x_info { 489 const char *name; 490 u16 major; 491 /* Unknown, seems to be plain enumeration */ 492 u8 mode; 493 u8 extmode; 494 /* Ports with integral GbE PHYs, not including MCU Port 10 */ 495 u16 internal_mask; 496 /* Note: xmii_mask and serdes_mask may overlap */ 497 u16 xmii_mask; 498 u16 serdes_mask; 499 }; 500 501 static inline u16 yt921x_info_ports_mask(const struct yt921x_info *info) 502 { 503 return info->internal_mask | info->xmii_mask | info->serdes_mask; 504 } 505 506 struct yt921x_priv { 507 struct dsa_switch ds; 508 509 const struct yt921x_info *info; 510 unsigned int meter_slot_ns; 511 unsigned int port_shape_slot_ns; 512 /* cache of dsa_cpu_ports(ds) */ 513 u16 cpu_ports_mask; 514 unsigned char cycle_ns; 515 516 /* protect the access to the switch registers */ 517 struct mutex reg_lock; 518 const struct yt921x_reg_ops *reg_ops; 519 void *reg_ctx; 520 521 /* mdio master bus */ 522 struct mii_bus *mbus_int; 523 struct mii_bus *mbus_ext; 524 525 struct yt921x_port ports[YT921X_PORT_NUM]; 526 527 u16 eee_ports_mask; 528 529 DECLARE_BITMAP(meters_map, YT921X_METER_NUM); 530 531 u8 acl_masks[YT921X_ACL_BLK_NUM]; 532 struct yt921x_acl_blk *acl_blks[YT921X_ACL_BLK_NUM]; 533 }; 534 535 #define dsa_to_yt921x_priv(_ds) container_of_const(_ds, struct yt921x_priv, ds) 536 #define yt921x_port_to_priv(pp) \ 537 container_of_const((pp), struct yt921x_priv, ports[(pp)->index]) 538 #define yt921x_priv_to_device(priv) ((priv)->ds.dev) 539 540 static inline int ethtool_speed_to_yt921x(int speed) 541 { 542 switch (speed) { 543 case SPEED_10: 544 return YT921X_SPEED_10; 545 case SPEED_100: 546 return YT921X_SPEED_100; 547 case SPEED_1000: 548 return YT921X_SPEED_1000; 549 case SPEED_2500: 550 return YT921X_SPEED_2500; 551 case SPEED_10000: 552 return YT921X_SPEED_10000; 553 default: 554 return YT921X_SPEED_INVALID; 555 } 556 } 557 558 static inline u32 ethaddr_hi4_to_u32(const unsigned char *addr) 559 { 560 return (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 561 } 562 563 static inline u32 ethaddr_lo2_to_u32(const unsigned char *addr) 564 { 565 return (addr[4] << 8) | addr[5]; 566 } 567 568 #endif 569