1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Microchip switch driver common header 3 * 4 * Copyright (C) 2017-2024 Microchip Technology Inc. 5 */ 6 7 #ifndef __KSZ_COMMON_H 8 #define __KSZ_COMMON_H 9 10 #include <linux/etherdevice.h> 11 #include <linux/kernel.h> 12 #include <linux/mutex.h> 13 #include <linux/phy.h> 14 #include <linux/regmap.h> 15 #include <net/dsa.h> 16 #include <linux/irq.h> 17 #include <linux/platform_data/microchip-ksz.h> 18 19 #include "ksz_ptp.h" 20 21 #define KSZ_MAX_NUM_PORTS 8 22 /* all KSZ switches count ports from 1 */ 23 #define KSZ_PORT_1 0 24 #define KSZ_PORT_2 1 25 #define KSZ_PORT_4 3 26 27 struct ksz_device; 28 struct ksz_port; 29 struct phylink_mac_ops; 30 31 enum ksz_regmap_width { 32 KSZ_REGMAP_8, 33 KSZ_REGMAP_16, 34 KSZ_REGMAP_32, 35 __KSZ_NUM_REGMAPS, 36 }; 37 38 struct vlan_table { 39 u32 table[3]; 40 }; 41 42 struct ksz_port_mib { 43 struct mutex cnt_mutex; /* structure access */ 44 u8 cnt_ptr; 45 u64 *counters; 46 struct rtnl_link_stats64 stats64; 47 struct ethtool_pause_stats pause_stats; 48 struct spinlock stats64_lock; 49 }; 50 51 struct ksz_mib_names { 52 int index; 53 char string[ETH_GSTRING_LEN]; 54 }; 55 56 struct ksz_chip_data { 57 u32 chip_id; 58 const char *dev_name; 59 int num_vlans; 60 int num_alus; 61 int num_statics; 62 int cpu_ports; 63 int port_cnt; 64 u8 port_nirqs; 65 u8 num_tx_queues; 66 u8 num_ipms; /* number of Internal Priority Maps */ 67 bool tc_cbs_supported; 68 const struct ksz_dev_ops *ops; 69 const struct phylink_mac_ops *phylink_mac_ops; 70 bool phy_errata_9477; 71 bool ksz87xx_eee_link_erratum; 72 const struct ksz_mib_names *mib_names; 73 int mib_cnt; 74 u8 reg_mib_cnt; 75 const u16 *regs; 76 const u32 *masks; 77 const u8 *shifts; 78 const u8 *xmii_ctrl0; 79 const u8 *xmii_ctrl1; 80 int stp_ctrl_reg; 81 int broadcast_ctrl_reg; 82 int multicast_ctrl_reg; 83 int start_ctrl_reg; 84 bool supports_mii[KSZ_MAX_NUM_PORTS]; 85 bool supports_rmii[KSZ_MAX_NUM_PORTS]; 86 bool supports_rgmii[KSZ_MAX_NUM_PORTS]; 87 bool internal_phy[KSZ_MAX_NUM_PORTS]; 88 bool gbit_capable[KSZ_MAX_NUM_PORTS]; 89 const struct regmap_access_table *wr_table; 90 const struct regmap_access_table *rd_table; 91 }; 92 93 struct ksz_irq { 94 u16 masked; 95 u16 reg_mask; 96 u16 reg_status; 97 struct irq_domain *domain; 98 int nirqs; 99 int irq_num; 100 char name[16]; 101 struct ksz_device *dev; 102 }; 103 104 struct ksz_ptp_irq { 105 struct ksz_port *port; 106 u16 ts_reg; 107 bool ts_en; 108 char name[16]; 109 int num; 110 }; 111 112 struct ksz_switch_macaddr { 113 unsigned char addr[ETH_ALEN]; 114 refcount_t refcount; 115 }; 116 117 struct ksz_port { 118 bool remove_tag; /* Remove Tag flag set, for ksz8795 only */ 119 bool learning; 120 bool isolated; 121 int stp_state; 122 struct phy_device phydev; 123 124 u32 fiber:1; /* port is fiber */ 125 u32 force:1; 126 u32 read:1; /* read MIB counters in background */ 127 u32 freeze:1; /* MIB counter freeze is enabled */ 128 129 struct ksz_port_mib mib; 130 phy_interface_t interface; 131 u32 rgmii_tx_val; 132 u32 rgmii_rx_val; 133 struct ksz_device *ksz_dev; 134 void *acl_priv; 135 struct ksz_irq pirq; 136 u8 num; 137 #if IS_ENABLED(CONFIG_NET_DSA_MICROCHIP_KSZ_PTP) 138 struct hwtstamp_config tstamp_config; 139 bool hwts_tx_en; 140 bool hwts_rx_en; 141 struct ksz_irq ptpirq; 142 struct ksz_ptp_irq ptpmsg_irq[3]; 143 ktime_t tstamp_msg; 144 struct completion tstamp_msg_comp; 145 #endif 146 bool manual_flow; 147 }; 148 149 struct ksz_device { 150 struct dsa_switch *ds; 151 struct ksz_platform_data *pdata; 152 const struct ksz_chip_data *info; 153 154 struct mutex dev_mutex; /* device access */ 155 struct mutex regmap_mutex; /* regmap access */ 156 struct mutex alu_mutex; /* ALU access */ 157 struct mutex vlan_mutex; /* vlan access */ 158 const struct ksz_dev_ops *dev_ops; 159 160 struct device *dev; 161 struct regmap *regmap[__KSZ_NUM_REGMAPS]; 162 163 void *priv; 164 int irq; 165 166 struct gpio_desc *reset_gpio; /* Optional reset GPIO */ 167 168 /* chip specific data */ 169 u32 chip_id; 170 u8 chip_rev; 171 int cpu_port; /* port connected to CPU */ 172 int phy_port_cnt; 173 phy_interface_t compat_interface; 174 bool synclko_125; 175 bool synclko_disable; 176 bool wakeup_source; 177 bool pme_active_high; 178 179 struct vlan_table *vlan_cache; 180 181 struct ksz_port *ports; 182 struct delayed_work mib_read; 183 unsigned long mib_read_interval; 184 u16 mirror_rx; 185 u16 mirror_tx; 186 u16 port_mask; 187 struct mutex lock_irq; /* IRQ Access */ 188 struct ksz_irq girq; 189 struct ksz_ptp_data ptp_data; 190 191 struct ksz_switch_macaddr *switch_macaddr; 192 struct net_device *hsr_dev; /* HSR */ 193 u8 hsr_ports; 194 }; 195 196 /* List of supported models */ 197 enum ksz_model { 198 KSZ8563, 199 KSZ8567, 200 KSZ8795, 201 KSZ8794, 202 KSZ8765, 203 KSZ88X3, 204 KSZ8864, 205 KSZ8895, 206 KSZ9477, 207 KSZ9896, 208 KSZ9897, 209 KSZ9893, 210 KSZ9563, 211 KSZ9567, 212 LAN9370, 213 LAN9371, 214 LAN9372, 215 LAN9373, 216 LAN9374, 217 }; 218 219 enum ksz_regs { 220 REG_SW_MAC_ADDR, 221 REG_IND_CTRL_0, 222 REG_IND_DATA_8, 223 REG_IND_DATA_CHECK, 224 REG_IND_DATA_HI, 225 REG_IND_DATA_LO, 226 REG_IND_MIB_CHECK, 227 REG_IND_BYTE, 228 P_FORCE_CTRL, 229 P_LINK_STATUS, 230 P_LOCAL_CTRL, 231 P_NEG_RESTART_CTRL, 232 P_REMOTE_STATUS, 233 P_SPEED_STATUS, 234 S_TAIL_TAG_CTRL, 235 P_STP_CTRL, 236 S_START_CTRL, 237 S_BROADCAST_CTRL, 238 S_MULTICAST_CTRL, 239 P_XMII_CTRL_0, 240 P_XMII_CTRL_1, 241 REG_SW_PME_CTRL, 242 REG_PORT_PME_STATUS, 243 REG_PORT_PME_CTRL, 244 }; 245 246 enum ksz_masks { 247 PORT_802_1P_REMAPPING, 248 SW_TAIL_TAG_ENABLE, 249 MIB_COUNTER_OVERFLOW, 250 MIB_COUNTER_VALID, 251 VLAN_TABLE_FID, 252 VLAN_TABLE_MEMBERSHIP, 253 VLAN_TABLE_VALID, 254 STATIC_MAC_TABLE_VALID, 255 STATIC_MAC_TABLE_USE_FID, 256 STATIC_MAC_TABLE_FID, 257 STATIC_MAC_TABLE_OVERRIDE, 258 STATIC_MAC_TABLE_FWD_PORTS, 259 DYNAMIC_MAC_TABLE_ENTRIES_H, 260 DYNAMIC_MAC_TABLE_MAC_EMPTY, 261 DYNAMIC_MAC_TABLE_NOT_READY, 262 DYNAMIC_MAC_TABLE_ENTRIES, 263 DYNAMIC_MAC_TABLE_FID, 264 DYNAMIC_MAC_TABLE_SRC_PORT, 265 DYNAMIC_MAC_TABLE_TIMESTAMP, 266 ALU_STAT_WRITE, 267 ALU_STAT_READ, 268 P_MII_TX_FLOW_CTRL, 269 P_MII_RX_FLOW_CTRL, 270 }; 271 272 enum ksz_shifts { 273 VLAN_TABLE_MEMBERSHIP_S, 274 VLAN_TABLE, 275 STATIC_MAC_FWD_PORTS, 276 STATIC_MAC_FID, 277 DYNAMIC_MAC_ENTRIES_H, 278 DYNAMIC_MAC_ENTRIES, 279 DYNAMIC_MAC_FID, 280 DYNAMIC_MAC_TIMESTAMP, 281 DYNAMIC_MAC_SRC_PORT, 282 ALU_STAT_INDEX, 283 }; 284 285 enum ksz_xmii_ctrl0 { 286 P_MII_100MBIT, 287 P_MII_10MBIT, 288 P_MII_FULL_DUPLEX, 289 P_MII_HALF_DUPLEX, 290 }; 291 292 enum ksz_xmii_ctrl1 { 293 P_RGMII_SEL, 294 P_RMII_SEL, 295 P_GMII_SEL, 296 P_MII_SEL, 297 P_GMII_1GBIT, 298 P_GMII_NOT_1GBIT, 299 }; 300 301 struct alu_struct { 302 /* entry 1 */ 303 u8 is_static:1; 304 u8 is_src_filter:1; 305 u8 is_dst_filter:1; 306 u8 prio_age:3; 307 u32 _reserv_0_1:23; 308 u8 mstp:3; 309 /* entry 2 */ 310 u8 is_override:1; 311 u8 is_use_fid:1; 312 u32 _reserv_1_1:23; 313 u8 port_forward:7; 314 /* entry 3 & 4*/ 315 u32 _reserv_2_1:9; 316 u8 fid:7; 317 u8 mac[ETH_ALEN]; 318 }; 319 320 struct ksz_dev_ops { 321 int (*setup)(struct dsa_switch *ds); 322 void (*teardown)(struct dsa_switch *ds); 323 u32 (*get_port_addr)(int port, int offset); 324 void (*cfg_port_member)(struct ksz_device *dev, int port, u8 member); 325 void (*flush_dyn_mac_table)(struct ksz_device *dev, int port); 326 void (*port_cleanup)(struct ksz_device *dev, int port); 327 void (*port_setup)(struct ksz_device *dev, int port, bool cpu_port); 328 int (*set_ageing_time)(struct ksz_device *dev, unsigned int msecs); 329 int (*r_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 *val); 330 int (*w_phy)(struct ksz_device *dev, u16 phy, u16 reg, u16 val); 331 void (*r_mib_cnt)(struct ksz_device *dev, int port, u16 addr, 332 u64 *cnt); 333 void (*r_mib_pkt)(struct ksz_device *dev, int port, u16 addr, 334 u64 *dropped, u64 *cnt); 335 void (*r_mib_stat64)(struct ksz_device *dev, int port); 336 int (*vlan_filtering)(struct ksz_device *dev, int port, 337 bool flag, struct netlink_ext_ack *extack); 338 int (*vlan_add)(struct ksz_device *dev, int port, 339 const struct switchdev_obj_port_vlan *vlan, 340 struct netlink_ext_ack *extack); 341 int (*vlan_del)(struct ksz_device *dev, int port, 342 const struct switchdev_obj_port_vlan *vlan); 343 int (*mirror_add)(struct ksz_device *dev, int port, 344 struct dsa_mall_mirror_tc_entry *mirror, 345 bool ingress, struct netlink_ext_ack *extack); 346 void (*mirror_del)(struct ksz_device *dev, int port, 347 struct dsa_mall_mirror_tc_entry *mirror); 348 int (*fdb_add)(struct ksz_device *dev, int port, 349 const unsigned char *addr, u16 vid, struct dsa_db db); 350 int (*fdb_del)(struct ksz_device *dev, int port, 351 const unsigned char *addr, u16 vid, struct dsa_db db); 352 int (*fdb_dump)(struct ksz_device *dev, int port, 353 dsa_fdb_dump_cb_t *cb, void *data); 354 int (*mdb_add)(struct ksz_device *dev, int port, 355 const struct switchdev_obj_port_mdb *mdb, 356 struct dsa_db db); 357 int (*mdb_del)(struct ksz_device *dev, int port, 358 const struct switchdev_obj_port_mdb *mdb, 359 struct dsa_db db); 360 void (*get_caps)(struct ksz_device *dev, int port, 361 struct phylink_config *config); 362 int (*change_mtu)(struct ksz_device *dev, int port, int mtu); 363 int (*pme_write8)(struct ksz_device *dev, u32 reg, u8 value); 364 int (*pme_pread8)(struct ksz_device *dev, int port, int offset, 365 u8 *data); 366 int (*pme_pwrite8)(struct ksz_device *dev, int port, int offset, 367 u8 data); 368 void (*freeze_mib)(struct ksz_device *dev, int port, bool freeze); 369 void (*port_init_cnt)(struct ksz_device *dev, int port); 370 void (*phylink_mac_link_up)(struct ksz_device *dev, int port, 371 unsigned int mode, 372 phy_interface_t interface, 373 struct phy_device *phydev, int speed, 374 int duplex, bool tx_pause, bool rx_pause); 375 void (*setup_rgmii_delay)(struct ksz_device *dev, int port); 376 int (*tc_cbs_set_cinc)(struct ksz_device *dev, int port, u32 val); 377 void (*config_cpu_port)(struct dsa_switch *ds); 378 int (*enable_stp_addr)(struct ksz_device *dev); 379 int (*reset)(struct ksz_device *dev); 380 int (*init)(struct ksz_device *dev); 381 void (*exit)(struct ksz_device *dev); 382 }; 383 384 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv); 385 int ksz_switch_register(struct ksz_device *dev); 386 void ksz_switch_remove(struct ksz_device *dev); 387 388 void ksz_init_mib_timer(struct ksz_device *dev); 389 bool ksz_is_port_mac_global_usable(struct dsa_switch *ds, int port); 390 void ksz_r_mib_stats64(struct ksz_device *dev, int port); 391 void ksz88xx_r_mib_stats64(struct ksz_device *dev, int port); 392 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state); 393 bool ksz_get_gbit(struct ksz_device *dev, int port); 394 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit); 395 extern const struct ksz_chip_data ksz_switch_chips[]; 396 int ksz_switch_macaddr_get(struct dsa_switch *ds, int port, 397 struct netlink_ext_ack *extack); 398 void ksz_switch_macaddr_put(struct dsa_switch *ds); 399 void ksz_switch_shutdown(struct ksz_device *dev); 400 int ksz_handle_wake_reason(struct ksz_device *dev, int port); 401 402 /* Common register access functions */ 403 static inline struct regmap *ksz_regmap_8(struct ksz_device *dev) 404 { 405 return dev->regmap[KSZ_REGMAP_8]; 406 } 407 408 static inline struct regmap *ksz_regmap_16(struct ksz_device *dev) 409 { 410 return dev->regmap[KSZ_REGMAP_16]; 411 } 412 413 static inline struct regmap *ksz_regmap_32(struct ksz_device *dev) 414 { 415 return dev->regmap[KSZ_REGMAP_32]; 416 } 417 418 static inline int ksz_read8(struct ksz_device *dev, u32 reg, u8 *val) 419 { 420 unsigned int value; 421 int ret = regmap_read(ksz_regmap_8(dev), reg, &value); 422 423 if (ret) 424 dev_err(dev->dev, "can't read 8bit reg: 0x%x %pe\n", reg, 425 ERR_PTR(ret)); 426 427 *val = value; 428 return ret; 429 } 430 431 static inline int ksz_read16(struct ksz_device *dev, u32 reg, u16 *val) 432 { 433 unsigned int value; 434 int ret = regmap_read(ksz_regmap_16(dev), reg, &value); 435 436 if (ret) 437 dev_err(dev->dev, "can't read 16bit reg: 0x%x %pe\n", reg, 438 ERR_PTR(ret)); 439 440 *val = value; 441 return ret; 442 } 443 444 static inline int ksz_read32(struct ksz_device *dev, u32 reg, u32 *val) 445 { 446 unsigned int value; 447 int ret = regmap_read(ksz_regmap_32(dev), reg, &value); 448 449 if (ret) 450 dev_err(dev->dev, "can't read 32bit reg: 0x%x %pe\n", reg, 451 ERR_PTR(ret)); 452 453 *val = value; 454 return ret; 455 } 456 457 static inline int ksz_read64(struct ksz_device *dev, u32 reg, u64 *val) 458 { 459 u32 value[2]; 460 int ret; 461 462 ret = regmap_bulk_read(ksz_regmap_32(dev), reg, value, 2); 463 if (ret) 464 dev_err(dev->dev, "can't read 64bit reg: 0x%x %pe\n", reg, 465 ERR_PTR(ret)); 466 else 467 *val = (u64)value[0] << 32 | value[1]; 468 469 return ret; 470 } 471 472 static inline int ksz_write8(struct ksz_device *dev, u32 reg, u8 value) 473 { 474 int ret; 475 476 ret = regmap_write(ksz_regmap_8(dev), reg, value); 477 if (ret) 478 dev_err(dev->dev, "can't write 8bit reg: 0x%x %pe\n", reg, 479 ERR_PTR(ret)); 480 481 return ret; 482 } 483 484 static inline int ksz_write16(struct ksz_device *dev, u32 reg, u16 value) 485 { 486 int ret; 487 488 ret = regmap_write(ksz_regmap_16(dev), reg, value); 489 if (ret) 490 dev_err(dev->dev, "can't write 16bit reg: 0x%x %pe\n", reg, 491 ERR_PTR(ret)); 492 493 return ret; 494 } 495 496 static inline int ksz_write32(struct ksz_device *dev, u32 reg, u32 value) 497 { 498 int ret; 499 500 ret = regmap_write(ksz_regmap_32(dev), reg, value); 501 if (ret) 502 dev_err(dev->dev, "can't write 32bit reg: 0x%x %pe\n", reg, 503 ERR_PTR(ret)); 504 505 return ret; 506 } 507 508 static inline int ksz_rmw16(struct ksz_device *dev, u32 reg, u16 mask, 509 u16 value) 510 { 511 int ret; 512 513 ret = regmap_update_bits(ksz_regmap_16(dev), reg, mask, value); 514 if (ret) 515 dev_err(dev->dev, "can't rmw 16bit reg 0x%x: %pe\n", reg, 516 ERR_PTR(ret)); 517 518 return ret; 519 } 520 521 static inline int ksz_rmw32(struct ksz_device *dev, u32 reg, u32 mask, 522 u32 value) 523 { 524 int ret; 525 526 ret = regmap_update_bits(ksz_regmap_32(dev), reg, mask, value); 527 if (ret) 528 dev_err(dev->dev, "can't rmw 32bit reg 0x%x: %pe\n", reg, 529 ERR_PTR(ret)); 530 531 return ret; 532 } 533 534 static inline int ksz_write64(struct ksz_device *dev, u32 reg, u64 value) 535 { 536 u32 val[2]; 537 538 /* Ick! ToDo: Add 64bit R/W to regmap on 32bit systems */ 539 value = swab64(value); 540 val[0] = swab32(value & 0xffffffffULL); 541 val[1] = swab32(value >> 32ULL); 542 543 return regmap_bulk_write(ksz_regmap_32(dev), reg, val, 2); 544 } 545 546 static inline int ksz_rmw8(struct ksz_device *dev, int offset, u8 mask, u8 val) 547 { 548 int ret; 549 550 ret = regmap_update_bits(ksz_regmap_8(dev), offset, mask, val); 551 if (ret) 552 dev_err(dev->dev, "can't rmw 8bit reg 0x%x: %pe\n", offset, 553 ERR_PTR(ret)); 554 555 return ret; 556 } 557 558 static inline int ksz_pread8(struct ksz_device *dev, int port, int offset, 559 u8 *data) 560 { 561 return ksz_read8(dev, dev->dev_ops->get_port_addr(port, offset), data); 562 } 563 564 static inline int ksz_pread16(struct ksz_device *dev, int port, int offset, 565 u16 *data) 566 { 567 return ksz_read16(dev, dev->dev_ops->get_port_addr(port, offset), data); 568 } 569 570 static inline int ksz_pread32(struct ksz_device *dev, int port, int offset, 571 u32 *data) 572 { 573 return ksz_read32(dev, dev->dev_ops->get_port_addr(port, offset), data); 574 } 575 576 static inline int ksz_pwrite8(struct ksz_device *dev, int port, int offset, 577 u8 data) 578 { 579 return ksz_write8(dev, dev->dev_ops->get_port_addr(port, offset), data); 580 } 581 582 static inline int ksz_pwrite16(struct ksz_device *dev, int port, int offset, 583 u16 data) 584 { 585 return ksz_write16(dev, dev->dev_ops->get_port_addr(port, offset), 586 data); 587 } 588 589 static inline int ksz_pwrite32(struct ksz_device *dev, int port, int offset, 590 u32 data) 591 { 592 return ksz_write32(dev, dev->dev_ops->get_port_addr(port, offset), 593 data); 594 } 595 596 static inline int ksz_prmw8(struct ksz_device *dev, int port, int offset, 597 u8 mask, u8 val) 598 { 599 return ksz_rmw8(dev, dev->dev_ops->get_port_addr(port, offset), 600 mask, val); 601 } 602 603 static inline int ksz_prmw32(struct ksz_device *dev, int port, int offset, 604 u32 mask, u32 val) 605 { 606 return ksz_rmw32(dev, dev->dev_ops->get_port_addr(port, offset), 607 mask, val); 608 } 609 610 static inline void ksz_regmap_lock(void *__mtx) 611 { 612 struct mutex *mtx = __mtx; 613 mutex_lock(mtx); 614 } 615 616 static inline void ksz_regmap_unlock(void *__mtx) 617 { 618 struct mutex *mtx = __mtx; 619 mutex_unlock(mtx); 620 } 621 622 static inline bool ksz_is_ksz87xx(struct ksz_device *dev) 623 { 624 return dev->chip_id == KSZ8795_CHIP_ID || 625 dev->chip_id == KSZ8794_CHIP_ID || 626 dev->chip_id == KSZ8765_CHIP_ID; 627 } 628 629 static inline bool ksz_is_ksz88x3(struct ksz_device *dev) 630 { 631 return dev->chip_id == KSZ88X3_CHIP_ID; 632 } 633 634 static inline bool ksz_is_8895_family(struct ksz_device *dev) 635 { 636 return dev->chip_id == KSZ8895_CHIP_ID || 637 dev->chip_id == KSZ8864_CHIP_ID; 638 } 639 640 static inline bool is_ksz8(struct ksz_device *dev) 641 { 642 return ksz_is_ksz87xx(dev) || ksz_is_ksz88x3(dev) || 643 ksz_is_8895_family(dev); 644 } 645 646 static inline bool is_ksz88xx(struct ksz_device *dev) 647 { 648 return ksz_is_ksz88x3(dev) || ksz_is_8895_family(dev); 649 } 650 651 static inline bool is_ksz9477(struct ksz_device *dev) 652 { 653 return dev->chip_id == KSZ9477_CHIP_ID; 654 } 655 656 static inline int is_lan937x(struct ksz_device *dev) 657 { 658 return dev->chip_id == LAN9370_CHIP_ID || 659 dev->chip_id == LAN9371_CHIP_ID || 660 dev->chip_id == LAN9372_CHIP_ID || 661 dev->chip_id == LAN9373_CHIP_ID || 662 dev->chip_id == LAN9374_CHIP_ID; 663 } 664 665 static inline bool is_lan937x_tx_phy(struct ksz_device *dev, int port) 666 { 667 return (dev->chip_id == LAN9371_CHIP_ID || 668 dev->chip_id == LAN9372_CHIP_ID) && port == KSZ_PORT_4; 669 } 670 671 /* STP State Defines */ 672 #define PORT_TX_ENABLE BIT(2) 673 #define PORT_RX_ENABLE BIT(1) 674 #define PORT_LEARN_DISABLE BIT(0) 675 676 /* Switch ID Defines */ 677 #define REG_CHIP_ID0 0x00 678 679 #define SW_FAMILY_ID_M GENMASK(15, 8) 680 #define KSZ87_FAMILY_ID 0x87 681 #define KSZ88_FAMILY_ID 0x88 682 #define KSZ8895_FAMILY_ID 0x95 683 684 #define KSZ8_PORT_STATUS_0 0x08 685 #define KSZ8_PORT_FIBER_MODE BIT(7) 686 687 #define SW_CHIP_ID_M GENMASK(7, 4) 688 #define KSZ87_CHIP_ID_94 0x6 689 #define KSZ87_CHIP_ID_95 0x9 690 #define KSZ88_CHIP_ID_63 0x3 691 #define KSZ8895_CHIP_ID_95 0x4 692 #define KSZ8895_CHIP_ID_95R 0x6 693 694 /* KSZ8895 specific register */ 695 #define REG_KSZ8864_CHIP_ID 0xFE 696 #define SW_KSZ8864 BIT(7) 697 698 #define SW_REV_ID_M GENMASK(7, 4) 699 700 /* KSZ9893, KSZ9563, KSZ8563 specific register */ 701 #define REG_CHIP_ID4 0x0f 702 #define SKU_ID_KSZ8563 0x3c 703 #define SKU_ID_KSZ9563 0x1c 704 705 /* Driver set switch broadcast storm protection at 10% rate. */ 706 #define BROADCAST_STORM_PROT_RATE 10 707 708 /* 148,800 frames * 67 ms / 100 */ 709 #define BROADCAST_STORM_VALUE 9969 710 711 #define BROADCAST_STORM_RATE_HI 0x07 712 #define BROADCAST_STORM_RATE_LO 0xFF 713 #define BROADCAST_STORM_RATE 0x07FF 714 715 #define MULTICAST_STORM_DISABLE BIT(6) 716 717 #define SW_START 0x01 718 719 /* xMII configuration */ 720 #define P_MII_DUPLEX_M BIT(6) 721 #define P_MII_100MBIT_M BIT(4) 722 723 #define P_GMII_1GBIT_M BIT(6) 724 #define P_RGMII_ID_IG_ENABLE BIT(4) 725 #define P_RGMII_ID_EG_ENABLE BIT(3) 726 #define P_MII_MAC_MODE BIT(2) 727 #define P_MII_SEL_M 0x3 728 729 /* KSZ9477, KSZ87xx Wake-on-LAN (WoL) masks */ 730 #define PME_WOL_MAGICPKT BIT(2) 731 #define PME_WOL_LINKUP BIT(1) 732 #define PME_WOL_ENERGY BIT(0) 733 734 #define PME_ENABLE BIT(1) 735 #define PME_POLARITY BIT(0) 736 737 #define KSZ87XX_REG_INT_EN 0x7D 738 #define KSZ87XX_INT_PME_MASK BIT(4) 739 740 /* Interrupt */ 741 #define REG_SW_PORT_INT_STATUS__1 0x001B 742 #define REG_SW_PORT_INT_MASK__1 0x001F 743 744 #define REG_PORT_INT_STATUS 0x001B 745 #define REG_PORT_INT_MASK 0x001F 746 747 #define PORT_SRC_PHY_INT 1 748 #define PORT_SRC_PTP_INT 2 749 750 #define KSZ8795_HUGE_PACKET_SIZE 2000 751 #define KSZ8863_HUGE_PACKET_SIZE 1916 752 #define KSZ8863_NORMAL_PACKET_SIZE 1536 753 #define KSZ8_LEGAL_PACKET_SIZE 1518 754 #define KSZ9477_MAX_FRAME_SIZE 9000 755 756 #define KSZ8873_REG_GLOBAL_CTRL_12 0x0e 757 /* Drive Strength of I/O Pad 758 * 0: 8mA, 1: 16mA 759 */ 760 #define KSZ8873_DRIVE_STRENGTH_16MA BIT(6) 761 762 #define KSZ8795_REG_SW_CTRL_20 0xa3 763 #define KSZ9477_REG_SW_IO_STRENGTH 0x010d 764 #define SW_DRIVE_STRENGTH_M 0x7 765 #define SW_DRIVE_STRENGTH_2MA 0 766 #define SW_DRIVE_STRENGTH_4MA 1 767 #define SW_DRIVE_STRENGTH_8MA 2 768 #define SW_DRIVE_STRENGTH_12MA 3 769 #define SW_DRIVE_STRENGTH_16MA 4 770 #define SW_DRIVE_STRENGTH_20MA 5 771 #define SW_DRIVE_STRENGTH_24MA 6 772 #define SW_DRIVE_STRENGTH_28MA 7 773 #define SW_HI_SPEED_DRIVE_STRENGTH_S 4 774 #define SW_LO_SPEED_DRIVE_STRENGTH_S 0 775 776 #define KSZ9477_REG_PORT_OUT_RATE_0 0x0420 777 #define KSZ9477_OUT_RATE_NO_LIMIT 0 778 779 #define KSZ9477_PORT_MRI_TC_MAP__4 0x0808 780 781 #define KSZ9477_PORT_TC_MAP_S 4 782 783 /* CBS related registers */ 784 #define REG_PORT_MTI_QUEUE_INDEX__4 0x0900 785 786 #define REG_PORT_MTI_QUEUE_CTRL_0 0x0914 787 788 #define MTI_SCHEDULE_MODE_M GENMASK(7, 6) 789 #define MTI_SCHEDULE_STRICT_PRIO 0 790 #define MTI_SCHEDULE_WRR 2 791 #define MTI_SHAPING_M GENMASK(5, 4) 792 #define MTI_SHAPING_OFF 0 793 #define MTI_SHAPING_SRP 1 794 #define MTI_SHAPING_TIME_AWARE 2 795 796 #define KSZ9477_PORT_MTI_QUEUE_CTRL_1 0x0915 797 #define KSZ9477_DEFAULT_WRR_WEIGHT 1 798 799 #define REG_PORT_MTI_HI_WATER_MARK 0x0916 800 #define REG_PORT_MTI_LO_WATER_MARK 0x0918 801 802 /* Regmap tables generation */ 803 #define KSZ_SPI_OP_RD 3 804 #define KSZ_SPI_OP_WR 2 805 806 #define swabnot_used(x) 0 807 808 #define KSZ_SPI_OP_FLAG_MASK(opcode, swp, regbits, regpad) \ 809 swab##swp((opcode) << ((regbits) + (regpad))) 810 811 #define KSZ_REGMAP_ENTRY(width, swp, regbits, regpad, regalign) \ 812 { \ 813 .name = #width, \ 814 .val_bits = (width), \ 815 .reg_stride = 1, \ 816 .reg_bits = (regbits) + (regalign), \ 817 .pad_bits = (regpad), \ 818 .max_register = BIT(regbits) - 1, \ 819 .cache_type = REGCACHE_NONE, \ 820 .read_flag_mask = \ 821 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_RD, swp, \ 822 regbits, regpad), \ 823 .write_flag_mask = \ 824 KSZ_SPI_OP_FLAG_MASK(KSZ_SPI_OP_WR, swp, \ 825 regbits, regpad), \ 826 .lock = ksz_regmap_lock, \ 827 .unlock = ksz_regmap_unlock, \ 828 .reg_format_endian = REGMAP_ENDIAN_BIG, \ 829 .val_format_endian = REGMAP_ENDIAN_BIG \ 830 } 831 832 #define KSZ_REGMAP_TABLE(ksz, swp, regbits, regpad, regalign) \ 833 static const struct regmap_config ksz##_regmap_config[] = { \ 834 [KSZ_REGMAP_8] = KSZ_REGMAP_ENTRY(8, swp, (regbits), (regpad), (regalign)), \ 835 [KSZ_REGMAP_16] = KSZ_REGMAP_ENTRY(16, swp, (regbits), (regpad), (regalign)), \ 836 [KSZ_REGMAP_32] = KSZ_REGMAP_ENTRY(32, swp, (regbits), (regpad), (regalign)), \ 837 } 838 839 #endif 840