1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200, xRX300 and xRX330 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_RESET BIT(15) 97 #define GSWIP_MII_CFG_EN BIT(14) 98 #define GSWIP_MII_CFG_ISOLATE BIT(13) 99 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 100 #define GSWIP_MII_CFG_RGMII_IBS BIT(8) 101 #define GSWIP_MII_CFG_RMII_CLK BIT(7) 102 #define GSWIP_MII_CFG_MODE_MIIP 0x0 103 #define GSWIP_MII_CFG_MODE_MIIM 0x1 104 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 105 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 106 #define GSWIP_MII_CFG_MODE_RGMII 0x4 107 #define GSWIP_MII_CFG_MODE_GMII 0x9 108 #define GSWIP_MII_CFG_MODE_MASK 0xf 109 #define GSWIP_MII_CFG_RATE_M2P5 0x00 110 #define GSWIP_MII_CFG_RATE_M25 0x10 111 #define GSWIP_MII_CFG_RATE_M125 0x20 112 #define GSWIP_MII_CFG_RATE_M50 0x30 113 #define GSWIP_MII_CFG_RATE_AUTO 0x40 114 #define GSWIP_MII_CFG_RATE_MASK 0x70 115 #define GSWIP_MII_PCDU0 0x01 116 #define GSWIP_MII_PCDU1 0x03 117 #define GSWIP_MII_PCDU5 0x05 118 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 119 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 120 121 /* GSWIP Core Registers */ 122 #define GSWIP_SWRES 0x000 123 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 124 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 125 #define GSWIP_VERSION 0x013 126 #define GSWIP_VERSION_REV_SHIFT 0 127 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 128 #define GSWIP_VERSION_MOD_SHIFT 8 129 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 130 #define GSWIP_VERSION_2_0 0x100 131 #define GSWIP_VERSION_2_1 0x021 132 #define GSWIP_VERSION_2_2 0x122 133 #define GSWIP_VERSION_2_2_ETC 0x022 134 135 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 136 #define GSWIP_BM_RAM_ADDR 0x044 137 #define GSWIP_BM_RAM_CTRL 0x045 138 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 139 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 140 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 141 #define GSWIP_BM_QUEUE_GCTRL 0x04A 142 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 143 /* buffer management Port Configuration Register */ 144 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 145 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 146 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 147 /* buffer management Port Control Register */ 148 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 149 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 150 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 151 152 /* PCE */ 153 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 154 #define GSWIP_PCE_TBL_MASK 0x448 155 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 156 #define GSWIP_PCE_TBL_ADDR 0x44E 157 #define GSWIP_PCE_TBL_CTRL 0x44F 158 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 159 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 160 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 161 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 162 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 163 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 164 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 165 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 166 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 167 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 168 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 169 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 170 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 171 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 172 #define GSWIP_PCE_GCTRL_0 0x456 173 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 174 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 175 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 176 #define GSWIP_PCE_GCTRL_1 0x457 177 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 178 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 179 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 180 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 181 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 182 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 183 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 184 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 185 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 186 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 187 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 188 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 189 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 190 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 191 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 192 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 193 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 194 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 195 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 196 197 #define GSWIP_MAC_FLEN 0x8C5 198 #define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC)) 199 #define GSWIP_MAC_CTRL_0_PADEN BIT(8) 200 #define GSWIP_MAC_CTRL_0_FCS_EN BIT(7) 201 #define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070 202 #define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000 203 #define GSWIP_MAC_CTRL_0_FCON_RX 0x0010 204 #define GSWIP_MAC_CTRL_0_FCON_TX 0x0020 205 #define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030 206 #define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040 207 #define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C 208 #define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000 209 #define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004 210 #define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C 211 #define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003 212 #define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000 213 #define GSWIP_MAC_CTRL_0_GMII_MII 0x0001 214 #define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002 215 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 216 #define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */ 217 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 218 219 /* Ethernet Switch Fetch DMA Port Control Register */ 220 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 221 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 222 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 223 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 224 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 225 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 226 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 227 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 228 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 229 230 /* Ethernet Switch Store DMA Port Control Register */ 231 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 232 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 233 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 234 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */ 235 236 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 237 #define GSWIP_TABLE_VLAN_MAPPING 0x02 238 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 239 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 240 241 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 242 243 /* Maximum packet size supported by the switch. In theory this should be 10240, 244 * but long packets currently cause lock-ups with an MTU of over 2526. Medium 245 * packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP 246 * over 2526), hence an MTU value of 2400 seems safe. This issue only affects 247 * packet reception. This is probably caused by the PPA engine, which is on the 248 * RX part of the device. Packet transmission works properly up to 10240. 249 */ 250 #define GSWIP_MAX_PACKET_LENGTH 2400 251 252 struct gswip_hw_info { 253 int max_ports; 254 int cpu_port; 255 const struct dsa_switch_ops *ops; 256 }; 257 258 struct xway_gphy_match_data { 259 char *fe_firmware_name; 260 char *ge_firmware_name; 261 }; 262 263 struct gswip_gphy_fw { 264 struct clk *clk_gate; 265 struct reset_control *reset; 266 u32 fw_addr_offset; 267 char *fw_name; 268 }; 269 270 struct gswip_vlan { 271 struct net_device *bridge; 272 u16 vid; 273 u8 fid; 274 }; 275 276 struct gswip_priv { 277 __iomem void *gswip; 278 __iomem void *mdio; 279 __iomem void *mii; 280 const struct gswip_hw_info *hw_info; 281 const struct xway_gphy_match_data *gphy_fw_name_cfg; 282 struct dsa_switch *ds; 283 struct device *dev; 284 struct regmap *rcu_regmap; 285 struct gswip_vlan vlans[64]; 286 int num_gphy_fw; 287 struct gswip_gphy_fw *gphy_fw; 288 u32 port_vlan_filter; 289 struct mutex pce_table_lock; 290 }; 291 292 struct gswip_pce_table_entry { 293 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 294 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 295 u16 key[8]; 296 u16 val[5]; 297 u16 mask; 298 u8 gmap; 299 bool type; 300 bool valid; 301 bool key_mode; 302 }; 303 304 struct gswip_rmon_cnt_desc { 305 unsigned int size; 306 unsigned int offset; 307 const char *name; 308 }; 309 310 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 311 312 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 313 /** Receive Packet Count (only packets that are accepted and not discarded). */ 314 MIB_DESC(1, 0x1F, "RxGoodPkts"), 315 MIB_DESC(1, 0x23, "RxUnicastPkts"), 316 MIB_DESC(1, 0x22, "RxMulticastPkts"), 317 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 318 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 319 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 320 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 321 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 322 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 323 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 324 MIB_DESC(1, 0x12, "Rx64BytePkts"), 325 MIB_DESC(1, 0x13, "Rx127BytePkts"), 326 MIB_DESC(1, 0x14, "Rx255BytePkts"), 327 MIB_DESC(1, 0x15, "Rx511BytePkts"), 328 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 329 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 330 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 331 MIB_DESC(1, 0x18, "RxDroppedPkts"), 332 MIB_DESC(1, 0x19, "RxFilteredPkts"), 333 MIB_DESC(2, 0x24, "RxGoodBytes"), 334 MIB_DESC(2, 0x26, "RxBadBytes"), 335 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 336 MIB_DESC(1, 0x0C, "TxGoodPkts"), 337 MIB_DESC(1, 0x06, "TxUnicastPkts"), 338 MIB_DESC(1, 0x07, "TxMulticastPkts"), 339 MIB_DESC(1, 0x00, "Tx64BytePkts"), 340 MIB_DESC(1, 0x01, "Tx127BytePkts"), 341 MIB_DESC(1, 0x02, "Tx255BytePkts"), 342 MIB_DESC(1, 0x03, "Tx511BytePkts"), 343 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 344 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 345 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 346 MIB_DESC(1, 0x08, "TxSingleCollCount"), 347 MIB_DESC(1, 0x09, "TxMultCollCount"), 348 MIB_DESC(1, 0x0A, "TxLateCollCount"), 349 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 350 MIB_DESC(1, 0x0D, "TxPauseCount"), 351 MIB_DESC(1, 0x10, "TxDroppedPkts"), 352 MIB_DESC(2, 0x0E, "TxGoodBytes"), 353 }; 354 355 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 356 { 357 return __raw_readl(priv->gswip + (offset * 4)); 358 } 359 360 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 361 { 362 __raw_writel(val, priv->gswip + (offset * 4)); 363 } 364 365 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 366 u32 offset) 367 { 368 u32 val = gswip_switch_r(priv, offset); 369 370 val &= ~(clear); 371 val |= set; 372 gswip_switch_w(priv, val, offset); 373 } 374 375 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 376 u32 cleared) 377 { 378 u32 val; 379 380 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 381 (val & cleared) == 0, 20, 50000); 382 } 383 384 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 385 { 386 return __raw_readl(priv->mdio + (offset * 4)); 387 } 388 389 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 390 { 391 __raw_writel(val, priv->mdio + (offset * 4)); 392 } 393 394 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 395 u32 offset) 396 { 397 u32 val = gswip_mdio_r(priv, offset); 398 399 val &= ~(clear); 400 val |= set; 401 gswip_mdio_w(priv, val, offset); 402 } 403 404 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 405 { 406 return __raw_readl(priv->mii + (offset * 4)); 407 } 408 409 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 410 { 411 __raw_writel(val, priv->mii + (offset * 4)); 412 } 413 414 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 415 u32 offset) 416 { 417 u32 val = gswip_mii_r(priv, offset); 418 419 val &= ~(clear); 420 val |= set; 421 gswip_mii_w(priv, val, offset); 422 } 423 424 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 425 int port) 426 { 427 /* There's no MII_CFG register for the CPU port */ 428 if (!dsa_is_cpu_port(priv->ds, port)) 429 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 430 } 431 432 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 433 int port) 434 { 435 switch (port) { 436 case 0: 437 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 438 break; 439 case 1: 440 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 441 break; 442 case 5: 443 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 444 break; 445 } 446 } 447 448 static int gswip_mdio_poll(struct gswip_priv *priv) 449 { 450 int cnt = 100; 451 452 while (likely(cnt--)) { 453 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 454 455 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 456 return 0; 457 usleep_range(20, 40); 458 } 459 460 return -ETIMEDOUT; 461 } 462 463 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 464 { 465 struct gswip_priv *priv = bus->priv; 466 int err; 467 468 err = gswip_mdio_poll(priv); 469 if (err) { 470 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 471 return err; 472 } 473 474 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 475 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 476 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 477 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 478 GSWIP_MDIO_CTRL); 479 480 return 0; 481 } 482 483 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 484 { 485 struct gswip_priv *priv = bus->priv; 486 int err; 487 488 err = gswip_mdio_poll(priv); 489 if (err) { 490 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 491 return err; 492 } 493 494 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 495 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 496 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 497 GSWIP_MDIO_CTRL); 498 499 err = gswip_mdio_poll(priv); 500 if (err) { 501 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 502 return err; 503 } 504 505 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 506 } 507 508 static int gswip_mdio(struct gswip_priv *priv) 509 { 510 struct device_node *mdio_np, *switch_np = priv->dev->of_node; 511 struct device *dev = priv->dev; 512 struct mii_bus *bus; 513 int err = 0; 514 515 mdio_np = of_get_compatible_child(switch_np, "lantiq,xrx200-mdio"); 516 if (!of_device_is_available(mdio_np)) 517 goto out_put_node; 518 519 bus = devm_mdiobus_alloc(dev); 520 if (!bus) { 521 err = -ENOMEM; 522 goto out_put_node; 523 } 524 525 bus->priv = priv; 526 bus->read = gswip_mdio_rd; 527 bus->write = gswip_mdio_wr; 528 bus->name = "lantiq,xrx200-mdio"; 529 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev)); 530 bus->parent = priv->dev; 531 532 err = devm_of_mdiobus_register(dev, bus, mdio_np); 533 534 out_put_node: 535 of_node_put(mdio_np); 536 537 return err; 538 } 539 540 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 541 struct gswip_pce_table_entry *tbl) 542 { 543 int i; 544 int err; 545 u16 crtl; 546 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 547 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 548 549 mutex_lock(&priv->pce_table_lock); 550 551 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 552 GSWIP_PCE_TBL_CTRL_BAS); 553 if (err) { 554 mutex_unlock(&priv->pce_table_lock); 555 return err; 556 } 557 558 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 559 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 560 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 561 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 562 GSWIP_PCE_TBL_CTRL); 563 564 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 565 GSWIP_PCE_TBL_CTRL_BAS); 566 if (err) { 567 mutex_unlock(&priv->pce_table_lock); 568 return err; 569 } 570 571 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 572 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 573 574 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 575 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 576 577 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 578 579 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 580 581 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 582 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 583 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 584 585 mutex_unlock(&priv->pce_table_lock); 586 587 return 0; 588 } 589 590 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 591 struct gswip_pce_table_entry *tbl) 592 { 593 int i; 594 int err; 595 u16 crtl; 596 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 597 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 598 599 mutex_lock(&priv->pce_table_lock); 600 601 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 602 GSWIP_PCE_TBL_CTRL_BAS); 603 if (err) { 604 mutex_unlock(&priv->pce_table_lock); 605 return err; 606 } 607 608 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 609 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 610 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 611 tbl->table | addr_mode, 612 GSWIP_PCE_TBL_CTRL); 613 614 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 615 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 616 617 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 618 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 619 620 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 621 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 622 tbl->table | addr_mode, 623 GSWIP_PCE_TBL_CTRL); 624 625 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 626 627 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 628 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 629 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 630 if (tbl->type) 631 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 632 if (tbl->valid) 633 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 634 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 635 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 636 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 637 638 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 639 GSWIP_PCE_TBL_CTRL_BAS); 640 641 mutex_unlock(&priv->pce_table_lock); 642 643 return err; 644 } 645 646 /* Add the LAN port into a bridge with the CPU port by 647 * default. This prevents automatic forwarding of 648 * packages between the LAN ports when no explicit 649 * bridge is configured. 650 */ 651 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 652 { 653 struct gswip_pce_table_entry vlan_active = {0,}; 654 struct gswip_pce_table_entry vlan_mapping = {0,}; 655 unsigned int cpu_port = priv->hw_info->cpu_port; 656 unsigned int max_ports = priv->hw_info->max_ports; 657 int err; 658 659 if (port >= max_ports) { 660 dev_err(priv->dev, "single port for %i supported\n", port); 661 return -EIO; 662 } 663 664 vlan_active.index = port + 1; 665 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 666 vlan_active.key[0] = 0; /* vid */ 667 vlan_active.val[0] = port + 1 /* fid */; 668 vlan_active.valid = add; 669 err = gswip_pce_table_entry_write(priv, &vlan_active); 670 if (err) { 671 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 672 return err; 673 } 674 675 if (!add) 676 return 0; 677 678 vlan_mapping.index = port + 1; 679 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 680 vlan_mapping.val[0] = 0 /* vid */; 681 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 682 vlan_mapping.val[2] = 0; 683 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 684 if (err) { 685 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 686 return err; 687 } 688 689 return 0; 690 } 691 692 static int gswip_port_enable(struct dsa_switch *ds, int port, 693 struct phy_device *phydev) 694 { 695 struct gswip_priv *priv = ds->priv; 696 int err; 697 698 if (!dsa_is_cpu_port(ds, port)) { 699 u32 mdio_phy = 0; 700 701 err = gswip_add_single_port_br(priv, port, true); 702 if (err) 703 return err; 704 705 if (phydev) 706 mdio_phy = phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK; 707 708 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_ADDR_MASK, mdio_phy, 709 GSWIP_MDIO_PHYp(port)); 710 } 711 712 /* RMON Counter Enable for port */ 713 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 714 715 /* enable port fetch/store dma & VLAN Modification */ 716 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 717 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 718 GSWIP_FDMA_PCTRLp(port)); 719 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 720 GSWIP_SDMA_PCTRLp(port)); 721 722 return 0; 723 } 724 725 static void gswip_port_disable(struct dsa_switch *ds, int port) 726 { 727 struct gswip_priv *priv = ds->priv; 728 729 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 730 GSWIP_FDMA_PCTRLp(port)); 731 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 732 GSWIP_SDMA_PCTRLp(port)); 733 } 734 735 static int gswip_pce_load_microcode(struct gswip_priv *priv) 736 { 737 int i; 738 int err; 739 740 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 741 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 742 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 743 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 744 745 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 746 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 747 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 748 GSWIP_PCE_TBL_VAL(0)); 749 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 750 GSWIP_PCE_TBL_VAL(1)); 751 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 752 GSWIP_PCE_TBL_VAL(2)); 753 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 754 GSWIP_PCE_TBL_VAL(3)); 755 756 /* start the table access: */ 757 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 758 GSWIP_PCE_TBL_CTRL); 759 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 760 GSWIP_PCE_TBL_CTRL_BAS); 761 if (err) 762 return err; 763 } 764 765 /* tell the switch that the microcode is loaded */ 766 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 767 GSWIP_PCE_GCTRL_0); 768 769 return 0; 770 } 771 772 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 773 bool vlan_filtering, 774 struct netlink_ext_ack *extack) 775 { 776 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 777 struct gswip_priv *priv = ds->priv; 778 779 /* Do not allow changing the VLAN filtering options while in bridge */ 780 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 781 NL_SET_ERR_MSG_MOD(extack, 782 "Dynamic toggling of vlan_filtering not supported"); 783 return -EIO; 784 } 785 786 if (vlan_filtering) { 787 /* Use port based VLAN tag */ 788 gswip_switch_mask(priv, 789 GSWIP_PCE_VCTRL_VSR, 790 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 791 GSWIP_PCE_VCTRL_VEMR, 792 GSWIP_PCE_VCTRL(port)); 793 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 794 GSWIP_PCE_PCTRL_0p(port)); 795 } else { 796 /* Use port based VLAN tag */ 797 gswip_switch_mask(priv, 798 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 799 GSWIP_PCE_VCTRL_VEMR, 800 GSWIP_PCE_VCTRL_VSR, 801 GSWIP_PCE_VCTRL(port)); 802 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 803 GSWIP_PCE_PCTRL_0p(port)); 804 } 805 806 return 0; 807 } 808 809 static int gswip_setup(struct dsa_switch *ds) 810 { 811 struct gswip_priv *priv = ds->priv; 812 unsigned int cpu_port = priv->hw_info->cpu_port; 813 int i; 814 int err; 815 816 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 817 usleep_range(5000, 10000); 818 gswip_switch_w(priv, 0, GSWIP_SWRES); 819 820 /* disable port fetch/store dma on all ports */ 821 for (i = 0; i < priv->hw_info->max_ports; i++) { 822 gswip_port_disable(ds, i); 823 gswip_port_vlan_filtering(ds, i, false, NULL); 824 } 825 826 /* enable Switch */ 827 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 828 829 err = gswip_pce_load_microcode(priv); 830 if (err) { 831 dev_err(priv->dev, "writing PCE microcode failed, %i\n", err); 832 return err; 833 } 834 835 /* Default unknown Broadcast/Multicast/Unicast port maps */ 836 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 837 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 838 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 839 840 /* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an 841 * interoperability problem with this auto polling mechanism because 842 * their status registers think that the link is in a different state 843 * than it actually is. For the AR8030 it has the BMSR_ESTATEN bit set 844 * as well as ESTATUS_1000_TFULL and ESTATUS_1000_XFULL. This makes the 845 * auto polling state machine consider the link being negotiated with 846 * 1Gbit/s. Since the PHY itself is a Fast Ethernet RMII PHY this leads 847 * to the switch port being completely dead (RX and TX are both not 848 * working). 849 * Also with various other PHY / port combinations (PHY11G GPHY, PHY22F 850 * GPHY, external RGMII PEF7071/7072) any traffic would stop. Sometimes 851 * it would work fine for a few minutes to hours and then stop, on 852 * other device it would no traffic could be sent or received at all. 853 * Testing shows that when PHY auto polling is disabled these problems 854 * go away. 855 */ 856 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 857 858 /* Configure the MDIO Clock 2.5 MHz */ 859 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 860 861 /* Disable the xMII interface and clear it's isolation bit */ 862 for (i = 0; i < priv->hw_info->max_ports; i++) 863 gswip_mii_mask_cfg(priv, 864 GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE, 865 0, i); 866 867 /* enable special tag insertion on cpu port */ 868 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 869 GSWIP_FDMA_PCTRLp(cpu_port)); 870 871 /* accept special tag in ingress direction */ 872 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 873 GSWIP_PCE_PCTRL_0p(cpu_port)); 874 875 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 876 GSWIP_BM_QUEUE_GCTRL); 877 878 /* VLAN aware Switching */ 879 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 880 881 /* Flush MAC Table */ 882 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 883 884 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 885 GSWIP_PCE_GCTRL_0_MTFL); 886 if (err) { 887 dev_err(priv->dev, "MAC flushing didn't finish\n"); 888 return err; 889 } 890 891 ds->mtu_enforcement_ingress = true; 892 893 ds->configure_vlan_while_not_filtering = false; 894 895 return 0; 896 } 897 898 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 899 int port, 900 enum dsa_tag_protocol mp) 901 { 902 return DSA_TAG_PROTO_GSWIP; 903 } 904 905 static int gswip_vlan_active_create(struct gswip_priv *priv, 906 struct net_device *bridge, 907 int fid, u16 vid) 908 { 909 struct gswip_pce_table_entry vlan_active = {0,}; 910 unsigned int max_ports = priv->hw_info->max_ports; 911 int idx = -1; 912 int err; 913 int i; 914 915 /* Look for a free slot */ 916 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 917 if (!priv->vlans[i].bridge) { 918 idx = i; 919 break; 920 } 921 } 922 923 if (idx == -1) 924 return -ENOSPC; 925 926 if (fid == -1) 927 fid = idx; 928 929 vlan_active.index = idx; 930 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 931 vlan_active.key[0] = vid; 932 vlan_active.val[0] = fid; 933 vlan_active.valid = true; 934 935 err = gswip_pce_table_entry_write(priv, &vlan_active); 936 if (err) { 937 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 938 return err; 939 } 940 941 priv->vlans[idx].bridge = bridge; 942 priv->vlans[idx].vid = vid; 943 priv->vlans[idx].fid = fid; 944 945 return idx; 946 } 947 948 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 949 { 950 struct gswip_pce_table_entry vlan_active = {0,}; 951 int err; 952 953 vlan_active.index = idx; 954 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 955 vlan_active.valid = false; 956 err = gswip_pce_table_entry_write(priv, &vlan_active); 957 if (err) 958 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 959 priv->vlans[idx].bridge = NULL; 960 961 return err; 962 } 963 964 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 965 struct net_device *bridge, int port) 966 { 967 struct gswip_pce_table_entry vlan_mapping = {0,}; 968 unsigned int max_ports = priv->hw_info->max_ports; 969 unsigned int cpu_port = priv->hw_info->cpu_port; 970 bool active_vlan_created = false; 971 int idx = -1; 972 int i; 973 int err; 974 975 /* Check if there is already a page for this bridge */ 976 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 977 if (priv->vlans[i].bridge == bridge) { 978 idx = i; 979 break; 980 } 981 } 982 983 /* If this bridge is not programmed yet, add a Active VLAN table 984 * entry in a free slot and prepare the VLAN mapping table entry. 985 */ 986 if (idx == -1) { 987 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 988 if (idx < 0) 989 return idx; 990 active_vlan_created = true; 991 992 vlan_mapping.index = idx; 993 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 994 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 995 vlan_mapping.val[0] = 0; 996 } else { 997 /* Read the existing VLAN mapping entry from the switch */ 998 vlan_mapping.index = idx; 999 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1000 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1001 if (err) { 1002 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1003 err); 1004 return err; 1005 } 1006 } 1007 1008 /* Update the VLAN mapping entry and write it to the switch */ 1009 vlan_mapping.val[1] |= BIT(cpu_port); 1010 vlan_mapping.val[1] |= BIT(port); 1011 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1012 if (err) { 1013 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1014 /* In case an Active VLAN was creaetd delete it again */ 1015 if (active_vlan_created) 1016 gswip_vlan_active_remove(priv, idx); 1017 return err; 1018 } 1019 1020 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1021 return 0; 1022 } 1023 1024 static int gswip_vlan_add_aware(struct gswip_priv *priv, 1025 struct net_device *bridge, int port, 1026 u16 vid, bool untagged, 1027 bool pvid) 1028 { 1029 struct gswip_pce_table_entry vlan_mapping = {0,}; 1030 unsigned int max_ports = priv->hw_info->max_ports; 1031 unsigned int cpu_port = priv->hw_info->cpu_port; 1032 bool active_vlan_created = false; 1033 int idx = -1; 1034 int fid = -1; 1035 int i; 1036 int err; 1037 1038 /* Check if there is already a page for this bridge */ 1039 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1040 if (priv->vlans[i].bridge == bridge) { 1041 if (fid != -1 && fid != priv->vlans[i].fid) 1042 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 1043 fid = priv->vlans[i].fid; 1044 if (priv->vlans[i].vid == vid) { 1045 idx = i; 1046 break; 1047 } 1048 } 1049 } 1050 1051 /* If this bridge is not programmed yet, add a Active VLAN table 1052 * entry in a free slot and prepare the VLAN mapping table entry. 1053 */ 1054 if (idx == -1) { 1055 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 1056 if (idx < 0) 1057 return idx; 1058 active_vlan_created = true; 1059 1060 vlan_mapping.index = idx; 1061 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1062 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1063 vlan_mapping.val[0] = vid; 1064 } else { 1065 /* Read the existing VLAN mapping entry from the switch */ 1066 vlan_mapping.index = idx; 1067 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1068 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1069 if (err) { 1070 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1071 err); 1072 return err; 1073 } 1074 } 1075 1076 vlan_mapping.val[0] = vid; 1077 /* Update the VLAN mapping entry and write it to the switch */ 1078 vlan_mapping.val[1] |= BIT(cpu_port); 1079 vlan_mapping.val[2] |= BIT(cpu_port); 1080 vlan_mapping.val[1] |= BIT(port); 1081 if (untagged) 1082 vlan_mapping.val[2] &= ~BIT(port); 1083 else 1084 vlan_mapping.val[2] |= BIT(port); 1085 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1086 if (err) { 1087 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1088 /* In case an Active VLAN was creaetd delete it again */ 1089 if (active_vlan_created) 1090 gswip_vlan_active_remove(priv, idx); 1091 return err; 1092 } 1093 1094 if (pvid) 1095 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1096 1097 return 0; 1098 } 1099 1100 static int gswip_vlan_remove(struct gswip_priv *priv, 1101 struct net_device *bridge, int port, 1102 u16 vid, bool pvid, bool vlan_aware) 1103 { 1104 struct gswip_pce_table_entry vlan_mapping = {0,}; 1105 unsigned int max_ports = priv->hw_info->max_ports; 1106 unsigned int cpu_port = priv->hw_info->cpu_port; 1107 int idx = -1; 1108 int i; 1109 int err; 1110 1111 /* Check if there is already a page for this bridge */ 1112 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1113 if (priv->vlans[i].bridge == bridge && 1114 (!vlan_aware || priv->vlans[i].vid == vid)) { 1115 idx = i; 1116 break; 1117 } 1118 } 1119 1120 if (idx == -1) { 1121 dev_err(priv->dev, "bridge to leave does not exists\n"); 1122 return -ENOENT; 1123 } 1124 1125 vlan_mapping.index = idx; 1126 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1127 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1128 if (err) { 1129 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1130 return err; 1131 } 1132 1133 vlan_mapping.val[1] &= ~BIT(port); 1134 vlan_mapping.val[2] &= ~BIT(port); 1135 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1136 if (err) { 1137 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1138 return err; 1139 } 1140 1141 /* In case all ports are removed from the bridge, remove the VLAN */ 1142 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1143 err = gswip_vlan_active_remove(priv, idx); 1144 if (err) { 1145 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1146 err); 1147 return err; 1148 } 1149 } 1150 1151 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1152 if (pvid) 1153 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1154 1155 return 0; 1156 } 1157 1158 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1159 struct dsa_bridge bridge, 1160 bool *tx_fwd_offload, 1161 struct netlink_ext_ack *extack) 1162 { 1163 struct net_device *br = bridge.dev; 1164 struct gswip_priv *priv = ds->priv; 1165 int err; 1166 1167 /* When the bridge uses VLAN filtering we have to configure VLAN 1168 * specific bridges. No bridge is configured here. 1169 */ 1170 if (!br_vlan_enabled(br)) { 1171 err = gswip_vlan_add_unaware(priv, br, port); 1172 if (err) 1173 return err; 1174 priv->port_vlan_filter &= ~BIT(port); 1175 } else { 1176 priv->port_vlan_filter |= BIT(port); 1177 } 1178 return gswip_add_single_port_br(priv, port, false); 1179 } 1180 1181 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1182 struct dsa_bridge bridge) 1183 { 1184 struct net_device *br = bridge.dev; 1185 struct gswip_priv *priv = ds->priv; 1186 1187 gswip_add_single_port_br(priv, port, true); 1188 1189 /* When the bridge uses VLAN filtering we have to configure VLAN 1190 * specific bridges. No bridge is configured here. 1191 */ 1192 if (!br_vlan_enabled(br)) 1193 gswip_vlan_remove(priv, br, port, 0, true, false); 1194 } 1195 1196 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1197 const struct switchdev_obj_port_vlan *vlan, 1198 struct netlink_ext_ack *extack) 1199 { 1200 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1201 struct gswip_priv *priv = ds->priv; 1202 unsigned int max_ports = priv->hw_info->max_ports; 1203 int pos = max_ports; 1204 int i, idx = -1; 1205 1206 /* We only support VLAN filtering on bridges */ 1207 if (!dsa_is_cpu_port(ds, port) && !bridge) 1208 return -EOPNOTSUPP; 1209 1210 /* Check if there is already a page for this VLAN */ 1211 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1212 if (priv->vlans[i].bridge == bridge && 1213 priv->vlans[i].vid == vlan->vid) { 1214 idx = i; 1215 break; 1216 } 1217 } 1218 1219 /* If this VLAN is not programmed yet, we have to reserve 1220 * one entry in the VLAN table. Make sure we start at the 1221 * next position round. 1222 */ 1223 if (idx == -1) { 1224 /* Look for a free slot */ 1225 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1226 if (!priv->vlans[pos].bridge) { 1227 idx = pos; 1228 pos++; 1229 break; 1230 } 1231 } 1232 1233 if (idx == -1) { 1234 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1235 return -ENOSPC; 1236 } 1237 } 1238 1239 return 0; 1240 } 1241 1242 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1243 const struct switchdev_obj_port_vlan *vlan, 1244 struct netlink_ext_ack *extack) 1245 { 1246 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1247 struct gswip_priv *priv = ds->priv; 1248 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1249 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1250 int err; 1251 1252 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1253 if (err) 1254 return err; 1255 1256 /* We have to receive all packets on the CPU port and should not 1257 * do any VLAN filtering here. This is also called with bridge 1258 * NULL and then we do not know for which bridge to configure 1259 * this. 1260 */ 1261 if (dsa_is_cpu_port(ds, port)) 1262 return 0; 1263 1264 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1265 untagged, pvid); 1266 } 1267 1268 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1269 const struct switchdev_obj_port_vlan *vlan) 1270 { 1271 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1272 struct gswip_priv *priv = ds->priv; 1273 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1274 1275 /* We have to receive all packets on the CPU port and should not 1276 * do any VLAN filtering here. This is also called with bridge 1277 * NULL and then we do not know for which bridge to configure 1278 * this. 1279 */ 1280 if (dsa_is_cpu_port(ds, port)) 1281 return 0; 1282 1283 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1284 } 1285 1286 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1287 { 1288 struct gswip_priv *priv = ds->priv; 1289 struct gswip_pce_table_entry mac_bridge = {0,}; 1290 int i; 1291 int err; 1292 1293 for (i = 0; i < 2048; i++) { 1294 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1295 mac_bridge.index = i; 1296 1297 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1298 if (err) { 1299 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1300 err); 1301 return; 1302 } 1303 1304 if (!mac_bridge.valid) 1305 continue; 1306 1307 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1308 continue; 1309 1310 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1311 continue; 1312 1313 mac_bridge.valid = false; 1314 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1315 if (err) { 1316 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1317 err); 1318 return; 1319 } 1320 } 1321 } 1322 1323 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1324 { 1325 struct gswip_priv *priv = ds->priv; 1326 u32 stp_state; 1327 1328 switch (state) { 1329 case BR_STATE_DISABLED: 1330 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1331 GSWIP_SDMA_PCTRLp(port)); 1332 return; 1333 case BR_STATE_BLOCKING: 1334 case BR_STATE_LISTENING: 1335 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1336 break; 1337 case BR_STATE_LEARNING: 1338 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1339 break; 1340 case BR_STATE_FORWARDING: 1341 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1342 break; 1343 default: 1344 dev_err(priv->dev, "invalid STP state: %d\n", state); 1345 return; 1346 } 1347 1348 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1349 GSWIP_SDMA_PCTRLp(port)); 1350 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1351 GSWIP_PCE_PCTRL_0p(port)); 1352 } 1353 1354 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1355 const unsigned char *addr, u16 vid, bool add) 1356 { 1357 struct net_device *bridge = dsa_port_bridge_dev_get(dsa_to_port(ds, port)); 1358 struct gswip_priv *priv = ds->priv; 1359 struct gswip_pce_table_entry mac_bridge = {0,}; 1360 unsigned int max_ports = priv->hw_info->max_ports; 1361 int fid = -1; 1362 int i; 1363 int err; 1364 1365 if (!bridge) 1366 return -EINVAL; 1367 1368 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1369 if (priv->vlans[i].bridge == bridge) { 1370 fid = priv->vlans[i].fid; 1371 break; 1372 } 1373 } 1374 1375 if (fid == -1) { 1376 dev_err(priv->dev, "Port not part of a bridge\n"); 1377 return -EINVAL; 1378 } 1379 1380 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1381 mac_bridge.key_mode = true; 1382 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1383 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1384 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1385 mac_bridge.key[3] = fid; 1386 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1387 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1388 mac_bridge.valid = add; 1389 1390 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1391 if (err) 1392 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1393 1394 return err; 1395 } 1396 1397 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1398 const unsigned char *addr, u16 vid, 1399 struct dsa_db db) 1400 { 1401 return gswip_port_fdb(ds, port, addr, vid, true); 1402 } 1403 1404 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1405 const unsigned char *addr, u16 vid, 1406 struct dsa_db db) 1407 { 1408 return gswip_port_fdb(ds, port, addr, vid, false); 1409 } 1410 1411 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1412 dsa_fdb_dump_cb_t *cb, void *data) 1413 { 1414 struct gswip_priv *priv = ds->priv; 1415 struct gswip_pce_table_entry mac_bridge = {0,}; 1416 unsigned char addr[ETH_ALEN]; 1417 int i; 1418 int err; 1419 1420 for (i = 0; i < 2048; i++) { 1421 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1422 mac_bridge.index = i; 1423 1424 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1425 if (err) { 1426 dev_err(priv->dev, 1427 "failed to read mac bridge entry %d: %d\n", 1428 i, err); 1429 return err; 1430 } 1431 1432 if (!mac_bridge.valid) 1433 continue; 1434 1435 addr[5] = mac_bridge.key[0] & 0xff; 1436 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1437 addr[3] = mac_bridge.key[1] & 0xff; 1438 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1439 addr[1] = mac_bridge.key[2] & 0xff; 1440 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1441 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1442 if (mac_bridge.val[0] & BIT(port)) { 1443 err = cb(addr, 0, true, data); 1444 if (err) 1445 return err; 1446 } 1447 } else { 1448 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) { 1449 err = cb(addr, 0, false, data); 1450 if (err) 1451 return err; 1452 } 1453 } 1454 } 1455 return 0; 1456 } 1457 1458 static int gswip_port_max_mtu(struct dsa_switch *ds, int port) 1459 { 1460 /* Includes 8 bytes for special header. */ 1461 return GSWIP_MAX_PACKET_LENGTH - VLAN_ETH_HLEN - ETH_FCS_LEN; 1462 } 1463 1464 static int gswip_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1465 { 1466 struct gswip_priv *priv = ds->priv; 1467 1468 /* CPU port always has maximum mtu of user ports, so use it to set 1469 * switch frame size, including 8 byte special header. 1470 */ 1471 if (dsa_is_cpu_port(ds, port)) { 1472 new_mtu += 8; 1473 gswip_switch_w(priv, VLAN_ETH_HLEN + new_mtu + ETH_FCS_LEN, 1474 GSWIP_MAC_FLEN); 1475 } 1476 1477 /* Enable MLEN for ports with non-standard MTUs, including the special 1478 * header on the CPU port added above. 1479 */ 1480 if (new_mtu != ETH_DATA_LEN) 1481 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 1482 GSWIP_MAC_CTRL_2p(port)); 1483 else 1484 gswip_switch_mask(priv, GSWIP_MAC_CTRL_2_MLEN, 0, 1485 GSWIP_MAC_CTRL_2p(port)); 1486 1487 return 0; 1488 } 1489 1490 static void gswip_xrx200_phylink_get_caps(struct dsa_switch *ds, int port, 1491 struct phylink_config *config) 1492 { 1493 switch (port) { 1494 case 0: 1495 case 1: 1496 phy_interface_set_rgmii(config->supported_interfaces); 1497 __set_bit(PHY_INTERFACE_MODE_MII, 1498 config->supported_interfaces); 1499 __set_bit(PHY_INTERFACE_MODE_REVMII, 1500 config->supported_interfaces); 1501 __set_bit(PHY_INTERFACE_MODE_RMII, 1502 config->supported_interfaces); 1503 break; 1504 1505 case 2: 1506 case 3: 1507 case 4: 1508 case 6: 1509 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1510 config->supported_interfaces); 1511 break; 1512 1513 case 5: 1514 phy_interface_set_rgmii(config->supported_interfaces); 1515 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1516 config->supported_interfaces); 1517 break; 1518 } 1519 1520 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1521 MAC_10 | MAC_100 | MAC_1000; 1522 } 1523 1524 static void gswip_xrx300_phylink_get_caps(struct dsa_switch *ds, int port, 1525 struct phylink_config *config) 1526 { 1527 switch (port) { 1528 case 0: 1529 phy_interface_set_rgmii(config->supported_interfaces); 1530 __set_bit(PHY_INTERFACE_MODE_GMII, 1531 config->supported_interfaces); 1532 __set_bit(PHY_INTERFACE_MODE_RMII, 1533 config->supported_interfaces); 1534 break; 1535 1536 case 1: 1537 case 2: 1538 case 3: 1539 case 4: 1540 case 6: 1541 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1542 config->supported_interfaces); 1543 break; 1544 1545 case 5: 1546 phy_interface_set_rgmii(config->supported_interfaces); 1547 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 1548 config->supported_interfaces); 1549 __set_bit(PHY_INTERFACE_MODE_RMII, 1550 config->supported_interfaces); 1551 break; 1552 } 1553 1554 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1555 MAC_10 | MAC_100 | MAC_1000; 1556 } 1557 1558 static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link) 1559 { 1560 u32 mdio_phy; 1561 1562 if (link) 1563 mdio_phy = GSWIP_MDIO_PHY_LINK_UP; 1564 else 1565 mdio_phy = GSWIP_MDIO_PHY_LINK_DOWN; 1566 1567 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_MASK, mdio_phy, 1568 GSWIP_MDIO_PHYp(port)); 1569 } 1570 1571 static void gswip_port_set_speed(struct gswip_priv *priv, int port, int speed, 1572 phy_interface_t interface) 1573 { 1574 u32 mdio_phy = 0, mii_cfg = 0, mac_ctrl_0 = 0; 1575 1576 switch (speed) { 1577 case SPEED_10: 1578 mdio_phy = GSWIP_MDIO_PHY_SPEED_M10; 1579 1580 if (interface == PHY_INTERFACE_MODE_RMII) 1581 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1582 else 1583 mii_cfg = GSWIP_MII_CFG_RATE_M2P5; 1584 1585 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1586 break; 1587 1588 case SPEED_100: 1589 mdio_phy = GSWIP_MDIO_PHY_SPEED_M100; 1590 1591 if (interface == PHY_INTERFACE_MODE_RMII) 1592 mii_cfg = GSWIP_MII_CFG_RATE_M50; 1593 else 1594 mii_cfg = GSWIP_MII_CFG_RATE_M25; 1595 1596 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_MII; 1597 break; 1598 1599 case SPEED_1000: 1600 mdio_phy = GSWIP_MDIO_PHY_SPEED_G1; 1601 1602 mii_cfg = GSWIP_MII_CFG_RATE_M125; 1603 1604 mac_ctrl_0 = GSWIP_MAC_CTRL_0_GMII_RGMII; 1605 break; 1606 } 1607 1608 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_SPEED_MASK, mdio_phy, 1609 GSWIP_MDIO_PHYp(port)); 1610 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_RATE_MASK, mii_cfg, port); 1611 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_GMII_MASK, mac_ctrl_0, 1612 GSWIP_MAC_CTRL_0p(port)); 1613 } 1614 1615 static void gswip_port_set_duplex(struct gswip_priv *priv, int port, int duplex) 1616 { 1617 u32 mac_ctrl_0, mdio_phy; 1618 1619 if (duplex == DUPLEX_FULL) { 1620 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_EN; 1621 mdio_phy = GSWIP_MDIO_PHY_FDUP_EN; 1622 } else { 1623 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FDUP_DIS; 1624 mdio_phy = GSWIP_MDIO_PHY_FDUP_DIS; 1625 } 1626 1627 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FDUP_MASK, mac_ctrl_0, 1628 GSWIP_MAC_CTRL_0p(port)); 1629 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_FDUP_MASK, mdio_phy, 1630 GSWIP_MDIO_PHYp(port)); 1631 } 1632 1633 static void gswip_port_set_pause(struct gswip_priv *priv, int port, 1634 bool tx_pause, bool rx_pause) 1635 { 1636 u32 mac_ctrl_0, mdio_phy; 1637 1638 if (tx_pause && rx_pause) { 1639 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RXTX; 1640 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1641 GSWIP_MDIO_PHY_FCONRX_EN; 1642 } else if (tx_pause) { 1643 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_TX; 1644 mdio_phy = GSWIP_MDIO_PHY_FCONTX_EN | 1645 GSWIP_MDIO_PHY_FCONRX_DIS; 1646 } else if (rx_pause) { 1647 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_RX; 1648 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1649 GSWIP_MDIO_PHY_FCONRX_EN; 1650 } else { 1651 mac_ctrl_0 = GSWIP_MAC_CTRL_0_FCON_NONE; 1652 mdio_phy = GSWIP_MDIO_PHY_FCONTX_DIS | 1653 GSWIP_MDIO_PHY_FCONRX_DIS; 1654 } 1655 1656 gswip_switch_mask(priv, GSWIP_MAC_CTRL_0_FCON_MASK, 1657 mac_ctrl_0, GSWIP_MAC_CTRL_0p(port)); 1658 gswip_mdio_mask(priv, 1659 GSWIP_MDIO_PHY_FCONTX_MASK | 1660 GSWIP_MDIO_PHY_FCONRX_MASK, 1661 mdio_phy, GSWIP_MDIO_PHYp(port)); 1662 } 1663 1664 static void gswip_phylink_mac_config(struct phylink_config *config, 1665 unsigned int mode, 1666 const struct phylink_link_state *state) 1667 { 1668 struct dsa_port *dp = dsa_phylink_to_port(config); 1669 struct gswip_priv *priv = dp->ds->priv; 1670 int port = dp->index; 1671 u32 miicfg = 0; 1672 1673 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1674 1675 switch (state->interface) { 1676 case PHY_INTERFACE_MODE_MII: 1677 case PHY_INTERFACE_MODE_INTERNAL: 1678 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1679 break; 1680 case PHY_INTERFACE_MODE_REVMII: 1681 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1682 break; 1683 case PHY_INTERFACE_MODE_RMII: 1684 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1685 break; 1686 case PHY_INTERFACE_MODE_RGMII: 1687 case PHY_INTERFACE_MODE_RGMII_ID: 1688 case PHY_INTERFACE_MODE_RGMII_RXID: 1689 case PHY_INTERFACE_MODE_RGMII_TXID: 1690 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1691 break; 1692 case PHY_INTERFACE_MODE_GMII: 1693 miicfg |= GSWIP_MII_CFG_MODE_GMII; 1694 break; 1695 default: 1696 dev_err(dp->ds->dev, 1697 "Unsupported interface: %d\n", state->interface); 1698 return; 1699 } 1700 1701 gswip_mii_mask_cfg(priv, 1702 GSWIP_MII_CFG_MODE_MASK | GSWIP_MII_CFG_RMII_CLK | 1703 GSWIP_MII_CFG_RGMII_IBS | GSWIP_MII_CFG_LDCLKDIS, 1704 miicfg, port); 1705 1706 switch (state->interface) { 1707 case PHY_INTERFACE_MODE_RGMII_ID: 1708 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1709 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1710 break; 1711 case PHY_INTERFACE_MODE_RGMII_RXID: 1712 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1713 break; 1714 case PHY_INTERFACE_MODE_RGMII_TXID: 1715 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1716 break; 1717 default: 1718 break; 1719 } 1720 } 1721 1722 static void gswip_phylink_mac_link_down(struct phylink_config *config, 1723 unsigned int mode, 1724 phy_interface_t interface) 1725 { 1726 struct dsa_port *dp = dsa_phylink_to_port(config); 1727 struct gswip_priv *priv = dp->ds->priv; 1728 int port = dp->index; 1729 1730 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1731 1732 if (!dsa_port_is_cpu(dp)) 1733 gswip_port_set_link(priv, port, false); 1734 } 1735 1736 static void gswip_phylink_mac_link_up(struct phylink_config *config, 1737 struct phy_device *phydev, 1738 unsigned int mode, 1739 phy_interface_t interface, 1740 int speed, int duplex, 1741 bool tx_pause, bool rx_pause) 1742 { 1743 struct dsa_port *dp = dsa_phylink_to_port(config); 1744 struct gswip_priv *priv = dp->ds->priv; 1745 int port = dp->index; 1746 1747 if (!dsa_port_is_cpu(dp)) { 1748 gswip_port_set_link(priv, port, true); 1749 gswip_port_set_speed(priv, port, speed, interface); 1750 gswip_port_set_duplex(priv, port, duplex); 1751 gswip_port_set_pause(priv, port, tx_pause, rx_pause); 1752 } 1753 1754 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1755 } 1756 1757 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1758 uint8_t *data) 1759 { 1760 int i; 1761 1762 if (stringset != ETH_SS_STATS) 1763 return; 1764 1765 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1766 ethtool_puts(&data, gswip_rmon_cnt[i].name); 1767 } 1768 1769 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1770 u32 index) 1771 { 1772 u32 result; 1773 int err; 1774 1775 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1776 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1777 GSWIP_BM_RAM_CTRL_OPMOD, 1778 table | GSWIP_BM_RAM_CTRL_BAS, 1779 GSWIP_BM_RAM_CTRL); 1780 1781 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1782 GSWIP_BM_RAM_CTRL_BAS); 1783 if (err) { 1784 dev_err(priv->dev, "timeout while reading table: %u, index: %u\n", 1785 table, index); 1786 return 0; 1787 } 1788 1789 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1790 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1791 1792 return result; 1793 } 1794 1795 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1796 uint64_t *data) 1797 { 1798 struct gswip_priv *priv = ds->priv; 1799 const struct gswip_rmon_cnt_desc *rmon_cnt; 1800 int i; 1801 u64 high; 1802 1803 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1804 rmon_cnt = &gswip_rmon_cnt[i]; 1805 1806 data[i] = gswip_bcm_ram_entry_read(priv, port, 1807 rmon_cnt->offset); 1808 if (rmon_cnt->size == 2) { 1809 high = gswip_bcm_ram_entry_read(priv, port, 1810 rmon_cnt->offset + 1); 1811 data[i] |= high << 32; 1812 } 1813 } 1814 } 1815 1816 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1817 { 1818 if (sset != ETH_SS_STATS) 1819 return 0; 1820 1821 return ARRAY_SIZE(gswip_rmon_cnt); 1822 } 1823 1824 static const struct phylink_mac_ops gswip_phylink_mac_ops = { 1825 .mac_config = gswip_phylink_mac_config, 1826 .mac_link_down = gswip_phylink_mac_link_down, 1827 .mac_link_up = gswip_phylink_mac_link_up, 1828 }; 1829 1830 static const struct dsa_switch_ops gswip_xrx200_switch_ops = { 1831 .get_tag_protocol = gswip_get_tag_protocol, 1832 .setup = gswip_setup, 1833 .port_enable = gswip_port_enable, 1834 .port_disable = gswip_port_disable, 1835 .port_bridge_join = gswip_port_bridge_join, 1836 .port_bridge_leave = gswip_port_bridge_leave, 1837 .port_fast_age = gswip_port_fast_age, 1838 .port_vlan_filtering = gswip_port_vlan_filtering, 1839 .port_vlan_add = gswip_port_vlan_add, 1840 .port_vlan_del = gswip_port_vlan_del, 1841 .port_stp_state_set = gswip_port_stp_state_set, 1842 .port_fdb_add = gswip_port_fdb_add, 1843 .port_fdb_del = gswip_port_fdb_del, 1844 .port_fdb_dump = gswip_port_fdb_dump, 1845 .port_change_mtu = gswip_port_change_mtu, 1846 .port_max_mtu = gswip_port_max_mtu, 1847 .phylink_get_caps = gswip_xrx200_phylink_get_caps, 1848 .get_strings = gswip_get_strings, 1849 .get_ethtool_stats = gswip_get_ethtool_stats, 1850 .get_sset_count = gswip_get_sset_count, 1851 }; 1852 1853 static const struct dsa_switch_ops gswip_xrx300_switch_ops = { 1854 .get_tag_protocol = gswip_get_tag_protocol, 1855 .setup = gswip_setup, 1856 .port_enable = gswip_port_enable, 1857 .port_disable = gswip_port_disable, 1858 .port_bridge_join = gswip_port_bridge_join, 1859 .port_bridge_leave = gswip_port_bridge_leave, 1860 .port_fast_age = gswip_port_fast_age, 1861 .port_vlan_filtering = gswip_port_vlan_filtering, 1862 .port_vlan_add = gswip_port_vlan_add, 1863 .port_vlan_del = gswip_port_vlan_del, 1864 .port_stp_state_set = gswip_port_stp_state_set, 1865 .port_fdb_add = gswip_port_fdb_add, 1866 .port_fdb_del = gswip_port_fdb_del, 1867 .port_fdb_dump = gswip_port_fdb_dump, 1868 .port_change_mtu = gswip_port_change_mtu, 1869 .port_max_mtu = gswip_port_max_mtu, 1870 .phylink_get_caps = gswip_xrx300_phylink_get_caps, 1871 .get_strings = gswip_get_strings, 1872 .get_ethtool_stats = gswip_get_ethtool_stats, 1873 .get_sset_count = gswip_get_sset_count, 1874 }; 1875 1876 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1877 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1878 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1879 }; 1880 1881 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1882 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1883 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1884 }; 1885 1886 static const struct xway_gphy_match_data xrx300_gphy_data = { 1887 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1888 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1889 }; 1890 1891 static const struct of_device_id xway_gphy_match[] __maybe_unused = { 1892 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1893 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1894 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1895 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1896 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1897 {}, 1898 }; 1899 1900 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1901 { 1902 struct device *dev = priv->dev; 1903 const struct firmware *fw; 1904 void *fw_addr; 1905 dma_addr_t dma_addr; 1906 dma_addr_t dev_addr; 1907 size_t size; 1908 int ret; 1909 1910 ret = clk_prepare_enable(gphy_fw->clk_gate); 1911 if (ret) 1912 return ret; 1913 1914 reset_control_assert(gphy_fw->reset); 1915 1916 /* The vendor BSP uses a 200ms delay after asserting the reset line. 1917 * Without this some users are observing that the PHY is not coming up 1918 * on the MDIO bus. 1919 */ 1920 msleep(200); 1921 1922 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1923 if (ret) 1924 return dev_err_probe(dev, ret, "failed to load firmware: %s\n", 1925 gphy_fw->fw_name); 1926 1927 /* GPHY cores need the firmware code in a persistent and contiguous 1928 * memory area with a 16 kB boundary aligned start address. 1929 */ 1930 size = fw->size + XRX200_GPHY_FW_ALIGN; 1931 1932 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1933 if (fw_addr) { 1934 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1935 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1936 memcpy(fw_addr, fw->data, fw->size); 1937 } else { 1938 release_firmware(fw); 1939 return dev_err_probe(dev, -ENOMEM, 1940 "failed to alloc firmware memory\n"); 1941 } 1942 1943 release_firmware(fw); 1944 1945 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1946 if (ret) 1947 return ret; 1948 1949 reset_control_deassert(gphy_fw->reset); 1950 1951 return ret; 1952 } 1953 1954 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1955 struct gswip_gphy_fw *gphy_fw, 1956 struct device_node *gphy_fw_np, int i) 1957 { 1958 struct device *dev = priv->dev; 1959 u32 gphy_mode; 1960 int ret; 1961 char gphyname[10]; 1962 1963 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1964 1965 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1966 if (IS_ERR(gphy_fw->clk_gate)) { 1967 return dev_err_probe(dev, PTR_ERR(gphy_fw->clk_gate), 1968 "Failed to lookup gate clock\n"); 1969 } 1970 1971 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1972 if (ret) 1973 return ret; 1974 1975 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1976 /* Default to GE mode */ 1977 if (ret) 1978 gphy_mode = GPHY_MODE_GE; 1979 1980 switch (gphy_mode) { 1981 case GPHY_MODE_FE: 1982 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1983 break; 1984 case GPHY_MODE_GE: 1985 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1986 break; 1987 default: 1988 return dev_err_probe(dev, -EINVAL, "Unknown GPHY mode %d\n", 1989 gphy_mode); 1990 } 1991 1992 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1993 if (IS_ERR(gphy_fw->reset)) 1994 return dev_err_probe(dev, PTR_ERR(gphy_fw->reset), 1995 "Failed to lookup gphy reset\n"); 1996 1997 return gswip_gphy_fw_load(priv, gphy_fw); 1998 } 1999 2000 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 2001 struct gswip_gphy_fw *gphy_fw) 2002 { 2003 int ret; 2004 2005 /* check if the device was fully probed */ 2006 if (!gphy_fw->fw_name) 2007 return; 2008 2009 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 2010 if (ret) 2011 dev_err(priv->dev, "can not reset GPHY FW pointer\n"); 2012 2013 clk_disable_unprepare(gphy_fw->clk_gate); 2014 2015 reset_control_put(gphy_fw->reset); 2016 } 2017 2018 static int gswip_gphy_fw_list(struct gswip_priv *priv, 2019 struct device_node *gphy_fw_list_np, u32 version) 2020 { 2021 struct device *dev = priv->dev; 2022 struct device_node *gphy_fw_np; 2023 const struct of_device_id *match; 2024 int err; 2025 int i = 0; 2026 2027 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 2028 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 2029 * needs a different GPHY firmware. 2030 */ 2031 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 2032 switch (version) { 2033 case GSWIP_VERSION_2_0: 2034 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 2035 break; 2036 case GSWIP_VERSION_2_1: 2037 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 2038 break; 2039 default: 2040 return dev_err_probe(dev, -ENOENT, 2041 "unknown GSWIP version: 0x%x\n", 2042 version); 2043 } 2044 } 2045 2046 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 2047 if (match && match->data) 2048 priv->gphy_fw_name_cfg = match->data; 2049 2050 if (!priv->gphy_fw_name_cfg) 2051 return dev_err_probe(dev, -ENOENT, 2052 "GPHY compatible type not supported\n"); 2053 2054 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 2055 if (!priv->num_gphy_fw) 2056 return -ENOENT; 2057 2058 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 2059 "lantiq,rcu"); 2060 if (IS_ERR(priv->rcu_regmap)) 2061 return PTR_ERR(priv->rcu_regmap); 2062 2063 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 2064 sizeof(*priv->gphy_fw), 2065 GFP_KERNEL | __GFP_ZERO); 2066 if (!priv->gphy_fw) 2067 return -ENOMEM; 2068 2069 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 2070 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 2071 gphy_fw_np, i); 2072 if (err) { 2073 of_node_put(gphy_fw_np); 2074 goto remove_gphy; 2075 } 2076 i++; 2077 } 2078 2079 /* The standalone PHY11G requires 300ms to be fully 2080 * initialized and ready for any MDIO communication after being 2081 * taken out of reset. For the SoC-internal GPHY variant there 2082 * is no (known) documentation for the minimum time after a 2083 * reset. Use the same value as for the standalone variant as 2084 * some users have reported internal PHYs not being detected 2085 * without any delay. 2086 */ 2087 msleep(300); 2088 2089 return 0; 2090 2091 remove_gphy: 2092 for (i = 0; i < priv->num_gphy_fw; i++) 2093 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2094 return err; 2095 } 2096 2097 static int gswip_probe(struct platform_device *pdev) 2098 { 2099 struct device_node *np, *gphy_fw_np; 2100 struct device *dev = &pdev->dev; 2101 struct gswip_priv *priv; 2102 int err; 2103 int i; 2104 u32 version; 2105 2106 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 2107 if (!priv) 2108 return -ENOMEM; 2109 2110 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 2111 if (IS_ERR(priv->gswip)) 2112 return PTR_ERR(priv->gswip); 2113 2114 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 2115 if (IS_ERR(priv->mdio)) 2116 return PTR_ERR(priv->mdio); 2117 2118 priv->mii = devm_platform_ioremap_resource(pdev, 2); 2119 if (IS_ERR(priv->mii)) 2120 return PTR_ERR(priv->mii); 2121 2122 priv->hw_info = of_device_get_match_data(dev); 2123 if (!priv->hw_info) 2124 return -EINVAL; 2125 2126 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 2127 if (!priv->ds) 2128 return -ENOMEM; 2129 2130 priv->ds->dev = dev; 2131 priv->ds->num_ports = priv->hw_info->max_ports; 2132 priv->ds->priv = priv; 2133 priv->ds->ops = priv->hw_info->ops; 2134 priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops; 2135 priv->dev = dev; 2136 mutex_init(&priv->pce_table_lock); 2137 version = gswip_switch_r(priv, GSWIP_VERSION); 2138 2139 np = dev->of_node; 2140 switch (version) { 2141 case GSWIP_VERSION_2_0: 2142 case GSWIP_VERSION_2_1: 2143 if (!of_device_is_compatible(np, "lantiq,xrx200-gswip")) 2144 return -EINVAL; 2145 break; 2146 case GSWIP_VERSION_2_2: 2147 case GSWIP_VERSION_2_2_ETC: 2148 if (!of_device_is_compatible(np, "lantiq,xrx300-gswip") && 2149 !of_device_is_compatible(np, "lantiq,xrx330-gswip")) 2150 return -EINVAL; 2151 break; 2152 default: 2153 return dev_err_probe(dev, -ENOENT, 2154 "unknown GSWIP version: 0x%x\n", version); 2155 } 2156 2157 /* bring up the mdio bus */ 2158 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 2159 if (gphy_fw_np) { 2160 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 2161 of_node_put(gphy_fw_np); 2162 if (err) 2163 return dev_err_probe(dev, err, 2164 "gphy fw probe failed\n"); 2165 } 2166 2167 /* bring up the mdio bus */ 2168 err = gswip_mdio(priv); 2169 if (err) { 2170 dev_err_probe(dev, err, "mdio probe failed\n"); 2171 goto gphy_fw_remove; 2172 } 2173 2174 err = dsa_register_switch(priv->ds); 2175 if (err) { 2176 dev_err_probe(dev, err, "dsa switch registration failed\n"); 2177 goto gphy_fw_remove; 2178 } 2179 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 2180 err = dev_err_probe(dev, -EINVAL, 2181 "wrong CPU port defined, HW only supports port: %i\n", 2182 priv->hw_info->cpu_port); 2183 goto disable_switch; 2184 } 2185 2186 platform_set_drvdata(pdev, priv); 2187 2188 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 2189 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 2190 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 2191 return 0; 2192 2193 disable_switch: 2194 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2195 dsa_unregister_switch(priv->ds); 2196 gphy_fw_remove: 2197 for (i = 0; i < priv->num_gphy_fw; i++) 2198 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2199 return err; 2200 } 2201 2202 static void gswip_remove(struct platform_device *pdev) 2203 { 2204 struct gswip_priv *priv = platform_get_drvdata(pdev); 2205 int i; 2206 2207 if (!priv) 2208 return; 2209 2210 /* disable the switch */ 2211 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 2212 2213 dsa_unregister_switch(priv->ds); 2214 2215 for (i = 0; i < priv->num_gphy_fw; i++) 2216 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 2217 } 2218 2219 static void gswip_shutdown(struct platform_device *pdev) 2220 { 2221 struct gswip_priv *priv = platform_get_drvdata(pdev); 2222 2223 if (!priv) 2224 return; 2225 2226 dsa_switch_shutdown(priv->ds); 2227 2228 platform_set_drvdata(pdev, NULL); 2229 } 2230 2231 static const struct gswip_hw_info gswip_xrx200 = { 2232 .max_ports = 7, 2233 .cpu_port = 6, 2234 .ops = &gswip_xrx200_switch_ops, 2235 }; 2236 2237 static const struct gswip_hw_info gswip_xrx300 = { 2238 .max_ports = 7, 2239 .cpu_port = 6, 2240 .ops = &gswip_xrx300_switch_ops, 2241 }; 2242 2243 static const struct of_device_id gswip_of_match[] = { 2244 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 2245 { .compatible = "lantiq,xrx300-gswip", .data = &gswip_xrx300 }, 2246 { .compatible = "lantiq,xrx330-gswip", .data = &gswip_xrx300 }, 2247 {}, 2248 }; 2249 MODULE_DEVICE_TABLE(of, gswip_of_match); 2250 2251 static struct platform_driver gswip_driver = { 2252 .probe = gswip_probe, 2253 .remove_new = gswip_remove, 2254 .shutdown = gswip_shutdown, 2255 .driver = { 2256 .name = "gswip", 2257 .of_match_table = gswip_of_match, 2258 }, 2259 }; 2260 2261 module_platform_driver(gswip_driver); 2262 2263 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 2264 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 2265 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 2266 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 2267 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 2268 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 2269 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 2270 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 2271 MODULE_LICENSE("GPL v2"); 2272