1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Lantiq / Intel GSWIP switch driver for VRX200 SoCs 4 * 5 * Copyright (C) 2010 Lantiq Deutschland 6 * Copyright (C) 2012 John Crispin <john@phrozen.org> 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * 9 * The VLAN and bridge model the GSWIP hardware uses does not directly 10 * matches the model DSA uses. 11 * 12 * The hardware has 64 possible table entries for bridges with one VLAN 13 * ID, one flow id and a list of ports for each bridge. All entries which 14 * match the same flow ID are combined in the mac learning table, they 15 * act as one global bridge. 16 * The hardware does not support VLAN filter on the port, but on the 17 * bridge, this driver converts the DSA model to the hardware. 18 * 19 * The CPU gets all the exception frames which do not match any forwarding 20 * rule and the CPU port is also added to all bridges. This makes it possible 21 * to handle all the special cases easily in software. 22 * At the initialization the driver allocates one bridge table entry for 23 * each switch port which is used when the port is used without an 24 * explicit bridge. This prevents the frames from being forwarded 25 * between all LAN ports by default. 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/delay.h> 30 #include <linux/etherdevice.h> 31 #include <linux/firmware.h> 32 #include <linux/if_bridge.h> 33 #include <linux/if_vlan.h> 34 #include <linux/iopoll.h> 35 #include <linux/mfd/syscon.h> 36 #include <linux/module.h> 37 #include <linux/of_mdio.h> 38 #include <linux/of_net.h> 39 #include <linux/of_platform.h> 40 #include <linux/phy.h> 41 #include <linux/phylink.h> 42 #include <linux/platform_device.h> 43 #include <linux/regmap.h> 44 #include <linux/reset.h> 45 #include <net/dsa.h> 46 #include <dt-bindings/mips/lantiq_rcu_gphy.h> 47 48 #include "lantiq_pce.h" 49 50 /* GSWIP MDIO Registers */ 51 #define GSWIP_MDIO_GLOB 0x00 52 #define GSWIP_MDIO_GLOB_ENABLE BIT(15) 53 #define GSWIP_MDIO_CTRL 0x08 54 #define GSWIP_MDIO_CTRL_BUSY BIT(12) 55 #define GSWIP_MDIO_CTRL_RD BIT(11) 56 #define GSWIP_MDIO_CTRL_WR BIT(10) 57 #define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f 58 #define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5 59 #define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f 60 #define GSWIP_MDIO_READ 0x09 61 #define GSWIP_MDIO_WRITE 0x0A 62 #define GSWIP_MDIO_MDC_CFG0 0x0B 63 #define GSWIP_MDIO_MDC_CFG1 0x0C 64 #define GSWIP_MDIO_PHYp(p) (0x15 - (p)) 65 #define GSWIP_MDIO_PHY_LINK_MASK 0x6000 66 #define GSWIP_MDIO_PHY_LINK_AUTO 0x0000 67 #define GSWIP_MDIO_PHY_LINK_DOWN 0x4000 68 #define GSWIP_MDIO_PHY_LINK_UP 0x2000 69 #define GSWIP_MDIO_PHY_SPEED_MASK 0x1800 70 #define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800 71 #define GSWIP_MDIO_PHY_SPEED_M10 0x0000 72 #define GSWIP_MDIO_PHY_SPEED_M100 0x0800 73 #define GSWIP_MDIO_PHY_SPEED_G1 0x1000 74 #define GSWIP_MDIO_PHY_FDUP_MASK 0x0600 75 #define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000 76 #define GSWIP_MDIO_PHY_FDUP_EN 0x0200 77 #define GSWIP_MDIO_PHY_FDUP_DIS 0x0600 78 #define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180 79 #define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000 80 #define GSWIP_MDIO_PHY_FCONTX_EN 0x0100 81 #define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180 82 #define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060 83 #define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000 84 #define GSWIP_MDIO_PHY_FCONRX_EN 0x0020 85 #define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060 86 #define GSWIP_MDIO_PHY_ADDR_MASK 0x001f 87 #define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \ 88 GSWIP_MDIO_PHY_FCONRX_MASK | \ 89 GSWIP_MDIO_PHY_FCONTX_MASK | \ 90 GSWIP_MDIO_PHY_LINK_MASK | \ 91 GSWIP_MDIO_PHY_SPEED_MASK | \ 92 GSWIP_MDIO_PHY_FDUP_MASK) 93 94 /* GSWIP MII Registers */ 95 #define GSWIP_MII_CFGp(p) (0x2 * (p)) 96 #define GSWIP_MII_CFG_EN BIT(14) 97 #define GSWIP_MII_CFG_LDCLKDIS BIT(12) 98 #define GSWIP_MII_CFG_MODE_MIIP 0x0 99 #define GSWIP_MII_CFG_MODE_MIIM 0x1 100 #define GSWIP_MII_CFG_MODE_RMIIP 0x2 101 #define GSWIP_MII_CFG_MODE_RMIIM 0x3 102 #define GSWIP_MII_CFG_MODE_RGMII 0x4 103 #define GSWIP_MII_CFG_MODE_MASK 0xf 104 #define GSWIP_MII_CFG_RATE_M2P5 0x00 105 #define GSWIP_MII_CFG_RATE_M25 0x10 106 #define GSWIP_MII_CFG_RATE_M125 0x20 107 #define GSWIP_MII_CFG_RATE_M50 0x30 108 #define GSWIP_MII_CFG_RATE_AUTO 0x40 109 #define GSWIP_MII_CFG_RATE_MASK 0x70 110 #define GSWIP_MII_PCDU0 0x01 111 #define GSWIP_MII_PCDU1 0x03 112 #define GSWIP_MII_PCDU5 0x05 113 #define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0) 114 #define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7) 115 116 /* GSWIP Core Registers */ 117 #define GSWIP_SWRES 0x000 118 #define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */ 119 #define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */ 120 #define GSWIP_VERSION 0x013 121 #define GSWIP_VERSION_REV_SHIFT 0 122 #define GSWIP_VERSION_REV_MASK GENMASK(7, 0) 123 #define GSWIP_VERSION_MOD_SHIFT 8 124 #define GSWIP_VERSION_MOD_MASK GENMASK(15, 8) 125 #define GSWIP_VERSION_2_0 0x100 126 #define GSWIP_VERSION_2_1 0x021 127 #define GSWIP_VERSION_2_2 0x122 128 #define GSWIP_VERSION_2_2_ETC 0x022 129 130 #define GSWIP_BM_RAM_VAL(x) (0x043 - (x)) 131 #define GSWIP_BM_RAM_ADDR 0x044 132 #define GSWIP_BM_RAM_CTRL 0x045 133 #define GSWIP_BM_RAM_CTRL_BAS BIT(15) 134 #define GSWIP_BM_RAM_CTRL_OPMOD BIT(5) 135 #define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0) 136 #define GSWIP_BM_QUEUE_GCTRL 0x04A 137 #define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10) 138 /* buffer management Port Configuration Register */ 139 #define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2)) 140 #define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */ 141 #define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */ 142 /* buffer management Port Control Register */ 143 #define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2)) 144 #define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */ 145 #define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */ 146 147 /* PCE */ 148 #define GSWIP_PCE_TBL_KEY(x) (0x447 - (x)) 149 #define GSWIP_PCE_TBL_MASK 0x448 150 #define GSWIP_PCE_TBL_VAL(x) (0x44D - (x)) 151 #define GSWIP_PCE_TBL_ADDR 0x44E 152 #define GSWIP_PCE_TBL_CTRL 0x44F 153 #define GSWIP_PCE_TBL_CTRL_BAS BIT(15) 154 #define GSWIP_PCE_TBL_CTRL_TYPE BIT(13) 155 #define GSWIP_PCE_TBL_CTRL_VLD BIT(12) 156 #define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11) 157 #define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7) 158 #define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5) 159 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00 160 #define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20 161 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40 162 #define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60 163 #define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0) 164 #define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */ 165 #define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */ 166 #define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */ 167 #define GSWIP_PCE_GCTRL_0 0x456 168 #define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */ 169 #define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3) 170 #define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */ 171 #define GSWIP_PCE_GCTRL_1 0x457 172 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */ 173 #define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */ 174 #define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA)) 175 #define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */ 176 #define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */ 177 #define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */ 178 #define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0 179 #define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1 180 #define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2 181 #define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3 182 #define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7 183 #define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0) 184 #define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA)) 185 #define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */ 186 #define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */ 187 #define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */ 188 #define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */ 189 #define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */ 190 #define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA)) 191 192 #define GSWIP_MAC_FLEN 0x8C5 193 #define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC)) 194 #define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */ 195 196 /* Ethernet Switch Fetch DMA Port Control Register */ 197 #define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6)) 198 #define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */ 199 #define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */ 200 #define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */ 201 #define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */ 202 #define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 203 #define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 204 #define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 205 #define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT) 206 207 /* Ethernet Switch Store DMA Port Control Register */ 208 #define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6)) 209 #define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */ 210 #define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */ 211 #define GSWIP_SDMA_PCTRL_PAUFWD BIT(1) /* Pause Frame Forwarding */ 212 213 #define GSWIP_TABLE_ACTIVE_VLAN 0x01 214 #define GSWIP_TABLE_VLAN_MAPPING 0x02 215 #define GSWIP_TABLE_MAC_BRIDGE 0x0b 216 #define GSWIP_TABLE_MAC_BRIDGE_STATIC 0x01 /* Static not, aging entry */ 217 218 #define XRX200_GPHY_FW_ALIGN (16 * 1024) 219 220 struct gswip_hw_info { 221 int max_ports; 222 int cpu_port; 223 }; 224 225 struct xway_gphy_match_data { 226 char *fe_firmware_name; 227 char *ge_firmware_name; 228 }; 229 230 struct gswip_gphy_fw { 231 struct clk *clk_gate; 232 struct reset_control *reset; 233 u32 fw_addr_offset; 234 char *fw_name; 235 }; 236 237 struct gswip_vlan { 238 struct net_device *bridge; 239 u16 vid; 240 u8 fid; 241 }; 242 243 struct gswip_priv { 244 __iomem void *gswip; 245 __iomem void *mdio; 246 __iomem void *mii; 247 const struct gswip_hw_info *hw_info; 248 const struct xway_gphy_match_data *gphy_fw_name_cfg; 249 struct dsa_switch *ds; 250 struct device *dev; 251 struct regmap *rcu_regmap; 252 struct gswip_vlan vlans[64]; 253 int num_gphy_fw; 254 struct gswip_gphy_fw *gphy_fw; 255 u32 port_vlan_filter; 256 }; 257 258 struct gswip_pce_table_entry { 259 u16 index; // PCE_TBL_ADDR.ADDR = pData->table_index 260 u16 table; // PCE_TBL_CTRL.ADDR = pData->table 261 u16 key[8]; 262 u16 val[5]; 263 u16 mask; 264 u8 gmap; 265 bool type; 266 bool valid; 267 bool key_mode; 268 }; 269 270 struct gswip_rmon_cnt_desc { 271 unsigned int size; 272 unsigned int offset; 273 const char *name; 274 }; 275 276 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} 277 278 static const struct gswip_rmon_cnt_desc gswip_rmon_cnt[] = { 279 /** Receive Packet Count (only packets that are accepted and not discarded). */ 280 MIB_DESC(1, 0x1F, "RxGoodPkts"), 281 MIB_DESC(1, 0x23, "RxUnicastPkts"), 282 MIB_DESC(1, 0x22, "RxMulticastPkts"), 283 MIB_DESC(1, 0x21, "RxFCSErrorPkts"), 284 MIB_DESC(1, 0x1D, "RxUnderSizeGoodPkts"), 285 MIB_DESC(1, 0x1E, "RxUnderSizeErrorPkts"), 286 MIB_DESC(1, 0x1B, "RxOversizeGoodPkts"), 287 MIB_DESC(1, 0x1C, "RxOversizeErrorPkts"), 288 MIB_DESC(1, 0x20, "RxGoodPausePkts"), 289 MIB_DESC(1, 0x1A, "RxAlignErrorPkts"), 290 MIB_DESC(1, 0x12, "Rx64BytePkts"), 291 MIB_DESC(1, 0x13, "Rx127BytePkts"), 292 MIB_DESC(1, 0x14, "Rx255BytePkts"), 293 MIB_DESC(1, 0x15, "Rx511BytePkts"), 294 MIB_DESC(1, 0x16, "Rx1023BytePkts"), 295 /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ 296 MIB_DESC(1, 0x17, "RxMaxBytePkts"), 297 MIB_DESC(1, 0x18, "RxDroppedPkts"), 298 MIB_DESC(1, 0x19, "RxFilteredPkts"), 299 MIB_DESC(2, 0x24, "RxGoodBytes"), 300 MIB_DESC(2, 0x26, "RxBadBytes"), 301 MIB_DESC(1, 0x11, "TxAcmDroppedPkts"), 302 MIB_DESC(1, 0x0C, "TxGoodPkts"), 303 MIB_DESC(1, 0x06, "TxUnicastPkts"), 304 MIB_DESC(1, 0x07, "TxMulticastPkts"), 305 MIB_DESC(1, 0x00, "Tx64BytePkts"), 306 MIB_DESC(1, 0x01, "Tx127BytePkts"), 307 MIB_DESC(1, 0x02, "Tx255BytePkts"), 308 MIB_DESC(1, 0x03, "Tx511BytePkts"), 309 MIB_DESC(1, 0x04, "Tx1023BytePkts"), 310 /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ 311 MIB_DESC(1, 0x05, "TxMaxBytePkts"), 312 MIB_DESC(1, 0x08, "TxSingleCollCount"), 313 MIB_DESC(1, 0x09, "TxMultCollCount"), 314 MIB_DESC(1, 0x0A, "TxLateCollCount"), 315 MIB_DESC(1, 0x0B, "TxExcessCollCount"), 316 MIB_DESC(1, 0x0D, "TxPauseCount"), 317 MIB_DESC(1, 0x10, "TxDroppedPkts"), 318 MIB_DESC(2, 0x0E, "TxGoodBytes"), 319 }; 320 321 static u32 gswip_switch_r(struct gswip_priv *priv, u32 offset) 322 { 323 return __raw_readl(priv->gswip + (offset * 4)); 324 } 325 326 static void gswip_switch_w(struct gswip_priv *priv, u32 val, u32 offset) 327 { 328 __raw_writel(val, priv->gswip + (offset * 4)); 329 } 330 331 static void gswip_switch_mask(struct gswip_priv *priv, u32 clear, u32 set, 332 u32 offset) 333 { 334 u32 val = gswip_switch_r(priv, offset); 335 336 val &= ~(clear); 337 val |= set; 338 gswip_switch_w(priv, val, offset); 339 } 340 341 static u32 gswip_switch_r_timeout(struct gswip_priv *priv, u32 offset, 342 u32 cleared) 343 { 344 u32 val; 345 346 return readx_poll_timeout(__raw_readl, priv->gswip + (offset * 4), val, 347 (val & cleared) == 0, 20, 50000); 348 } 349 350 static u32 gswip_mdio_r(struct gswip_priv *priv, u32 offset) 351 { 352 return __raw_readl(priv->mdio + (offset * 4)); 353 } 354 355 static void gswip_mdio_w(struct gswip_priv *priv, u32 val, u32 offset) 356 { 357 __raw_writel(val, priv->mdio + (offset * 4)); 358 } 359 360 static void gswip_mdio_mask(struct gswip_priv *priv, u32 clear, u32 set, 361 u32 offset) 362 { 363 u32 val = gswip_mdio_r(priv, offset); 364 365 val &= ~(clear); 366 val |= set; 367 gswip_mdio_w(priv, val, offset); 368 } 369 370 static u32 gswip_mii_r(struct gswip_priv *priv, u32 offset) 371 { 372 return __raw_readl(priv->mii + (offset * 4)); 373 } 374 375 static void gswip_mii_w(struct gswip_priv *priv, u32 val, u32 offset) 376 { 377 __raw_writel(val, priv->mii + (offset * 4)); 378 } 379 380 static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, 381 u32 offset) 382 { 383 u32 val = gswip_mii_r(priv, offset); 384 385 val &= ~(clear); 386 val |= set; 387 gswip_mii_w(priv, val, offset); 388 } 389 390 static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, 391 int port) 392 { 393 /* There's no MII_CFG register for the CPU port */ 394 if (!dsa_is_cpu_port(priv->ds, port)) 395 gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); 396 } 397 398 static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, 399 int port) 400 { 401 switch (port) { 402 case 0: 403 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); 404 break; 405 case 1: 406 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU1); 407 break; 408 case 5: 409 gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU5); 410 break; 411 } 412 } 413 414 static int gswip_mdio_poll(struct gswip_priv *priv) 415 { 416 int cnt = 100; 417 418 while (likely(cnt--)) { 419 u32 ctrl = gswip_mdio_r(priv, GSWIP_MDIO_CTRL); 420 421 if ((ctrl & GSWIP_MDIO_CTRL_BUSY) == 0) 422 return 0; 423 usleep_range(20, 40); 424 } 425 426 return -ETIMEDOUT; 427 } 428 429 static int gswip_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val) 430 { 431 struct gswip_priv *priv = bus->priv; 432 int err; 433 434 err = gswip_mdio_poll(priv); 435 if (err) { 436 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 437 return err; 438 } 439 440 gswip_mdio_w(priv, val, GSWIP_MDIO_WRITE); 441 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_WR | 442 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 443 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 444 GSWIP_MDIO_CTRL); 445 446 return 0; 447 } 448 449 static int gswip_mdio_rd(struct mii_bus *bus, int addr, int reg) 450 { 451 struct gswip_priv *priv = bus->priv; 452 int err; 453 454 err = gswip_mdio_poll(priv); 455 if (err) { 456 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 457 return err; 458 } 459 460 gswip_mdio_w(priv, GSWIP_MDIO_CTRL_BUSY | GSWIP_MDIO_CTRL_RD | 461 ((addr & GSWIP_MDIO_CTRL_PHYAD_MASK) << GSWIP_MDIO_CTRL_PHYAD_SHIFT) | 462 (reg & GSWIP_MDIO_CTRL_REGAD_MASK), 463 GSWIP_MDIO_CTRL); 464 465 err = gswip_mdio_poll(priv); 466 if (err) { 467 dev_err(&bus->dev, "waiting for MDIO bus busy timed out\n"); 468 return err; 469 } 470 471 return gswip_mdio_r(priv, GSWIP_MDIO_READ); 472 } 473 474 static int gswip_mdio(struct gswip_priv *priv, struct device_node *mdio_np) 475 { 476 struct dsa_switch *ds = priv->ds; 477 478 ds->slave_mii_bus = devm_mdiobus_alloc(priv->dev); 479 if (!ds->slave_mii_bus) 480 return -ENOMEM; 481 482 ds->slave_mii_bus->priv = priv; 483 ds->slave_mii_bus->read = gswip_mdio_rd; 484 ds->slave_mii_bus->write = gswip_mdio_wr; 485 ds->slave_mii_bus->name = "lantiq,xrx200-mdio"; 486 snprintf(ds->slave_mii_bus->id, MII_BUS_ID_SIZE, "%s-mii", 487 dev_name(priv->dev)); 488 ds->slave_mii_bus->parent = priv->dev; 489 ds->slave_mii_bus->phy_mask = ~ds->phys_mii_mask; 490 491 return of_mdiobus_register(ds->slave_mii_bus, mdio_np); 492 } 493 494 static int gswip_pce_table_entry_read(struct gswip_priv *priv, 495 struct gswip_pce_table_entry *tbl) 496 { 497 int i; 498 int err; 499 u16 crtl; 500 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSRD : 501 GSWIP_PCE_TBL_CTRL_OPMOD_ADRD; 502 503 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 504 GSWIP_PCE_TBL_CTRL_BAS); 505 if (err) 506 return err; 507 508 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 509 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 510 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 511 tbl->table | addr_mode | GSWIP_PCE_TBL_CTRL_BAS, 512 GSWIP_PCE_TBL_CTRL); 513 514 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 515 GSWIP_PCE_TBL_CTRL_BAS); 516 if (err) 517 return err; 518 519 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 520 tbl->key[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_KEY(i)); 521 522 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 523 tbl->val[i] = gswip_switch_r(priv, GSWIP_PCE_TBL_VAL(i)); 524 525 tbl->mask = gswip_switch_r(priv, GSWIP_PCE_TBL_MASK); 526 527 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 528 529 tbl->type = !!(crtl & GSWIP_PCE_TBL_CTRL_TYPE); 530 tbl->valid = !!(crtl & GSWIP_PCE_TBL_CTRL_VLD); 531 tbl->gmap = (crtl & GSWIP_PCE_TBL_CTRL_GMAP_MASK) >> 7; 532 533 return 0; 534 } 535 536 static int gswip_pce_table_entry_write(struct gswip_priv *priv, 537 struct gswip_pce_table_entry *tbl) 538 { 539 int i; 540 int err; 541 u16 crtl; 542 u16 addr_mode = tbl->key_mode ? GSWIP_PCE_TBL_CTRL_OPMOD_KSWR : 543 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR; 544 545 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 546 GSWIP_PCE_TBL_CTRL_BAS); 547 if (err) 548 return err; 549 550 gswip_switch_w(priv, tbl->index, GSWIP_PCE_TBL_ADDR); 551 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 552 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 553 tbl->table | addr_mode, 554 GSWIP_PCE_TBL_CTRL); 555 556 for (i = 0; i < ARRAY_SIZE(tbl->key); i++) 557 gswip_switch_w(priv, tbl->key[i], GSWIP_PCE_TBL_KEY(i)); 558 559 for (i = 0; i < ARRAY_SIZE(tbl->val); i++) 560 gswip_switch_w(priv, tbl->val[i], GSWIP_PCE_TBL_VAL(i)); 561 562 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 563 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 564 tbl->table | addr_mode, 565 GSWIP_PCE_TBL_CTRL); 566 567 gswip_switch_w(priv, tbl->mask, GSWIP_PCE_TBL_MASK); 568 569 crtl = gswip_switch_r(priv, GSWIP_PCE_TBL_CTRL); 570 crtl &= ~(GSWIP_PCE_TBL_CTRL_TYPE | GSWIP_PCE_TBL_CTRL_VLD | 571 GSWIP_PCE_TBL_CTRL_GMAP_MASK); 572 if (tbl->type) 573 crtl |= GSWIP_PCE_TBL_CTRL_TYPE; 574 if (tbl->valid) 575 crtl |= GSWIP_PCE_TBL_CTRL_VLD; 576 crtl |= (tbl->gmap << 7) & GSWIP_PCE_TBL_CTRL_GMAP_MASK; 577 crtl |= GSWIP_PCE_TBL_CTRL_BAS; 578 gswip_switch_w(priv, crtl, GSWIP_PCE_TBL_CTRL); 579 580 return gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 581 GSWIP_PCE_TBL_CTRL_BAS); 582 } 583 584 /* Add the LAN port into a bridge with the CPU port by 585 * default. This prevents automatic forwarding of 586 * packages between the LAN ports when no explicit 587 * bridge is configured. 588 */ 589 static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add) 590 { 591 struct gswip_pce_table_entry vlan_active = {0,}; 592 struct gswip_pce_table_entry vlan_mapping = {0,}; 593 unsigned int cpu_port = priv->hw_info->cpu_port; 594 unsigned int max_ports = priv->hw_info->max_ports; 595 int err; 596 597 if (port >= max_ports) { 598 dev_err(priv->dev, "single port for %i supported\n", port); 599 return -EIO; 600 } 601 602 vlan_active.index = port + 1; 603 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 604 vlan_active.key[0] = 0; /* vid */ 605 vlan_active.val[0] = port + 1 /* fid */; 606 vlan_active.valid = add; 607 err = gswip_pce_table_entry_write(priv, &vlan_active); 608 if (err) { 609 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 610 return err; 611 } 612 613 if (!add) 614 return 0; 615 616 vlan_mapping.index = port + 1; 617 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 618 vlan_mapping.val[0] = 0 /* vid */; 619 vlan_mapping.val[1] = BIT(port) | BIT(cpu_port); 620 vlan_mapping.val[2] = 0; 621 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 622 if (err) { 623 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 624 return err; 625 } 626 627 return 0; 628 } 629 630 static int gswip_port_enable(struct dsa_switch *ds, int port, 631 struct phy_device *phydev) 632 { 633 struct gswip_priv *priv = ds->priv; 634 int err; 635 636 if (!dsa_is_user_port(ds, port)) 637 return 0; 638 639 if (!dsa_is_cpu_port(ds, port)) { 640 err = gswip_add_single_port_br(priv, port, true); 641 if (err) 642 return err; 643 } 644 645 /* RMON Counter Enable for port */ 646 gswip_switch_w(priv, GSWIP_BM_PCFG_CNTEN, GSWIP_BM_PCFGp(port)); 647 648 /* enable port fetch/store dma & VLAN Modification */ 649 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_EN | 650 GSWIP_FDMA_PCTRL_VLANMOD_BOTH, 651 GSWIP_FDMA_PCTRLp(port)); 652 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 653 GSWIP_SDMA_PCTRLp(port)); 654 655 if (!dsa_is_cpu_port(ds, port)) { 656 u32 macconf = GSWIP_MDIO_PHY_LINK_AUTO | 657 GSWIP_MDIO_PHY_SPEED_AUTO | 658 GSWIP_MDIO_PHY_FDUP_AUTO | 659 GSWIP_MDIO_PHY_FCONTX_AUTO | 660 GSWIP_MDIO_PHY_FCONRX_AUTO | 661 (phydev->mdio.addr & GSWIP_MDIO_PHY_ADDR_MASK); 662 663 gswip_mdio_w(priv, macconf, GSWIP_MDIO_PHYp(port)); 664 /* Activate MDIO auto polling */ 665 gswip_mdio_mask(priv, 0, BIT(port), GSWIP_MDIO_MDC_CFG0); 666 } 667 668 return 0; 669 } 670 671 static void gswip_port_disable(struct dsa_switch *ds, int port) 672 { 673 struct gswip_priv *priv = ds->priv; 674 675 if (!dsa_is_user_port(ds, port)) 676 return; 677 678 if (!dsa_is_cpu_port(ds, port)) { 679 gswip_mdio_mask(priv, GSWIP_MDIO_PHY_LINK_DOWN, 680 GSWIP_MDIO_PHY_LINK_MASK, 681 GSWIP_MDIO_PHYp(port)); 682 /* Deactivate MDIO auto polling */ 683 gswip_mdio_mask(priv, BIT(port), 0, GSWIP_MDIO_MDC_CFG0); 684 } 685 686 gswip_switch_mask(priv, GSWIP_FDMA_PCTRL_EN, 0, 687 GSWIP_FDMA_PCTRLp(port)); 688 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 689 GSWIP_SDMA_PCTRLp(port)); 690 } 691 692 static int gswip_pce_load_microcode(struct gswip_priv *priv) 693 { 694 int i; 695 int err; 696 697 gswip_switch_mask(priv, GSWIP_PCE_TBL_CTRL_ADDR_MASK | 698 GSWIP_PCE_TBL_CTRL_OPMOD_MASK, 699 GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL); 700 gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK); 701 702 for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) { 703 gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR); 704 gswip_switch_w(priv, gswip_pce_microcode[i].val_0, 705 GSWIP_PCE_TBL_VAL(0)); 706 gswip_switch_w(priv, gswip_pce_microcode[i].val_1, 707 GSWIP_PCE_TBL_VAL(1)); 708 gswip_switch_w(priv, gswip_pce_microcode[i].val_2, 709 GSWIP_PCE_TBL_VAL(2)); 710 gswip_switch_w(priv, gswip_pce_microcode[i].val_3, 711 GSWIP_PCE_TBL_VAL(3)); 712 713 /* start the table access: */ 714 gswip_switch_mask(priv, 0, GSWIP_PCE_TBL_CTRL_BAS, 715 GSWIP_PCE_TBL_CTRL); 716 err = gswip_switch_r_timeout(priv, GSWIP_PCE_TBL_CTRL, 717 GSWIP_PCE_TBL_CTRL_BAS); 718 if (err) 719 return err; 720 } 721 722 /* tell the switch that the microcode is loaded */ 723 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MC_VALID, 724 GSWIP_PCE_GCTRL_0); 725 726 return 0; 727 } 728 729 static int gswip_port_vlan_filtering(struct dsa_switch *ds, int port, 730 bool vlan_filtering, 731 struct netlink_ext_ack *extack) 732 { 733 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 734 struct gswip_priv *priv = ds->priv; 735 736 /* Do not allow changing the VLAN filtering options while in bridge */ 737 if (bridge && !!(priv->port_vlan_filter & BIT(port)) != vlan_filtering) { 738 NL_SET_ERR_MSG_MOD(extack, 739 "Dynamic toggling of vlan_filtering not supported"); 740 return -EIO; 741 } 742 743 if (vlan_filtering) { 744 /* Use port based VLAN tag */ 745 gswip_switch_mask(priv, 746 GSWIP_PCE_VCTRL_VSR, 747 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 748 GSWIP_PCE_VCTRL_VEMR, 749 GSWIP_PCE_VCTRL(port)); 750 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_TVM, 0, 751 GSWIP_PCE_PCTRL_0p(port)); 752 } else { 753 /* Use port based VLAN tag */ 754 gswip_switch_mask(priv, 755 GSWIP_PCE_VCTRL_UVR | GSWIP_PCE_VCTRL_VIMR | 756 GSWIP_PCE_VCTRL_VEMR, 757 GSWIP_PCE_VCTRL_VSR, 758 GSWIP_PCE_VCTRL(port)); 759 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_TVM, 760 GSWIP_PCE_PCTRL_0p(port)); 761 } 762 763 return 0; 764 } 765 766 static int gswip_setup(struct dsa_switch *ds) 767 { 768 struct gswip_priv *priv = ds->priv; 769 unsigned int cpu_port = priv->hw_info->cpu_port; 770 int i; 771 int err; 772 773 gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES); 774 usleep_range(5000, 10000); 775 gswip_switch_w(priv, 0, GSWIP_SWRES); 776 777 /* disable port fetch/store dma on all ports */ 778 for (i = 0; i < priv->hw_info->max_ports; i++) { 779 gswip_port_disable(ds, i); 780 gswip_port_vlan_filtering(ds, i, false, NULL); 781 } 782 783 /* enable Switch */ 784 gswip_mdio_mask(priv, 0, GSWIP_MDIO_GLOB_ENABLE, GSWIP_MDIO_GLOB); 785 786 err = gswip_pce_load_microcode(priv); 787 if (err) { 788 dev_err(priv->dev, "writing PCE microcode failed, %i", err); 789 return err; 790 } 791 792 /* Default unknown Broadcast/Multicast/Unicast port maps */ 793 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1); 794 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2); 795 gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3); 796 797 /* disable PHY auto polling */ 798 gswip_mdio_w(priv, 0x0, GSWIP_MDIO_MDC_CFG0); 799 /* Configure the MDIO Clock 2.5 MHz */ 800 gswip_mdio_mask(priv, 0xff, 0x09, GSWIP_MDIO_MDC_CFG1); 801 802 /* Disable the xMII link */ 803 for (i = 0; i < priv->hw_info->max_ports; i++) 804 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, i); 805 806 /* enable special tag insertion on cpu port */ 807 gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN, 808 GSWIP_FDMA_PCTRLp(cpu_port)); 809 810 /* accept special tag in ingress direction */ 811 gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS, 812 GSWIP_PCE_PCTRL_0p(cpu_port)); 813 814 gswip_switch_mask(priv, 0, GSWIP_MAC_CTRL_2_MLEN, 815 GSWIP_MAC_CTRL_2p(cpu_port)); 816 gswip_switch_w(priv, VLAN_ETH_FRAME_LEN + 8, GSWIP_MAC_FLEN); 817 gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD, 818 GSWIP_BM_QUEUE_GCTRL); 819 820 /* VLAN aware Switching */ 821 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_VLAN, GSWIP_PCE_GCTRL_0); 822 823 /* Flush MAC Table */ 824 gswip_switch_mask(priv, 0, GSWIP_PCE_GCTRL_0_MTFL, GSWIP_PCE_GCTRL_0); 825 826 err = gswip_switch_r_timeout(priv, GSWIP_PCE_GCTRL_0, 827 GSWIP_PCE_GCTRL_0_MTFL); 828 if (err) { 829 dev_err(priv->dev, "MAC flushing didn't finish\n"); 830 return err; 831 } 832 833 gswip_port_enable(ds, cpu_port, NULL); 834 835 ds->configure_vlan_while_not_filtering = false; 836 837 return 0; 838 } 839 840 static enum dsa_tag_protocol gswip_get_tag_protocol(struct dsa_switch *ds, 841 int port, 842 enum dsa_tag_protocol mp) 843 { 844 return DSA_TAG_PROTO_GSWIP; 845 } 846 847 static int gswip_vlan_active_create(struct gswip_priv *priv, 848 struct net_device *bridge, 849 int fid, u16 vid) 850 { 851 struct gswip_pce_table_entry vlan_active = {0,}; 852 unsigned int max_ports = priv->hw_info->max_ports; 853 int idx = -1; 854 int err; 855 int i; 856 857 /* Look for a free slot */ 858 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 859 if (!priv->vlans[i].bridge) { 860 idx = i; 861 break; 862 } 863 } 864 865 if (idx == -1) 866 return -ENOSPC; 867 868 if (fid == -1) 869 fid = idx; 870 871 vlan_active.index = idx; 872 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 873 vlan_active.key[0] = vid; 874 vlan_active.val[0] = fid; 875 vlan_active.valid = true; 876 877 err = gswip_pce_table_entry_write(priv, &vlan_active); 878 if (err) { 879 dev_err(priv->dev, "failed to write active VLAN: %d\n", err); 880 return err; 881 } 882 883 priv->vlans[idx].bridge = bridge; 884 priv->vlans[idx].vid = vid; 885 priv->vlans[idx].fid = fid; 886 887 return idx; 888 } 889 890 static int gswip_vlan_active_remove(struct gswip_priv *priv, int idx) 891 { 892 struct gswip_pce_table_entry vlan_active = {0,}; 893 int err; 894 895 vlan_active.index = idx; 896 vlan_active.table = GSWIP_TABLE_ACTIVE_VLAN; 897 vlan_active.valid = false; 898 err = gswip_pce_table_entry_write(priv, &vlan_active); 899 if (err) 900 dev_err(priv->dev, "failed to delete active VLAN: %d\n", err); 901 priv->vlans[idx].bridge = NULL; 902 903 return err; 904 } 905 906 static int gswip_vlan_add_unaware(struct gswip_priv *priv, 907 struct net_device *bridge, int port) 908 { 909 struct gswip_pce_table_entry vlan_mapping = {0,}; 910 unsigned int max_ports = priv->hw_info->max_ports; 911 unsigned int cpu_port = priv->hw_info->cpu_port; 912 bool active_vlan_created = false; 913 int idx = -1; 914 int i; 915 int err; 916 917 /* Check if there is already a page for this bridge */ 918 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 919 if (priv->vlans[i].bridge == bridge) { 920 idx = i; 921 break; 922 } 923 } 924 925 /* If this bridge is not programmed yet, add a Active VLAN table 926 * entry in a free slot and prepare the VLAN mapping table entry. 927 */ 928 if (idx == -1) { 929 idx = gswip_vlan_active_create(priv, bridge, -1, 0); 930 if (idx < 0) 931 return idx; 932 active_vlan_created = true; 933 934 vlan_mapping.index = idx; 935 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 936 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 937 vlan_mapping.val[0] = 0; 938 } else { 939 /* Read the existing VLAN mapping entry from the switch */ 940 vlan_mapping.index = idx; 941 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 942 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 943 if (err) { 944 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 945 err); 946 return err; 947 } 948 } 949 950 /* Update the VLAN mapping entry and write it to the switch */ 951 vlan_mapping.val[1] |= BIT(cpu_port); 952 vlan_mapping.val[1] |= BIT(port); 953 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 954 if (err) { 955 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 956 /* In case an Active VLAN was creaetd delete it again */ 957 if (active_vlan_created) 958 gswip_vlan_active_remove(priv, idx); 959 return err; 960 } 961 962 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 963 return 0; 964 } 965 966 static int gswip_vlan_add_aware(struct gswip_priv *priv, 967 struct net_device *bridge, int port, 968 u16 vid, bool untagged, 969 bool pvid) 970 { 971 struct gswip_pce_table_entry vlan_mapping = {0,}; 972 unsigned int max_ports = priv->hw_info->max_ports; 973 unsigned int cpu_port = priv->hw_info->cpu_port; 974 bool active_vlan_created = false; 975 int idx = -1; 976 int fid = -1; 977 int i; 978 int err; 979 980 /* Check if there is already a page for this bridge */ 981 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 982 if (priv->vlans[i].bridge == bridge) { 983 if (fid != -1 && fid != priv->vlans[i].fid) 984 dev_err(priv->dev, "one bridge with multiple flow ids\n"); 985 fid = priv->vlans[i].fid; 986 if (priv->vlans[i].vid == vid) { 987 idx = i; 988 break; 989 } 990 } 991 } 992 993 /* If this bridge is not programmed yet, add a Active VLAN table 994 * entry in a free slot and prepare the VLAN mapping table entry. 995 */ 996 if (idx == -1) { 997 idx = gswip_vlan_active_create(priv, bridge, fid, vid); 998 if (idx < 0) 999 return idx; 1000 active_vlan_created = true; 1001 1002 vlan_mapping.index = idx; 1003 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1004 /* VLAN ID byte, maps to the VLAN ID of vlan active table */ 1005 vlan_mapping.val[0] = vid; 1006 } else { 1007 /* Read the existing VLAN mapping entry from the switch */ 1008 vlan_mapping.index = idx; 1009 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1010 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1011 if (err) { 1012 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", 1013 err); 1014 return err; 1015 } 1016 } 1017 1018 vlan_mapping.val[0] = vid; 1019 /* Update the VLAN mapping entry and write it to the switch */ 1020 vlan_mapping.val[1] |= BIT(cpu_port); 1021 vlan_mapping.val[2] |= BIT(cpu_port); 1022 vlan_mapping.val[1] |= BIT(port); 1023 if (untagged) 1024 vlan_mapping.val[2] &= ~BIT(port); 1025 else 1026 vlan_mapping.val[2] |= BIT(port); 1027 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1028 if (err) { 1029 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1030 /* In case an Active VLAN was creaetd delete it again */ 1031 if (active_vlan_created) 1032 gswip_vlan_active_remove(priv, idx); 1033 return err; 1034 } 1035 1036 if (pvid) 1037 gswip_switch_w(priv, idx, GSWIP_PCE_DEFPVID(port)); 1038 1039 return 0; 1040 } 1041 1042 static int gswip_vlan_remove(struct gswip_priv *priv, 1043 struct net_device *bridge, int port, 1044 u16 vid, bool pvid, bool vlan_aware) 1045 { 1046 struct gswip_pce_table_entry vlan_mapping = {0,}; 1047 unsigned int max_ports = priv->hw_info->max_ports; 1048 unsigned int cpu_port = priv->hw_info->cpu_port; 1049 int idx = -1; 1050 int i; 1051 int err; 1052 1053 /* Check if there is already a page for this bridge */ 1054 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1055 if (priv->vlans[i].bridge == bridge && 1056 (!vlan_aware || priv->vlans[i].vid == vid)) { 1057 idx = i; 1058 break; 1059 } 1060 } 1061 1062 if (idx == -1) { 1063 dev_err(priv->dev, "bridge to leave does not exists\n"); 1064 return -ENOENT; 1065 } 1066 1067 vlan_mapping.index = idx; 1068 vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING; 1069 err = gswip_pce_table_entry_read(priv, &vlan_mapping); 1070 if (err) { 1071 dev_err(priv->dev, "failed to read VLAN mapping: %d\n", err); 1072 return err; 1073 } 1074 1075 vlan_mapping.val[1] &= ~BIT(port); 1076 vlan_mapping.val[2] &= ~BIT(port); 1077 err = gswip_pce_table_entry_write(priv, &vlan_mapping); 1078 if (err) { 1079 dev_err(priv->dev, "failed to write VLAN mapping: %d\n", err); 1080 return err; 1081 } 1082 1083 /* In case all ports are removed from the bridge, remove the VLAN */ 1084 if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) { 1085 err = gswip_vlan_active_remove(priv, idx); 1086 if (err) { 1087 dev_err(priv->dev, "failed to write active VLAN: %d\n", 1088 err); 1089 return err; 1090 } 1091 } 1092 1093 /* GSWIP 2.2 (GRX300) and later program here the VID directly. */ 1094 if (pvid) 1095 gswip_switch_w(priv, 0, GSWIP_PCE_DEFPVID(port)); 1096 1097 return 0; 1098 } 1099 1100 static int gswip_port_bridge_join(struct dsa_switch *ds, int port, 1101 struct net_device *bridge) 1102 { 1103 struct gswip_priv *priv = ds->priv; 1104 int err; 1105 1106 /* When the bridge uses VLAN filtering we have to configure VLAN 1107 * specific bridges. No bridge is configured here. 1108 */ 1109 if (!br_vlan_enabled(bridge)) { 1110 err = gswip_vlan_add_unaware(priv, bridge, port); 1111 if (err) 1112 return err; 1113 priv->port_vlan_filter &= ~BIT(port); 1114 } else { 1115 priv->port_vlan_filter |= BIT(port); 1116 } 1117 return gswip_add_single_port_br(priv, port, false); 1118 } 1119 1120 static void gswip_port_bridge_leave(struct dsa_switch *ds, int port, 1121 struct net_device *bridge) 1122 { 1123 struct gswip_priv *priv = ds->priv; 1124 1125 gswip_add_single_port_br(priv, port, true); 1126 1127 /* When the bridge uses VLAN filtering we have to configure VLAN 1128 * specific bridges. No bridge is configured here. 1129 */ 1130 if (!br_vlan_enabled(bridge)) 1131 gswip_vlan_remove(priv, bridge, port, 0, true, false); 1132 } 1133 1134 static int gswip_port_vlan_prepare(struct dsa_switch *ds, int port, 1135 const struct switchdev_obj_port_vlan *vlan, 1136 struct netlink_ext_ack *extack) 1137 { 1138 struct gswip_priv *priv = ds->priv; 1139 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1140 unsigned int max_ports = priv->hw_info->max_ports; 1141 int pos = max_ports; 1142 int i, idx = -1; 1143 1144 /* We only support VLAN filtering on bridges */ 1145 if (!dsa_is_cpu_port(ds, port) && !bridge) 1146 return -EOPNOTSUPP; 1147 1148 /* Check if there is already a page for this VLAN */ 1149 for (i = max_ports; i < ARRAY_SIZE(priv->vlans); i++) { 1150 if (priv->vlans[i].bridge == bridge && 1151 priv->vlans[i].vid == vlan->vid) { 1152 idx = i; 1153 break; 1154 } 1155 } 1156 1157 /* If this VLAN is not programmed yet, we have to reserve 1158 * one entry in the VLAN table. Make sure we start at the 1159 * next position round. 1160 */ 1161 if (idx == -1) { 1162 /* Look for a free slot */ 1163 for (; pos < ARRAY_SIZE(priv->vlans); pos++) { 1164 if (!priv->vlans[pos].bridge) { 1165 idx = pos; 1166 pos++; 1167 break; 1168 } 1169 } 1170 1171 if (idx == -1) { 1172 NL_SET_ERR_MSG_MOD(extack, "No slot in VLAN table"); 1173 return -ENOSPC; 1174 } 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int gswip_port_vlan_add(struct dsa_switch *ds, int port, 1181 const struct switchdev_obj_port_vlan *vlan, 1182 struct netlink_ext_ack *extack) 1183 { 1184 struct gswip_priv *priv = ds->priv; 1185 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1186 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1187 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1188 int err; 1189 1190 err = gswip_port_vlan_prepare(ds, port, vlan, extack); 1191 if (err) 1192 return err; 1193 1194 /* We have to receive all packets on the CPU port and should not 1195 * do any VLAN filtering here. This is also called with bridge 1196 * NULL and then we do not know for which bridge to configure 1197 * this. 1198 */ 1199 if (dsa_is_cpu_port(ds, port)) 1200 return 0; 1201 1202 return gswip_vlan_add_aware(priv, bridge, port, vlan->vid, 1203 untagged, pvid); 1204 } 1205 1206 static int gswip_port_vlan_del(struct dsa_switch *ds, int port, 1207 const struct switchdev_obj_port_vlan *vlan) 1208 { 1209 struct gswip_priv *priv = ds->priv; 1210 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1211 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1212 1213 /* We have to receive all packets on the CPU port and should not 1214 * do any VLAN filtering here. This is also called with bridge 1215 * NULL and then we do not know for which bridge to configure 1216 * this. 1217 */ 1218 if (dsa_is_cpu_port(ds, port)) 1219 return 0; 1220 1221 return gswip_vlan_remove(priv, bridge, port, vlan->vid, pvid, true); 1222 } 1223 1224 static void gswip_port_fast_age(struct dsa_switch *ds, int port) 1225 { 1226 struct gswip_priv *priv = ds->priv; 1227 struct gswip_pce_table_entry mac_bridge = {0,}; 1228 int i; 1229 int err; 1230 1231 for (i = 0; i < 2048; i++) { 1232 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1233 mac_bridge.index = i; 1234 1235 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1236 if (err) { 1237 dev_err(priv->dev, "failed to read mac bridge: %d\n", 1238 err); 1239 return; 1240 } 1241 1242 if (!mac_bridge.valid) 1243 continue; 1244 1245 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) 1246 continue; 1247 1248 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) != port) 1249 continue; 1250 1251 mac_bridge.valid = false; 1252 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1253 if (err) { 1254 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1255 err); 1256 return; 1257 } 1258 } 1259 } 1260 1261 static void gswip_port_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1262 { 1263 struct gswip_priv *priv = ds->priv; 1264 u32 stp_state; 1265 1266 switch (state) { 1267 case BR_STATE_DISABLED: 1268 gswip_switch_mask(priv, GSWIP_SDMA_PCTRL_EN, 0, 1269 GSWIP_SDMA_PCTRLp(port)); 1270 return; 1271 case BR_STATE_BLOCKING: 1272 case BR_STATE_LISTENING: 1273 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LISTEN; 1274 break; 1275 case BR_STATE_LEARNING: 1276 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_LEARNING; 1277 break; 1278 case BR_STATE_FORWARDING: 1279 stp_state = GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING; 1280 break; 1281 default: 1282 dev_err(priv->dev, "invalid STP state: %d\n", state); 1283 return; 1284 } 1285 1286 gswip_switch_mask(priv, 0, GSWIP_SDMA_PCTRL_EN, 1287 GSWIP_SDMA_PCTRLp(port)); 1288 gswip_switch_mask(priv, GSWIP_PCE_PCTRL_0_PSTATE_MASK, stp_state, 1289 GSWIP_PCE_PCTRL_0p(port)); 1290 } 1291 1292 static int gswip_port_fdb(struct dsa_switch *ds, int port, 1293 const unsigned char *addr, u16 vid, bool add) 1294 { 1295 struct gswip_priv *priv = ds->priv; 1296 struct net_device *bridge = dsa_to_port(ds, port)->bridge_dev; 1297 struct gswip_pce_table_entry mac_bridge = {0,}; 1298 unsigned int cpu_port = priv->hw_info->cpu_port; 1299 int fid = -1; 1300 int i; 1301 int err; 1302 1303 if (!bridge) 1304 return -EINVAL; 1305 1306 for (i = cpu_port; i < ARRAY_SIZE(priv->vlans); i++) { 1307 if (priv->vlans[i].bridge == bridge) { 1308 fid = priv->vlans[i].fid; 1309 break; 1310 } 1311 } 1312 1313 if (fid == -1) { 1314 dev_err(priv->dev, "Port not part of a bridge\n"); 1315 return -EINVAL; 1316 } 1317 1318 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1319 mac_bridge.key_mode = true; 1320 mac_bridge.key[0] = addr[5] | (addr[4] << 8); 1321 mac_bridge.key[1] = addr[3] | (addr[2] << 8); 1322 mac_bridge.key[2] = addr[1] | (addr[0] << 8); 1323 mac_bridge.key[3] = fid; 1324 mac_bridge.val[0] = add ? BIT(port) : 0; /* port map */ 1325 mac_bridge.val[1] = GSWIP_TABLE_MAC_BRIDGE_STATIC; 1326 mac_bridge.valid = add; 1327 1328 err = gswip_pce_table_entry_write(priv, &mac_bridge); 1329 if (err) 1330 dev_err(priv->dev, "failed to write mac bridge: %d\n", err); 1331 1332 return err; 1333 } 1334 1335 static int gswip_port_fdb_add(struct dsa_switch *ds, int port, 1336 const unsigned char *addr, u16 vid) 1337 { 1338 return gswip_port_fdb(ds, port, addr, vid, true); 1339 } 1340 1341 static int gswip_port_fdb_del(struct dsa_switch *ds, int port, 1342 const unsigned char *addr, u16 vid) 1343 { 1344 return gswip_port_fdb(ds, port, addr, vid, false); 1345 } 1346 1347 static int gswip_port_fdb_dump(struct dsa_switch *ds, int port, 1348 dsa_fdb_dump_cb_t *cb, void *data) 1349 { 1350 struct gswip_priv *priv = ds->priv; 1351 struct gswip_pce_table_entry mac_bridge = {0,}; 1352 unsigned char addr[6]; 1353 int i; 1354 int err; 1355 1356 for (i = 0; i < 2048; i++) { 1357 mac_bridge.table = GSWIP_TABLE_MAC_BRIDGE; 1358 mac_bridge.index = i; 1359 1360 err = gswip_pce_table_entry_read(priv, &mac_bridge); 1361 if (err) { 1362 dev_err(priv->dev, "failed to write mac bridge: %d\n", 1363 err); 1364 return err; 1365 } 1366 1367 if (!mac_bridge.valid) 1368 continue; 1369 1370 addr[5] = mac_bridge.key[0] & 0xff; 1371 addr[4] = (mac_bridge.key[0] >> 8) & 0xff; 1372 addr[3] = mac_bridge.key[1] & 0xff; 1373 addr[2] = (mac_bridge.key[1] >> 8) & 0xff; 1374 addr[1] = mac_bridge.key[2] & 0xff; 1375 addr[0] = (mac_bridge.key[2] >> 8) & 0xff; 1376 if (mac_bridge.val[1] & GSWIP_TABLE_MAC_BRIDGE_STATIC) { 1377 if (mac_bridge.val[0] & BIT(port)) 1378 cb(addr, 0, true, data); 1379 } else { 1380 if (((mac_bridge.val[0] & GENMASK(7, 4)) >> 4) == port) 1381 cb(addr, 0, false, data); 1382 } 1383 } 1384 return 0; 1385 } 1386 1387 static void gswip_phylink_validate(struct dsa_switch *ds, int port, 1388 unsigned long *supported, 1389 struct phylink_link_state *state) 1390 { 1391 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 1392 1393 switch (port) { 1394 case 0: 1395 case 1: 1396 if (!phy_interface_mode_is_rgmii(state->interface) && 1397 state->interface != PHY_INTERFACE_MODE_MII && 1398 state->interface != PHY_INTERFACE_MODE_REVMII && 1399 state->interface != PHY_INTERFACE_MODE_RMII) 1400 goto unsupported; 1401 break; 1402 case 2: 1403 case 3: 1404 case 4: 1405 if (state->interface != PHY_INTERFACE_MODE_INTERNAL) 1406 goto unsupported; 1407 break; 1408 case 5: 1409 if (!phy_interface_mode_is_rgmii(state->interface) && 1410 state->interface != PHY_INTERFACE_MODE_INTERNAL) 1411 goto unsupported; 1412 break; 1413 default: 1414 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1415 dev_err(ds->dev, "Unsupported port: %i\n", port); 1416 return; 1417 } 1418 1419 /* Allow all the expected bits */ 1420 phylink_set(mask, Autoneg); 1421 phylink_set_port_modes(mask); 1422 phylink_set(mask, Pause); 1423 phylink_set(mask, Asym_Pause); 1424 1425 /* With the exclusion of MII, Reverse MII and Reduced MII, we 1426 * support Gigabit, including Half duplex 1427 */ 1428 if (state->interface != PHY_INTERFACE_MODE_MII && 1429 state->interface != PHY_INTERFACE_MODE_REVMII && 1430 state->interface != PHY_INTERFACE_MODE_RMII) { 1431 phylink_set(mask, 1000baseT_Full); 1432 phylink_set(mask, 1000baseT_Half); 1433 } 1434 1435 phylink_set(mask, 10baseT_Half); 1436 phylink_set(mask, 10baseT_Full); 1437 phylink_set(mask, 100baseT_Half); 1438 phylink_set(mask, 100baseT_Full); 1439 1440 bitmap_and(supported, supported, mask, 1441 __ETHTOOL_LINK_MODE_MASK_NBITS); 1442 bitmap_and(state->advertising, state->advertising, mask, 1443 __ETHTOOL_LINK_MODE_MASK_NBITS); 1444 return; 1445 1446 unsupported: 1447 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); 1448 dev_err(ds->dev, "Unsupported interface '%s' for port %d\n", 1449 phy_modes(state->interface), port); 1450 return; 1451 } 1452 1453 static void gswip_phylink_mac_config(struct dsa_switch *ds, int port, 1454 unsigned int mode, 1455 const struct phylink_link_state *state) 1456 { 1457 struct gswip_priv *priv = ds->priv; 1458 u32 miicfg = 0; 1459 1460 miicfg |= GSWIP_MII_CFG_LDCLKDIS; 1461 1462 switch (state->interface) { 1463 case PHY_INTERFACE_MODE_MII: 1464 case PHY_INTERFACE_MODE_INTERNAL: 1465 miicfg |= GSWIP_MII_CFG_MODE_MIIM; 1466 break; 1467 case PHY_INTERFACE_MODE_REVMII: 1468 miicfg |= GSWIP_MII_CFG_MODE_MIIP; 1469 break; 1470 case PHY_INTERFACE_MODE_RMII: 1471 miicfg |= GSWIP_MII_CFG_MODE_RMIIM; 1472 break; 1473 case PHY_INTERFACE_MODE_RGMII: 1474 case PHY_INTERFACE_MODE_RGMII_ID: 1475 case PHY_INTERFACE_MODE_RGMII_RXID: 1476 case PHY_INTERFACE_MODE_RGMII_TXID: 1477 miicfg |= GSWIP_MII_CFG_MODE_RGMII; 1478 break; 1479 default: 1480 dev_err(ds->dev, 1481 "Unsupported interface: %d\n", state->interface); 1482 return; 1483 } 1484 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_MODE_MASK, miicfg, port); 1485 1486 switch (state->interface) { 1487 case PHY_INTERFACE_MODE_RGMII_ID: 1488 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK | 1489 GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1490 break; 1491 case PHY_INTERFACE_MODE_RGMII_RXID: 1492 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_RXDLY_MASK, 0, port); 1493 break; 1494 case PHY_INTERFACE_MODE_RGMII_TXID: 1495 gswip_mii_mask_pcdu(priv, GSWIP_MII_PCDU_TXDLY_MASK, 0, port); 1496 break; 1497 default: 1498 break; 1499 } 1500 } 1501 1502 static void gswip_phylink_mac_link_down(struct dsa_switch *ds, int port, 1503 unsigned int mode, 1504 phy_interface_t interface) 1505 { 1506 struct gswip_priv *priv = ds->priv; 1507 1508 gswip_mii_mask_cfg(priv, GSWIP_MII_CFG_EN, 0, port); 1509 } 1510 1511 static void gswip_phylink_mac_link_up(struct dsa_switch *ds, int port, 1512 unsigned int mode, 1513 phy_interface_t interface, 1514 struct phy_device *phydev, 1515 int speed, int duplex, 1516 bool tx_pause, bool rx_pause) 1517 { 1518 struct gswip_priv *priv = ds->priv; 1519 1520 gswip_mii_mask_cfg(priv, 0, GSWIP_MII_CFG_EN, port); 1521 } 1522 1523 static void gswip_get_strings(struct dsa_switch *ds, int port, u32 stringset, 1524 uint8_t *data) 1525 { 1526 int i; 1527 1528 if (stringset != ETH_SS_STATS) 1529 return; 1530 1531 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) 1532 strncpy(data + i * ETH_GSTRING_LEN, gswip_rmon_cnt[i].name, 1533 ETH_GSTRING_LEN); 1534 } 1535 1536 static u32 gswip_bcm_ram_entry_read(struct gswip_priv *priv, u32 table, 1537 u32 index) 1538 { 1539 u32 result; 1540 int err; 1541 1542 gswip_switch_w(priv, index, GSWIP_BM_RAM_ADDR); 1543 gswip_switch_mask(priv, GSWIP_BM_RAM_CTRL_ADDR_MASK | 1544 GSWIP_BM_RAM_CTRL_OPMOD, 1545 table | GSWIP_BM_RAM_CTRL_BAS, 1546 GSWIP_BM_RAM_CTRL); 1547 1548 err = gswip_switch_r_timeout(priv, GSWIP_BM_RAM_CTRL, 1549 GSWIP_BM_RAM_CTRL_BAS); 1550 if (err) { 1551 dev_err(priv->dev, "timeout while reading table: %u, index: %u", 1552 table, index); 1553 return 0; 1554 } 1555 1556 result = gswip_switch_r(priv, GSWIP_BM_RAM_VAL(0)); 1557 result |= gswip_switch_r(priv, GSWIP_BM_RAM_VAL(1)) << 16; 1558 1559 return result; 1560 } 1561 1562 static void gswip_get_ethtool_stats(struct dsa_switch *ds, int port, 1563 uint64_t *data) 1564 { 1565 struct gswip_priv *priv = ds->priv; 1566 const struct gswip_rmon_cnt_desc *rmon_cnt; 1567 int i; 1568 u64 high; 1569 1570 for (i = 0; i < ARRAY_SIZE(gswip_rmon_cnt); i++) { 1571 rmon_cnt = &gswip_rmon_cnt[i]; 1572 1573 data[i] = gswip_bcm_ram_entry_read(priv, port, 1574 rmon_cnt->offset); 1575 if (rmon_cnt->size == 2) { 1576 high = gswip_bcm_ram_entry_read(priv, port, 1577 rmon_cnt->offset + 1); 1578 data[i] |= high << 32; 1579 } 1580 } 1581 } 1582 1583 static int gswip_get_sset_count(struct dsa_switch *ds, int port, int sset) 1584 { 1585 if (sset != ETH_SS_STATS) 1586 return 0; 1587 1588 return ARRAY_SIZE(gswip_rmon_cnt); 1589 } 1590 1591 static const struct dsa_switch_ops gswip_switch_ops = { 1592 .get_tag_protocol = gswip_get_tag_protocol, 1593 .setup = gswip_setup, 1594 .port_enable = gswip_port_enable, 1595 .port_disable = gswip_port_disable, 1596 .port_bridge_join = gswip_port_bridge_join, 1597 .port_bridge_leave = gswip_port_bridge_leave, 1598 .port_fast_age = gswip_port_fast_age, 1599 .port_vlan_filtering = gswip_port_vlan_filtering, 1600 .port_vlan_add = gswip_port_vlan_add, 1601 .port_vlan_del = gswip_port_vlan_del, 1602 .port_stp_state_set = gswip_port_stp_state_set, 1603 .port_fdb_add = gswip_port_fdb_add, 1604 .port_fdb_del = gswip_port_fdb_del, 1605 .port_fdb_dump = gswip_port_fdb_dump, 1606 .phylink_validate = gswip_phylink_validate, 1607 .phylink_mac_config = gswip_phylink_mac_config, 1608 .phylink_mac_link_down = gswip_phylink_mac_link_down, 1609 .phylink_mac_link_up = gswip_phylink_mac_link_up, 1610 .get_strings = gswip_get_strings, 1611 .get_ethtool_stats = gswip_get_ethtool_stats, 1612 .get_sset_count = gswip_get_sset_count, 1613 }; 1614 1615 static const struct xway_gphy_match_data xrx200a1x_gphy_data = { 1616 .fe_firmware_name = "lantiq/xrx200_phy22f_a14.bin", 1617 .ge_firmware_name = "lantiq/xrx200_phy11g_a14.bin", 1618 }; 1619 1620 static const struct xway_gphy_match_data xrx200a2x_gphy_data = { 1621 .fe_firmware_name = "lantiq/xrx200_phy22f_a22.bin", 1622 .ge_firmware_name = "lantiq/xrx200_phy11g_a22.bin", 1623 }; 1624 1625 static const struct xway_gphy_match_data xrx300_gphy_data = { 1626 .fe_firmware_name = "lantiq/xrx300_phy22f_a21.bin", 1627 .ge_firmware_name = "lantiq/xrx300_phy11g_a21.bin", 1628 }; 1629 1630 static const struct of_device_id xway_gphy_match[] = { 1631 { .compatible = "lantiq,xrx200-gphy-fw", .data = NULL }, 1632 { .compatible = "lantiq,xrx200a1x-gphy-fw", .data = &xrx200a1x_gphy_data }, 1633 { .compatible = "lantiq,xrx200a2x-gphy-fw", .data = &xrx200a2x_gphy_data }, 1634 { .compatible = "lantiq,xrx300-gphy-fw", .data = &xrx300_gphy_data }, 1635 { .compatible = "lantiq,xrx330-gphy-fw", .data = &xrx300_gphy_data }, 1636 {}, 1637 }; 1638 1639 static int gswip_gphy_fw_load(struct gswip_priv *priv, struct gswip_gphy_fw *gphy_fw) 1640 { 1641 struct device *dev = priv->dev; 1642 const struct firmware *fw; 1643 void *fw_addr; 1644 dma_addr_t dma_addr; 1645 dma_addr_t dev_addr; 1646 size_t size; 1647 int ret; 1648 1649 ret = clk_prepare_enable(gphy_fw->clk_gate); 1650 if (ret) 1651 return ret; 1652 1653 reset_control_assert(gphy_fw->reset); 1654 1655 ret = request_firmware(&fw, gphy_fw->fw_name, dev); 1656 if (ret) { 1657 dev_err(dev, "failed to load firmware: %s, error: %i\n", 1658 gphy_fw->fw_name, ret); 1659 return ret; 1660 } 1661 1662 /* GPHY cores need the firmware code in a persistent and contiguous 1663 * memory area with a 16 kB boundary aligned start address. 1664 */ 1665 size = fw->size + XRX200_GPHY_FW_ALIGN; 1666 1667 fw_addr = dmam_alloc_coherent(dev, size, &dma_addr, GFP_KERNEL); 1668 if (fw_addr) { 1669 fw_addr = PTR_ALIGN(fw_addr, XRX200_GPHY_FW_ALIGN); 1670 dev_addr = ALIGN(dma_addr, XRX200_GPHY_FW_ALIGN); 1671 memcpy(fw_addr, fw->data, fw->size); 1672 } else { 1673 dev_err(dev, "failed to alloc firmware memory\n"); 1674 release_firmware(fw); 1675 return -ENOMEM; 1676 } 1677 1678 release_firmware(fw); 1679 1680 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, dev_addr); 1681 if (ret) 1682 return ret; 1683 1684 reset_control_deassert(gphy_fw->reset); 1685 1686 return ret; 1687 } 1688 1689 static int gswip_gphy_fw_probe(struct gswip_priv *priv, 1690 struct gswip_gphy_fw *gphy_fw, 1691 struct device_node *gphy_fw_np, int i) 1692 { 1693 struct device *dev = priv->dev; 1694 u32 gphy_mode; 1695 int ret; 1696 char gphyname[10]; 1697 1698 snprintf(gphyname, sizeof(gphyname), "gphy%d", i); 1699 1700 gphy_fw->clk_gate = devm_clk_get(dev, gphyname); 1701 if (IS_ERR(gphy_fw->clk_gate)) { 1702 dev_err(dev, "Failed to lookup gate clock\n"); 1703 return PTR_ERR(gphy_fw->clk_gate); 1704 } 1705 1706 ret = of_property_read_u32(gphy_fw_np, "reg", &gphy_fw->fw_addr_offset); 1707 if (ret) 1708 return ret; 1709 1710 ret = of_property_read_u32(gphy_fw_np, "lantiq,gphy-mode", &gphy_mode); 1711 /* Default to GE mode */ 1712 if (ret) 1713 gphy_mode = GPHY_MODE_GE; 1714 1715 switch (gphy_mode) { 1716 case GPHY_MODE_FE: 1717 gphy_fw->fw_name = priv->gphy_fw_name_cfg->fe_firmware_name; 1718 break; 1719 case GPHY_MODE_GE: 1720 gphy_fw->fw_name = priv->gphy_fw_name_cfg->ge_firmware_name; 1721 break; 1722 default: 1723 dev_err(dev, "Unknown GPHY mode %d\n", gphy_mode); 1724 return -EINVAL; 1725 } 1726 1727 gphy_fw->reset = of_reset_control_array_get_exclusive(gphy_fw_np); 1728 if (IS_ERR(gphy_fw->reset)) { 1729 if (PTR_ERR(gphy_fw->reset) != -EPROBE_DEFER) 1730 dev_err(dev, "Failed to lookup gphy reset\n"); 1731 return PTR_ERR(gphy_fw->reset); 1732 } 1733 1734 return gswip_gphy_fw_load(priv, gphy_fw); 1735 } 1736 1737 static void gswip_gphy_fw_remove(struct gswip_priv *priv, 1738 struct gswip_gphy_fw *gphy_fw) 1739 { 1740 int ret; 1741 1742 /* check if the device was fully probed */ 1743 if (!gphy_fw->fw_name) 1744 return; 1745 1746 ret = regmap_write(priv->rcu_regmap, gphy_fw->fw_addr_offset, 0); 1747 if (ret) 1748 dev_err(priv->dev, "can not reset GPHY FW pointer"); 1749 1750 clk_disable_unprepare(gphy_fw->clk_gate); 1751 1752 reset_control_put(gphy_fw->reset); 1753 } 1754 1755 static int gswip_gphy_fw_list(struct gswip_priv *priv, 1756 struct device_node *gphy_fw_list_np, u32 version) 1757 { 1758 struct device *dev = priv->dev; 1759 struct device_node *gphy_fw_np; 1760 const struct of_device_id *match; 1761 int err; 1762 int i = 0; 1763 1764 /* The VRX200 rev 1.1 uses the GSWIP 2.0 and needs the older 1765 * GPHY firmware. The VRX200 rev 1.2 uses the GSWIP 2.1 and also 1766 * needs a different GPHY firmware. 1767 */ 1768 if (of_device_is_compatible(gphy_fw_list_np, "lantiq,xrx200-gphy-fw")) { 1769 switch (version) { 1770 case GSWIP_VERSION_2_0: 1771 priv->gphy_fw_name_cfg = &xrx200a1x_gphy_data; 1772 break; 1773 case GSWIP_VERSION_2_1: 1774 priv->gphy_fw_name_cfg = &xrx200a2x_gphy_data; 1775 break; 1776 default: 1777 dev_err(dev, "unknown GSWIP version: 0x%x", version); 1778 return -ENOENT; 1779 } 1780 } 1781 1782 match = of_match_node(xway_gphy_match, gphy_fw_list_np); 1783 if (match && match->data) 1784 priv->gphy_fw_name_cfg = match->data; 1785 1786 if (!priv->gphy_fw_name_cfg) { 1787 dev_err(dev, "GPHY compatible type not supported"); 1788 return -ENOENT; 1789 } 1790 1791 priv->num_gphy_fw = of_get_available_child_count(gphy_fw_list_np); 1792 if (!priv->num_gphy_fw) 1793 return -ENOENT; 1794 1795 priv->rcu_regmap = syscon_regmap_lookup_by_phandle(gphy_fw_list_np, 1796 "lantiq,rcu"); 1797 if (IS_ERR(priv->rcu_regmap)) 1798 return PTR_ERR(priv->rcu_regmap); 1799 1800 priv->gphy_fw = devm_kmalloc_array(dev, priv->num_gphy_fw, 1801 sizeof(*priv->gphy_fw), 1802 GFP_KERNEL | __GFP_ZERO); 1803 if (!priv->gphy_fw) 1804 return -ENOMEM; 1805 1806 for_each_available_child_of_node(gphy_fw_list_np, gphy_fw_np) { 1807 err = gswip_gphy_fw_probe(priv, &priv->gphy_fw[i], 1808 gphy_fw_np, i); 1809 if (err) 1810 goto remove_gphy; 1811 i++; 1812 } 1813 1814 /* The standalone PHY11G requires 300ms to be fully 1815 * initialized and ready for any MDIO communication after being 1816 * taken out of reset. For the SoC-internal GPHY variant there 1817 * is no (known) documentation for the minimum time after a 1818 * reset. Use the same value as for the standalone variant as 1819 * some users have reported internal PHYs not being detected 1820 * without any delay. 1821 */ 1822 msleep(300); 1823 1824 return 0; 1825 1826 remove_gphy: 1827 for (i = 0; i < priv->num_gphy_fw; i++) 1828 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1829 return err; 1830 } 1831 1832 static int gswip_probe(struct platform_device *pdev) 1833 { 1834 struct gswip_priv *priv; 1835 struct device_node *mdio_np, *gphy_fw_np; 1836 struct device *dev = &pdev->dev; 1837 int err; 1838 int i; 1839 u32 version; 1840 1841 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1842 if (!priv) 1843 return -ENOMEM; 1844 1845 priv->gswip = devm_platform_ioremap_resource(pdev, 0); 1846 if (IS_ERR(priv->gswip)) 1847 return PTR_ERR(priv->gswip); 1848 1849 priv->mdio = devm_platform_ioremap_resource(pdev, 1); 1850 if (IS_ERR(priv->mdio)) 1851 return PTR_ERR(priv->mdio); 1852 1853 priv->mii = devm_platform_ioremap_resource(pdev, 2); 1854 if (IS_ERR(priv->mii)) 1855 return PTR_ERR(priv->mii); 1856 1857 priv->hw_info = of_device_get_match_data(dev); 1858 if (!priv->hw_info) 1859 return -EINVAL; 1860 1861 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 1862 if (!priv->ds) 1863 return -ENOMEM; 1864 1865 priv->ds->dev = dev; 1866 priv->ds->num_ports = priv->hw_info->max_ports; 1867 priv->ds->priv = priv; 1868 priv->ds->ops = &gswip_switch_ops; 1869 priv->dev = dev; 1870 version = gswip_switch_r(priv, GSWIP_VERSION); 1871 1872 /* bring up the mdio bus */ 1873 gphy_fw_np = of_get_compatible_child(dev->of_node, "lantiq,gphy-fw"); 1874 if (gphy_fw_np) { 1875 err = gswip_gphy_fw_list(priv, gphy_fw_np, version); 1876 of_node_put(gphy_fw_np); 1877 if (err) { 1878 dev_err(dev, "gphy fw probe failed\n"); 1879 return err; 1880 } 1881 } 1882 1883 /* bring up the mdio bus */ 1884 mdio_np = of_get_compatible_child(dev->of_node, "lantiq,xrx200-mdio"); 1885 if (mdio_np) { 1886 err = gswip_mdio(priv, mdio_np); 1887 if (err) { 1888 dev_err(dev, "mdio probe failed\n"); 1889 goto put_mdio_node; 1890 } 1891 } 1892 1893 err = dsa_register_switch(priv->ds); 1894 if (err) { 1895 dev_err(dev, "dsa switch register failed: %i\n", err); 1896 goto mdio_bus; 1897 } 1898 if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) { 1899 dev_err(dev, "wrong CPU port defined, HW only supports port: %i", 1900 priv->hw_info->cpu_port); 1901 err = -EINVAL; 1902 goto disable_switch; 1903 } 1904 1905 platform_set_drvdata(pdev, priv); 1906 1907 dev_info(dev, "probed GSWIP version %lx mod %lx\n", 1908 (version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT, 1909 (version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT); 1910 return 0; 1911 1912 disable_switch: 1913 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1914 dsa_unregister_switch(priv->ds); 1915 mdio_bus: 1916 if (mdio_np) 1917 mdiobus_unregister(priv->ds->slave_mii_bus); 1918 put_mdio_node: 1919 of_node_put(mdio_np); 1920 for (i = 0; i < priv->num_gphy_fw; i++) 1921 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1922 return err; 1923 } 1924 1925 static int gswip_remove(struct platform_device *pdev) 1926 { 1927 struct gswip_priv *priv = platform_get_drvdata(pdev); 1928 int i; 1929 1930 /* disable the switch */ 1931 gswip_mdio_mask(priv, GSWIP_MDIO_GLOB_ENABLE, 0, GSWIP_MDIO_GLOB); 1932 1933 dsa_unregister_switch(priv->ds); 1934 1935 if (priv->ds->slave_mii_bus) { 1936 mdiobus_unregister(priv->ds->slave_mii_bus); 1937 of_node_put(priv->ds->slave_mii_bus->dev.of_node); 1938 } 1939 1940 for (i = 0; i < priv->num_gphy_fw; i++) 1941 gswip_gphy_fw_remove(priv, &priv->gphy_fw[i]); 1942 1943 return 0; 1944 } 1945 1946 static const struct gswip_hw_info gswip_xrx200 = { 1947 .max_ports = 7, 1948 .cpu_port = 6, 1949 }; 1950 1951 static const struct of_device_id gswip_of_match[] = { 1952 { .compatible = "lantiq,xrx200-gswip", .data = &gswip_xrx200 }, 1953 {}, 1954 }; 1955 MODULE_DEVICE_TABLE(of, gswip_of_match); 1956 1957 static struct platform_driver gswip_driver = { 1958 .probe = gswip_probe, 1959 .remove = gswip_remove, 1960 .driver = { 1961 .name = "gswip", 1962 .of_match_table = gswip_of_match, 1963 }, 1964 }; 1965 1966 module_platform_driver(gswip_driver); 1967 1968 MODULE_FIRMWARE("lantiq/xrx300_phy11g_a21.bin"); 1969 MODULE_FIRMWARE("lantiq/xrx300_phy22f_a21.bin"); 1970 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a14.bin"); 1971 MODULE_FIRMWARE("lantiq/xrx200_phy11g_a22.bin"); 1972 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a14.bin"); 1973 MODULE_FIRMWARE("lantiq/xrx200_phy22f_a22.bin"); 1974 MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>"); 1975 MODULE_DESCRIPTION("Lantiq / Intel GSWIP driver"); 1976 MODULE_LICENSE("GPL v2"); 1977