1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PCE microcode code update for driver for MaxLinear GSW1xx switch chips 4 * 5 * Copyright (C) 2023 - 2024 MaxLinear Inc. 6 * Copyright (C) 2022 Snap One, LLC. All rights reserved. 7 * Copyright (C) 2017 - 2019 Hauke Mehrtens <hauke@hauke-m.de> 8 * Copyright (C) 2012 John Crispin <john@phrozen.org> 9 * Copyright (C) 2010 Lantiq Deutschland 10 */ 11 12 #include "lantiq_gswip.h" 13 14 #define INSTR 0 15 #define IPV6 1 16 #define LENACCU 2 17 18 /* GSWIP_2.X */ 19 enum { 20 OUT_MAC0 = 0, 21 OUT_MAC1, 22 OUT_MAC2, 23 OUT_MAC3, 24 OUT_MAC4, 25 OUT_MAC5, 26 OUT_ETHTYP, 27 OUT_VTAG0, 28 OUT_VTAG1, 29 OUT_ITAG0, 30 OUT_ITAG1, /* 10 */ 31 OUT_ITAG2, 32 OUT_ITAG3, 33 OUT_IP0, 34 OUT_IP1, 35 OUT_IP2, 36 OUT_IP3, 37 OUT_SIP0, 38 OUT_SIP1, 39 OUT_SIP2, 40 OUT_SIP3, /* 20 */ 41 OUT_SIP4, 42 OUT_SIP5, 43 OUT_SIP6, 44 OUT_SIP7, 45 OUT_DIP0, 46 OUT_DIP1, 47 OUT_DIP2, 48 OUT_DIP3, 49 OUT_DIP4, 50 OUT_DIP5, /* 30 */ 51 OUT_DIP6, 52 OUT_DIP7, 53 OUT_SESID, 54 OUT_PROT, 55 OUT_APP0, 56 OUT_APP1, 57 OUT_IGMP0, 58 OUT_IGMP1, 59 OUT_STAG0 = 61, 60 OUT_STAG1 = 62, 61 OUT_NONE = 63, 62 }; 63 64 /* parser's microcode flag type */ 65 enum { 66 FLAG_ITAG = 0, 67 FLAG_VLAN, 68 FLAG_SNAP, 69 FLAG_PPPOE, 70 FLAG_IPV6, 71 FLAG_IPV6FL, 72 FLAG_IPV4, 73 FLAG_IGMP, 74 FLAG_TU, 75 FLAG_HOP, 76 FLAG_NN1, /* 10 */ 77 FLAG_NN2, 78 FLAG_END, 79 FLAG_NO, /* 13 */ 80 FLAG_SVLAN, /* 14 */ 81 }; 82 83 #define PCE_MC_M(val, msk, ns, out, len, type, flags, ipv4_len) \ 84 { (val), (msk), ((ns) << 10 | (out) << 4 | (len) >> 1),\ 85 ((len) & 1) << 15 | (type) << 13 | (flags) << 9 | (ipv4_len) << 8 } 86 87 /* V22_2X (IPv6 issue fixed) */ 88 static const struct gswip_pce_microcode gsw1xx_pce_microcode[] = { 89 /* value mask ns fields L type flags ipv4_len */ 90 PCE_MC_M(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0), 91 PCE_MC_M(0x8100, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0), 92 PCE_MC_M(0x88A8, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0), 93 PCE_MC_M(0x9100, 0xFFFF, 4, OUT_STAG0, 2, INSTR, FLAG_SVLAN, 0), 94 PCE_MC_M(0x8100, 0xFFFF, 5, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), 95 PCE_MC_M(0x88A8, 0xFFFF, 6, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), 96 PCE_MC_M(0x9100, 0xFFFF, 4, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0), 97 PCE_MC_M(0x8864, 0xFFFF, 20, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 98 PCE_MC_M(0x0800, 0xFFFF, 24, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 99 PCE_MC_M(0x86DD, 0xFFFF, 25, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 100 PCE_MC_M(0x8863, 0xFFFF, 19, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 101 PCE_MC_M(0x0000, 0xF800, 13, OUT_NONE, 0, INSTR, FLAG_NO, 0), 102 PCE_MC_M(0x0000, 0x0000, 44, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 103 PCE_MC_M(0x0600, 0x0600, 44, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0), 104 PCE_MC_M(0x0000, 0x0000, 15, OUT_NONE, 1, INSTR, FLAG_NO, 0), 105 PCE_MC_M(0xAAAA, 0xFFFF, 17, OUT_NONE, 1, INSTR, FLAG_NO, 0), 106 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0), 107 PCE_MC_M(0x0300, 0xFF00, 45, OUT_NONE, 0, INSTR, FLAG_SNAP, 0), 108 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0), 109 PCE_MC_M(0x0000, 0x0000, 45, OUT_DIP7, 3, INSTR, FLAG_NO, 0), 110 PCE_MC_M(0x0000, 0x0000, 21, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0), 111 PCE_MC_M(0x0021, 0xFFFF, 24, OUT_NONE, 1, INSTR, FLAG_NO, 0), 112 PCE_MC_M(0x0057, 0xFFFF, 25, OUT_NONE, 1, INSTR, FLAG_NO, 0), 113 PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, INSTR, FLAG_NO, 0), 114 PCE_MC_M(0x4000, 0xF000, 27, OUT_IP0, 4, INSTR, FLAG_IPV4, 1), 115 PCE_MC_M(0x6000, 0xF000, 30, OUT_IP0, 3, INSTR, FLAG_IPV6, 0), 116 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_NO, 0), 117 PCE_MC_M(0x0000, 0x0000, 28, OUT_IP3, 2, INSTR, FLAG_NO, 0), 118 PCE_MC_M(0x0000, 0x0000, 29, OUT_SIP0, 4, INSTR, FLAG_NO, 0), 119 PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, LENACCU, FLAG_NO, 0), 120 PCE_MC_M(0x1100, 0xFF00, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0), 121 PCE_MC_M(0x0600, 0xFF00, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0), 122 PCE_MC_M(0x0000, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_HOP, 0), 123 PCE_MC_M(0x2B00, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_NN1, 0), 124 PCE_MC_M(0x3C00, 0xFF00, 36, OUT_IP3, 17, INSTR, FLAG_NN2, 0), 125 PCE_MC_M(0x0000, 0x0000, 43, OUT_PROT, 1, INSTR, FLAG_NO, 0), 126 PCE_MC_M(0x0000, 0x00F0, 38, OUT_NONE, 0, INSTR, FLAG_NO, 0), 127 PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, INSTR, FLAG_NO, 0), 128 PCE_MC_M(0x0000, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_HOP, 0), 129 PCE_MC_M(0x2B00, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_NN1, 0), 130 PCE_MC_M(0x3C00, 0xFF00, 36, OUT_NONE, 0, IPV6, FLAG_NN2, 0), 131 PCE_MC_M(0x0000, 0x00FC, 44, OUT_PROT, 0, IPV6, FLAG_NO, 0), 132 PCE_MC_M(0x0000, 0x0000, 44, OUT_NONE, 0, IPV6, FLAG_NO, 0), 133 PCE_MC_M(0x0000, 0x0000, 44, OUT_SIP0, 16, INSTR, FLAG_NO, 0), 134 PCE_MC_M(0x0000, 0x0000, 45, OUT_APP0, 4, INSTR, FLAG_IGMP, 0), 135 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 136 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 137 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 138 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 139 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 140 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 141 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 142 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 143 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 144 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 145 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 146 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 147 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 148 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 149 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 150 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 151 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 152 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 153 PCE_MC_M(0x0000, 0x0000, 45, OUT_NONE, 0, INSTR, FLAG_END, 0), 154 }; 155