1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Register definitions for MaxLinear GSW1xx series switches 3 * 4 * Copyright (C) 2025 Daniel Golle <daniel@makrotopia.org> 5 * Copyright (C) 2023 - 2024 MaxLinear Inc. 6 */ 7 #ifndef __MXL_GSW1XX_H 8 #define __MXL_GSW1XX_H 9 10 #include <linux/bitfield.h> 11 12 #define GSW1XX_PORTS 6 13 #define GSW150_PORTS 7 14 15 /* Port used for RGMII or optional RMII */ 16 #define GSW1XX_MII_PORT 5 17 /* Port used for SGMII */ 18 #define GSW1XX_SGMII_PORT 4 19 20 #define GSW1XX_SYS_CLK_FREQ 340000000 21 22 /* SMDIO switch register base address */ 23 #define GSW1XX_SMDIO_BADR 0x1f 24 #define GSW1XX_SMDIO_BADR_UNKNOWN -1 25 26 /* GSW1XX SGMII PCS */ 27 #define GSW1XX_SGMII_BASE 0xd000 28 #define GSW1XX_SGMII_PHY_HWBU_CTRL 0x009 29 #define GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM BIT(0) 30 #define GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN BIT(3) 31 #define GSW1XX_SGMII_TBI_TXANEGH 0x300 32 #define GSW1XX_SGMII_TBI_TXANEGL 0x301 33 #define GSW1XX_SGMII_TBI_ANEGCTL 0x304 34 #define GSW1XX_SGMII_TBI_ANEGCTL_LT GENMASK(1, 0) 35 #define GSW1XX_SGMII_TBI_ANEGCTL_LT_10US 0 36 #define GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS 1 37 #define GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS 2 38 #define GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS 3 39 #define GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN BIT(2) 40 #define GSW1XX_SGMII_TBI_ANEGCTL_RANEG BIT(3) 41 #define GSW1XX_SGMII_TBI_ANEGCTL_OVRABL BIT(4) 42 #define GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG BIT(5) 43 #define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE GENMASK(7, 6) 44 #define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX 1 45 #define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_PHY 2 46 #define GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC 3 47 #define GSW1XX_SGMII_TBI_ANEGCTL_BCOMP BIT(15) 48 49 #define GSW1XX_SGMII_TBI_TBICTL 0x305 50 #define GSW1XX_SGMII_TBI_TBICTL_INITTBI BIT(0) 51 #define GSW1XX_SGMII_TBI_TBICTL_ENTBI BIT(1) 52 #define GSW1XX_SGMII_TBI_TBICTL_CRSTRR BIT(4) 53 #define GSW1XX_SGMII_TBI_TBICTL_CRSOFF BIT(5) 54 #define GSW1XX_SGMII_TBI_TBISTAT 0x309 55 #define GSW1XX_SGMII_TBI_TBISTAT_LINK BIT(0) 56 #define GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE BIT(1) 57 #define GSW1XX_SGMII_TBI_LPSTAT 0x30a 58 #define GSW1XX_SGMII_TBI_LPSTAT_DUPLEX BIT(0) 59 #define GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX BIT(1) 60 #define GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX BIT(2) 61 #define GSW1XX_SGMII_TBI_LPSTAT_SPEED GENMASK(6, 5) 62 #define GSW1XX_SGMII_TBI_LPSTAT_SPEED_10 0 63 #define GSW1XX_SGMII_TBI_LPSTAT_SPEED_100 1 64 #define GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000 2 65 #define GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII 3 66 #define GSW1XX_SGMII_PHY_D 0x100 67 #define GSW1XX_SGMII_PHY_A 0x101 68 #define GSW1XX_SGMII_PHY_C 0x102 69 #define GSW1XX_SGMII_PHY_STATUS BIT(0) 70 #define GSW1XX_SGMII_PHY_READ BIT(4) 71 #define GSW1XX_SGMII_PHY_WRITE BIT(8) 72 #define GSW1XX_SGMII_PHY_RESET_N BIT(12) 73 #define GSW1XX_SGMII_PCS_RXB_CTL 0x401 74 #define GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB BIT(1) 75 #define GSW1XX_SGMII_PCS_TXB_CTL 0x404 76 #define GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB BIT(1) 77 78 #define GSW1XX_SGMII_PHY_RX0_CFG2 0x004 79 #define GSW1XX_SGMII_PHY_RX0_CFG2_EQ GENMASK(2, 0) 80 #define GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF 2 81 #define GSW1XX_SGMII_PHY_RX0_CFG2_INVERT BIT(3) 82 #define GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN BIT(4) 83 #define GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN BIT(5) 84 #define GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT GENMASK(12, 6) 85 #define GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF 20 86 87 #define GSW1XX_SGMII_PHY_TX0_CFG3 0x007 88 #define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_EN BIT(12) 89 #define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL GENMASK(11, 9) 90 #define GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF 4 91 #define GSW1XX_SGMII_PHY_TX0_CFG3_INVERT BIT(8) 92 93 /* GSW1XX PDI Registers */ 94 #define GSW1XX_SWITCH_BASE 0xe000 95 96 /* GSW1XX MII Registers */ 97 #define GSW1XX_RGMII_BASE 0xf100 98 99 /* GSW1XX GPIO Registers */ 100 #define GSW1XX_GPIO_BASE 0xf300 101 #define GPIO_ALTSEL0 0x83 102 #define GPIO_ALTSEL0_EXTPHY_MUX_VAL 0x03c3 103 #define GPIO_ALTSEL1 0x84 104 #define GPIO_ALTSEL1_EXTPHY_MUX_VAL 0x003f 105 106 /* MDIO bus controller */ 107 #define GSW1XX_MMDIO_BASE 0xf400 108 109 /* generic IC registers */ 110 #define GSW1XX_SHELL_BASE 0xfa00 111 #define GSW1XX_SHELL_RST_REQ 0x01 112 #define GSW1XX_RST_REQ_SGMII_SHELL BIT(5) 113 #define GSW1XX_SHELL_MANU_ID 0x10 114 #define GSW1XX_SHELL_MANU_ID_PNUML GENMASK(15, 12) 115 #define GSW1XX_SHELL_MANU_ID_MANID GENMASK(11, 1) 116 #define GSW1XX_SHELL_MANU_ID_MANID_VAL 0x389 117 #define GSW1XX_SHELL_MANU_ID_FIX1 BIT(0) 118 #define GSW1XX_SHELL_PNUM_ID 0x11 119 #define GSW1XX_SHELL_PNUM_ID_VER GENMASK(15, 12) 120 #define GSW1XX_SHELL_PNUM_ID_PNUMM GENMASK(11, 0) 121 122 /* RGMII PAD Slew Control Register */ 123 #define GSW1XX_SHELL_RGMII_SLEW_CFG 0x78 124 #define RGMII_SLEW_CFG_DRV_TXC BIT(2) 125 #define RGMII_SLEW_CFG_DRV_TXD BIT(3) 126 #define RGMII_SLEW_CFG_RX_2_5_V BIT(4) 127 #define RGMII_SLEW_CFG_TX_2_5_V BIT(5) 128 129 /* SGMII clock related settings */ 130 #define GSW1XX_CLK_BASE 0xf900 131 #define GSW1XX_CLK_NCO_CTRL 0x68 132 #define GSW1XX_SGMII_HSP_MASK GENMASK(3, 2) 133 #define GSW1XX_SGMII_SEL BIT(1) 134 #define GSW1XX_SGMII_1G 0x0 135 #define GSW1XX_SGMII_2G5 0xc 136 #define GSW1XX_SGMII_1G_NCO1 0x0 137 #define GSW1XX_SGMII_2G5_NCO2 0x2 138 139 #endif /* __MXL_GSW1XX_H */ 140