1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // flexcan.c - FLEXCAN CAN controller driver 4 // 5 // Copyright (c) 2005-2006 Varma Electronics Oy 6 // Copyright (c) 2009 Sascha Hauer, Pengutronix 7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de> 8 // Copyright (c) 2014 David Jander, Protonic Holland 9 // 10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com> 11 12 #include <dt-bindings/firmware/imx/rsrc.h> 13 #include <linux/bitfield.h> 14 #include <linux/can.h> 15 #include <linux/can/dev.h> 16 #include <linux/can/error.h> 17 #include <linux/clk.h> 18 #include <linux/delay.h> 19 #include <linux/firmware/imx/sci.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mfd/syscon.h> 23 #include <linux/module.h> 24 #include <linux/netdevice.h> 25 #include <linux/of.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/platform_device.h> 28 #include <linux/can/platform/flexcan.h> 29 #include <linux/pm_runtime.h> 30 #include <linux/property.h> 31 #include <linux/regmap.h> 32 #include <linux/regulator/consumer.h> 33 34 #include "flexcan.h" 35 36 #define DRV_NAME "flexcan" 37 38 /* 8 for RX fifo and 2 error handling */ 39 #define FLEXCAN_NAPI_WEIGHT (8 + 2) 40 41 /* FLEXCAN module configuration register (CANMCR) bits */ 42 #define FLEXCAN_MCR_MDIS BIT(31) 43 #define FLEXCAN_MCR_FRZ BIT(30) 44 #define FLEXCAN_MCR_FEN BIT(29) 45 #define FLEXCAN_MCR_HALT BIT(28) 46 #define FLEXCAN_MCR_NOT_RDY BIT(27) 47 #define FLEXCAN_MCR_WAK_MSK BIT(26) 48 #define FLEXCAN_MCR_SOFTRST BIT(25) 49 #define FLEXCAN_MCR_FRZ_ACK BIT(24) 50 #define FLEXCAN_MCR_SUPV BIT(23) 51 #define FLEXCAN_MCR_SLF_WAK BIT(22) 52 #define FLEXCAN_MCR_WRN_EN BIT(21) 53 #define FLEXCAN_MCR_LPM_ACK BIT(20) 54 #define FLEXCAN_MCR_WAK_SRC BIT(19) 55 #define FLEXCAN_MCR_DOZE BIT(18) 56 #define FLEXCAN_MCR_SRX_DIS BIT(17) 57 #define FLEXCAN_MCR_IRMQ BIT(16) 58 #define FLEXCAN_MCR_LPRIO_EN BIT(13) 59 #define FLEXCAN_MCR_AEN BIT(12) 60 #define FLEXCAN_MCR_FDEN BIT(11) 61 /* MCR_MAXMB: maximum used MBs is MAXMB + 1 */ 62 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f) 63 #define FLEXCAN_MCR_IDAM_A (0x0 << 8) 64 #define FLEXCAN_MCR_IDAM_B (0x1 << 8) 65 #define FLEXCAN_MCR_IDAM_C (0x2 << 8) 66 #define FLEXCAN_MCR_IDAM_D (0x3 << 8) 67 68 /* FLEXCAN control register (CANCTRL) bits */ 69 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24) 70 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22) 71 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19) 72 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16) 73 #define FLEXCAN_CTRL_BOFF_MSK BIT(15) 74 #define FLEXCAN_CTRL_ERR_MSK BIT(14) 75 #define FLEXCAN_CTRL_CLK_SRC BIT(13) 76 #define FLEXCAN_CTRL_LPB BIT(12) 77 #define FLEXCAN_CTRL_TWRN_MSK BIT(11) 78 #define FLEXCAN_CTRL_RWRN_MSK BIT(10) 79 #define FLEXCAN_CTRL_SMP BIT(7) 80 #define FLEXCAN_CTRL_BOFF_REC BIT(6) 81 #define FLEXCAN_CTRL_TSYN BIT(5) 82 #define FLEXCAN_CTRL_LBUF BIT(4) 83 #define FLEXCAN_CTRL_LOM BIT(3) 84 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07) 85 #define FLEXCAN_CTRL_ERR_BUS (FLEXCAN_CTRL_ERR_MSK) 86 #define FLEXCAN_CTRL_ERR_STATE \ 87 (FLEXCAN_CTRL_TWRN_MSK | FLEXCAN_CTRL_RWRN_MSK | \ 88 FLEXCAN_CTRL_BOFF_MSK) 89 #define FLEXCAN_CTRL_ERR_ALL \ 90 (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE) 91 92 /* FLEXCAN control register 2 (CTRL2) bits */ 93 #define FLEXCAN_CTRL2_ECRWRE BIT(29) 94 #define FLEXCAN_CTRL2_WRMFRZ BIT(28) 95 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24) 96 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19) 97 #define FLEXCAN_CTRL2_MRP BIT(18) 98 #define FLEXCAN_CTRL2_RRS BIT(17) 99 #define FLEXCAN_CTRL2_EACEN BIT(16) 100 #define FLEXCAN_CTRL2_ISOCANFDEN BIT(12) 101 102 /* FLEXCAN memory error control register (MECR) bits */ 103 #define FLEXCAN_MECR_ECRWRDIS BIT(31) 104 #define FLEXCAN_MECR_HANCEI_MSK BIT(19) 105 #define FLEXCAN_MECR_FANCEI_MSK BIT(18) 106 #define FLEXCAN_MECR_CEI_MSK BIT(16) 107 #define FLEXCAN_MECR_HAERRIE BIT(15) 108 #define FLEXCAN_MECR_FAERRIE BIT(14) 109 #define FLEXCAN_MECR_EXTERRIE BIT(13) 110 #define FLEXCAN_MECR_RERRDIS BIT(9) 111 #define FLEXCAN_MECR_ECCDIS BIT(8) 112 #define FLEXCAN_MECR_NCEFAFRZ BIT(7) 113 114 /* FLEXCAN error and status register (ESR) bits */ 115 #define FLEXCAN_ESR_TWRN_INT BIT(17) 116 #define FLEXCAN_ESR_RWRN_INT BIT(16) 117 #define FLEXCAN_ESR_BIT1_ERR BIT(15) 118 #define FLEXCAN_ESR_BIT0_ERR BIT(14) 119 #define FLEXCAN_ESR_ACK_ERR BIT(13) 120 #define FLEXCAN_ESR_CRC_ERR BIT(12) 121 #define FLEXCAN_ESR_FRM_ERR BIT(11) 122 #define FLEXCAN_ESR_STF_ERR BIT(10) 123 #define FLEXCAN_ESR_TX_WRN BIT(9) 124 #define FLEXCAN_ESR_RX_WRN BIT(8) 125 #define FLEXCAN_ESR_IDLE BIT(7) 126 #define FLEXCAN_ESR_TXRX BIT(6) 127 #define FLEXCAN_EST_FLT_CONF_SHIFT (4) 128 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT) 129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT) 130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT) 131 #define FLEXCAN_ESR_BOFF_INT BIT(2) 132 #define FLEXCAN_ESR_ERR_INT BIT(1) 133 #define FLEXCAN_ESR_WAK_INT BIT(0) 134 #define FLEXCAN_ESR_ERR_BUS \ 135 (FLEXCAN_ESR_BIT1_ERR | FLEXCAN_ESR_BIT0_ERR | \ 136 FLEXCAN_ESR_ACK_ERR | FLEXCAN_ESR_CRC_ERR | \ 137 FLEXCAN_ESR_FRM_ERR | FLEXCAN_ESR_STF_ERR) 138 #define FLEXCAN_ESR_ERR_STATE \ 139 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) 140 #define FLEXCAN_ESR_ERR_ALL \ 141 (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) 142 #define FLEXCAN_ESR_ALL_INT \ 143 (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ 144 FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) 145 146 /* FLEXCAN Bit Timing register (CBT) bits */ 147 #define FLEXCAN_CBT_BTF BIT(31) 148 #define FLEXCAN_CBT_EPRESDIV_MASK GENMASK(30, 21) 149 #define FLEXCAN_CBT_ERJW_MASK GENMASK(20, 16) 150 #define FLEXCAN_CBT_EPROPSEG_MASK GENMASK(15, 10) 151 #define FLEXCAN_CBT_EPSEG1_MASK GENMASK(9, 5) 152 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0) 153 154 /* FLEXCAN FD control register (FDCTRL) bits */ 155 #define FLEXCAN_FDCTRL_FDRATE BIT(31) 156 #define FLEXCAN_FDCTRL_MBDSR1 GENMASK(20, 19) 157 #define FLEXCAN_FDCTRL_MBDSR0 GENMASK(17, 16) 158 #define FLEXCAN_FDCTRL_MBDSR_8 0x0 159 #define FLEXCAN_FDCTRL_MBDSR_12 0x1 160 #define FLEXCAN_FDCTRL_MBDSR_32 0x2 161 #define FLEXCAN_FDCTRL_MBDSR_64 0x3 162 #define FLEXCAN_FDCTRL_TDCEN BIT(15) 163 #define FLEXCAN_FDCTRL_TDCFAIL BIT(14) 164 #define FLEXCAN_FDCTRL_TDCOFF GENMASK(12, 8) 165 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0) 166 167 /* FLEXCAN FD Bit Timing register (FDCBT) bits */ 168 #define FLEXCAN_FDCBT_FPRESDIV_MASK GENMASK(29, 20) 169 #define FLEXCAN_FDCBT_FRJW_MASK GENMASK(18, 16) 170 #define FLEXCAN_FDCBT_FPROPSEG_MASK GENMASK(14, 10) 171 #define FLEXCAN_FDCBT_FPSEG1_MASK GENMASK(7, 5) 172 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0) 173 174 /* FLEXCAN interrupt flag register (IFLAG) bits */ 175 /* Errata ERR005829 step7: Reserve first valid MB */ 176 #define FLEXCAN_TX_MB_RESERVED_RX_FIFO 8 177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0 178 #define FLEXCAN_RX_MB_RX_MAILBOX_FIRST (FLEXCAN_TX_MB_RESERVED_RX_MAILBOX + 1) 179 #define FLEXCAN_IFLAG_MB(x) BIT_ULL(x) 180 #define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7) 181 #define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6) 182 #define FLEXCAN_IFLAG_RX_FIFO_AVAILABLE BIT(5) 183 184 /* FLEXCAN message buffers */ 185 #define FLEXCAN_MB_CODE_MASK (0xf << 24) 186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24) 187 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24) 188 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24) 189 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24) 190 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24) 191 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24) 192 193 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24) 194 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24) 195 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24) 196 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24) 197 198 #define FLEXCAN_MB_CNT_EDL BIT(31) 199 #define FLEXCAN_MB_CNT_BRS BIT(30) 200 #define FLEXCAN_MB_CNT_ESI BIT(29) 201 #define FLEXCAN_MB_CNT_SRR BIT(22) 202 #define FLEXCAN_MB_CNT_IDE BIT(21) 203 #define FLEXCAN_MB_CNT_RTR BIT(20) 204 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16) 205 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff) 206 207 #define FLEXCAN_TIMEOUT_US (250) 208 209 /* Structure of the message buffer */ 210 struct flexcan_mb { 211 u32 can_ctrl; 212 u32 can_id; 213 u32 data[]; 214 }; 215 216 /* Structure of the hardware registers */ 217 struct flexcan_regs { 218 u32 mcr; /* 0x00 */ 219 u32 ctrl; /* 0x04 - Not affected by Soft Reset */ 220 u32 timer; /* 0x08 */ 221 u32 tcr; /* 0x0c */ 222 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */ 223 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */ 224 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */ 225 u32 ecr; /* 0x1c */ 226 u32 esr; /* 0x20 */ 227 u32 imask2; /* 0x24 */ 228 u32 imask1; /* 0x28 */ 229 u32 iflag2; /* 0x2c */ 230 u32 iflag1; /* 0x30 */ 231 union { /* 0x34 */ 232 u32 gfwr_mx28; /* MX28, MX53 */ 233 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */ 234 }; 235 u32 esr2; /* 0x38 */ 236 u32 imeur; /* 0x3c */ 237 u32 lrfr; /* 0x40 */ 238 u32 crcr; /* 0x44 */ 239 u32 rxfgmask; /* 0x48 */ 240 u32 rxfir; /* 0x4c - Not affected by Soft Reset */ 241 u32 cbt; /* 0x50 - Not affected by Soft Reset */ 242 u32 _reserved2; /* 0x54 */ 243 u32 dbg1; /* 0x58 */ 244 u32 dbg2; /* 0x5c */ 245 u32 _reserved3[8]; /* 0x60 */ 246 struct_group(init, 247 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */ 248 /* FIFO-mode: 249 * MB 250 * 0x080...0x08f 0 RX message buffer 251 * 0x090...0x0df 1-5 reserved 252 * 0x0e0...0x0ff 6-7 8 entry ID table 253 * (mx25, mx28, mx35, mx53) 254 * 0x0e0...0x2df 6-7..37 8..128 entry ID table 255 * size conf'ed via ctrl2::RFFN 256 * (mx6, vf610) 257 */ 258 u32 _reserved4[256]; /* 0x480 */ 259 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */ 260 u32 _reserved5[24]; /* 0x980 */ 261 u32 gfwr_mx6; /* 0x9e0 - MX6 */ 262 u32 _reserved6[39]; /* 0x9e4 */ 263 u32 _rxfir[6]; /* 0xa80 */ 264 u32 _reserved8[2]; /* 0xa98 */ 265 u32 _rxmgmask; /* 0xaa0 */ 266 u32 _rxfgmask; /* 0xaa4 */ 267 u32 _rx14mask; /* 0xaa8 */ 268 u32 _rx15mask; /* 0xaac */ 269 u32 tx_smb[4]; /* 0xab0 */ 270 u32 rx_smb0[4]; /* 0xac0 */ 271 u32 rx_smb1[4]; /* 0xad0 */ 272 ); 273 u32 mecr; /* 0xae0 */ 274 u32 erriar; /* 0xae4 */ 275 u32 erridpr; /* 0xae8 */ 276 u32 errippr; /* 0xaec */ 277 u32 rerrar; /* 0xaf0 */ 278 u32 rerrdr; /* 0xaf4 */ 279 u32 rerrsynr; /* 0xaf8 */ 280 u32 errsr; /* 0xafc */ 281 u32 _reserved7[64]; /* 0xb00 */ 282 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */ 283 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */ 284 u32 fdcrc; /* 0xc08 */ 285 u32 _reserved9[199]; /* 0xc0c */ 286 struct_group(init_fd, 287 u32 tx_smb_fd[18]; /* 0xf28 */ 288 u32 rx_smb0_fd[18]; /* 0xf70 */ 289 u32 rx_smb1_fd[18]; /* 0xfb8 */ 290 ); 291 }; 292 293 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8); 294 295 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = { 296 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 297 FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 | 298 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 299 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 300 }; 301 302 static const struct flexcan_devtype_data fsl_p1010_devtype_data = { 303 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 304 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 305 FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN | 306 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 307 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 308 }; 309 310 static const struct flexcan_devtype_data fsl_imx25_devtype_data = { 311 .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE | 312 FLEXCAN_QUIRK_BROKEN_PERR_STATE | 313 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 314 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 315 }; 316 317 static const struct flexcan_devtype_data fsl_imx28_devtype_data = { 318 .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE | 319 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 320 FLEXCAN_QUIRK_SUPPORT_RX_FIFO, 321 }; 322 323 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = { 324 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 325 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 326 FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 327 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 328 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 329 }; 330 331 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = { 332 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 333 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 334 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW | 335 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 336 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 337 }; 338 339 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = { 340 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 341 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 342 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 343 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC | 344 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 345 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 346 }; 347 348 static struct flexcan_devtype_data fsl_imx93_devtype_data = { 349 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 350 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 351 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR | 352 FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC | 353 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 354 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 355 }; 356 357 static const struct flexcan_devtype_data fsl_imx95_devtype_data = { 358 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 359 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 360 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_FD | 361 FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 362 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, 363 }; 364 365 static const struct flexcan_devtype_data fsl_vf610_devtype_data = { 366 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 367 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX | 368 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC | 369 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 370 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 371 }; 372 373 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = { 374 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 375 FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX | 376 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 377 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 378 }; 379 380 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = { 381 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 382 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 383 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | 384 FLEXCAN_QUIRK_SUPPORT_ECC | 385 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 386 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR, 387 }; 388 389 static const struct flexcan_devtype_data nxp_s32g2_devtype_data = { 390 .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS | 391 FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE | 392 FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD | 393 FLEXCAN_QUIRK_SUPPORT_ECC | FLEXCAN_QUIRK_NR_IRQ_3 | 394 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 395 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | 396 FLEXCAN_QUIRK_SECONDARY_MB_IRQ, 397 }; 398 399 static const struct can_bittiming_const flexcan_bittiming_const = { 400 .name = DRV_NAME, 401 .tseg1_min = 4, 402 .tseg1_max = 16, 403 .tseg2_min = 2, 404 .tseg2_max = 8, 405 .sjw_max = 4, 406 .brp_min = 1, 407 .brp_max = 256, 408 .brp_inc = 1, 409 }; 410 411 static const struct can_bittiming_const flexcan_fd_bittiming_const = { 412 .name = DRV_NAME, 413 .tseg1_min = 2, 414 .tseg1_max = 96, 415 .tseg2_min = 2, 416 .tseg2_max = 32, 417 .sjw_max = 16, 418 .brp_min = 1, 419 .brp_max = 1024, 420 .brp_inc = 1, 421 }; 422 423 static const struct can_bittiming_const flexcan_fd_data_bittiming_const = { 424 .name = DRV_NAME, 425 .tseg1_min = 2, 426 .tseg1_max = 39, 427 .tseg2_min = 2, 428 .tseg2_max = 8, 429 .sjw_max = 4, 430 .brp_min = 1, 431 .brp_max = 1024, 432 .brp_inc = 1, 433 }; 434 435 /* FlexCAN module is essentially modelled as a little-endian IP in most 436 * SoCs, i.e the registers as well as the message buffer areas are 437 * implemented in a little-endian fashion. 438 * 439 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN 440 * module in a big-endian fashion (i.e the registers as well as the 441 * message buffer areas are implemented in a big-endian way). 442 * 443 * In addition, the FlexCAN module can be found on SoCs having ARM or 444 * PPC cores. So, we need to abstract off the register read/write 445 * functions, ensuring that these cater to all the combinations of module 446 * endianness and underlying CPU endianness. 447 */ 448 static inline u32 flexcan_read_be(void __iomem *addr) 449 { 450 return ioread32be(addr); 451 } 452 453 static inline void flexcan_write_be(u32 val, void __iomem *addr) 454 { 455 iowrite32be(val, addr); 456 } 457 458 static inline u32 flexcan_read_le(void __iomem *addr) 459 { 460 return ioread32(addr); 461 } 462 463 static inline void flexcan_write_le(u32 val, void __iomem *addr) 464 { 465 iowrite32(val, addr); 466 } 467 468 static struct flexcan_mb __iomem *flexcan_get_mb(const struct flexcan_priv *priv, 469 u8 mb_index) 470 { 471 u8 bank_size; 472 bool bank; 473 474 if (WARN_ON(mb_index >= priv->mb_count)) 475 return NULL; 476 477 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; 478 479 bank = mb_index >= bank_size; 480 if (bank) 481 mb_index -= bank_size; 482 483 return (struct flexcan_mb __iomem *) 484 (&priv->regs->mb[bank][priv->mb_size * mb_index]); 485 } 486 487 static int flexcan_low_power_enter_ack(struct flexcan_priv *priv) 488 { 489 struct flexcan_regs __iomem *regs = priv->regs; 490 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 491 492 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 493 udelay(10); 494 495 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 496 return -ETIMEDOUT; 497 498 return 0; 499 } 500 501 static int flexcan_low_power_exit_ack(struct flexcan_priv *priv) 502 { 503 struct flexcan_regs __iomem *regs = priv->regs; 504 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 505 506 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) 507 udelay(10); 508 509 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) 510 return -ETIMEDOUT; 511 512 return 0; 513 } 514 515 static void flexcan_enable_wakeup_irq(struct flexcan_priv *priv, bool enable) 516 { 517 struct flexcan_regs __iomem *regs = priv->regs; 518 u32 reg_mcr; 519 520 reg_mcr = priv->read(®s->mcr); 521 522 if (enable) 523 reg_mcr |= FLEXCAN_MCR_WAK_MSK; 524 else 525 reg_mcr &= ~FLEXCAN_MCR_WAK_MSK; 526 527 priv->write(reg_mcr, ®s->mcr); 528 } 529 530 static int flexcan_stop_mode_enable_scfw(struct flexcan_priv *priv, bool enabled) 531 { 532 u8 idx = priv->scu_idx; 533 u32 rsrc_id, val; 534 535 rsrc_id = IMX_SC_R_CAN(idx); 536 537 if (enabled) 538 val = 1; 539 else 540 val = 0; 541 542 /* stop mode request via scu firmware */ 543 return imx_sc_misc_set_control(priv->sc_ipc_handle, rsrc_id, 544 IMX_SC_C_IPG_STOP, val); 545 } 546 547 static inline int flexcan_enter_stop_mode(struct flexcan_priv *priv) 548 { 549 struct flexcan_regs __iomem *regs = priv->regs; 550 u32 reg_mcr; 551 int ret; 552 553 reg_mcr = priv->read(®s->mcr); 554 reg_mcr |= FLEXCAN_MCR_SLF_WAK; 555 priv->write(reg_mcr, ®s->mcr); 556 557 /* enable stop request */ 558 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 559 ret = flexcan_stop_mode_enable_scfw(priv, true); 560 if (ret < 0) 561 return ret; 562 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) { 563 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 564 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); 565 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) { 566 /* For the SCMI mode, driver do nothing, ATF will send request to 567 * SM(system manager, M33 core) through SCMI protocol after linux 568 * suspend. Once SM get this request, it will send IPG_STOP signal 569 * to Flex_CAN, let CAN in STOP mode. 570 */ 571 return 0; 572 } 573 574 return flexcan_low_power_enter_ack(priv); 575 } 576 577 static inline int flexcan_exit_stop_mode(struct flexcan_priv *priv) 578 { 579 struct flexcan_regs __iomem *regs = priv->regs; 580 u32 reg_mcr; 581 int ret; 582 583 /* Remove stop request, for FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, 584 * do nothing here, because ATF already send request to SM before 585 * linux resume. Once SM get this request, it will deassert the 586 * IPG_STOP signal to Flex_CAN. 587 */ 588 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) { 589 ret = flexcan_stop_mode_enable_scfw(priv, false); 590 if (ret < 0) 591 return ret; 592 } else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) { 593 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, 594 1 << priv->stm.req_bit, 0); 595 } 596 597 reg_mcr = priv->read(®s->mcr); 598 reg_mcr &= ~FLEXCAN_MCR_SLF_WAK; 599 priv->write(reg_mcr, ®s->mcr); 600 601 return flexcan_low_power_exit_ack(priv); 602 } 603 604 static inline void flexcan_error_irq_enable(const struct flexcan_priv *priv) 605 { 606 struct flexcan_regs __iomem *regs = priv->regs; 607 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); 608 609 priv->write(reg_ctrl, ®s->ctrl); 610 } 611 612 static inline void flexcan_error_irq_disable(const struct flexcan_priv *priv) 613 { 614 struct flexcan_regs __iomem *regs = priv->regs; 615 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); 616 617 priv->write(reg_ctrl, ®s->ctrl); 618 } 619 620 static int flexcan_clks_enable(const struct flexcan_priv *priv) 621 { 622 int err = 0; 623 624 if (priv->clk_ipg) { 625 err = clk_prepare_enable(priv->clk_ipg); 626 if (err) 627 return err; 628 } 629 630 if (priv->clk_per) { 631 err = clk_prepare_enable(priv->clk_per); 632 if (err) 633 clk_disable_unprepare(priv->clk_ipg); 634 } 635 636 return err; 637 } 638 639 static void flexcan_clks_disable(const struct flexcan_priv *priv) 640 { 641 clk_disable_unprepare(priv->clk_per); 642 clk_disable_unprepare(priv->clk_ipg); 643 } 644 645 static inline int flexcan_transceiver_enable(const struct flexcan_priv *priv) 646 { 647 if (!priv->reg_xceiver) 648 return 0; 649 650 return regulator_enable(priv->reg_xceiver); 651 } 652 653 static inline int flexcan_transceiver_disable(const struct flexcan_priv *priv) 654 { 655 if (!priv->reg_xceiver) 656 return 0; 657 658 return regulator_disable(priv->reg_xceiver); 659 } 660 661 static int flexcan_chip_enable(struct flexcan_priv *priv) 662 { 663 struct flexcan_regs __iomem *regs = priv->regs; 664 u32 reg; 665 666 reg = priv->read(®s->mcr); 667 reg &= ~FLEXCAN_MCR_MDIS; 668 priv->write(reg, ®s->mcr); 669 670 return flexcan_low_power_exit_ack(priv); 671 } 672 673 static int flexcan_chip_disable(struct flexcan_priv *priv) 674 { 675 struct flexcan_regs __iomem *regs = priv->regs; 676 u32 reg; 677 678 reg = priv->read(®s->mcr); 679 reg |= FLEXCAN_MCR_MDIS; 680 priv->write(reg, ®s->mcr); 681 682 return flexcan_low_power_enter_ack(priv); 683 } 684 685 static int flexcan_chip_freeze(struct flexcan_priv *priv) 686 { 687 struct flexcan_regs __iomem *regs = priv->regs; 688 unsigned int timeout; 689 u32 bitrate = priv->can.bittiming.bitrate; 690 u32 reg; 691 692 if (bitrate) 693 timeout = 1000 * 1000 * 10 / bitrate; 694 else 695 timeout = FLEXCAN_TIMEOUT_US / 10; 696 697 reg = priv->read(®s->mcr); 698 reg |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_HALT; 699 priv->write(reg, ®s->mcr); 700 701 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 702 udelay(100); 703 704 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 705 return -ETIMEDOUT; 706 707 return 0; 708 } 709 710 static int flexcan_chip_unfreeze(struct flexcan_priv *priv) 711 { 712 struct flexcan_regs __iomem *regs = priv->regs; 713 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 714 u32 reg; 715 716 reg = priv->read(®s->mcr); 717 reg &= ~FLEXCAN_MCR_HALT; 718 priv->write(reg, ®s->mcr); 719 720 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) 721 udelay(10); 722 723 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) 724 return -ETIMEDOUT; 725 726 return 0; 727 } 728 729 static int flexcan_chip_softreset(struct flexcan_priv *priv) 730 { 731 struct flexcan_regs __iomem *regs = priv->regs; 732 unsigned int timeout = FLEXCAN_TIMEOUT_US / 10; 733 734 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); 735 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) 736 udelay(10); 737 738 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) 739 return -ETIMEDOUT; 740 741 return 0; 742 } 743 744 static int __flexcan_get_berr_counter(const struct net_device *dev, 745 struct can_berr_counter *bec) 746 { 747 const struct flexcan_priv *priv = netdev_priv(dev); 748 struct flexcan_regs __iomem *regs = priv->regs; 749 u32 reg = priv->read(®s->ecr); 750 751 bec->txerr = (reg >> 0) & 0xff; 752 bec->rxerr = (reg >> 8) & 0xff; 753 754 return 0; 755 } 756 757 static int flexcan_get_berr_counter(const struct net_device *dev, 758 struct can_berr_counter *bec) 759 { 760 const struct flexcan_priv *priv = netdev_priv(dev); 761 int err; 762 763 err = pm_runtime_resume_and_get(priv->dev); 764 if (err < 0) 765 return err; 766 767 err = __flexcan_get_berr_counter(dev, bec); 768 769 pm_runtime_put(priv->dev); 770 771 return err; 772 } 773 774 static netdev_tx_t flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev) 775 { 776 const struct flexcan_priv *priv = netdev_priv(dev); 777 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; 778 u32 can_id; 779 u32 data; 780 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_fd_len2dlc(cfd->len)) << 16); 781 int i; 782 783 if (can_dev_dropped_skb(dev, skb)) 784 return NETDEV_TX_OK; 785 786 netif_stop_queue(dev); 787 788 if (cfd->can_id & CAN_EFF_FLAG) { 789 can_id = cfd->can_id & CAN_EFF_MASK; 790 ctrl |= FLEXCAN_MB_CNT_IDE | FLEXCAN_MB_CNT_SRR; 791 } else { 792 can_id = (cfd->can_id & CAN_SFF_MASK) << 18; 793 } 794 795 if (cfd->can_id & CAN_RTR_FLAG) 796 ctrl |= FLEXCAN_MB_CNT_RTR; 797 798 if (can_is_canfd_skb(skb)) { 799 ctrl |= FLEXCAN_MB_CNT_EDL; 800 801 if (cfd->flags & CANFD_BRS) 802 ctrl |= FLEXCAN_MB_CNT_BRS; 803 } 804 805 for (i = 0; i < cfd->len; i += sizeof(u32)) { 806 data = be32_to_cpup((__be32 *)&cfd->data[i]); 807 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); 808 } 809 810 can_put_echo_skb(skb, dev, 0, 0); 811 812 priv->write(can_id, &priv->tx_mb->can_id); 813 priv->write(ctrl, &priv->tx_mb->can_ctrl); 814 815 /* Errata ERR005829 step8: 816 * Write twice INACTIVE(0x8) code to first MB. 817 */ 818 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 819 &priv->tx_mb_reserved->can_ctrl); 820 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 821 &priv->tx_mb_reserved->can_ctrl); 822 823 return NETDEV_TX_OK; 824 } 825 826 static void flexcan_irq_bus_err(struct net_device *dev, u32 reg_esr) 827 { 828 struct flexcan_priv *priv = netdev_priv(dev); 829 struct flexcan_regs __iomem *regs = priv->regs; 830 struct sk_buff *skb; 831 struct can_frame *cf; 832 bool rx_errors = false, tx_errors = false; 833 u32 timestamp; 834 int err; 835 836 timestamp = priv->read(®s->timer) << 16; 837 838 skb = alloc_can_err_skb(dev, &cf); 839 if (unlikely(!skb)) 840 return; 841 842 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 843 844 if (reg_esr & FLEXCAN_ESR_BIT1_ERR) { 845 netdev_dbg(dev, "BIT1_ERR irq\n"); 846 cf->data[2] |= CAN_ERR_PROT_BIT1; 847 tx_errors = true; 848 } 849 if (reg_esr & FLEXCAN_ESR_BIT0_ERR) { 850 netdev_dbg(dev, "BIT0_ERR irq\n"); 851 cf->data[2] |= CAN_ERR_PROT_BIT0; 852 tx_errors = true; 853 } 854 if (reg_esr & FLEXCAN_ESR_ACK_ERR) { 855 netdev_dbg(dev, "ACK_ERR irq\n"); 856 cf->can_id |= CAN_ERR_ACK; 857 cf->data[3] = CAN_ERR_PROT_LOC_ACK; 858 tx_errors = true; 859 } 860 if (reg_esr & FLEXCAN_ESR_CRC_ERR) { 861 netdev_dbg(dev, "CRC_ERR irq\n"); 862 cf->data[2] |= CAN_ERR_PROT_BIT; 863 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; 864 rx_errors = true; 865 } 866 if (reg_esr & FLEXCAN_ESR_FRM_ERR) { 867 netdev_dbg(dev, "FRM_ERR irq\n"); 868 cf->data[2] |= CAN_ERR_PROT_FORM; 869 rx_errors = true; 870 } 871 if (reg_esr & FLEXCAN_ESR_STF_ERR) { 872 netdev_dbg(dev, "STF_ERR irq\n"); 873 cf->data[2] |= CAN_ERR_PROT_STUFF; 874 rx_errors = true; 875 } 876 877 priv->can.can_stats.bus_error++; 878 if (rx_errors) 879 dev->stats.rx_errors++; 880 if (tx_errors) 881 dev->stats.tx_errors++; 882 883 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 884 if (err) 885 dev->stats.rx_fifo_errors++; 886 } 887 888 static void flexcan_irq_state(struct net_device *dev, u32 reg_esr) 889 { 890 struct flexcan_priv *priv = netdev_priv(dev); 891 struct flexcan_regs __iomem *regs = priv->regs; 892 struct sk_buff *skb; 893 struct can_frame *cf; 894 enum can_state new_state, rx_state, tx_state; 895 int flt; 896 struct can_berr_counter bec; 897 u32 timestamp; 898 int err; 899 900 flt = reg_esr & FLEXCAN_ESR_FLT_CONF_MASK; 901 if (likely(flt == FLEXCAN_ESR_FLT_CONF_ACTIVE)) { 902 tx_state = unlikely(reg_esr & FLEXCAN_ESR_TX_WRN) ? 903 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 904 rx_state = unlikely(reg_esr & FLEXCAN_ESR_RX_WRN) ? 905 CAN_STATE_ERROR_WARNING : CAN_STATE_ERROR_ACTIVE; 906 new_state = max(tx_state, rx_state); 907 } else { 908 __flexcan_get_berr_counter(dev, &bec); 909 new_state = flt == FLEXCAN_ESR_FLT_CONF_PASSIVE ? 910 CAN_STATE_ERROR_PASSIVE : CAN_STATE_BUS_OFF; 911 rx_state = bec.rxerr >= bec.txerr ? new_state : 0; 912 tx_state = bec.rxerr <= bec.txerr ? new_state : 0; 913 } 914 915 /* state hasn't changed */ 916 if (likely(new_state == priv->can.state)) 917 return; 918 919 timestamp = priv->read(®s->timer) << 16; 920 921 skb = alloc_can_err_skb(dev, &cf); 922 if (unlikely(!skb)) 923 return; 924 925 can_change_state(dev, cf, tx_state, rx_state); 926 927 if (unlikely(new_state == CAN_STATE_BUS_OFF)) 928 can_bus_off(dev); 929 930 err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp); 931 if (err) 932 dev->stats.rx_fifo_errors++; 933 } 934 935 static inline u64 flexcan_read64_mask(struct flexcan_priv *priv, void __iomem *addr, u64 mask) 936 { 937 u64 reg = 0; 938 939 if (upper_32_bits(mask)) 940 reg = (u64)priv->read(addr - 4) << 32; 941 if (lower_32_bits(mask)) 942 reg |= priv->read(addr); 943 944 return reg & mask; 945 } 946 947 static inline void flexcan_write64(struct flexcan_priv *priv, u64 val, void __iomem *addr) 948 { 949 if (upper_32_bits(val)) 950 priv->write(upper_32_bits(val), addr - 4); 951 if (lower_32_bits(val)) 952 priv->write(lower_32_bits(val), addr); 953 } 954 955 static inline u64 flexcan_read_reg_iflag_rx(struct flexcan_priv *priv) 956 { 957 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask); 958 } 959 960 static inline u64 flexcan_read_reg_iflag_tx(struct flexcan_priv *priv) 961 { 962 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); 963 } 964 965 static inline struct flexcan_priv *rx_offload_to_priv(struct can_rx_offload *offload) 966 { 967 return container_of(offload, struct flexcan_priv, offload); 968 } 969 970 static struct sk_buff *flexcan_mailbox_read(struct can_rx_offload *offload, 971 unsigned int n, u32 *timestamp, 972 bool drop) 973 { 974 struct flexcan_priv *priv = rx_offload_to_priv(offload); 975 struct flexcan_regs __iomem *regs = priv->regs; 976 struct flexcan_mb __iomem *mb; 977 struct sk_buff *skb; 978 struct canfd_frame *cfd; 979 u32 reg_ctrl, reg_id, reg_iflag1; 980 int i; 981 982 mb = flexcan_get_mb(priv, n); 983 984 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 985 u32 code; 986 987 do { 988 reg_ctrl = priv->read(&mb->can_ctrl); 989 } while (reg_ctrl & FLEXCAN_MB_CODE_RX_BUSY_BIT); 990 991 /* is this MB empty? */ 992 code = reg_ctrl & FLEXCAN_MB_CODE_MASK; 993 if ((code != FLEXCAN_MB_CODE_RX_FULL) && 994 (code != FLEXCAN_MB_CODE_RX_OVERRUN)) 995 return NULL; 996 997 if (code == FLEXCAN_MB_CODE_RX_OVERRUN) { 998 /* This MB was overrun, we lost data */ 999 offload->dev->stats.rx_over_errors++; 1000 offload->dev->stats.rx_errors++; 1001 } 1002 } else { 1003 reg_iflag1 = priv->read(®s->iflag1); 1004 if (!(reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE)) 1005 return NULL; 1006 1007 reg_ctrl = priv->read(&mb->can_ctrl); 1008 } 1009 1010 if (unlikely(drop)) { 1011 skb = ERR_PTR(-ENOBUFS); 1012 goto mark_as_read; 1013 } 1014 1015 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) 1016 skb = alloc_canfd_skb(offload->dev, &cfd); 1017 else 1018 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd); 1019 if (unlikely(!skb)) { 1020 skb = ERR_PTR(-ENOMEM); 1021 goto mark_as_read; 1022 } 1023 1024 /* increase timstamp to full 32 bit */ 1025 *timestamp = reg_ctrl << 16; 1026 1027 reg_id = priv->read(&mb->can_id); 1028 if (reg_ctrl & FLEXCAN_MB_CNT_IDE) 1029 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 1030 else 1031 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK; 1032 1033 if (reg_ctrl & FLEXCAN_MB_CNT_EDL) { 1034 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf); 1035 1036 if (reg_ctrl & FLEXCAN_MB_CNT_BRS) 1037 cfd->flags |= CANFD_BRS; 1038 } else { 1039 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf); 1040 1041 if (reg_ctrl & FLEXCAN_MB_CNT_RTR) 1042 cfd->can_id |= CAN_RTR_FLAG; 1043 } 1044 1045 if (reg_ctrl & FLEXCAN_MB_CNT_ESI) 1046 cfd->flags |= CANFD_ESI; 1047 1048 for (i = 0; i < cfd->len; i += sizeof(u32)) { 1049 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); 1050 *(__be32 *)(cfd->data + i) = data; 1051 } 1052 1053 mark_as_read: 1054 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1055 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1); 1056 else 1057 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); 1058 1059 /* Read the Free Running Timer. It is optional but recommended 1060 * to unlock Mailbox as soon as possible and make it available 1061 * for reception. 1062 */ 1063 priv->read(®s->timer); 1064 1065 return skb; 1066 } 1067 1068 static irqreturn_t flexcan_irq(int irq, void *dev_id) 1069 { 1070 struct net_device *dev = dev_id; 1071 struct net_device_stats *stats = &dev->stats; 1072 struct flexcan_priv *priv = netdev_priv(dev); 1073 struct flexcan_regs __iomem *regs = priv->regs; 1074 irqreturn_t handled = IRQ_NONE; 1075 u64 reg_iflag_tx; 1076 u32 reg_esr; 1077 enum can_state last_state = priv->can.state; 1078 1079 /* reception interrupt */ 1080 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1081 u64 reg_iflag_rx; 1082 int ret; 1083 1084 while ((reg_iflag_rx = flexcan_read_reg_iflag_rx(priv))) { 1085 handled = IRQ_HANDLED; 1086 ret = can_rx_offload_irq_offload_timestamp(&priv->offload, 1087 reg_iflag_rx); 1088 if (!ret) 1089 break; 1090 } 1091 } else { 1092 u32 reg_iflag1; 1093 1094 reg_iflag1 = priv->read(®s->iflag1); 1095 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_AVAILABLE) { 1096 handled = IRQ_HANDLED; 1097 can_rx_offload_irq_offload_fifo(&priv->offload); 1098 } 1099 1100 /* FIFO overflow interrupt */ 1101 if (reg_iflag1 & FLEXCAN_IFLAG_RX_FIFO_OVERFLOW) { 1102 handled = IRQ_HANDLED; 1103 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, 1104 ®s->iflag1); 1105 dev->stats.rx_over_errors++; 1106 dev->stats.rx_errors++; 1107 } 1108 } 1109 1110 reg_iflag_tx = flexcan_read_reg_iflag_tx(priv); 1111 1112 /* transmission complete interrupt */ 1113 if (reg_iflag_tx & priv->tx_mask) { 1114 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); 1115 1116 handled = IRQ_HANDLED; 1117 stats->tx_bytes += 1118 can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0, 1119 reg_ctrl << 16, NULL); 1120 stats->tx_packets++; 1121 1122 /* after sending a RTR frame MB is in RX mode */ 1123 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1124 &priv->tx_mb->can_ctrl); 1125 flexcan_write64(priv, priv->tx_mask, ®s->iflag1); 1126 netif_wake_queue(dev); 1127 } 1128 1129 reg_esr = priv->read(®s->esr); 1130 1131 /* ACK all bus error, state change and wake IRQ sources */ 1132 if (reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT)) { 1133 handled = IRQ_HANDLED; 1134 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr); 1135 } 1136 1137 /* state change interrupt or broken error state quirk fix is enabled */ 1138 if ((reg_esr & FLEXCAN_ESR_ERR_STATE) || 1139 (priv->devtype_data.quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | 1140 FLEXCAN_QUIRK_BROKEN_PERR_STATE))) 1141 flexcan_irq_state(dev, reg_esr); 1142 1143 /* bus error IRQ - handle if bus error reporting is activated */ 1144 if ((reg_esr & FLEXCAN_ESR_ERR_BUS) && 1145 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) 1146 flexcan_irq_bus_err(dev, reg_esr); 1147 1148 /* availability of error interrupt among state transitions in case 1149 * bus error reporting is de-activated and 1150 * FLEXCAN_QUIRK_BROKEN_PERR_STATE is enabled: 1151 * +--------------------------------------------------------------+ 1152 * | +----------------------------------------------+ [stopped / | 1153 * | | | sleeping] -+ 1154 * +-+-> active <-> warning <-> passive -> bus off -+ 1155 * ___________^^^^^^^^^^^^_______________________________ 1156 * disabled(1) enabled disabled 1157 * 1158 * (1): enabled if FLEXCAN_QUIRK_BROKEN_WERR_STATE is enabled 1159 */ 1160 if ((last_state != priv->can.state) && 1161 (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && 1162 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { 1163 switch (priv->can.state) { 1164 case CAN_STATE_ERROR_ACTIVE: 1165 if (priv->devtype_data.quirks & 1166 FLEXCAN_QUIRK_BROKEN_WERR_STATE) 1167 flexcan_error_irq_enable(priv); 1168 else 1169 flexcan_error_irq_disable(priv); 1170 break; 1171 1172 case CAN_STATE_ERROR_WARNING: 1173 flexcan_error_irq_enable(priv); 1174 break; 1175 1176 case CAN_STATE_ERROR_PASSIVE: 1177 case CAN_STATE_BUS_OFF: 1178 flexcan_error_irq_disable(priv); 1179 break; 1180 1181 default: 1182 break; 1183 } 1184 } 1185 1186 if (handled) 1187 can_rx_offload_irq_finish(&priv->offload); 1188 1189 return handled; 1190 } 1191 1192 static void flexcan_set_bittiming_ctrl(const struct net_device *dev) 1193 { 1194 const struct flexcan_priv *priv = netdev_priv(dev); 1195 const struct can_bittiming *bt = &priv->can.bittiming; 1196 struct flexcan_regs __iomem *regs = priv->regs; 1197 u32 reg; 1198 1199 reg = priv->read(®s->ctrl); 1200 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | 1201 FLEXCAN_CTRL_RJW(0x3) | 1202 FLEXCAN_CTRL_PSEG1(0x7) | 1203 FLEXCAN_CTRL_PSEG2(0x7) | 1204 FLEXCAN_CTRL_PROPSEG(0x7)); 1205 1206 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | 1207 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | 1208 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | 1209 FLEXCAN_CTRL_RJW(bt->sjw - 1) | 1210 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); 1211 1212 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1213 priv->write(reg, ®s->ctrl); 1214 1215 /* print chip status */ 1216 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, 1217 priv->read(®s->mcr), priv->read(®s->ctrl)); 1218 } 1219 1220 static void flexcan_set_bittiming_cbt(const struct net_device *dev) 1221 { 1222 struct flexcan_priv *priv = netdev_priv(dev); 1223 struct can_bittiming *bt = &priv->can.bittiming; 1224 struct can_bittiming *dbt = &priv->can.data_bittiming; 1225 struct flexcan_regs __iomem *regs = priv->regs; 1226 u32 reg_cbt, reg_fdctrl; 1227 1228 /* CBT */ 1229 /* CBT[EPSEG1] is 5 bit long and CBT[EPROPSEG] is 6 bit 1230 * long. The can_calc_bittiming() tries to divide the tseg1 1231 * equally between phase_seg1 and prop_seg, which may not fit 1232 * in CBT register. Therefore, if phase_seg1 is more than 1233 * possible value, increase prop_seg and decrease phase_seg1. 1234 */ 1235 if (bt->phase_seg1 > 0x20) { 1236 bt->prop_seg += (bt->phase_seg1 - 0x20); 1237 bt->phase_seg1 = 0x20; 1238 } 1239 1240 reg_cbt = FLEXCAN_CBT_BTF | 1241 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) | 1242 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) | 1243 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) | 1244 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) | 1245 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1); 1246 1247 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt); 1248 priv->write(reg_cbt, ®s->cbt); 1249 1250 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1251 u32 reg_fdcbt, reg_ctrl2; 1252 1253 if (bt->brp != dbt->brp) 1254 netdev_warn(dev, "Data brp=%d and brp=%d don't match, this may result in a phase error. Consider using different bitrate and/or data bitrate.\n", 1255 dbt->brp, bt->brp); 1256 1257 /* FDCBT */ 1258 /* FDCBT[FPSEG1] is 3 bit long and FDCBT[FPROPSEG] is 1259 * 5 bit long. The can_calc_bittiming tries to divide 1260 * the tseg1 equally between phase_seg1 and prop_seg, 1261 * which may not fit in FDCBT register. Therefore, if 1262 * phase_seg1 is more than possible value, increase 1263 * prop_seg and decrease phase_seg1 1264 */ 1265 if (dbt->phase_seg1 > 0x8) { 1266 dbt->prop_seg += (dbt->phase_seg1 - 0x8); 1267 dbt->phase_seg1 = 0x8; 1268 } 1269 1270 reg_fdcbt = priv->read(®s->fdcbt); 1271 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) | 1272 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) | 1273 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) | 1274 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) | 1275 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7)); 1276 1277 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) | 1278 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) | 1279 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) | 1280 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) | 1281 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1); 1282 1283 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt); 1284 priv->write(reg_fdcbt, ®s->fdcbt); 1285 1286 /* CTRL2 */ 1287 reg_ctrl2 = priv->read(®s->ctrl2); 1288 reg_ctrl2 &= ~FLEXCAN_CTRL2_ISOCANFDEN; 1289 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) 1290 reg_ctrl2 |= FLEXCAN_CTRL2_ISOCANFDEN; 1291 1292 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); 1293 priv->write(reg_ctrl2, ®s->ctrl2); 1294 } 1295 1296 /* FDCTRL */ 1297 reg_fdctrl = priv->read(®s->fdctrl); 1298 reg_fdctrl &= ~(FLEXCAN_FDCTRL_FDRATE | 1299 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f)); 1300 1301 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1302 reg_fdctrl |= FLEXCAN_FDCTRL_FDRATE; 1303 1304 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { 1305 /* TDC must be disabled for Loop Back mode */ 1306 reg_fdctrl &= ~FLEXCAN_FDCTRL_TDCEN; 1307 } else { 1308 reg_fdctrl |= FLEXCAN_FDCTRL_TDCEN | 1309 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 1310 ((dbt->phase_seg1 - 1) + 1311 dbt->prop_seg + 2) * 1312 ((dbt->brp - 1 ) + 1)); 1313 } 1314 } 1315 1316 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl); 1317 priv->write(reg_fdctrl, ®s->fdctrl); 1318 1319 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n", 1320 __func__, 1321 priv->read(®s->mcr), priv->read(®s->ctrl), 1322 priv->read(®s->ctrl2), priv->read(®s->fdctrl), 1323 priv->read(®s->cbt), priv->read(®s->fdcbt)); 1324 } 1325 1326 static void flexcan_set_bittiming(struct net_device *dev) 1327 { 1328 const struct flexcan_priv *priv = netdev_priv(dev); 1329 struct flexcan_regs __iomem *regs = priv->regs; 1330 u32 reg; 1331 1332 reg = priv->read(®s->ctrl); 1333 reg &= ~(FLEXCAN_CTRL_LPB | FLEXCAN_CTRL_SMP | 1334 FLEXCAN_CTRL_LOM); 1335 1336 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1337 reg |= FLEXCAN_CTRL_LPB; 1338 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) 1339 reg |= FLEXCAN_CTRL_LOM; 1340 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) 1341 reg |= FLEXCAN_CTRL_SMP; 1342 1343 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); 1344 priv->write(reg, ®s->ctrl); 1345 1346 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) 1347 return flexcan_set_bittiming_cbt(dev); 1348 else 1349 return flexcan_set_bittiming_ctrl(dev); 1350 } 1351 1352 static void flexcan_ram_init(struct net_device *dev) 1353 { 1354 struct flexcan_priv *priv = netdev_priv(dev); 1355 struct flexcan_regs __iomem *regs = priv->regs; 1356 u32 reg_ctrl2; 1357 1358 /* 11.8.3.13 Detection and correction of memory errors: 1359 * CTRL2[WRMFRZ] grants write access to all memory positions 1360 * that require initialization, ranging from 0x080 to 0xADF 1361 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled. 1362 * The RXMGMASK, RX14MASK, RX15MASK, and RXFGMASK registers 1363 * need to be initialized as well. MCR[RFEN] must not be set 1364 * during memory initialization. 1365 */ 1366 reg_ctrl2 = priv->read(®s->ctrl2); 1367 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ; 1368 priv->write(reg_ctrl2, ®s->ctrl2); 1369 1370 memset_io(®s->init, 0, sizeof(regs->init)); 1371 1372 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1373 memset_io(®s->init_fd, 0, sizeof(regs->init_fd)); 1374 1375 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ; 1376 priv->write(reg_ctrl2, ®s->ctrl2); 1377 } 1378 1379 static int flexcan_rx_offload_setup(struct net_device *dev) 1380 { 1381 struct flexcan_priv *priv = netdev_priv(dev); 1382 int err; 1383 1384 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1385 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN; 1386 else 1387 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; 1388 1389 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_MB_16) 1390 priv->mb_count = 16; 1391 else 1392 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + 1393 (sizeof(priv->regs->mb[1]) / priv->mb_size); 1394 1395 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1396 priv->tx_mb_reserved = 1397 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_MAILBOX); 1398 else 1399 priv->tx_mb_reserved = 1400 flexcan_get_mb(priv, FLEXCAN_TX_MB_RESERVED_RX_FIFO); 1401 priv->tx_mb_idx = priv->mb_count - 1; 1402 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); 1403 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); 1404 1405 priv->offload.mailbox_read = flexcan_mailbox_read; 1406 1407 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1408 priv->offload.mb_first = FLEXCAN_RX_MB_RX_MAILBOX_FIRST; 1409 priv->offload.mb_last = priv->mb_count - 2; 1410 1411 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, 1412 priv->offload.mb_first); 1413 err = can_rx_offload_add_timestamp(dev, &priv->offload); 1414 } else { 1415 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | 1416 FLEXCAN_IFLAG_RX_FIFO_AVAILABLE; 1417 err = can_rx_offload_add_fifo(dev, &priv->offload, 1418 FLEXCAN_NAPI_WEIGHT); 1419 } 1420 1421 return err; 1422 } 1423 1424 static void flexcan_chip_interrupts_enable(const struct net_device *dev) 1425 { 1426 const struct flexcan_priv *priv = netdev_priv(dev); 1427 struct flexcan_regs __iomem *regs = priv->regs; 1428 u64 reg_imask; 1429 1430 disable_irq(dev->irq); 1431 priv->write(priv->reg_ctrl_default, ®s->ctrl); 1432 reg_imask = priv->rx_mask | priv->tx_mask; 1433 priv->write(upper_32_bits(reg_imask), ®s->imask2); 1434 priv->write(lower_32_bits(reg_imask), ®s->imask1); 1435 enable_irq(dev->irq); 1436 } 1437 1438 static void flexcan_chip_interrupts_disable(const struct net_device *dev) 1439 { 1440 const struct flexcan_priv *priv = netdev_priv(dev); 1441 struct flexcan_regs __iomem *regs = priv->regs; 1442 1443 priv->write(0, ®s->imask2); 1444 priv->write(0, ®s->imask1); 1445 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, 1446 ®s->ctrl); 1447 } 1448 1449 /* flexcan_chip_start 1450 * 1451 * this functions is entered with clocks enabled 1452 * 1453 */ 1454 static int flexcan_chip_start(struct net_device *dev) 1455 { 1456 struct flexcan_priv *priv = netdev_priv(dev); 1457 struct flexcan_regs __iomem *regs = priv->regs; 1458 u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr; 1459 int err, i; 1460 struct flexcan_mb __iomem *mb; 1461 1462 /* enable module */ 1463 err = flexcan_chip_enable(priv); 1464 if (err) 1465 return err; 1466 1467 /* soft reset */ 1468 err = flexcan_chip_softreset(priv); 1469 if (err) 1470 goto out_chip_disable; 1471 1472 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_ECC) 1473 flexcan_ram_init(dev); 1474 1475 flexcan_set_bittiming(dev); 1476 1477 /* set freeze, halt */ 1478 err = flexcan_chip_freeze(priv); 1479 if (err) 1480 goto out_chip_disable; 1481 1482 /* MCR 1483 * 1484 * only supervisor access 1485 * enable warning int 1486 * enable individual RX masking 1487 * choose format C 1488 * set max mailbox number 1489 */ 1490 reg_mcr = priv->read(®s->mcr); 1491 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); 1492 reg_mcr |= FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN | FLEXCAN_MCR_IRMQ | 1493 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); 1494 1495 /* MCR 1496 * 1497 * FIFO: 1498 * - disable for mailbox mode 1499 * - enable for FIFO mode 1500 */ 1501 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) 1502 reg_mcr &= ~FLEXCAN_MCR_FEN; 1503 else 1504 reg_mcr |= FLEXCAN_MCR_FEN; 1505 1506 /* MCR 1507 * 1508 * NOTE: In loopback mode, the CAN_MCR[SRXDIS] cannot be 1509 * asserted because this will impede the self reception 1510 * of a transmitted message. This is not documented in 1511 * earlier versions of flexcan block guide. 1512 * 1513 * Self Reception: 1514 * - enable Self Reception for loopback mode 1515 * (by clearing "Self Reception Disable" bit) 1516 * - disable for normal operation 1517 */ 1518 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) 1519 reg_mcr &= ~FLEXCAN_MCR_SRX_DIS; 1520 else 1521 reg_mcr |= FLEXCAN_MCR_SRX_DIS; 1522 1523 /* MCR - CAN-FD */ 1524 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) 1525 reg_mcr |= FLEXCAN_MCR_FDEN; 1526 else 1527 reg_mcr &= ~FLEXCAN_MCR_FDEN; 1528 1529 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); 1530 priv->write(reg_mcr, ®s->mcr); 1531 1532 /* CTRL 1533 * 1534 * disable timer sync feature 1535 * 1536 * disable auto busoff recovery 1537 * transmit lowest buffer first 1538 * 1539 * enable tx and rx warning interrupt 1540 * enable bus off interrupt 1541 * (== FLEXCAN_CTRL_ERR_STATE) 1542 */ 1543 reg_ctrl = priv->read(®s->ctrl); 1544 reg_ctrl &= ~FLEXCAN_CTRL_TSYN; 1545 reg_ctrl |= FLEXCAN_CTRL_BOFF_REC | FLEXCAN_CTRL_LBUF | 1546 FLEXCAN_CTRL_ERR_STATE; 1547 1548 /* enable the "error interrupt" (FLEXCAN_CTRL_ERR_MSK), 1549 * on most Flexcan cores, too. Otherwise we don't get 1550 * any error warning or passive interrupts. 1551 */ 1552 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || 1553 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) 1554 reg_ctrl |= FLEXCAN_CTRL_ERR_MSK; 1555 else 1556 reg_ctrl &= ~FLEXCAN_CTRL_ERR_MSK; 1557 1558 /* save for later use */ 1559 priv->reg_ctrl_default = reg_ctrl; 1560 /* leave interrupts disabled for now */ 1561 reg_ctrl &= ~FLEXCAN_CTRL_ERR_ALL; 1562 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); 1563 priv->write(reg_ctrl, ®s->ctrl); 1564 1565 if ((priv->devtype_data.quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { 1566 reg_ctrl2 = priv->read(®s->ctrl2); 1567 reg_ctrl2 |= FLEXCAN_CTRL2_EACEN | FLEXCAN_CTRL2_RRS; 1568 priv->write(reg_ctrl2, ®s->ctrl2); 1569 } 1570 1571 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) { 1572 u32 reg_fdctrl; 1573 1574 reg_fdctrl = priv->read(®s->fdctrl); 1575 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) | 1576 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3)); 1577 1578 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { 1579 reg_fdctrl |= 1580 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1581 FLEXCAN_FDCTRL_MBDSR_64) | 1582 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1583 FLEXCAN_FDCTRL_MBDSR_64); 1584 } else { 1585 reg_fdctrl |= 1586 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 1587 FLEXCAN_FDCTRL_MBDSR_8) | 1588 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 1589 FLEXCAN_FDCTRL_MBDSR_8); 1590 } 1591 1592 netdev_dbg(dev, "%s: writing fdctrl=0x%08x", 1593 __func__, reg_fdctrl); 1594 priv->write(reg_fdctrl, ®s->fdctrl); 1595 } 1596 1597 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX) { 1598 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { 1599 mb = flexcan_get_mb(priv, i); 1600 priv->write(FLEXCAN_MB_CODE_RX_EMPTY, 1601 &mb->can_ctrl); 1602 } 1603 } else { 1604 /* clear and invalidate unused mailboxes first */ 1605 for (i = FLEXCAN_TX_MB_RESERVED_RX_FIFO; i < priv->mb_count; i++) { 1606 mb = flexcan_get_mb(priv, i); 1607 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, 1608 &mb->can_ctrl); 1609 } 1610 } 1611 1612 /* Errata ERR005829: mark first TX mailbox as INACTIVE */ 1613 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1614 &priv->tx_mb_reserved->can_ctrl); 1615 1616 /* mark TX mailbox as INACTIVE */ 1617 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, 1618 &priv->tx_mb->can_ctrl); 1619 1620 /* acceptance mask/acceptance code (accept everything) */ 1621 priv->write(0x0, ®s->rxgmask); 1622 priv->write(0x0, ®s->rx14mask); 1623 priv->write(0x0, ®s->rx15mask); 1624 1625 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_RXFG) 1626 priv->write(0x0, ®s->rxfgmask); 1627 1628 /* clear acceptance filters */ 1629 for (i = 0; i < priv->mb_count; i++) 1630 priv->write(0, ®s->rximr[i]); 1631 1632 /* On Vybrid, disable non-correctable errors interrupt and 1633 * freeze mode. It still can correct the correctable errors 1634 * when HW supports ECC. 1635 * 1636 * This also works around errata e5295 which generates false 1637 * positive memory errors and put the device in freeze mode. 1638 */ 1639 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_DISABLE_MECR) { 1640 /* Follow the protocol as described in "Detection 1641 * and Correction of Memory Errors" to write to 1642 * MECR register (step 1 - 5) 1643 * 1644 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1 1645 * 2. set CTRL2[ECRWRE] 1646 */ 1647 reg_ctrl2 = priv->read(®s->ctrl2); 1648 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; 1649 priv->write(reg_ctrl2, ®s->ctrl2); 1650 1651 /* 3. clear MECR[ECRWRDIS] */ 1652 reg_mecr = priv->read(®s->mecr); 1653 reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS; 1654 priv->write(reg_mecr, ®s->mecr); 1655 1656 /* 4. all writes to MECR must keep MECR[ECRWRDIS] cleared */ 1657 reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK | 1658 FLEXCAN_MECR_FANCEI_MSK); 1659 priv->write(reg_mecr, ®s->mecr); 1660 1661 /* 5. after configuration done, lock MECR by either 1662 * setting MECR[ECRWRDIS] or clearing CTRL2[ECRWRE] 1663 */ 1664 reg_mecr |= FLEXCAN_MECR_ECRWRDIS; 1665 priv->write(reg_mecr, ®s->mecr); 1666 1667 reg_ctrl2 &= ~FLEXCAN_CTRL2_ECRWRE; 1668 priv->write(reg_ctrl2, ®s->ctrl2); 1669 } 1670 1671 /* synchronize with the can bus */ 1672 err = flexcan_chip_unfreeze(priv); 1673 if (err) 1674 goto out_chip_disable; 1675 1676 priv->can.state = CAN_STATE_ERROR_ACTIVE; 1677 1678 /* print chip status */ 1679 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, 1680 priv->read(®s->mcr), priv->read(®s->ctrl)); 1681 1682 return 0; 1683 1684 out_chip_disable: 1685 flexcan_chip_disable(priv); 1686 return err; 1687 } 1688 1689 /* __flexcan_chip_stop 1690 * 1691 * this function is entered with clocks enabled 1692 */ 1693 static int __flexcan_chip_stop(struct net_device *dev, bool disable_on_error) 1694 { 1695 struct flexcan_priv *priv = netdev_priv(dev); 1696 int err; 1697 1698 /* freeze + disable module */ 1699 err = flexcan_chip_freeze(priv); 1700 if (err && !disable_on_error) 1701 return err; 1702 err = flexcan_chip_disable(priv); 1703 if (err && !disable_on_error) 1704 goto out_chip_unfreeze; 1705 1706 priv->can.state = CAN_STATE_STOPPED; 1707 1708 return 0; 1709 1710 out_chip_unfreeze: 1711 flexcan_chip_unfreeze(priv); 1712 1713 return err; 1714 } 1715 1716 static inline int flexcan_chip_stop_disable_on_error(struct net_device *dev) 1717 { 1718 return __flexcan_chip_stop(dev, true); 1719 } 1720 1721 static inline int flexcan_chip_stop(struct net_device *dev) 1722 { 1723 return __flexcan_chip_stop(dev, false); 1724 } 1725 1726 static int flexcan_open(struct net_device *dev) 1727 { 1728 struct flexcan_priv *priv = netdev_priv(dev); 1729 int err; 1730 1731 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) && 1732 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) { 1733 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n"); 1734 return -EINVAL; 1735 } 1736 1737 err = pm_runtime_resume_and_get(priv->dev); 1738 if (err < 0) 1739 return err; 1740 1741 err = open_candev(dev); 1742 if (err) 1743 goto out_runtime_put; 1744 1745 err = flexcan_transceiver_enable(priv); 1746 if (err) 1747 goto out_close; 1748 1749 err = flexcan_rx_offload_setup(dev); 1750 if (err) 1751 goto out_transceiver_disable; 1752 1753 err = flexcan_chip_start(dev); 1754 if (err) 1755 goto out_can_rx_offload_del; 1756 1757 can_rx_offload_enable(&priv->offload); 1758 1759 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); 1760 if (err) 1761 goto out_can_rx_offload_disable; 1762 1763 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1764 err = request_irq(priv->irq_boff, 1765 flexcan_irq, IRQF_SHARED, dev->name, dev); 1766 if (err) 1767 goto out_free_irq; 1768 1769 err = request_irq(priv->irq_err, 1770 flexcan_irq, IRQF_SHARED, dev->name, dev); 1771 if (err) 1772 goto out_free_irq_boff; 1773 } 1774 1775 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) { 1776 err = request_irq(priv->irq_secondary_mb, 1777 flexcan_irq, IRQF_SHARED, dev->name, dev); 1778 if (err) 1779 goto out_free_irq_err; 1780 } 1781 1782 flexcan_chip_interrupts_enable(dev); 1783 1784 netif_start_queue(dev); 1785 1786 return 0; 1787 1788 out_free_irq_err: 1789 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) 1790 free_irq(priv->irq_err, dev); 1791 out_free_irq_boff: 1792 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) 1793 free_irq(priv->irq_boff, dev); 1794 out_free_irq: 1795 free_irq(dev->irq, dev); 1796 out_can_rx_offload_disable: 1797 can_rx_offload_disable(&priv->offload); 1798 flexcan_chip_stop(dev); 1799 out_can_rx_offload_del: 1800 can_rx_offload_del(&priv->offload); 1801 out_transceiver_disable: 1802 flexcan_transceiver_disable(priv); 1803 out_close: 1804 close_candev(dev); 1805 out_runtime_put: 1806 pm_runtime_put(priv->dev); 1807 1808 return err; 1809 } 1810 1811 static int flexcan_close(struct net_device *dev) 1812 { 1813 struct flexcan_priv *priv = netdev_priv(dev); 1814 1815 netif_stop_queue(dev); 1816 flexcan_chip_interrupts_disable(dev); 1817 1818 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) 1819 free_irq(priv->irq_secondary_mb, dev); 1820 1821 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 1822 free_irq(priv->irq_err, dev); 1823 free_irq(priv->irq_boff, dev); 1824 } 1825 1826 free_irq(dev->irq, dev); 1827 can_rx_offload_disable(&priv->offload); 1828 flexcan_chip_stop_disable_on_error(dev); 1829 1830 can_rx_offload_del(&priv->offload); 1831 flexcan_transceiver_disable(priv); 1832 close_candev(dev); 1833 1834 pm_runtime_put(priv->dev); 1835 1836 return 0; 1837 } 1838 1839 static int flexcan_set_mode(struct net_device *dev, enum can_mode mode) 1840 { 1841 int err; 1842 1843 switch (mode) { 1844 case CAN_MODE_START: 1845 err = flexcan_chip_start(dev); 1846 if (err) 1847 return err; 1848 1849 flexcan_chip_interrupts_enable(dev); 1850 1851 netif_wake_queue(dev); 1852 break; 1853 1854 default: 1855 return -EOPNOTSUPP; 1856 } 1857 1858 return 0; 1859 } 1860 1861 static const struct net_device_ops flexcan_netdev_ops = { 1862 .ndo_open = flexcan_open, 1863 .ndo_stop = flexcan_close, 1864 .ndo_start_xmit = flexcan_start_xmit, 1865 .ndo_change_mtu = can_change_mtu, 1866 }; 1867 1868 static int register_flexcandev(struct net_device *dev) 1869 { 1870 struct flexcan_priv *priv = netdev_priv(dev); 1871 struct flexcan_regs __iomem *regs = priv->regs; 1872 u32 reg, err; 1873 1874 err = flexcan_clks_enable(priv); 1875 if (err) 1876 return err; 1877 1878 /* select "bus clock", chip must be disabled */ 1879 err = flexcan_chip_disable(priv); 1880 if (err) 1881 goto out_clks_disable; 1882 1883 reg = priv->read(®s->ctrl); 1884 if (priv->clk_src) 1885 reg |= FLEXCAN_CTRL_CLK_SRC; 1886 else 1887 reg &= ~FLEXCAN_CTRL_CLK_SRC; 1888 priv->write(reg, ®s->ctrl); 1889 1890 err = flexcan_chip_enable(priv); 1891 if (err) 1892 goto out_chip_disable; 1893 1894 /* set freeze, halt */ 1895 err = flexcan_chip_freeze(priv); 1896 if (err) 1897 goto out_chip_disable; 1898 1899 /* activate FIFO, restrict register access */ 1900 reg = priv->read(®s->mcr); 1901 reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV; 1902 priv->write(reg, ®s->mcr); 1903 1904 /* Currently we only support newer versions of this core 1905 * featuring a RX hardware FIFO (although this driver doesn't 1906 * make use of it on some cores). Older cores, found on some 1907 * Coldfire derivates are not tested. 1908 */ 1909 reg = priv->read(®s->mcr); 1910 if (!(reg & FLEXCAN_MCR_FEN)) { 1911 netdev_err(dev, "Could not enable RX FIFO, unsupported core\n"); 1912 err = -ENODEV; 1913 goto out_chip_disable; 1914 } 1915 1916 err = register_candev(dev); 1917 if (err) 1918 goto out_chip_disable; 1919 1920 /* Disable core and let pm_runtime_put() disable the clocks. 1921 * If CONFIG_PM is not enabled, the clocks will stay powered. 1922 */ 1923 flexcan_chip_disable(priv); 1924 pm_runtime_put(priv->dev); 1925 1926 return 0; 1927 1928 out_chip_disable: 1929 flexcan_chip_disable(priv); 1930 out_clks_disable: 1931 flexcan_clks_disable(priv); 1932 return err; 1933 } 1934 1935 static void unregister_flexcandev(struct net_device *dev) 1936 { 1937 unregister_candev(dev); 1938 } 1939 1940 static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev) 1941 { 1942 struct net_device *dev = platform_get_drvdata(pdev); 1943 struct device_node *np = pdev->dev.of_node; 1944 struct device_node *gpr_np; 1945 struct flexcan_priv *priv; 1946 phandle phandle; 1947 u32 out_val[3]; 1948 int ret; 1949 1950 if (!np) 1951 return -EINVAL; 1952 1953 /* stop mode property format is: 1954 * <&gpr req_gpr req_bit>. 1955 */ 1956 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, 1957 ARRAY_SIZE(out_val)); 1958 if (ret) { 1959 dev_dbg(&pdev->dev, "no stop-mode property\n"); 1960 return ret; 1961 } 1962 phandle = *out_val; 1963 1964 gpr_np = of_find_node_by_phandle(phandle); 1965 if (!gpr_np) { 1966 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); 1967 return -ENODEV; 1968 } 1969 1970 priv = netdev_priv(dev); 1971 priv->stm.gpr = syscon_node_to_regmap(gpr_np); 1972 if (IS_ERR(priv->stm.gpr)) { 1973 dev_dbg(&pdev->dev, "could not find gpr regmap\n"); 1974 ret = PTR_ERR(priv->stm.gpr); 1975 goto out_put_node; 1976 } 1977 1978 priv->stm.req_gpr = out_val[1]; 1979 priv->stm.req_bit = out_val[2]; 1980 1981 dev_dbg(&pdev->dev, 1982 "gpr %s req_gpr=0x02%x req_bit=%u\n", 1983 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit); 1984 1985 return 0; 1986 1987 out_put_node: 1988 of_node_put(gpr_np); 1989 return ret; 1990 } 1991 1992 static int flexcan_setup_stop_mode_scfw(struct platform_device *pdev) 1993 { 1994 struct net_device *dev = platform_get_drvdata(pdev); 1995 struct flexcan_priv *priv; 1996 u8 scu_idx; 1997 int ret; 1998 1999 ret = of_property_read_u8(pdev->dev.of_node, "fsl,scu-index", &scu_idx); 2000 if (ret < 0) { 2001 dev_dbg(&pdev->dev, "failed to get scu index\n"); 2002 return ret; 2003 } 2004 2005 priv = netdev_priv(dev); 2006 priv->scu_idx = scu_idx; 2007 2008 /* this function could be deferred probe, return -EPROBE_DEFER */ 2009 return imx_scu_get_handle(&priv->sc_ipc_handle); 2010 } 2011 2012 /* flexcan_setup_stop_mode - Setup stop mode for wakeup 2013 * 2014 * Return: = 0 setup stop mode successfully or doesn't support this feature 2015 * < 0 fail to setup stop mode (could be deferred probe) 2016 */ 2017 static int flexcan_setup_stop_mode(struct platform_device *pdev) 2018 { 2019 struct net_device *dev = platform_get_drvdata(pdev); 2020 struct flexcan_priv *priv; 2021 int ret; 2022 2023 priv = netdev_priv(dev); 2024 2025 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW) 2026 ret = flexcan_setup_stop_mode_scfw(pdev); 2027 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR) 2028 ret = flexcan_setup_stop_mode_gpr(pdev); 2029 else if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI) 2030 /* ATF will handle all STOP_IPG related work */ 2031 ret = 0; 2032 else 2033 /* return 0 directly if doesn't support stop mode feature */ 2034 return 0; 2035 2036 /* If ret is -EINVAL, this means SoC claim to support stop mode, but 2037 * dts file lack the stop mode property definition. For this case, 2038 * directly return 0, this will skip the wakeup capable setting and 2039 * will not block the driver probe. 2040 */ 2041 if (ret == -EINVAL) 2042 return 0; 2043 else if (ret) 2044 return ret; 2045 2046 device_set_wakeup_capable(&pdev->dev, true); 2047 2048 if (of_property_read_bool(pdev->dev.of_node, "wakeup-source")) 2049 device_set_wakeup_enable(&pdev->dev, true); 2050 2051 return 0; 2052 } 2053 2054 static const struct of_device_id flexcan_of_match[] = { 2055 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, }, 2056 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, }, 2057 { .compatible = "fsl,imx93-flexcan", .data = &fsl_imx93_devtype_data, }, 2058 { .compatible = "fsl,imx95-flexcan", .data = &fsl_imx95_devtype_data, }, 2059 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, }, 2060 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, }, 2061 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, }, 2062 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, }, 2063 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, }, 2064 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, }, 2065 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, }, 2066 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, }, 2067 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, }, 2068 { .compatible = "nxp,s32g2-flexcan", .data = &nxp_s32g2_devtype_data, }, 2069 { /* sentinel */ }, 2070 }; 2071 MODULE_DEVICE_TABLE(of, flexcan_of_match); 2072 2073 static const struct platform_device_id flexcan_id_table[] = { 2074 { 2075 .name = "flexcan-mcf5441x", 2076 .driver_data = (kernel_ulong_t)&fsl_mcf5441x_devtype_data, 2077 }, { 2078 /* sentinel */ 2079 }, 2080 }; 2081 MODULE_DEVICE_TABLE(platform, flexcan_id_table); 2082 2083 static int flexcan_probe(struct platform_device *pdev) 2084 { 2085 const struct flexcan_devtype_data *devtype_data; 2086 struct net_device *dev; 2087 struct flexcan_priv *priv; 2088 struct regulator *reg_xceiver; 2089 struct clk *clk_ipg = NULL, *clk_per = NULL; 2090 struct flexcan_regs __iomem *regs; 2091 struct flexcan_platform_data *pdata; 2092 int err, irq; 2093 u8 clk_src = 1; 2094 u32 clock_freq = 0; 2095 2096 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver"); 2097 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) 2098 return -EPROBE_DEFER; 2099 else if (PTR_ERR(reg_xceiver) == -ENODEV) 2100 reg_xceiver = NULL; 2101 else if (IS_ERR(reg_xceiver)) 2102 return PTR_ERR(reg_xceiver); 2103 2104 if (pdev->dev.of_node) { 2105 of_property_read_u32(pdev->dev.of_node, 2106 "clock-frequency", &clock_freq); 2107 of_property_read_u8(pdev->dev.of_node, 2108 "fsl,clk-source", &clk_src); 2109 } else { 2110 pdata = dev_get_platdata(&pdev->dev); 2111 if (pdata) { 2112 clock_freq = pdata->clock_frequency; 2113 clk_src = pdata->clk_src; 2114 } 2115 } 2116 2117 if (!clock_freq) { 2118 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 2119 if (IS_ERR(clk_ipg)) { 2120 dev_err(&pdev->dev, "no ipg clock defined\n"); 2121 return PTR_ERR(clk_ipg); 2122 } 2123 2124 clk_per = devm_clk_get(&pdev->dev, "per"); 2125 if (IS_ERR(clk_per)) { 2126 dev_err(&pdev->dev, "no per clock defined\n"); 2127 return PTR_ERR(clk_per); 2128 } 2129 clock_freq = clk_get_rate(clk_per); 2130 } 2131 2132 irq = platform_get_irq(pdev, 0); 2133 if (irq < 0) 2134 return irq; 2135 2136 regs = devm_platform_ioremap_resource(pdev, 0); 2137 if (IS_ERR(regs)) 2138 return PTR_ERR(regs); 2139 2140 devtype_data = device_get_match_data(&pdev->dev); 2141 2142 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) && 2143 !((devtype_data->quirks & 2144 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2145 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2146 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR | 2147 FLEXCAN_QUIRK_SUPPORT_RX_FIFO)) == 2148 (FLEXCAN_QUIRK_USE_RX_MAILBOX | 2149 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2150 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR))) { 2151 dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n"); 2152 return -EINVAL; 2153 } 2154 2155 if ((devtype_data->quirks & 2156 (FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX | 2157 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR)) == 2158 FLEXCAN_QUIRK_SUPPORT_RX_MAILBOX_RTR) { 2159 dev_err(&pdev->dev, 2160 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n", 2161 devtype_data->quirks); 2162 return -EINVAL; 2163 } 2164 2165 dev = alloc_candev(sizeof(struct flexcan_priv), 1); 2166 if (!dev) 2167 return -ENOMEM; 2168 2169 platform_set_drvdata(pdev, dev); 2170 SET_NETDEV_DEV(dev, &pdev->dev); 2171 2172 dev->netdev_ops = &flexcan_netdev_ops; 2173 dev->ethtool_ops = &flexcan_ethtool_ops; 2174 dev->irq = irq; 2175 dev->flags |= IFF_ECHO; 2176 2177 priv = netdev_priv(dev); 2178 priv->devtype_data = *devtype_data; 2179 2180 if (of_property_read_bool(pdev->dev.of_node, "big-endian") || 2181 priv->devtype_data.quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { 2182 priv->read = flexcan_read_be; 2183 priv->write = flexcan_write_be; 2184 } else { 2185 priv->read = flexcan_read_le; 2186 priv->write = flexcan_write_le; 2187 } 2188 2189 priv->dev = &pdev->dev; 2190 priv->can.clock.freq = clock_freq; 2191 priv->can.do_set_mode = flexcan_set_mode; 2192 priv->can.do_get_berr_counter = flexcan_get_berr_counter; 2193 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | 2194 CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_3_SAMPLES | 2195 CAN_CTRLMODE_BERR_REPORTING; 2196 priv->regs = regs; 2197 priv->clk_ipg = clk_ipg; 2198 priv->clk_per = clk_per; 2199 priv->clk_src = clk_src; 2200 priv->reg_xceiver = reg_xceiver; 2201 2202 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) { 2203 priv->irq_boff = platform_get_irq(pdev, 1); 2204 if (priv->irq_boff < 0) { 2205 err = priv->irq_boff; 2206 goto failed_platform_get_irq; 2207 } 2208 priv->irq_err = platform_get_irq(pdev, 2); 2209 if (priv->irq_err < 0) { 2210 err = priv->irq_err; 2211 goto failed_platform_get_irq; 2212 } 2213 } 2214 2215 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SECONDARY_MB_IRQ) { 2216 priv->irq_secondary_mb = platform_get_irq_byname(pdev, "mb-1"); 2217 if (priv->irq_secondary_mb < 0) { 2218 err = priv->irq_secondary_mb; 2219 goto failed_platform_get_irq; 2220 } 2221 } 2222 2223 if (priv->devtype_data.quirks & FLEXCAN_QUIRK_SUPPORT_FD) { 2224 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | 2225 CAN_CTRLMODE_FD_NON_ISO; 2226 priv->can.bittiming_const = &flexcan_fd_bittiming_const; 2227 priv->can.data_bittiming_const = 2228 &flexcan_fd_data_bittiming_const; 2229 } else { 2230 priv->can.bittiming_const = &flexcan_bittiming_const; 2231 } 2232 2233 pm_runtime_get_noresume(&pdev->dev); 2234 pm_runtime_set_active(&pdev->dev); 2235 pm_runtime_enable(&pdev->dev); 2236 2237 err = register_flexcandev(dev); 2238 if (err) { 2239 dev_err(&pdev->dev, "registering netdev failed\n"); 2240 goto failed_register; 2241 } 2242 2243 err = flexcan_setup_stop_mode(pdev); 2244 if (err < 0) { 2245 dev_err_probe(&pdev->dev, err, "setup stop mode failed\n"); 2246 goto failed_setup_stop_mode; 2247 } 2248 2249 of_can_transceiver(dev); 2250 2251 return 0; 2252 2253 failed_setup_stop_mode: 2254 unregister_flexcandev(dev); 2255 failed_register: 2256 pm_runtime_put_noidle(&pdev->dev); 2257 pm_runtime_disable(&pdev->dev); 2258 failed_platform_get_irq: 2259 free_candev(dev); 2260 return err; 2261 } 2262 2263 static void flexcan_remove(struct platform_device *pdev) 2264 { 2265 struct net_device *dev = platform_get_drvdata(pdev); 2266 2267 device_set_wakeup_enable(&pdev->dev, false); 2268 device_set_wakeup_capable(&pdev->dev, false); 2269 unregister_flexcandev(dev); 2270 pm_runtime_disable(&pdev->dev); 2271 free_candev(dev); 2272 } 2273 2274 static int __maybe_unused flexcan_suspend(struct device *device) 2275 { 2276 struct net_device *dev = dev_get_drvdata(device); 2277 struct flexcan_priv *priv = netdev_priv(dev); 2278 int err; 2279 2280 if (netif_running(dev)) { 2281 /* if wakeup is enabled, enter stop mode 2282 * else enter disabled mode. 2283 */ 2284 if (device_may_wakeup(device)) { 2285 enable_irq_wake(dev->irq); 2286 err = flexcan_enter_stop_mode(priv); 2287 if (err) 2288 return err; 2289 } else { 2290 err = flexcan_chip_stop(dev); 2291 if (err) 2292 return err; 2293 2294 flexcan_chip_interrupts_disable(dev); 2295 2296 err = pinctrl_pm_select_sleep_state(device); 2297 if (err) 2298 return err; 2299 } 2300 netif_stop_queue(dev); 2301 netif_device_detach(dev); 2302 } 2303 priv->can.state = CAN_STATE_SLEEPING; 2304 2305 return 0; 2306 } 2307 2308 static int __maybe_unused flexcan_resume(struct device *device) 2309 { 2310 struct net_device *dev = dev_get_drvdata(device); 2311 struct flexcan_priv *priv = netdev_priv(dev); 2312 int err; 2313 2314 priv->can.state = CAN_STATE_ERROR_ACTIVE; 2315 if (netif_running(dev)) { 2316 netif_device_attach(dev); 2317 netif_start_queue(dev); 2318 if (device_may_wakeup(device)) { 2319 disable_irq_wake(dev->irq); 2320 err = flexcan_exit_stop_mode(priv); 2321 if (err) 2322 return err; 2323 } else { 2324 err = pinctrl_pm_select_default_state(device); 2325 if (err) 2326 return err; 2327 2328 err = flexcan_chip_start(dev); 2329 if (err) 2330 return err; 2331 2332 flexcan_chip_interrupts_enable(dev); 2333 } 2334 } 2335 2336 return 0; 2337 } 2338 2339 static int __maybe_unused flexcan_runtime_suspend(struct device *device) 2340 { 2341 struct net_device *dev = dev_get_drvdata(device); 2342 struct flexcan_priv *priv = netdev_priv(dev); 2343 2344 flexcan_clks_disable(priv); 2345 2346 return 0; 2347 } 2348 2349 static int __maybe_unused flexcan_runtime_resume(struct device *device) 2350 { 2351 struct net_device *dev = dev_get_drvdata(device); 2352 struct flexcan_priv *priv = netdev_priv(dev); 2353 2354 return flexcan_clks_enable(priv); 2355 } 2356 2357 static int __maybe_unused flexcan_noirq_suspend(struct device *device) 2358 { 2359 struct net_device *dev = dev_get_drvdata(device); 2360 struct flexcan_priv *priv = netdev_priv(dev); 2361 2362 if (netif_running(dev)) { 2363 int err; 2364 2365 if (device_may_wakeup(device)) 2366 flexcan_enable_wakeup_irq(priv, true); 2367 2368 /* For FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI, it need ATF to send 2369 * to SM through SCMI protocol, SM will assert the IPG_STOP 2370 * signal. But all this works need the CAN clocks keep on. 2371 * After the CAN module get the IPG_STOP mode, and switch to 2372 * STOP mode, whether still keep the CAN clocks on or gate them 2373 * off depend on the Hardware design. 2374 */ 2375 if (!(device_may_wakeup(device) && 2376 priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) { 2377 err = pm_runtime_force_suspend(device); 2378 if (err) 2379 return err; 2380 } 2381 } 2382 2383 return 0; 2384 } 2385 2386 static int __maybe_unused flexcan_noirq_resume(struct device *device) 2387 { 2388 struct net_device *dev = dev_get_drvdata(device); 2389 struct flexcan_priv *priv = netdev_priv(dev); 2390 2391 if (netif_running(dev)) { 2392 int err; 2393 2394 if (!(device_may_wakeup(device) && 2395 priv->devtype_data.quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE_SCMI)) { 2396 err = pm_runtime_force_resume(device); 2397 if (err) 2398 return err; 2399 } 2400 2401 if (device_may_wakeup(device)) 2402 flexcan_enable_wakeup_irq(priv, false); 2403 } 2404 2405 return 0; 2406 } 2407 2408 static const struct dev_pm_ops flexcan_pm_ops = { 2409 SET_SYSTEM_SLEEP_PM_OPS(flexcan_suspend, flexcan_resume) 2410 SET_RUNTIME_PM_OPS(flexcan_runtime_suspend, flexcan_runtime_resume, NULL) 2411 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(flexcan_noirq_suspend, flexcan_noirq_resume) 2412 }; 2413 2414 static struct platform_driver flexcan_driver = { 2415 .driver = { 2416 .name = DRV_NAME, 2417 .pm = &flexcan_pm_ops, 2418 .of_match_table = flexcan_of_match, 2419 }, 2420 .probe = flexcan_probe, 2421 .remove = flexcan_remove, 2422 .id_table = flexcan_id_table, 2423 }; 2424 2425 module_platform_driver(flexcan_driver); 2426 2427 MODULE_AUTHOR("Sascha Hauer <kernel@pengutronix.de>, " 2428 "Marc Kleine-Budde <kernel@pengutronix.de>"); 2429 MODULE_LICENSE("GPL v2"); 2430 MODULE_DESCRIPTION("CAN port driver for flexcan based chip"); 2431