1 /* 2 * at91_can.c - CAN network driver for AT91 SoC CAN controller 3 * 4 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de> 5 * (C) 2008, 2009, 2010, 2011 by Marc Kleine-Budde <kernel@pengutronix.de> 6 * 7 * This software may be distributed under the terms of the GNU General 8 * Public License ("GPL") version 2 as distributed in the 'COPYING' 9 * file from the main directory of the linux kernel source. 10 * 11 * 12 * Your platform definition file should specify something like: 13 * 14 * static struct at91_can_data ek_can_data = { 15 * transceiver_switch = sam9263ek_transceiver_switch, 16 * }; 17 * 18 * at91_add_device_can(&ek_can_data); 19 * 20 */ 21 22 #include <linux/clk.h> 23 #include <linux/errno.h> 24 #include <linux/if_arp.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/netdevice.h> 30 #include <linux/of.h> 31 #include <linux/platform_device.h> 32 #include <linux/rtnetlink.h> 33 #include <linux/skbuff.h> 34 #include <linux/spinlock.h> 35 #include <linux/string.h> 36 #include <linux/types.h> 37 #include <linux/platform_data/atmel.h> 38 39 #include <linux/can/dev.h> 40 #include <linux/can/error.h> 41 #include <linux/can/led.h> 42 43 #define AT91_MB_MASK(i) ((1 << (i)) - 1) 44 45 /* Common registers */ 46 enum at91_reg { 47 AT91_MR = 0x000, 48 AT91_IER = 0x004, 49 AT91_IDR = 0x008, 50 AT91_IMR = 0x00C, 51 AT91_SR = 0x010, 52 AT91_BR = 0x014, 53 AT91_TIM = 0x018, 54 AT91_TIMESTP = 0x01C, 55 AT91_ECR = 0x020, 56 AT91_TCR = 0x024, 57 AT91_ACR = 0x028, 58 }; 59 60 /* Mailbox registers (0 <= i <= 15) */ 61 #define AT91_MMR(i) (enum at91_reg)(0x200 + ((i) * 0x20)) 62 #define AT91_MAM(i) (enum at91_reg)(0x204 + ((i) * 0x20)) 63 #define AT91_MID(i) (enum at91_reg)(0x208 + ((i) * 0x20)) 64 #define AT91_MFID(i) (enum at91_reg)(0x20C + ((i) * 0x20)) 65 #define AT91_MSR(i) (enum at91_reg)(0x210 + ((i) * 0x20)) 66 #define AT91_MDL(i) (enum at91_reg)(0x214 + ((i) * 0x20)) 67 #define AT91_MDH(i) (enum at91_reg)(0x218 + ((i) * 0x20)) 68 #define AT91_MCR(i) (enum at91_reg)(0x21C + ((i) * 0x20)) 69 70 /* Register bits */ 71 #define AT91_MR_CANEN BIT(0) 72 #define AT91_MR_LPM BIT(1) 73 #define AT91_MR_ABM BIT(2) 74 #define AT91_MR_OVL BIT(3) 75 #define AT91_MR_TEOF BIT(4) 76 #define AT91_MR_TTM BIT(5) 77 #define AT91_MR_TIMFRZ BIT(6) 78 #define AT91_MR_DRPT BIT(7) 79 80 #define AT91_SR_RBSY BIT(29) 81 82 #define AT91_MMR_PRIO_SHIFT (16) 83 84 #define AT91_MID_MIDE BIT(29) 85 86 #define AT91_MSR_MRTR BIT(20) 87 #define AT91_MSR_MABT BIT(22) 88 #define AT91_MSR_MRDY BIT(23) 89 #define AT91_MSR_MMI BIT(24) 90 91 #define AT91_MCR_MRTR BIT(20) 92 #define AT91_MCR_MTCR BIT(23) 93 94 /* Mailbox Modes */ 95 enum at91_mb_mode { 96 AT91_MB_MODE_DISABLED = 0, 97 AT91_MB_MODE_RX = 1, 98 AT91_MB_MODE_RX_OVRWR = 2, 99 AT91_MB_MODE_TX = 3, 100 AT91_MB_MODE_CONSUMER = 4, 101 AT91_MB_MODE_PRODUCER = 5, 102 }; 103 104 /* Interrupt mask bits */ 105 #define AT91_IRQ_ERRA (1 << 16) 106 #define AT91_IRQ_WARN (1 << 17) 107 #define AT91_IRQ_ERRP (1 << 18) 108 #define AT91_IRQ_BOFF (1 << 19) 109 #define AT91_IRQ_SLEEP (1 << 20) 110 #define AT91_IRQ_WAKEUP (1 << 21) 111 #define AT91_IRQ_TOVF (1 << 22) 112 #define AT91_IRQ_TSTP (1 << 23) 113 #define AT91_IRQ_CERR (1 << 24) 114 #define AT91_IRQ_SERR (1 << 25) 115 #define AT91_IRQ_AERR (1 << 26) 116 #define AT91_IRQ_FERR (1 << 27) 117 #define AT91_IRQ_BERR (1 << 28) 118 119 #define AT91_IRQ_ERR_ALL (0x1fff0000) 120 #define AT91_IRQ_ERR_FRAME (AT91_IRQ_CERR | AT91_IRQ_SERR | \ 121 AT91_IRQ_AERR | AT91_IRQ_FERR | AT91_IRQ_BERR) 122 #define AT91_IRQ_ERR_LINE (AT91_IRQ_ERRA | AT91_IRQ_WARN | \ 123 AT91_IRQ_ERRP | AT91_IRQ_BOFF) 124 125 #define AT91_IRQ_ALL (0x1fffffff) 126 127 enum at91_devtype { 128 AT91_DEVTYPE_SAM9263, 129 AT91_DEVTYPE_SAM9X5, 130 }; 131 132 struct at91_devtype_data { 133 unsigned int rx_first; 134 unsigned int rx_split; 135 unsigned int rx_last; 136 unsigned int tx_shift; 137 enum at91_devtype type; 138 }; 139 140 struct at91_priv { 141 struct can_priv can; /* must be the first member! */ 142 struct net_device *dev; 143 struct napi_struct napi; 144 145 void __iomem *reg_base; 146 147 u32 reg_sr; 148 unsigned int tx_next; 149 unsigned int tx_echo; 150 unsigned int rx_next; 151 struct at91_devtype_data devtype_data; 152 153 struct clk *clk; 154 struct at91_can_data *pdata; 155 156 canid_t mb0_id; 157 }; 158 159 static const struct at91_devtype_data at91_at91sam9263_data = { 160 .rx_first = 1, 161 .rx_split = 8, 162 .rx_last = 11, 163 .tx_shift = 2, 164 .type = AT91_DEVTYPE_SAM9263, 165 }; 166 167 static const struct at91_devtype_data at91_at91sam9x5_data = { 168 .rx_first = 0, 169 .rx_split = 4, 170 .rx_last = 5, 171 .tx_shift = 1, 172 .type = AT91_DEVTYPE_SAM9X5, 173 }; 174 175 static const struct can_bittiming_const at91_bittiming_const = { 176 .name = KBUILD_MODNAME, 177 .tseg1_min = 4, 178 .tseg1_max = 16, 179 .tseg2_min = 2, 180 .tseg2_max = 8, 181 .sjw_max = 4, 182 .brp_min = 2, 183 .brp_max = 128, 184 .brp_inc = 1, 185 }; 186 187 #define AT91_IS(_model) \ 188 static inline int at91_is_sam##_model(const struct at91_priv *priv) \ 189 { \ 190 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ 191 } 192 193 AT91_IS(9263); 194 AT91_IS(9X5); 195 196 static inline unsigned int get_mb_rx_first(const struct at91_priv *priv) 197 { 198 return priv->devtype_data.rx_first; 199 } 200 201 static inline unsigned int get_mb_rx_last(const struct at91_priv *priv) 202 { 203 return priv->devtype_data.rx_last; 204 } 205 206 static inline unsigned int get_mb_rx_split(const struct at91_priv *priv) 207 { 208 return priv->devtype_data.rx_split; 209 } 210 211 static inline unsigned int get_mb_rx_num(const struct at91_priv *priv) 212 { 213 return get_mb_rx_last(priv) - get_mb_rx_first(priv) + 1; 214 } 215 216 static inline unsigned int get_mb_rx_low_last(const struct at91_priv *priv) 217 { 218 return get_mb_rx_split(priv) - 1; 219 } 220 221 static inline unsigned int get_mb_rx_low_mask(const struct at91_priv *priv) 222 { 223 return AT91_MB_MASK(get_mb_rx_split(priv)) & 224 ~AT91_MB_MASK(get_mb_rx_first(priv)); 225 } 226 227 static inline unsigned int get_mb_tx_shift(const struct at91_priv *priv) 228 { 229 return priv->devtype_data.tx_shift; 230 } 231 232 static inline unsigned int get_mb_tx_num(const struct at91_priv *priv) 233 { 234 return 1 << get_mb_tx_shift(priv); 235 } 236 237 static inline unsigned int get_mb_tx_first(const struct at91_priv *priv) 238 { 239 return get_mb_rx_last(priv) + 1; 240 } 241 242 static inline unsigned int get_mb_tx_last(const struct at91_priv *priv) 243 { 244 return get_mb_tx_first(priv) + get_mb_tx_num(priv) - 1; 245 } 246 247 static inline unsigned int get_next_prio_shift(const struct at91_priv *priv) 248 { 249 return get_mb_tx_shift(priv); 250 } 251 252 static inline unsigned int get_next_prio_mask(const struct at91_priv *priv) 253 { 254 return 0xf << get_mb_tx_shift(priv); 255 } 256 257 static inline unsigned int get_next_mb_mask(const struct at91_priv *priv) 258 { 259 return AT91_MB_MASK(get_mb_tx_shift(priv)); 260 } 261 262 static inline unsigned int get_next_mask(const struct at91_priv *priv) 263 { 264 return get_next_mb_mask(priv) | get_next_prio_mask(priv); 265 } 266 267 static inline unsigned int get_irq_mb_rx(const struct at91_priv *priv) 268 { 269 return AT91_MB_MASK(get_mb_rx_last(priv) + 1) & 270 ~AT91_MB_MASK(get_mb_rx_first(priv)); 271 } 272 273 static inline unsigned int get_irq_mb_tx(const struct at91_priv *priv) 274 { 275 return AT91_MB_MASK(get_mb_tx_last(priv) + 1) & 276 ~AT91_MB_MASK(get_mb_tx_first(priv)); 277 } 278 279 static inline unsigned int get_tx_next_mb(const struct at91_priv *priv) 280 { 281 return (priv->tx_next & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 282 } 283 284 static inline unsigned int get_tx_next_prio(const struct at91_priv *priv) 285 { 286 return (priv->tx_next >> get_next_prio_shift(priv)) & 0xf; 287 } 288 289 static inline unsigned int get_tx_echo_mb(const struct at91_priv *priv) 290 { 291 return (priv->tx_echo & get_next_mb_mask(priv)) + get_mb_tx_first(priv); 292 } 293 294 static inline u32 at91_read(const struct at91_priv *priv, enum at91_reg reg) 295 { 296 return __raw_readl(priv->reg_base + reg); 297 } 298 299 static inline void at91_write(const struct at91_priv *priv, enum at91_reg reg, 300 u32 value) 301 { 302 __raw_writel(value, priv->reg_base + reg); 303 } 304 305 static inline void set_mb_mode_prio(const struct at91_priv *priv, 306 unsigned int mb, enum at91_mb_mode mode, int prio) 307 { 308 at91_write(priv, AT91_MMR(mb), (mode << 24) | (prio << 16)); 309 } 310 311 static inline void set_mb_mode(const struct at91_priv *priv, unsigned int mb, 312 enum at91_mb_mode mode) 313 { 314 set_mb_mode_prio(priv, mb, mode, 0); 315 } 316 317 static inline u32 at91_can_id_to_reg_mid(canid_t can_id) 318 { 319 u32 reg_mid; 320 321 if (can_id & CAN_EFF_FLAG) 322 reg_mid = (can_id & CAN_EFF_MASK) | AT91_MID_MIDE; 323 else 324 reg_mid = (can_id & CAN_SFF_MASK) << 18; 325 326 return reg_mid; 327 } 328 329 /* 330 * Swtich transceiver on or off 331 */ 332 static void at91_transceiver_switch(const struct at91_priv *priv, int on) 333 { 334 if (priv->pdata && priv->pdata->transceiver_switch) 335 priv->pdata->transceiver_switch(on); 336 } 337 338 static void at91_setup_mailboxes(struct net_device *dev) 339 { 340 struct at91_priv *priv = netdev_priv(dev); 341 unsigned int i; 342 u32 reg_mid; 343 344 /* 345 * Due to a chip bug (errata 50.2.6.3 & 50.3.5.3) the first 346 * mailbox is disabled. The next 11 mailboxes are used as a 347 * reception FIFO. The last mailbox is configured with 348 * overwrite option. The overwrite flag indicates a FIFO 349 * overflow. 350 */ 351 reg_mid = at91_can_id_to_reg_mid(priv->mb0_id); 352 for (i = 0; i < get_mb_rx_first(priv); i++) { 353 set_mb_mode(priv, i, AT91_MB_MODE_DISABLED); 354 at91_write(priv, AT91_MID(i), reg_mid); 355 at91_write(priv, AT91_MCR(i), 0x0); /* clear dlc */ 356 } 357 358 for (i = get_mb_rx_first(priv); i < get_mb_rx_last(priv); i++) 359 set_mb_mode(priv, i, AT91_MB_MODE_RX); 360 set_mb_mode(priv, get_mb_rx_last(priv), AT91_MB_MODE_RX_OVRWR); 361 362 /* reset acceptance mask and id register */ 363 for (i = get_mb_rx_first(priv); i <= get_mb_rx_last(priv); i++) { 364 at91_write(priv, AT91_MAM(i), 0x0); 365 at91_write(priv, AT91_MID(i), AT91_MID_MIDE); 366 } 367 368 /* The last 4 mailboxes are used for transmitting. */ 369 for (i = get_mb_tx_first(priv); i <= get_mb_tx_last(priv); i++) 370 set_mb_mode_prio(priv, i, AT91_MB_MODE_TX, 0); 371 372 /* Reset tx and rx helper pointers */ 373 priv->tx_next = priv->tx_echo = 0; 374 priv->rx_next = get_mb_rx_first(priv); 375 } 376 377 static int at91_set_bittiming(struct net_device *dev) 378 { 379 const struct at91_priv *priv = netdev_priv(dev); 380 const struct can_bittiming *bt = &priv->can.bittiming; 381 u32 reg_br; 382 383 reg_br = ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) ? 1 << 24 : 0) | 384 ((bt->brp - 1) << 16) | ((bt->sjw - 1) << 12) | 385 ((bt->prop_seg - 1) << 8) | ((bt->phase_seg1 - 1) << 4) | 386 ((bt->phase_seg2 - 1) << 0); 387 388 netdev_info(dev, "writing AT91_BR: 0x%08x\n", reg_br); 389 390 at91_write(priv, AT91_BR, reg_br); 391 392 return 0; 393 } 394 395 static int at91_get_berr_counter(const struct net_device *dev, 396 struct can_berr_counter *bec) 397 { 398 const struct at91_priv *priv = netdev_priv(dev); 399 u32 reg_ecr = at91_read(priv, AT91_ECR); 400 401 bec->rxerr = reg_ecr & 0xff; 402 bec->txerr = reg_ecr >> 16; 403 404 return 0; 405 } 406 407 static void at91_chip_start(struct net_device *dev) 408 { 409 struct at91_priv *priv = netdev_priv(dev); 410 u32 reg_mr, reg_ier; 411 412 /* disable interrupts */ 413 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 414 415 /* disable chip */ 416 reg_mr = at91_read(priv, AT91_MR); 417 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 418 419 at91_set_bittiming(dev); 420 at91_setup_mailboxes(dev); 421 at91_transceiver_switch(priv, 1); 422 423 /* enable chip */ 424 at91_write(priv, AT91_MR, AT91_MR_CANEN); 425 426 priv->can.state = CAN_STATE_ERROR_ACTIVE; 427 428 /* Enable interrupts */ 429 reg_ier = get_irq_mb_rx(priv) | AT91_IRQ_ERRP | AT91_IRQ_ERR_FRAME; 430 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 431 at91_write(priv, AT91_IER, reg_ier); 432 } 433 434 static void at91_chip_stop(struct net_device *dev, enum can_state state) 435 { 436 struct at91_priv *priv = netdev_priv(dev); 437 u32 reg_mr; 438 439 /* disable interrupts */ 440 at91_write(priv, AT91_IDR, AT91_IRQ_ALL); 441 442 reg_mr = at91_read(priv, AT91_MR); 443 at91_write(priv, AT91_MR, reg_mr & ~AT91_MR_CANEN); 444 445 at91_transceiver_switch(priv, 0); 446 priv->can.state = state; 447 } 448 449 /* 450 * theory of operation: 451 * 452 * According to the datasheet priority 0 is the highest priority, 15 453 * is the lowest. If two mailboxes have the same priority level the 454 * message of the mailbox with the lowest number is sent first. 455 * 456 * We use the first TX mailbox (AT91_MB_TX_FIRST) with prio 0, then 457 * the next mailbox with prio 0, and so on, until all mailboxes are 458 * used. Then we start from the beginning with mailbox 459 * AT91_MB_TX_FIRST, but with prio 1, mailbox AT91_MB_TX_FIRST + 1 460 * prio 1. When we reach the last mailbox with prio 15, we have to 461 * stop sending, waiting for all messages to be delivered, then start 462 * again with mailbox AT91_MB_TX_FIRST prio 0. 463 * 464 * We use the priv->tx_next as counter for the next transmission 465 * mailbox, but without the offset AT91_MB_TX_FIRST. The lower bits 466 * encode the mailbox number, the upper 4 bits the mailbox priority: 467 * 468 * priv->tx_next = (prio << get_next_prio_shift(priv)) | 469 * (mb - get_mb_tx_first(priv)); 470 * 471 */ 472 static netdev_tx_t at91_start_xmit(struct sk_buff *skb, struct net_device *dev) 473 { 474 struct at91_priv *priv = netdev_priv(dev); 475 struct net_device_stats *stats = &dev->stats; 476 struct can_frame *cf = (struct can_frame *)skb->data; 477 unsigned int mb, prio; 478 u32 reg_mid, reg_mcr; 479 480 if (can_dropped_invalid_skb(dev, skb)) 481 return NETDEV_TX_OK; 482 483 mb = get_tx_next_mb(priv); 484 prio = get_tx_next_prio(priv); 485 486 if (unlikely(!(at91_read(priv, AT91_MSR(mb)) & AT91_MSR_MRDY))) { 487 netif_stop_queue(dev); 488 489 netdev_err(dev, "BUG! TX buffer full when queue awake!\n"); 490 return NETDEV_TX_BUSY; 491 } 492 reg_mid = at91_can_id_to_reg_mid(cf->can_id); 493 reg_mcr = ((cf->can_id & CAN_RTR_FLAG) ? AT91_MCR_MRTR : 0) | 494 (cf->can_dlc << 16) | AT91_MCR_MTCR; 495 496 /* disable MB while writing ID (see datasheet) */ 497 set_mb_mode(priv, mb, AT91_MB_MODE_DISABLED); 498 at91_write(priv, AT91_MID(mb), reg_mid); 499 set_mb_mode_prio(priv, mb, AT91_MB_MODE_TX, prio); 500 501 at91_write(priv, AT91_MDL(mb), *(u32 *)(cf->data + 0)); 502 at91_write(priv, AT91_MDH(mb), *(u32 *)(cf->data + 4)); 503 504 /* This triggers transmission */ 505 at91_write(priv, AT91_MCR(mb), reg_mcr); 506 507 stats->tx_bytes += cf->can_dlc; 508 509 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 510 can_put_echo_skb(skb, dev, mb - get_mb_tx_first(priv)); 511 512 /* 513 * we have to stop the queue and deliver all messages in case 514 * of a prio+mb counter wrap around. This is the case if 515 * tx_next buffer prio and mailbox equals 0. 516 * 517 * also stop the queue if next buffer is still in use 518 * (== not ready) 519 */ 520 priv->tx_next++; 521 if (!(at91_read(priv, AT91_MSR(get_tx_next_mb(priv))) & 522 AT91_MSR_MRDY) || 523 (priv->tx_next & get_next_mask(priv)) == 0) 524 netif_stop_queue(dev); 525 526 /* Enable interrupt for this mailbox */ 527 at91_write(priv, AT91_IER, 1 << mb); 528 529 return NETDEV_TX_OK; 530 } 531 532 /** 533 * at91_activate_rx_low - activate lower rx mailboxes 534 * @priv: a91 context 535 * 536 * Reenables the lower mailboxes for reception of new CAN messages 537 */ 538 static inline void at91_activate_rx_low(const struct at91_priv *priv) 539 { 540 u32 mask = get_mb_rx_low_mask(priv); 541 at91_write(priv, AT91_TCR, mask); 542 } 543 544 /** 545 * at91_activate_rx_mb - reactive single rx mailbox 546 * @priv: a91 context 547 * @mb: mailbox to reactivate 548 * 549 * Reenables given mailbox for reception of new CAN messages 550 */ 551 static inline void at91_activate_rx_mb(const struct at91_priv *priv, 552 unsigned int mb) 553 { 554 u32 mask = 1 << mb; 555 at91_write(priv, AT91_TCR, mask); 556 } 557 558 /** 559 * at91_rx_overflow_err - send error frame due to rx overflow 560 * @dev: net device 561 */ 562 static void at91_rx_overflow_err(struct net_device *dev) 563 { 564 struct net_device_stats *stats = &dev->stats; 565 struct sk_buff *skb; 566 struct can_frame *cf; 567 568 netdev_dbg(dev, "RX buffer overflow\n"); 569 stats->rx_over_errors++; 570 stats->rx_errors++; 571 572 skb = alloc_can_err_skb(dev, &cf); 573 if (unlikely(!skb)) 574 return; 575 576 cf->can_id |= CAN_ERR_CRTL; 577 cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; 578 netif_receive_skb(skb); 579 580 stats->rx_packets++; 581 stats->rx_bytes += cf->can_dlc; 582 } 583 584 /** 585 * at91_read_mb - read CAN msg from mailbox (lowlevel impl) 586 * @dev: net device 587 * @mb: mailbox number to read from 588 * @cf: can frame where to store message 589 * 590 * Reads a CAN message from the given mailbox and stores data into 591 * given can frame. "mb" and "cf" must be valid. 592 */ 593 static void at91_read_mb(struct net_device *dev, unsigned int mb, 594 struct can_frame *cf) 595 { 596 const struct at91_priv *priv = netdev_priv(dev); 597 u32 reg_msr, reg_mid; 598 599 reg_mid = at91_read(priv, AT91_MID(mb)); 600 if (reg_mid & AT91_MID_MIDE) 601 cf->can_id = ((reg_mid >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; 602 else 603 cf->can_id = (reg_mid >> 18) & CAN_SFF_MASK; 604 605 reg_msr = at91_read(priv, AT91_MSR(mb)); 606 cf->can_dlc = get_can_dlc((reg_msr >> 16) & 0xf); 607 608 if (reg_msr & AT91_MSR_MRTR) 609 cf->can_id |= CAN_RTR_FLAG; 610 else { 611 *(u32 *)(cf->data + 0) = at91_read(priv, AT91_MDL(mb)); 612 *(u32 *)(cf->data + 4) = at91_read(priv, AT91_MDH(mb)); 613 } 614 615 /* allow RX of extended frames */ 616 at91_write(priv, AT91_MID(mb), AT91_MID_MIDE); 617 618 if (unlikely(mb == get_mb_rx_last(priv) && reg_msr & AT91_MSR_MMI)) 619 at91_rx_overflow_err(dev); 620 } 621 622 /** 623 * at91_read_msg - read CAN message from mailbox 624 * @dev: net device 625 * @mb: mail box to read from 626 * 627 * Reads a CAN message from given mailbox, and put into linux network 628 * RX queue, does all housekeeping chores (stats, ...) 629 */ 630 static void at91_read_msg(struct net_device *dev, unsigned int mb) 631 { 632 struct net_device_stats *stats = &dev->stats; 633 struct can_frame *cf; 634 struct sk_buff *skb; 635 636 skb = alloc_can_skb(dev, &cf); 637 if (unlikely(!skb)) { 638 stats->rx_dropped++; 639 return; 640 } 641 642 at91_read_mb(dev, mb, cf); 643 netif_receive_skb(skb); 644 645 stats->rx_packets++; 646 stats->rx_bytes += cf->can_dlc; 647 648 can_led_event(dev, CAN_LED_EVENT_RX); 649 } 650 651 /** 652 * at91_poll_rx - read multiple CAN messages from mailboxes 653 * @dev: net device 654 * @quota: max number of pkgs we're allowed to receive 655 * 656 * Theory of Operation: 657 * 658 * About 3/4 of the mailboxes (get_mb_rx_first()...get_mb_rx_last()) 659 * on the chip are reserved for RX. We split them into 2 groups. The 660 * lower group ranges from get_mb_rx_first() to get_mb_rx_low_last(). 661 * 662 * Like it or not, but the chip always saves a received CAN message 663 * into the first free mailbox it finds (starting with the 664 * lowest). This makes it very difficult to read the messages in the 665 * right order from the chip. This is how we work around that problem: 666 * 667 * The first message goes into mb nr. 1 and issues an interrupt. All 668 * rx ints are disabled in the interrupt handler and a napi poll is 669 * scheduled. We read the mailbox, but do _not_ reenable the mb (to 670 * receive another message). 671 * 672 * lower mbxs upper 673 * ____^______ __^__ 674 * / \ / \ 675 * +-+-+-+-+-+-+-+-++-+-+-+-+ 676 * | |x|x|x|x|x|x|x|| | | | | 677 * +-+-+-+-+-+-+-+-++-+-+-+-+ 678 * 0 0 0 0 0 0 0 0 0 0 1 1 \ mail 679 * 0 1 2 3 4 5 6 7 8 9 0 1 / box 680 * ^ 681 * | 682 * \ 683 * unused, due to chip bug 684 * 685 * The variable priv->rx_next points to the next mailbox to read a 686 * message from. As long we're in the lower mailboxes we just read the 687 * mailbox but not reenable it. 688 * 689 * With completion of the last of the lower mailboxes, we reenable the 690 * whole first group, but continue to look for filled mailboxes in the 691 * upper mailboxes. Imagine the second group like overflow mailboxes, 692 * which takes CAN messages if the lower goup is full. While in the 693 * upper group we reenable the mailbox right after reading it. Giving 694 * the chip more room to store messages. 695 * 696 * After finishing we look again in the lower group if we've still 697 * quota. 698 * 699 */ 700 static int at91_poll_rx(struct net_device *dev, int quota) 701 { 702 struct at91_priv *priv = netdev_priv(dev); 703 u32 reg_sr = at91_read(priv, AT91_SR); 704 const unsigned long *addr = (unsigned long *)®_sr; 705 unsigned int mb; 706 int received = 0; 707 708 if (priv->rx_next > get_mb_rx_low_last(priv) && 709 reg_sr & get_mb_rx_low_mask(priv)) 710 netdev_info(dev, 711 "order of incoming frames cannot be guaranteed\n"); 712 713 again: 714 for (mb = find_next_bit(addr, get_mb_tx_first(priv), priv->rx_next); 715 mb < get_mb_tx_first(priv) && quota > 0; 716 reg_sr = at91_read(priv, AT91_SR), 717 mb = find_next_bit(addr, get_mb_tx_first(priv), ++priv->rx_next)) { 718 at91_read_msg(dev, mb); 719 720 /* reactivate mailboxes */ 721 if (mb == get_mb_rx_low_last(priv)) 722 /* all lower mailboxed, if just finished it */ 723 at91_activate_rx_low(priv); 724 else if (mb > get_mb_rx_low_last(priv)) 725 /* only the mailbox we read */ 726 at91_activate_rx_mb(priv, mb); 727 728 received++; 729 quota--; 730 } 731 732 /* upper group completed, look again in lower */ 733 if (priv->rx_next > get_mb_rx_low_last(priv) && 734 quota > 0 && mb > get_mb_rx_last(priv)) { 735 priv->rx_next = get_mb_rx_first(priv); 736 goto again; 737 } 738 739 return received; 740 } 741 742 static void at91_poll_err_frame(struct net_device *dev, 743 struct can_frame *cf, u32 reg_sr) 744 { 745 struct at91_priv *priv = netdev_priv(dev); 746 747 /* CRC error */ 748 if (reg_sr & AT91_IRQ_CERR) { 749 netdev_dbg(dev, "CERR irq\n"); 750 dev->stats.rx_errors++; 751 priv->can.can_stats.bus_error++; 752 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 753 } 754 755 /* Stuffing Error */ 756 if (reg_sr & AT91_IRQ_SERR) { 757 netdev_dbg(dev, "SERR irq\n"); 758 dev->stats.rx_errors++; 759 priv->can.can_stats.bus_error++; 760 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 761 cf->data[2] |= CAN_ERR_PROT_STUFF; 762 } 763 764 /* Acknowledgement Error */ 765 if (reg_sr & AT91_IRQ_AERR) { 766 netdev_dbg(dev, "AERR irq\n"); 767 dev->stats.tx_errors++; 768 cf->can_id |= CAN_ERR_ACK; 769 } 770 771 /* Form error */ 772 if (reg_sr & AT91_IRQ_FERR) { 773 netdev_dbg(dev, "FERR irq\n"); 774 dev->stats.rx_errors++; 775 priv->can.can_stats.bus_error++; 776 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 777 cf->data[2] |= CAN_ERR_PROT_FORM; 778 } 779 780 /* Bit Error */ 781 if (reg_sr & AT91_IRQ_BERR) { 782 netdev_dbg(dev, "BERR irq\n"); 783 dev->stats.tx_errors++; 784 priv->can.can_stats.bus_error++; 785 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; 786 cf->data[2] |= CAN_ERR_PROT_BIT; 787 } 788 } 789 790 static int at91_poll_err(struct net_device *dev, int quota, u32 reg_sr) 791 { 792 struct sk_buff *skb; 793 struct can_frame *cf; 794 795 if (quota == 0) 796 return 0; 797 798 skb = alloc_can_err_skb(dev, &cf); 799 if (unlikely(!skb)) 800 return 0; 801 802 at91_poll_err_frame(dev, cf, reg_sr); 803 netif_receive_skb(skb); 804 805 dev->stats.rx_packets++; 806 dev->stats.rx_bytes += cf->can_dlc; 807 808 return 1; 809 } 810 811 static int at91_poll(struct napi_struct *napi, int quota) 812 { 813 struct net_device *dev = napi->dev; 814 const struct at91_priv *priv = netdev_priv(dev); 815 u32 reg_sr = at91_read(priv, AT91_SR); 816 int work_done = 0; 817 818 if (reg_sr & get_irq_mb_rx(priv)) 819 work_done += at91_poll_rx(dev, quota - work_done); 820 821 /* 822 * The error bits are clear on read, 823 * so use saved value from irq handler. 824 */ 825 reg_sr |= priv->reg_sr; 826 if (reg_sr & AT91_IRQ_ERR_FRAME) 827 work_done += at91_poll_err(dev, quota - work_done, reg_sr); 828 829 if (work_done < quota) { 830 /* enable IRQs for frame errors and all mailboxes >= rx_next */ 831 u32 reg_ier = AT91_IRQ_ERR_FRAME; 832 reg_ier |= get_irq_mb_rx(priv) & ~AT91_MB_MASK(priv->rx_next); 833 834 napi_complete(napi); 835 at91_write(priv, AT91_IER, reg_ier); 836 } 837 838 return work_done; 839 } 840 841 /* 842 * theory of operation: 843 * 844 * priv->tx_echo holds the number of the oldest can_frame put for 845 * transmission into the hardware, but not yet ACKed by the CAN tx 846 * complete IRQ. 847 * 848 * We iterate from priv->tx_echo to priv->tx_next and check if the 849 * packet has been transmitted, echo it back to the CAN framework. If 850 * we discover a not yet transmitted package, stop looking for more. 851 * 852 */ 853 static void at91_irq_tx(struct net_device *dev, u32 reg_sr) 854 { 855 struct at91_priv *priv = netdev_priv(dev); 856 u32 reg_msr; 857 unsigned int mb; 858 859 /* masking of reg_sr not needed, already done by at91_irq */ 860 861 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) { 862 mb = get_tx_echo_mb(priv); 863 864 /* no event in mailbox? */ 865 if (!(reg_sr & (1 << mb))) 866 break; 867 868 /* Disable irq for this TX mailbox */ 869 at91_write(priv, AT91_IDR, 1 << mb); 870 871 /* 872 * only echo if mailbox signals us a transfer 873 * complete (MSR_MRDY). Otherwise it's a tansfer 874 * abort. "can_bus_off()" takes care about the skbs 875 * parked in the echo queue. 876 */ 877 reg_msr = at91_read(priv, AT91_MSR(mb)); 878 if (likely(reg_msr & AT91_MSR_MRDY && 879 ~reg_msr & AT91_MSR_MABT)) { 880 /* _NOTE_: subtract AT91_MB_TX_FIRST offset from mb! */ 881 can_get_echo_skb(dev, mb - get_mb_tx_first(priv)); 882 dev->stats.tx_packets++; 883 can_led_event(dev, CAN_LED_EVENT_TX); 884 } 885 } 886 887 /* 888 * restart queue if we don't have a wrap around but restart if 889 * we get a TX int for the last can frame directly before a 890 * wrap around. 891 */ 892 if ((priv->tx_next & get_next_mask(priv)) != 0 || 893 (priv->tx_echo & get_next_mask(priv)) == 0) 894 netif_wake_queue(dev); 895 } 896 897 static void at91_irq_err_state(struct net_device *dev, 898 struct can_frame *cf, enum can_state new_state) 899 { 900 struct at91_priv *priv = netdev_priv(dev); 901 u32 reg_idr = 0, reg_ier = 0; 902 struct can_berr_counter bec; 903 904 at91_get_berr_counter(dev, &bec); 905 906 switch (priv->can.state) { 907 case CAN_STATE_ERROR_ACTIVE: 908 /* 909 * from: ERROR_ACTIVE 910 * to : ERROR_WARNING, ERROR_PASSIVE, BUS_OFF 911 * => : there was a warning int 912 */ 913 if (new_state >= CAN_STATE_ERROR_WARNING && 914 new_state <= CAN_STATE_BUS_OFF) { 915 netdev_dbg(dev, "Error Warning IRQ\n"); 916 priv->can.can_stats.error_warning++; 917 918 cf->can_id |= CAN_ERR_CRTL; 919 cf->data[1] = (bec.txerr > bec.rxerr) ? 920 CAN_ERR_CRTL_TX_WARNING : 921 CAN_ERR_CRTL_RX_WARNING; 922 } 923 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 924 /* 925 * from: ERROR_ACTIVE, ERROR_WARNING 926 * to : ERROR_PASSIVE, BUS_OFF 927 * => : error passive int 928 */ 929 if (new_state >= CAN_STATE_ERROR_PASSIVE && 930 new_state <= CAN_STATE_BUS_OFF) { 931 netdev_dbg(dev, "Error Passive IRQ\n"); 932 priv->can.can_stats.error_passive++; 933 934 cf->can_id |= CAN_ERR_CRTL; 935 cf->data[1] = (bec.txerr > bec.rxerr) ? 936 CAN_ERR_CRTL_TX_PASSIVE : 937 CAN_ERR_CRTL_RX_PASSIVE; 938 } 939 break; 940 case CAN_STATE_BUS_OFF: 941 /* 942 * from: BUS_OFF 943 * to : ERROR_ACTIVE, ERROR_WARNING, ERROR_PASSIVE 944 */ 945 if (new_state <= CAN_STATE_ERROR_PASSIVE) { 946 cf->can_id |= CAN_ERR_RESTARTED; 947 948 netdev_dbg(dev, "restarted\n"); 949 priv->can.can_stats.restarts++; 950 951 netif_carrier_on(dev); 952 netif_wake_queue(dev); 953 } 954 break; 955 default: 956 break; 957 } 958 959 960 /* process state changes depending on the new state */ 961 switch (new_state) { 962 case CAN_STATE_ERROR_ACTIVE: 963 /* 964 * actually we want to enable AT91_IRQ_WARN here, but 965 * it screws up the system under certain 966 * circumstances. so just enable AT91_IRQ_ERRP, thus 967 * the "fallthrough" 968 */ 969 netdev_dbg(dev, "Error Active\n"); 970 cf->can_id |= CAN_ERR_PROT; 971 cf->data[2] = CAN_ERR_PROT_ACTIVE; 972 case CAN_STATE_ERROR_WARNING: /* fallthrough */ 973 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_BOFF; 974 reg_ier = AT91_IRQ_ERRP; 975 break; 976 case CAN_STATE_ERROR_PASSIVE: 977 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_WARN | AT91_IRQ_ERRP; 978 reg_ier = AT91_IRQ_BOFF; 979 break; 980 case CAN_STATE_BUS_OFF: 981 reg_idr = AT91_IRQ_ERRA | AT91_IRQ_ERRP | 982 AT91_IRQ_WARN | AT91_IRQ_BOFF; 983 reg_ier = 0; 984 985 cf->can_id |= CAN_ERR_BUSOFF; 986 987 netdev_dbg(dev, "bus-off\n"); 988 netif_carrier_off(dev); 989 priv->can.can_stats.bus_off++; 990 991 /* turn off chip, if restart is disabled */ 992 if (!priv->can.restart_ms) { 993 at91_chip_stop(dev, CAN_STATE_BUS_OFF); 994 return; 995 } 996 break; 997 default: 998 break; 999 } 1000 1001 at91_write(priv, AT91_IDR, reg_idr); 1002 at91_write(priv, AT91_IER, reg_ier); 1003 } 1004 1005 static int at91_get_state_by_bec(const struct net_device *dev, 1006 enum can_state *state) 1007 { 1008 struct can_berr_counter bec; 1009 int err; 1010 1011 err = at91_get_berr_counter(dev, &bec); 1012 if (err) 1013 return err; 1014 1015 if (bec.txerr < 96 && bec.rxerr < 96) 1016 *state = CAN_STATE_ERROR_ACTIVE; 1017 else if (bec.txerr < 128 && bec.rxerr < 128) 1018 *state = CAN_STATE_ERROR_WARNING; 1019 else if (bec.txerr < 256 && bec.rxerr < 256) 1020 *state = CAN_STATE_ERROR_PASSIVE; 1021 else 1022 *state = CAN_STATE_BUS_OFF; 1023 1024 return 0; 1025 } 1026 1027 1028 static void at91_irq_err(struct net_device *dev) 1029 { 1030 struct at91_priv *priv = netdev_priv(dev); 1031 struct sk_buff *skb; 1032 struct can_frame *cf; 1033 enum can_state new_state; 1034 u32 reg_sr; 1035 int err; 1036 1037 if (at91_is_sam9263(priv)) { 1038 reg_sr = at91_read(priv, AT91_SR); 1039 1040 /* we need to look at the unmasked reg_sr */ 1041 if (unlikely(reg_sr & AT91_IRQ_BOFF)) 1042 new_state = CAN_STATE_BUS_OFF; 1043 else if (unlikely(reg_sr & AT91_IRQ_ERRP)) 1044 new_state = CAN_STATE_ERROR_PASSIVE; 1045 else if (unlikely(reg_sr & AT91_IRQ_WARN)) 1046 new_state = CAN_STATE_ERROR_WARNING; 1047 else if (likely(reg_sr & AT91_IRQ_ERRA)) 1048 new_state = CAN_STATE_ERROR_ACTIVE; 1049 else { 1050 netdev_err(dev, "BUG! hardware in undefined state\n"); 1051 return; 1052 } 1053 } else { 1054 err = at91_get_state_by_bec(dev, &new_state); 1055 if (err) 1056 return; 1057 } 1058 1059 /* state hasn't changed */ 1060 if (likely(new_state == priv->can.state)) 1061 return; 1062 1063 skb = alloc_can_err_skb(dev, &cf); 1064 if (unlikely(!skb)) 1065 return; 1066 1067 at91_irq_err_state(dev, cf, new_state); 1068 netif_rx(skb); 1069 1070 dev->stats.rx_packets++; 1071 dev->stats.rx_bytes += cf->can_dlc; 1072 1073 priv->can.state = new_state; 1074 } 1075 1076 /* 1077 * interrupt handler 1078 */ 1079 static irqreturn_t at91_irq(int irq, void *dev_id) 1080 { 1081 struct net_device *dev = dev_id; 1082 struct at91_priv *priv = netdev_priv(dev); 1083 irqreturn_t handled = IRQ_NONE; 1084 u32 reg_sr, reg_imr; 1085 1086 reg_sr = at91_read(priv, AT91_SR); 1087 reg_imr = at91_read(priv, AT91_IMR); 1088 1089 /* Ignore masked interrupts */ 1090 reg_sr &= reg_imr; 1091 if (!reg_sr) 1092 goto exit; 1093 1094 handled = IRQ_HANDLED; 1095 1096 /* Receive or error interrupt? -> napi */ 1097 if (reg_sr & (get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME)) { 1098 /* 1099 * The error bits are clear on read, 1100 * save for later use. 1101 */ 1102 priv->reg_sr = reg_sr; 1103 at91_write(priv, AT91_IDR, 1104 get_irq_mb_rx(priv) | AT91_IRQ_ERR_FRAME); 1105 napi_schedule(&priv->napi); 1106 } 1107 1108 /* Transmission complete interrupt */ 1109 if (reg_sr & get_irq_mb_tx(priv)) 1110 at91_irq_tx(dev, reg_sr); 1111 1112 at91_irq_err(dev); 1113 1114 exit: 1115 return handled; 1116 } 1117 1118 static int at91_open(struct net_device *dev) 1119 { 1120 struct at91_priv *priv = netdev_priv(dev); 1121 int err; 1122 1123 clk_enable(priv->clk); 1124 1125 /* check or determine and set bittime */ 1126 err = open_candev(dev); 1127 if (err) 1128 goto out; 1129 1130 /* register interrupt handler */ 1131 if (request_irq(dev->irq, at91_irq, IRQF_SHARED, 1132 dev->name, dev)) { 1133 err = -EAGAIN; 1134 goto out_close; 1135 } 1136 1137 can_led_event(dev, CAN_LED_EVENT_OPEN); 1138 1139 /* start chip and queuing */ 1140 at91_chip_start(dev); 1141 napi_enable(&priv->napi); 1142 netif_start_queue(dev); 1143 1144 return 0; 1145 1146 out_close: 1147 close_candev(dev); 1148 out: 1149 clk_disable(priv->clk); 1150 1151 return err; 1152 } 1153 1154 /* 1155 * stop CAN bus activity 1156 */ 1157 static int at91_close(struct net_device *dev) 1158 { 1159 struct at91_priv *priv = netdev_priv(dev); 1160 1161 netif_stop_queue(dev); 1162 napi_disable(&priv->napi); 1163 at91_chip_stop(dev, CAN_STATE_STOPPED); 1164 1165 free_irq(dev->irq, dev); 1166 clk_disable(priv->clk); 1167 1168 close_candev(dev); 1169 1170 can_led_event(dev, CAN_LED_EVENT_STOP); 1171 1172 return 0; 1173 } 1174 1175 static int at91_set_mode(struct net_device *dev, enum can_mode mode) 1176 { 1177 switch (mode) { 1178 case CAN_MODE_START: 1179 at91_chip_start(dev); 1180 netif_wake_queue(dev); 1181 break; 1182 1183 default: 1184 return -EOPNOTSUPP; 1185 } 1186 1187 return 0; 1188 } 1189 1190 static const struct net_device_ops at91_netdev_ops = { 1191 .ndo_open = at91_open, 1192 .ndo_stop = at91_close, 1193 .ndo_start_xmit = at91_start_xmit, 1194 }; 1195 1196 static ssize_t at91_sysfs_show_mb0_id(struct device *dev, 1197 struct device_attribute *attr, char *buf) 1198 { 1199 struct at91_priv *priv = netdev_priv(to_net_dev(dev)); 1200 1201 if (priv->mb0_id & CAN_EFF_FLAG) 1202 return snprintf(buf, PAGE_SIZE, "0x%08x\n", priv->mb0_id); 1203 else 1204 return snprintf(buf, PAGE_SIZE, "0x%03x\n", priv->mb0_id); 1205 } 1206 1207 static ssize_t at91_sysfs_set_mb0_id(struct device *dev, 1208 struct device_attribute *attr, const char *buf, size_t count) 1209 { 1210 struct net_device *ndev = to_net_dev(dev); 1211 struct at91_priv *priv = netdev_priv(ndev); 1212 unsigned long can_id; 1213 ssize_t ret; 1214 int err; 1215 1216 rtnl_lock(); 1217 1218 if (ndev->flags & IFF_UP) { 1219 ret = -EBUSY; 1220 goto out; 1221 } 1222 1223 err = kstrtoul(buf, 0, &can_id); 1224 if (err) { 1225 ret = err; 1226 goto out; 1227 } 1228 1229 if (can_id & CAN_EFF_FLAG) 1230 can_id &= CAN_EFF_MASK | CAN_EFF_FLAG; 1231 else 1232 can_id &= CAN_SFF_MASK; 1233 1234 priv->mb0_id = can_id; 1235 ret = count; 1236 1237 out: 1238 rtnl_unlock(); 1239 return ret; 1240 } 1241 1242 static DEVICE_ATTR(mb0_id, S_IWUSR | S_IRUGO, 1243 at91_sysfs_show_mb0_id, at91_sysfs_set_mb0_id); 1244 1245 static struct attribute *at91_sysfs_attrs[] = { 1246 &dev_attr_mb0_id.attr, 1247 NULL, 1248 }; 1249 1250 static struct attribute_group at91_sysfs_attr_group = { 1251 .attrs = at91_sysfs_attrs, 1252 }; 1253 1254 #if defined(CONFIG_OF) 1255 static const struct of_device_id at91_can_dt_ids[] = { 1256 { 1257 .compatible = "atmel,at91sam9x5-can", 1258 .data = &at91_at91sam9x5_data, 1259 }, { 1260 .compatible = "atmel,at91sam9263-can", 1261 .data = &at91_at91sam9263_data, 1262 }, { 1263 /* sentinel */ 1264 } 1265 }; 1266 MODULE_DEVICE_TABLE(of, at91_can_dt_ids); 1267 #endif 1268 1269 static const struct at91_devtype_data *at91_can_get_driver_data(struct platform_device *pdev) 1270 { 1271 if (pdev->dev.of_node) { 1272 const struct of_device_id *match; 1273 1274 match = of_match_node(at91_can_dt_ids, pdev->dev.of_node); 1275 if (!match) { 1276 dev_err(&pdev->dev, "no matching node found in dtb\n"); 1277 return NULL; 1278 } 1279 return (const struct at91_devtype_data *)match->data; 1280 } 1281 return (const struct at91_devtype_data *) 1282 platform_get_device_id(pdev)->driver_data; 1283 } 1284 1285 static int at91_can_probe(struct platform_device *pdev) 1286 { 1287 const struct at91_devtype_data *devtype_data; 1288 struct net_device *dev; 1289 struct at91_priv *priv; 1290 struct resource *res; 1291 struct clk *clk; 1292 void __iomem *addr; 1293 int err, irq; 1294 1295 devtype_data = at91_can_get_driver_data(pdev); 1296 if (!devtype_data) { 1297 dev_err(&pdev->dev, "no driver data\n"); 1298 err = -ENODEV; 1299 goto exit; 1300 } 1301 1302 clk = clk_get(&pdev->dev, "can_clk"); 1303 if (IS_ERR(clk)) { 1304 dev_err(&pdev->dev, "no clock defined\n"); 1305 err = -ENODEV; 1306 goto exit; 1307 } 1308 1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1310 irq = platform_get_irq(pdev, 0); 1311 if (!res || irq <= 0) { 1312 err = -ENODEV; 1313 goto exit_put; 1314 } 1315 1316 if (!request_mem_region(res->start, 1317 resource_size(res), 1318 pdev->name)) { 1319 err = -EBUSY; 1320 goto exit_put; 1321 } 1322 1323 addr = ioremap_nocache(res->start, resource_size(res)); 1324 if (!addr) { 1325 err = -ENOMEM; 1326 goto exit_release; 1327 } 1328 1329 dev = alloc_candev(sizeof(struct at91_priv), 1330 1 << devtype_data->tx_shift); 1331 if (!dev) { 1332 err = -ENOMEM; 1333 goto exit_iounmap; 1334 } 1335 1336 dev->netdev_ops = &at91_netdev_ops; 1337 dev->irq = irq; 1338 dev->flags |= IFF_ECHO; 1339 1340 priv = netdev_priv(dev); 1341 priv->can.clock.freq = clk_get_rate(clk); 1342 priv->can.bittiming_const = &at91_bittiming_const; 1343 priv->can.do_set_mode = at91_set_mode; 1344 priv->can.do_get_berr_counter = at91_get_berr_counter; 1345 priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES; 1346 priv->dev = dev; 1347 priv->reg_base = addr; 1348 priv->devtype_data = *devtype_data; 1349 priv->clk = clk; 1350 priv->pdata = pdev->dev.platform_data; 1351 priv->mb0_id = 0x7ff; 1352 1353 netif_napi_add(dev, &priv->napi, at91_poll, get_mb_rx_num(priv)); 1354 1355 if (at91_is_sam9263(priv)) 1356 dev->sysfs_groups[0] = &at91_sysfs_attr_group; 1357 1358 dev_set_drvdata(&pdev->dev, dev); 1359 SET_NETDEV_DEV(dev, &pdev->dev); 1360 1361 err = register_candev(dev); 1362 if (err) { 1363 dev_err(&pdev->dev, "registering netdev failed\n"); 1364 goto exit_free; 1365 } 1366 1367 devm_can_led_init(dev); 1368 1369 dev_info(&pdev->dev, "device registered (reg_base=%p, irq=%d)\n", 1370 priv->reg_base, dev->irq); 1371 1372 return 0; 1373 1374 exit_free: 1375 free_candev(dev); 1376 exit_iounmap: 1377 iounmap(addr); 1378 exit_release: 1379 release_mem_region(res->start, resource_size(res)); 1380 exit_put: 1381 clk_put(clk); 1382 exit: 1383 return err; 1384 } 1385 1386 static int at91_can_remove(struct platform_device *pdev) 1387 { 1388 struct net_device *dev = platform_get_drvdata(pdev); 1389 struct at91_priv *priv = netdev_priv(dev); 1390 struct resource *res; 1391 1392 unregister_netdev(dev); 1393 1394 iounmap(priv->reg_base); 1395 1396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1397 release_mem_region(res->start, resource_size(res)); 1398 1399 clk_put(priv->clk); 1400 1401 free_candev(dev); 1402 1403 return 0; 1404 } 1405 1406 static const struct platform_device_id at91_can_id_table[] = { 1407 { 1408 .name = "at91_can", 1409 .driver_data = (kernel_ulong_t)&at91_at91sam9x5_data, 1410 }, { 1411 .name = "at91sam9x5_can", 1412 .driver_data = (kernel_ulong_t)&at91_at91sam9263_data, 1413 }, { 1414 /* sentinel */ 1415 } 1416 }; 1417 MODULE_DEVICE_TABLE(platform, at91_can_id_table); 1418 1419 static struct platform_driver at91_can_driver = { 1420 .probe = at91_can_probe, 1421 .remove = at91_can_remove, 1422 .driver = { 1423 .name = KBUILD_MODNAME, 1424 .owner = THIS_MODULE, 1425 .of_match_table = of_match_ptr(at91_can_dt_ids), 1426 }, 1427 .id_table = at91_can_id_table, 1428 }; 1429 1430 module_platform_driver(at91_can_driver); 1431 1432 MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>"); 1433 MODULE_LICENSE("GPL v2"); 1434 MODULE_DESCRIPTION(KBUILD_MODNAME " CAN netdevice driver"); 1435