1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #include <linux/mtd/spi-nor.h> 8 9 #include "core.h" 10 11 #define WINBOND_NOR_OP_RDEAR 0xc8 /* Read Extended Address Register */ 12 #define WINBOND_NOR_OP_WREAR 0xc5 /* Write Extended Address Register */ 13 14 #define WINBOND_NOR_WREAR_OP(buf) \ 15 SPI_MEM_OP(SPI_MEM_OP_CMD(WINBOND_NOR_OP_WREAR, 0), \ 16 SPI_MEM_OP_NO_ADDR, \ 17 SPI_MEM_OP_NO_DUMMY, \ 18 SPI_MEM_OP_DATA_OUT(1, buf, 0)) 19 20 static int 21 w25q256_post_bfpt_fixups(struct spi_nor *nor, 22 const struct sfdp_parameter_header *bfpt_header, 23 const struct sfdp_bfpt *bfpt) 24 { 25 /* 26 * W25Q256JV supports 4B opcodes but W25Q256FV does not. 27 * Unfortunately, Winbond has re-used the same JEDEC ID for both 28 * variants which prevents us from defining a new entry in the parts 29 * table. 30 * To differentiate between W25Q256JV and W25Q256FV check SFDP header 31 * version: only JV has JESD216A compliant structure (version 5). 32 */ 33 if (bfpt_header->major == SFDP_JESD216_MAJOR && 34 bfpt_header->minor == SFDP_JESD216A_MINOR) 35 nor->flags |= SNOR_F_4B_OPCODES; 36 37 return 0; 38 } 39 40 static const struct spi_nor_fixups w25q256_fixups = { 41 .post_bfpt = w25q256_post_bfpt_fixups, 42 }; 43 44 static const struct flash_info winbond_nor_parts[] = { 45 { 46 .id = SNOR_ID(0xef, 0x30, 0x10), 47 .name = "w25x05", 48 .size = SZ_64K, 49 .no_sfdp_flags = SECT_4K, 50 }, { 51 .id = SNOR_ID(0xef, 0x30, 0x11), 52 .name = "w25x10", 53 .size = SZ_128K, 54 .no_sfdp_flags = SECT_4K, 55 }, { 56 .id = SNOR_ID(0xef, 0x30, 0x12), 57 .name = "w25x20", 58 .size = SZ_256K, 59 .no_sfdp_flags = SECT_4K, 60 }, { 61 .id = SNOR_ID(0xef, 0x30, 0x13), 62 .name = "w25x40", 63 .size = SZ_512K, 64 .no_sfdp_flags = SECT_4K, 65 }, { 66 .id = SNOR_ID(0xef, 0x30, 0x14), 67 .name = "w25x80", 68 .size = SZ_1M, 69 .no_sfdp_flags = SECT_4K, 70 }, { 71 .id = SNOR_ID(0xef, 0x30, 0x15), 72 .name = "w25x16", 73 .size = SZ_2M, 74 .no_sfdp_flags = SECT_4K, 75 }, { 76 .id = SNOR_ID(0xef, 0x30, 0x16), 77 .name = "w25x32", 78 .size = SZ_4M, 79 .no_sfdp_flags = SECT_4K, 80 }, { 81 .id = SNOR_ID(0xef, 0x30, 0x17), 82 .name = "w25x64", 83 .size = SZ_8M, 84 .no_sfdp_flags = SECT_4K, 85 }, { 86 .id = SNOR_ID(0xef, 0x40, 0x12), 87 .name = "w25q20cl", 88 .size = SZ_256K, 89 .no_sfdp_flags = SECT_4K, 90 }, { 91 .id = SNOR_ID(0xef, 0x40, 0x14), 92 .name = "w25q80bl", 93 .size = SZ_1M, 94 .no_sfdp_flags = SECT_4K, 95 }, { 96 .id = SNOR_ID(0xef, 0x40, 0x16), 97 .name = "w25q32", 98 .size = SZ_4M, 99 .no_sfdp_flags = SECT_4K, 100 }, { 101 .id = SNOR_ID(0xef, 0x40, 0x17), 102 .name = "w25q64", 103 .size = SZ_8M, 104 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 105 }, { 106 .id = SNOR_ID(0xef, 0x40, 0x18), 107 .name = "w25q128", 108 .size = SZ_16M, 109 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 110 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 111 }, { 112 .id = SNOR_ID(0xef, 0x40, 0x19), 113 .name = "w25q256", 114 .size = SZ_32M, 115 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 116 .fixups = &w25q256_fixups, 117 }, { 118 .id = SNOR_ID(0xef, 0x40, 0x20), 119 .name = "w25q512jvq", 120 .size = SZ_64M, 121 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 122 }, { 123 .id = SNOR_ID(0xef, 0x50, 0x12), 124 .name = "w25q20bw", 125 .size = SZ_256K, 126 .no_sfdp_flags = SECT_4K, 127 }, { 128 .id = SNOR_ID(0xef, 0x50, 0x14), 129 .name = "w25q80", 130 .size = SZ_1M, 131 .no_sfdp_flags = SECT_4K, 132 }, { 133 .id = SNOR_ID(0xef, 0x60, 0x12), 134 .name = "w25q20ew", 135 .size = SZ_256K, 136 .no_sfdp_flags = SECT_4K, 137 }, { 138 .id = SNOR_ID(0xef, 0x60, 0x15), 139 .name = "w25q16dw", 140 .size = SZ_2M, 141 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 142 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 143 }, { 144 .id = SNOR_ID(0xef, 0x60, 0x16), 145 .name = "w25q32dw", 146 .size = SZ_4M, 147 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 148 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 149 .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), 150 }, { 151 .id = SNOR_ID(0xef, 0x60, 0x17), 152 .name = "w25q64dw", 153 .size = SZ_8M, 154 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 155 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 156 }, { 157 .id = SNOR_ID(0xef, 0x60, 0x18), 158 .name = "w25q128fw", 159 .size = SZ_16M, 160 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 161 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 162 }, { 163 .id = SNOR_ID(0xef, 0x60, 0x19), 164 .name = "w25q256jw", 165 .size = SZ_32M, 166 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 167 }, { 168 .id = SNOR_ID(0xef, 0x60, 0x20), 169 .name = "w25q512nwq", 170 .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), 171 }, { 172 .id = SNOR_ID(0xef, 0x70, 0x15), 173 .name = "w25q16jv-im/jm", 174 .size = SZ_2M, 175 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 176 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 177 }, { 178 .id = SNOR_ID(0xef, 0x70, 0x16), 179 .name = "w25q32jv", 180 .size = SZ_4M, 181 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 182 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 183 }, { 184 .id = SNOR_ID(0xef, 0x70, 0x17), 185 .name = "w25q64jvm", 186 .size = SZ_8M, 187 .no_sfdp_flags = SECT_4K, 188 }, { 189 .id = SNOR_ID(0xef, 0x70, 0x18), 190 .name = "w25q128jv", 191 .size = SZ_16M, 192 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 193 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 194 }, { 195 .id = SNOR_ID(0xef, 0x70, 0x19), 196 .name = "w25q256jvm", 197 }, { 198 .id = SNOR_ID(0xef, 0x71, 0x19), 199 .name = "w25m512jv", 200 .size = SZ_64M, 201 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 202 }, { 203 .id = SNOR_ID(0xef, 0x80, 0x16), 204 .name = "w25q32jwm", 205 .size = SZ_4M, 206 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 207 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 208 .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), 209 }, { 210 .id = SNOR_ID(0xef, 0x80, 0x17), 211 .name = "w25q64jwm", 212 .size = SZ_8M, 213 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 214 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 215 }, { 216 .id = SNOR_ID(0xef, 0x80, 0x18), 217 .name = "w25q128jwm", 218 .size = SZ_16M, 219 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 220 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 221 }, { 222 .id = SNOR_ID(0xef, 0x80, 0x19), 223 .name = "w25q256jwm", 224 .size = SZ_32M, 225 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, 226 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, 227 }, { 228 .id = SNOR_ID(0xef, 0x80, 0x20), 229 .name = "w25q512nwm", 230 .otp = SNOR_OTP(256, 3, 0x1000, 0x1000), 231 }, 232 }; 233 234 /** 235 * winbond_nor_write_ear() - Write Extended Address Register. 236 * @nor: pointer to 'struct spi_nor'. 237 * @ear: value to write to the Extended Address Register. 238 * 239 * Return: 0 on success, -errno otherwise. 240 */ 241 static int winbond_nor_write_ear(struct spi_nor *nor, u8 ear) 242 { 243 int ret; 244 245 nor->bouncebuf[0] = ear; 246 247 if (nor->spimem) { 248 struct spi_mem_op op = WINBOND_NOR_WREAR_OP(nor->bouncebuf); 249 250 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); 251 252 ret = spi_mem_exec_op(nor->spimem, &op); 253 } else { 254 ret = spi_nor_controller_ops_write_reg(nor, 255 WINBOND_NOR_OP_WREAR, 256 nor->bouncebuf, 1); 257 } 258 259 if (ret) 260 dev_dbg(nor->dev, "error %d writing EAR\n", ret); 261 262 return ret; 263 } 264 265 /** 266 * winbond_nor_set_4byte_addr_mode() - Set 4-byte address mode for Winbond 267 * flashes. 268 * @nor: pointer to 'struct spi_nor'. 269 * @enable: true to enter the 4-byte address mode, false to exit the 4-byte 270 * address mode. 271 * 272 * Return: 0 on success, -errno otherwise. 273 */ 274 static int winbond_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable) 275 { 276 int ret; 277 278 ret = spi_nor_set_4byte_addr_mode_en4b_ex4b(nor, enable); 279 if (ret || enable) 280 return ret; 281 282 /* 283 * On Winbond W25Q256FV, leaving 4byte mode causes the Extended Address 284 * Register to be set to 1, so all 3-byte-address reads come from the 285 * second 16M. We must clear the register to enable normal behavior. 286 */ 287 ret = spi_nor_write_enable(nor); 288 if (ret) 289 return ret; 290 291 ret = winbond_nor_write_ear(nor, 0); 292 if (ret) 293 return ret; 294 295 return spi_nor_write_disable(nor); 296 } 297 298 static const struct spi_nor_otp_ops winbond_nor_otp_ops = { 299 .read = spi_nor_otp_read_secr, 300 .write = spi_nor_otp_write_secr, 301 .erase = spi_nor_otp_erase_secr, 302 .lock = spi_nor_otp_lock_sr2, 303 .is_locked = spi_nor_otp_is_locked_sr2, 304 }; 305 306 static int winbond_nor_late_init(struct spi_nor *nor) 307 { 308 struct spi_nor_flash_parameter *params = nor->params; 309 310 if (params->otp.org) 311 params->otp.ops = &winbond_nor_otp_ops; 312 313 /* 314 * Winbond seems to require that the Extended Address Register to be set 315 * to zero when exiting the 4-Byte Address Mode, at least for W25Q256FV. 316 * This requirement is not described in the JESD216 SFDP standard, thus 317 * it is Winbond specific. Since we do not know if other Winbond flashes 318 * have the same requirement, play safe and overwrite the method parsed 319 * from BFPT, if any. 320 */ 321 params->set_4byte_addr_mode = winbond_nor_set_4byte_addr_mode; 322 323 return 0; 324 } 325 326 static const struct spi_nor_fixups winbond_nor_fixups = { 327 .late_init = winbond_nor_late_init, 328 }; 329 330 const struct spi_nor_manufacturer spi_nor_winbond = { 331 .name = "winbond", 332 .parts = winbond_nor_parts, 333 .nparts = ARRAY_SIZE(winbond_nor_parts), 334 .fixups = &winbond_nor_fixups, 335 }; 336