1 /* 2 * Copyright (C) 2017 Free Electrons 3 * Copyright (C) 2017 NextThing Co 4 * 5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include <linux/sizes.h> 19 #include <linux/slab.h> 20 21 #include "internals.h" 22 23 #define NAND_HYNIX_CMD_SET_PARAMS 0x36 24 #define NAND_HYNIX_CMD_APPLY_PARAMS 0x16 25 26 #define NAND_HYNIX_1XNM_RR_REPEAT 8 27 28 /** 29 * struct hynix_read_retry - read-retry data 30 * @nregs: number of register to set when applying a new read-retry mode 31 * @regs: register offsets (NAND chip dependent) 32 * @values: array of values to set in registers. The array size is equal to 33 * (nregs * nmodes) 34 */ 35 struct hynix_read_retry { 36 int nregs; 37 const u8 *regs; 38 u8 values[0]; 39 }; 40 41 /** 42 * struct hynix_nand - private Hynix NAND struct 43 * @nand_technology: manufacturing process expressed in picometer 44 * @read_retry: read-retry information 45 */ 46 struct hynix_nand { 47 const struct hynix_read_retry *read_retry; 48 }; 49 50 /** 51 * struct hynix_read_retry_otp - structure describing how the read-retry OTP 52 * area 53 * @nregs: number of hynix private registers to set before reading the reading 54 * the OTP area 55 * @regs: registers that should be configured 56 * @values: values that should be set in regs 57 * @page: the address to pass to the READ_PAGE command. Depends on the NAND 58 * chip 59 * @size: size of the read-retry OTP section 60 */ 61 struct hynix_read_retry_otp { 62 int nregs; 63 const u8 *regs; 64 const u8 *values; 65 int page; 66 int size; 67 }; 68 69 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip) 70 { 71 u8 jedecid[5] = { }; 72 int ret; 73 74 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid)); 75 if (ret) 76 return false; 77 78 return !strncmp("JEDEC", jedecid, sizeof(jedecid)); 79 } 80 81 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd) 82 { 83 if (nand_has_exec_op(chip)) { 84 struct nand_op_instr instrs[] = { 85 NAND_OP_CMD(cmd, 0), 86 }; 87 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 88 89 return nand_exec_op(chip, &op); 90 } 91 92 chip->legacy.cmdfunc(chip, cmd, -1, -1); 93 94 return 0; 95 } 96 97 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val) 98 { 99 u16 column = ((u16)addr << 8) | addr; 100 101 if (nand_has_exec_op(chip)) { 102 struct nand_op_instr instrs[] = { 103 NAND_OP_ADDR(1, &addr, 0), 104 NAND_OP_8BIT_DATA_OUT(1, &val, 0), 105 }; 106 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); 107 108 return nand_exec_op(chip, &op); 109 } 110 111 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1); 112 chip->legacy.write_byte(chip, val); 113 114 return 0; 115 } 116 117 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode) 118 { 119 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); 120 const u8 *values; 121 int i, ret; 122 123 values = hynix->read_retry->values + 124 (retry_mode * hynix->read_retry->nregs); 125 126 /* Enter 'Set Hynix Parameters' mode */ 127 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); 128 if (ret) 129 return ret; 130 131 /* 132 * Configure the NAND in the requested read-retry mode. 133 * This is done by setting pre-defined values in internal NAND 134 * registers. 135 * 136 * The set of registers is NAND specific, and the values are either 137 * predefined or extracted from an OTP area on the NAND (values are 138 * probably tweaked at production in this case). 139 */ 140 for (i = 0; i < hynix->read_retry->nregs; i++) { 141 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i], 142 values[i]); 143 if (ret) 144 return ret; 145 } 146 147 /* Apply the new settings. */ 148 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); 149 } 150 151 /** 152 * hynix_get_majority - get the value that is occurring the most in a given 153 * set of values 154 * @in: the array of values to test 155 * @repeat: the size of the in array 156 * @out: pointer used to store the output value 157 * 158 * This function implements the 'majority check' logic that is supposed to 159 * overcome the unreliability of MLC NANDs when reading the OTP area storing 160 * the read-retry parameters. 161 * 162 * It's based on a pretty simple assumption: if we repeat the same value 163 * several times and then take the one that is occurring the most, we should 164 * find the correct value. 165 * Let's hope this dummy algorithm prevents us from losing the read-retry 166 * parameters. 167 */ 168 static int hynix_get_majority(const u8 *in, int repeat, u8 *out) 169 { 170 int i, j, half = repeat / 2; 171 172 /* 173 * We only test the first half of the in array because we must ensure 174 * that the value is at least occurring repeat / 2 times. 175 * 176 * This loop is suboptimal since we may count the occurrences of the 177 * same value several time, but we are doing that on small sets, which 178 * makes it acceptable. 179 */ 180 for (i = 0; i < half; i++) { 181 int cnt = 0; 182 u8 val = in[i]; 183 184 /* Count all values that are matching the one at index i. */ 185 for (j = i + 1; j < repeat; j++) { 186 if (in[j] == val) 187 cnt++; 188 } 189 190 /* We found a value occurring more than repeat / 2. */ 191 if (cnt > half) { 192 *out = val; 193 return 0; 194 } 195 } 196 197 return -EIO; 198 } 199 200 static int hynix_read_rr_otp(struct nand_chip *chip, 201 const struct hynix_read_retry_otp *info, 202 void *buf) 203 { 204 int i, ret; 205 206 ret = nand_reset_op(chip); 207 if (ret) 208 return ret; 209 210 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); 211 if (ret) 212 return ret; 213 214 for (i = 0; i < info->nregs; i++) { 215 ret = hynix_nand_reg_write_op(chip, info->regs[i], 216 info->values[i]); 217 if (ret) 218 return ret; 219 } 220 221 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); 222 if (ret) 223 return ret; 224 225 /* Sequence to enter OTP mode? */ 226 ret = hynix_nand_cmd_op(chip, 0x17); 227 if (ret) 228 return ret; 229 230 ret = hynix_nand_cmd_op(chip, 0x4); 231 if (ret) 232 return ret; 233 234 ret = hynix_nand_cmd_op(chip, 0x19); 235 if (ret) 236 return ret; 237 238 /* Now read the page */ 239 ret = nand_read_page_op(chip, info->page, 0, buf, info->size); 240 if (ret) 241 return ret; 242 243 /* Put everything back to normal */ 244 ret = nand_reset_op(chip); 245 if (ret) 246 return ret; 247 248 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); 249 if (ret) 250 return ret; 251 252 ret = hynix_nand_reg_write_op(chip, 0x38, 0); 253 if (ret) 254 return ret; 255 256 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); 257 if (ret) 258 return ret; 259 260 return nand_read_page_op(chip, 0, 0, NULL, 0); 261 } 262 263 #define NAND_HYNIX_1XNM_RR_COUNT_OFFS 0 264 #define NAND_HYNIX_1XNM_RR_REG_COUNT_OFFS 8 265 #define NAND_HYNIX_1XNM_RR_SET_OFFS(x, setsize, inv) \ 266 (16 + ((((x) * 2) + ((inv) ? 1 : 0)) * (setsize))) 267 268 static int hynix_mlc_1xnm_rr_value(const u8 *buf, int nmodes, int nregs, 269 int mode, int reg, bool inv, u8 *val) 270 { 271 u8 tmp[NAND_HYNIX_1XNM_RR_REPEAT]; 272 int val_offs = (mode * nregs) + reg; 273 int set_size = nmodes * nregs; 274 int i, ret; 275 276 for (i = 0; i < NAND_HYNIX_1XNM_RR_REPEAT; i++) { 277 int set_offs = NAND_HYNIX_1XNM_RR_SET_OFFS(i, set_size, inv); 278 279 tmp[i] = buf[val_offs + set_offs]; 280 } 281 282 ret = hynix_get_majority(tmp, NAND_HYNIX_1XNM_RR_REPEAT, val); 283 if (ret) 284 return ret; 285 286 if (inv) 287 *val = ~*val; 288 289 return 0; 290 } 291 292 static u8 hynix_1xnm_mlc_read_retry_regs[] = { 293 0xcc, 0xbf, 0xaa, 0xab, 0xcd, 0xad, 0xae, 0xaf 294 }; 295 296 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip, 297 const struct hynix_read_retry_otp *info) 298 { 299 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); 300 struct hynix_read_retry *rr = NULL; 301 int ret, i, j; 302 u8 nregs, nmodes; 303 u8 *buf; 304 305 buf = kmalloc(info->size, GFP_KERNEL); 306 if (!buf) 307 return -ENOMEM; 308 309 ret = hynix_read_rr_otp(chip, info, buf); 310 if (ret) 311 goto out; 312 313 ret = hynix_get_majority(buf, NAND_HYNIX_1XNM_RR_REPEAT, 314 &nmodes); 315 if (ret) 316 goto out; 317 318 ret = hynix_get_majority(buf + NAND_HYNIX_1XNM_RR_REPEAT, 319 NAND_HYNIX_1XNM_RR_REPEAT, 320 &nregs); 321 if (ret) 322 goto out; 323 324 rr = kzalloc(sizeof(*rr) + (nregs * nmodes), GFP_KERNEL); 325 if (!rr) { 326 ret = -ENOMEM; 327 goto out; 328 } 329 330 for (i = 0; i < nmodes; i++) { 331 for (j = 0; j < nregs; j++) { 332 u8 *val = rr->values + (i * nregs); 333 334 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j, 335 false, val); 336 if (!ret) 337 continue; 338 339 ret = hynix_mlc_1xnm_rr_value(buf, nmodes, nregs, i, j, 340 true, val); 341 if (ret) 342 goto out; 343 } 344 } 345 346 rr->nregs = nregs; 347 rr->regs = hynix_1xnm_mlc_read_retry_regs; 348 hynix->read_retry = rr; 349 chip->setup_read_retry = hynix_nand_setup_read_retry; 350 chip->read_retries = nmodes; 351 352 out: 353 kfree(buf); 354 355 if (ret) 356 kfree(rr); 357 358 return ret; 359 } 360 361 static const u8 hynix_mlc_1xnm_rr_otp_regs[] = { 0x38 }; 362 static const u8 hynix_mlc_1xnm_rr_otp_values[] = { 0x52 }; 363 364 static const struct hynix_read_retry_otp hynix_mlc_1xnm_rr_otps[] = { 365 { 366 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs), 367 .regs = hynix_mlc_1xnm_rr_otp_regs, 368 .values = hynix_mlc_1xnm_rr_otp_values, 369 .page = 0x21f, 370 .size = 784 371 }, 372 { 373 .nregs = ARRAY_SIZE(hynix_mlc_1xnm_rr_otp_regs), 374 .regs = hynix_mlc_1xnm_rr_otp_regs, 375 .values = hynix_mlc_1xnm_rr_otp_values, 376 .page = 0x200, 377 .size = 528, 378 }, 379 }; 380 381 static int hynix_nand_rr_init(struct nand_chip *chip) 382 { 383 int i, ret = 0; 384 bool valid_jedecid; 385 386 valid_jedecid = hynix_nand_has_valid_jedecid(chip); 387 388 /* 389 * We only support read-retry for 1xnm NANDs, and those NANDs all 390 * expose a valid JEDEC ID. 391 */ 392 if (valid_jedecid) { 393 u8 nand_tech = chip->id.data[5] >> 4; 394 395 /* 1xnm technology */ 396 if (nand_tech == 4) { 397 for (i = 0; i < ARRAY_SIZE(hynix_mlc_1xnm_rr_otps); 398 i++) { 399 /* 400 * FIXME: Hynix recommend to copy the 401 * read-retry OTP area into a normal page. 402 */ 403 ret = hynix_mlc_1xnm_rr_init(chip, 404 hynix_mlc_1xnm_rr_otps); 405 if (!ret) 406 break; 407 } 408 } 409 } 410 411 if (ret) 412 pr_warn("failed to initialize read-retry infrastructure"); 413 414 return 0; 415 } 416 417 static void hynix_nand_extract_oobsize(struct nand_chip *chip, 418 bool valid_jedecid) 419 { 420 struct mtd_info *mtd = nand_to_mtd(chip); 421 u8 oobsize; 422 423 oobsize = ((chip->id.data[3] >> 2) & 0x3) | 424 ((chip->id.data[3] >> 4) & 0x4); 425 426 if (valid_jedecid) { 427 switch (oobsize) { 428 case 0: 429 mtd->oobsize = 2048; 430 break; 431 case 1: 432 mtd->oobsize = 1664; 433 break; 434 case 2: 435 mtd->oobsize = 1024; 436 break; 437 case 3: 438 mtd->oobsize = 640; 439 break; 440 default: 441 /* 442 * We should never reach this case, but if that 443 * happens, this probably means Hynix decided to use 444 * a different extended ID format, and we should find 445 * a way to support it. 446 */ 447 WARN(1, "Invalid OOB size"); 448 break; 449 } 450 } else { 451 switch (oobsize) { 452 case 0: 453 mtd->oobsize = 128; 454 break; 455 case 1: 456 mtd->oobsize = 224; 457 break; 458 case 2: 459 mtd->oobsize = 448; 460 break; 461 case 3: 462 mtd->oobsize = 64; 463 break; 464 case 4: 465 mtd->oobsize = 32; 466 break; 467 case 5: 468 mtd->oobsize = 16; 469 break; 470 case 6: 471 mtd->oobsize = 640; 472 break; 473 default: 474 /* 475 * We should never reach this case, but if that 476 * happens, this probably means Hynix decided to use 477 * a different extended ID format, and we should find 478 * a way to support it. 479 */ 480 WARN(1, "Invalid OOB size"); 481 break; 482 } 483 484 /* 485 * The datasheet of H27UCG8T2BTR mentions that the "Redundant 486 * Area Size" is encoded "per 8KB" (page size). This chip uses 487 * a page size of 16KiB. The datasheet mentions an OOB size of 488 * 1.280 bytes, but the OOB size encoded in the ID bytes (using 489 * the existing logic above) is 640 bytes. 490 * Update the OOB size for this chip by taking the value 491 * determined above and scaling it to the actual page size (so 492 * the actual OOB size for this chip is: 640 * 16k / 8k). 493 */ 494 if (chip->id.data[1] == 0xde) 495 mtd->oobsize *= mtd->writesize / SZ_8K; 496 } 497 } 498 499 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, 500 bool valid_jedecid) 501 { 502 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; 503 504 if (valid_jedecid) { 505 /* Reference: H27UCG8T2E datasheet */ 506 chip->ecc_step_ds = 1024; 507 508 switch (ecc_level) { 509 case 0: 510 chip->ecc_step_ds = 0; 511 chip->ecc_strength_ds = 0; 512 break; 513 case 1: 514 chip->ecc_strength_ds = 4; 515 break; 516 case 2: 517 chip->ecc_strength_ds = 24; 518 break; 519 case 3: 520 chip->ecc_strength_ds = 32; 521 break; 522 case 4: 523 chip->ecc_strength_ds = 40; 524 break; 525 case 5: 526 chip->ecc_strength_ds = 50; 527 break; 528 case 6: 529 chip->ecc_strength_ds = 60; 530 break; 531 default: 532 /* 533 * We should never reach this case, but if that 534 * happens, this probably means Hynix decided to use 535 * a different extended ID format, and we should find 536 * a way to support it. 537 */ 538 WARN(1, "Invalid ECC requirements"); 539 } 540 } else { 541 /* 542 * The ECC requirements field meaning depends on the 543 * NAND technology. 544 */ 545 u8 nand_tech = chip->id.data[5] & 0x7; 546 547 if (nand_tech < 3) { 548 /* > 26nm, reference: H27UBG8T2A datasheet */ 549 if (ecc_level < 5) { 550 chip->ecc_step_ds = 512; 551 chip->ecc_strength_ds = 1 << ecc_level; 552 } else if (ecc_level < 7) { 553 if (ecc_level == 5) 554 chip->ecc_step_ds = 2048; 555 else 556 chip->ecc_step_ds = 1024; 557 chip->ecc_strength_ds = 24; 558 } else { 559 /* 560 * We should never reach this case, but if that 561 * happens, this probably means Hynix decided 562 * to use a different extended ID format, and 563 * we should find a way to support it. 564 */ 565 WARN(1, "Invalid ECC requirements"); 566 } 567 } else { 568 /* <= 26nm, reference: H27UBG8T2B datasheet */ 569 if (!ecc_level) { 570 chip->ecc_step_ds = 0; 571 chip->ecc_strength_ds = 0; 572 } else if (ecc_level < 5) { 573 chip->ecc_step_ds = 512; 574 chip->ecc_strength_ds = 1 << (ecc_level - 1); 575 } else { 576 chip->ecc_step_ds = 1024; 577 chip->ecc_strength_ds = 24 + 578 (8 * (ecc_level - 5)); 579 } 580 } 581 } 582 } 583 584 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip, 585 bool valid_jedecid) 586 { 587 u8 nand_tech; 588 589 /* We need scrambling on all TLC NANDs*/ 590 if (chip->bits_per_cell > 2) 591 chip->options |= NAND_NEED_SCRAMBLING; 592 593 /* And on MLC NANDs with sub-3xnm process */ 594 if (valid_jedecid) { 595 nand_tech = chip->id.data[5] >> 4; 596 597 /* < 3xnm */ 598 if (nand_tech > 0) 599 chip->options |= NAND_NEED_SCRAMBLING; 600 } else { 601 nand_tech = chip->id.data[5] & 0x7; 602 603 /* < 32nm */ 604 if (nand_tech > 2) 605 chip->options |= NAND_NEED_SCRAMBLING; 606 } 607 } 608 609 static void hynix_nand_decode_id(struct nand_chip *chip) 610 { 611 struct mtd_info *mtd = nand_to_mtd(chip); 612 bool valid_jedecid; 613 u8 tmp; 614 615 /* 616 * Exclude all SLC NANDs from this advanced detection scheme. 617 * According to the ranges defined in several datasheets, it might 618 * appear that even SLC NANDs could fall in this extended ID scheme. 619 * If that the case rework the test to let SLC NANDs go through the 620 * detection process. 621 */ 622 if (chip->id.len < 6 || nand_is_slc(chip)) { 623 nand_decode_ext_id(chip); 624 return; 625 } 626 627 /* Extract pagesize */ 628 mtd->writesize = 2048 << (chip->id.data[3] & 0x03); 629 630 tmp = (chip->id.data[3] >> 4) & 0x3; 631 /* 632 * When bit7 is set that means we start counting at 1MiB, otherwise 633 * we start counting at 128KiB and shift this value the content of 634 * ID[3][4:5]. 635 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in 636 * this case the erasesize is set to 768KiB. 637 */ 638 if (chip->id.data[3] & 0x80) 639 mtd->erasesize = SZ_1M << tmp; 640 else if (tmp == 3) 641 mtd->erasesize = SZ_512K + SZ_256K; 642 else 643 mtd->erasesize = SZ_128K << tmp; 644 645 /* 646 * Modern Toggle DDR NANDs have a valid JEDECID even though they are 647 * not exposing a valid JEDEC parameter table. 648 * These NANDs use a different NAND ID scheme. 649 */ 650 valid_jedecid = hynix_nand_has_valid_jedecid(chip); 651 652 hynix_nand_extract_oobsize(chip, valid_jedecid); 653 hynix_nand_extract_ecc_requirements(chip, valid_jedecid); 654 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid); 655 } 656 657 static void hynix_nand_cleanup(struct nand_chip *chip) 658 { 659 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); 660 661 if (!hynix) 662 return; 663 664 kfree(hynix->read_retry); 665 kfree(hynix); 666 nand_set_manufacturer_data(chip, NULL); 667 } 668 669 static int hynix_nand_init(struct nand_chip *chip) 670 { 671 struct hynix_nand *hynix; 672 int ret; 673 674 if (!nand_is_slc(chip)) 675 chip->bbt_options |= NAND_BBT_SCANLASTPAGE; 676 else 677 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE; 678 679 hynix = kzalloc(sizeof(*hynix), GFP_KERNEL); 680 if (!hynix) 681 return -ENOMEM; 682 683 nand_set_manufacturer_data(chip, hynix); 684 685 ret = hynix_nand_rr_init(chip); 686 if (ret) 687 hynix_nand_cleanup(chip); 688 689 return ret; 690 } 691 692 const struct nand_manufacturer_ops hynix_nand_manuf_ops = { 693 .detect = hynix_nand_decode_id, 694 .init = hynix_nand_init, 695 .cleanup = hynix_nand_cleanup, 696 }; 697