1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2023-2026 Intel Corporation */ 3 #ifndef _ISSEI_HW_HECI_REGS_H_ 4 #define _ISSEI_HW_HECI_REGS_H_ 5 6 #include <linux/bits.h> 7 8 /* H_CB_WW - Host Circular Buffer (CB) Write Window register */ 9 #define H_CB_WW 0x0 10 /* H_CSR - Host Control Status register */ 11 #define H_CSR 0x4 12 #define H_CSR_CBD GENMASK(31, 24) /* Host Circular Buffer Depth */ 13 #define H_CSR_CBWP GENMASK(23, 16) /* Host Circular Buffer Write Pointer */ 14 #define H_CSR_CBRP GENMASK(15, 8) /* Host Circular Buffer Read Pointer */ 15 #define H_CSR_RST BIT(4) /* Host Reset */ 16 #define H_CSR_RDY BIT(3) /* Host Ready */ 17 #define H_CSR_IG BIT(2) /* Host Interrupt Generate */ 18 #define H_CSR_IS BIT(1) /* Host Interrupt Status */ 19 #define H_CSR_IE BIT(0) /* Host Interrupt Enable */ 20 /* FW_CB_RW - FW Circular Buffer Read Window register (read only) */ 21 #define FW_CB_RW 0x8 22 /* FW_CSR_HA - FW Control Status Host Access register (read only) */ 23 #define FW_CSR_HA 0xC 24 #define FW_CSR_CBD GENMASK(31, 24) /* FW CB (Circular Buffer) Depth */ 25 #define FW_CSR_CBWP GENMASK(23, 16) /* FW CB Write Pointer */ 26 #define FW_CSR_CBRP GENMASK(15, 8) /* FW CB Read Pointer */ 27 #define FW_CSR_RST BIT(4) /* FW Reset */ 28 #define FW_CSR_RDY BIT(3) /* FW Ready */ 29 #define FW_CSR_IG BIT(2) /* FW Interrupt Generate */ 30 #define FW_CSR_IS BIT(1) /* FW Interrupt Status */ 31 #define FW_CSR_IE BIT(0) /* FW Interrupt Enable */ 32 33 #define CB_SLOT_SIZE sizeof(u32) /* Circular Buffer windows size */ 34 35 #endif /* _ISSEI_HW_HECI_REGS_H_ */ 36