1*2401dc4dSSumit Gupta /* SPDX-License-Identifier: GPL-2.0-only */ 2*2401dc4dSSumit Gupta /* Copyright (C) 2025 NVIDIA CORPORATION. All rights reserved. */ 3*2401dc4dSSumit Gupta 4*2401dc4dSSumit Gupta #ifndef MEMORY_TEGRA_TEGRA264_BWMGR_H 5*2401dc4dSSumit Gupta #define MEMORY_TEGRA_TEGRA264_BWMGR_H 6*2401dc4dSSumit Gupta 7*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_ICC_PRIMARY 1 8*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_DEBUG 2 9*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER0 3 10*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER1 4 11*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER2 5 12*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER3 6 13*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER4 7 14*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER5 8 15*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CPU_CLUSTER6 9 16*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_CACTMON 10 17*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_DISPLAY 11 18*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_VI 12 19*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_APE 13 20*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_VIFAL 14 21*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_GPU 15 22*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_EQOS 16 23*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_0 17 24*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_1 18 25*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_2 19 26*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_3 20 27*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_4 21 28*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PCIE_5 22 29*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_SDMMC_1 23 30*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_SDMMC_2 24 31*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_NVDEC 25 32*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_NVENC 26 33*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_NVJPG_0 27 34*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_NVJPG_1 28 35*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_OFAA 29 36*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_XUSB_HOST 30 37*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_XUSB_DEV 31 38*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_TSEC 32 39*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_VIC 33 40*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_APEDMA 34 41*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_SE 35 42*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_ISP 36 43*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_HDA 37 44*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_VI2FAL 38 45*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_VI2 39 46*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_RCE 40 47*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_PVA 41 48*2401dc4dSSumit Gupta #define TEGRA264_BWMGR_NVPMODEL 42 49*2401dc4dSSumit Gupta 50*2401dc4dSSumit Gupta #endif 51