1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (C) 2025 NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef MEMORY_TEGRA_TEGRA264_BWMGR_H 5 #define MEMORY_TEGRA_TEGRA264_BWMGR_H 6 7 #define TEGRA264_BWMGR_ICC_PRIMARY 1 8 #define TEGRA264_BWMGR_DEBUG 2 9 #define TEGRA264_BWMGR_CPU_CLUSTER0 3 10 #define TEGRA264_BWMGR_CPU_CLUSTER1 4 11 #define TEGRA264_BWMGR_CPU_CLUSTER2 5 12 #define TEGRA264_BWMGR_CPU_CLUSTER3 6 13 #define TEGRA264_BWMGR_CPU_CLUSTER4 7 14 #define TEGRA264_BWMGR_CPU_CLUSTER5 8 15 #define TEGRA264_BWMGR_CPU_CLUSTER6 9 16 #define TEGRA264_BWMGR_CACTMON 10 17 #define TEGRA264_BWMGR_DISPLAY 11 18 #define TEGRA264_BWMGR_VI 12 19 #define TEGRA264_BWMGR_APE 13 20 #define TEGRA264_BWMGR_VIFAL 14 21 #define TEGRA264_BWMGR_GPU 15 22 #define TEGRA264_BWMGR_EQOS 16 23 #define TEGRA264_BWMGR_PCIE_0 17 24 #define TEGRA264_BWMGR_PCIE_1 18 25 #define TEGRA264_BWMGR_PCIE_2 19 26 #define TEGRA264_BWMGR_PCIE_3 20 27 #define TEGRA264_BWMGR_PCIE_4 21 28 #define TEGRA264_BWMGR_PCIE_5 22 29 #define TEGRA264_BWMGR_SDMMC_1 23 30 #define TEGRA264_BWMGR_SDMMC_2 24 31 #define TEGRA264_BWMGR_NVDEC 25 32 #define TEGRA264_BWMGR_NVENC 26 33 #define TEGRA264_BWMGR_NVJPG_0 27 34 #define TEGRA264_BWMGR_NVJPG_1 28 35 #define TEGRA264_BWMGR_OFAA 29 36 #define TEGRA264_BWMGR_XUSB_HOST 30 37 #define TEGRA264_BWMGR_XUSB_DEV 31 38 #define TEGRA264_BWMGR_TSEC 32 39 #define TEGRA264_BWMGR_VIC 33 40 #define TEGRA264_BWMGR_APEDMA 34 41 #define TEGRA264_BWMGR_SE 35 42 #define TEGRA264_BWMGR_ISP 36 43 #define TEGRA264_BWMGR_HDA 37 44 #define TEGRA264_BWMGR_VI2FAL 38 45 #define TEGRA264_BWMGR_VI2 39 46 #define TEGRA264_BWMGR_RCE 40 47 #define TEGRA264_BWMGR_PVA 41 48 #define TEGRA264_BWMGR_NVPMODEL 42 49 50 #endif 51