xref: /linux/drivers/memory/tegra/tegra238.c (revision 9611c0ce215a66770ccbe5c126bf57ba8c31bcad) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2026, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <soc/tegra/mc.h>
7 
8 #include <dt-bindings/memory/tegra234-mc.h>
9 #include <dt-bindings/memory/nvidia,tegra238-mc.h>
10 #include <linux/interconnect.h>
11 #include <linux/tegra-icc.h>
12 
13 #include <soc/tegra/bpmp.h>
14 #include "mc.h"
15 
16 static const struct tegra_mc_client tegra238_mc_clients[] = {
17 	{
18 		.id = TEGRA234_MEMORY_CLIENT_HDAR,
19 		.name = "hdar",
20 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
21 		.type = TEGRA_ICC_ISO_AUDIO,
22 		.sid = TEGRA238_SID_HDA,
23 		.regs = {
24 			.sid = {
25 				.override = 0xa8,
26 				.security = 0xac,
27 			},
28 		},
29 	}, {
30 		.id = TEGRA234_MEMORY_CLIENT_HDAW,
31 		.name = "hdaw",
32 		.bpmp_id = TEGRA_ICC_BPMP_HDA,
33 		.type = TEGRA_ICC_ISO_AUDIO,
34 		.sid = TEGRA238_SID_HDA,
35 		.regs = {
36 			.sid = {
37 				.override = 0x1a8,
38 				.security = 0x1ac,
39 			},
40 		},
41 	}, {
42 		.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
43 		.name = "sdmmcrab",
44 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
45 		.type = TEGRA_ICC_NISO,
46 		.sid = TEGRA238_SID_SDMMC4A,
47 		.regs = {
48 			.sid = {
49 				.override = 0x318,
50 				.security = 0x31c,
51 			},
52 		},
53 	}, {
54 		.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
55 		.name = "sdmmcwab",
56 		.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
57 		.type = TEGRA_ICC_NISO,
58 		.sid = TEGRA238_SID_SDMMC4A,
59 		.regs = {
60 			.sid = {
61 				.override = 0x338,
62 				.security = 0x33c,
63 			},
64 		},
65 	}, {
66 		.id = TEGRA234_MEMORY_CLIENT_APER,
67 		.name = "aper",
68 		.bpmp_id = TEGRA_ICC_BPMP_APE,
69 		.type = TEGRA_ICC_ISO_AUDIO,
70 		.sid = TEGRA238_SID_ISO_APE0,
71 		.regs = {
72 			.sid = {
73 				.override = 0x3d0,
74 				.security = 0x3d4,
75 			},
76 		},
77 	}, {
78 		.id = TEGRA234_MEMORY_CLIENT_APEW,
79 		.name = "apew",
80 		.bpmp_id = TEGRA_ICC_BPMP_APE,
81 		.type = TEGRA_ICC_ISO_AUDIO,
82 		.sid = TEGRA238_SID_ISO_APE0,
83 		.regs = {
84 			.sid = {
85 				.override = 0x3d8,
86 				.security = 0x3dc,
87 			},
88 		},
89 	}, {
90 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
91 		.name = "nvdisplayr",
92 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
93 		.type = TEGRA_ICC_ISO_DISPLAY,
94 		.sid = TEGRA238_SID_ISO_NVDISPLAY,
95 		.regs = {
96 			.sid = {
97 				.override = 0x490,
98 				.security = 0x494,
99 			},
100 		},
101 	}, {
102 		.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
103 		.name = "nvdisplayr1",
104 		.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
105 		.type = TEGRA_ICC_ISO_DISPLAY,
106 		.sid = TEGRA238_SID_ISO_NVDISPLAY,
107 		.regs = {
108 			.sid = {
109 				.override = 0x508,
110 				.security = 0x50c,
111 			},
112 		},
113 	}, {
114 		.id = TEGRA234_MEMORY_CLIENT_BPMPR,
115 		.name = "bpmpr",
116 		.sid = TEGRA238_SID_BPMP,
117 		.regs = {
118 			.sid = {
119 				.override = 0x498,
120 				.security = 0x49c,
121 			},
122 		},
123 	}, {
124 		.id = TEGRA234_MEMORY_CLIENT_BPMPW,
125 		.name = "bpmpw",
126 		.sid = TEGRA238_SID_BPMP,
127 		.regs = {
128 			.sid = {
129 				.override = 0x4a0,
130 				.security = 0x4a4,
131 			},
132 		},
133 	}, {
134 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
135 		.name = "bpmpdmar",
136 		.sid = TEGRA238_SID_BPMP,
137 		.regs = {
138 			.sid = {
139 				.override = 0x4a8,
140 				.security = 0x4ac,
141 			},
142 		},
143 	}, {
144 		.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
145 		.name = "bpmpdmaw",
146 		.sid = TEGRA238_SID_BPMP,
147 		.regs = {
148 			.sid = {
149 				.override = 0x4b0,
150 				.security = 0x4b4,
151 			},
152 		},
153 	}, {
154 		.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
155 		.name = "apedmar",
156 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
157 		.type = TEGRA_ICC_ISO_AUDIO,
158 		.sid = TEGRA238_SID_ISO_APE1,
159 		.regs = {
160 			.sid = {
161 				.override = 0x4f8,
162 				.security = 0x4fc,
163 			},
164 		},
165 	}, {
166 		.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
167 		.name = "apedmaw",
168 		.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
169 		.type = TEGRA_ICC_ISO_AUDIO,
170 		.sid = TEGRA238_SID_ISO_APE1,
171 		.regs = {
172 			.sid = {
173 				.override = 0x500,
174 				.security = 0x504,
175 			},
176 		},
177 	}, {
178 		.id = TEGRA234_MEMORY_CLIENT_VICSRD,
179 		.name = "vicsrd",
180 		.bpmp_id = TEGRA_ICC_BPMP_VIC,
181 		.type = TEGRA_ICC_NISO,
182 		.sid = TEGRA238_SID_VIC,
183 		.regs = {
184 			.sid = {
185 				.override = 0x360,
186 				.security = 0x364,
187 			},
188 		},
189 	}, {
190 		.id = TEGRA234_MEMORY_CLIENT_VICSWR,
191 		.name = "vicswr",
192 		.bpmp_id = TEGRA_ICC_BPMP_VIC,
193 		.type = TEGRA_ICC_NISO,
194 		.sid = TEGRA238_SID_VIC,
195 		.regs = {
196 			.sid = {
197 				.override = 0x368,
198 				.security = 0x36c,
199 			},
200 		},
201 	}, {
202 		.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
203 		.name = "nvdecsrd",
204 		.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
205 		.type = TEGRA_ICC_NISO,
206 		.sid = TEGRA238_SID_NVDEC,
207 		.regs = {
208 			.sid = {
209 				.override = 0x3c0,
210 				.security = 0x3c4,
211 			},
212 		},
213 	}, {
214 		.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
215 		.name = "nvdecswr",
216 		.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
217 		.type = TEGRA_ICC_NISO,
218 		.sid = TEGRA238_SID_NVDEC,
219 		.regs = {
220 			.sid = {
221 				.override = 0x3c8,
222 				.security = 0x3cc,
223 			},
224 		},
225 	}, {
226 		.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
227 		.name = "nvencsrd",
228 		.bpmp_id = TEGRA_ICC_BPMP_NVENC,
229 		.type = TEGRA_ICC_NISO,
230 		.sid = TEGRA238_SID_NVENC,
231 		.regs = {
232 			.sid = {
233 				.override = 0xe0,
234 				.security = 0xe4,
235 			},
236 		},
237 	}, {
238 		.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
239 		.name = "nvencswr",
240 		.bpmp_id = TEGRA_ICC_BPMP_NVENC,
241 		.type = TEGRA_ICC_NISO,
242 		.sid = TEGRA238_SID_NVENC,
243 		.regs = {
244 			.sid = {
245 				.override = 0x158,
246 				.security = 0x15c,
247 			},
248 		},
249 	}, {
250 		.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
251 		.name = "pcie0r",
252 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
253 		.type = TEGRA_ICC_NISO,
254 		.sid = TEGRA238_SID_PCIE0,
255 		.regs = {
256 			.sid = {
257 				.override = 0x6c0,
258 				.security = 0x6c4,
259 			},
260 		},
261 	}, {
262 		.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
263 		.name = "pcie0w",
264 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
265 		.type = TEGRA_ICC_NISO,
266 		.sid = TEGRA238_SID_PCIE0,
267 		.regs = {
268 			.sid = {
269 				.override = 0x6c8,
270 				.security = 0x6cc,
271 			},
272 		},
273 	}, {
274 		.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
275 		.name = "pcie1r",
276 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
277 		.type = TEGRA_ICC_NISO,
278 		.sid = TEGRA238_SID_PCIE1,
279 		.regs = {
280 			.sid = {
281 				.override = 0x6d0,
282 				.security = 0x6d4,
283 			},
284 		},
285 	}, {
286 		.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
287 		.name = "pcie1w",
288 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
289 		.type = TEGRA_ICC_NISO,
290 		.sid = TEGRA238_SID_PCIE1,
291 		.regs = {
292 			.sid = {
293 				.override = 0x6d8,
294 				.security = 0x6dc,
295 			},
296 		},
297 	}, {
298 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
299 		.name = "pcie2ar",
300 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
301 		.type = TEGRA_ICC_NISO,
302 		.sid = TEGRA238_SID_PCIE2,
303 		.regs = {
304 			.sid = {
305 				.override = 0x6e0,
306 				.security = 0x6e4,
307 			},
308 		},
309 	}, {
310 		.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
311 		.name = "pcie2aw",
312 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
313 		.type = TEGRA_ICC_NISO,
314 		.sid = TEGRA238_SID_PCIE2,
315 		.regs = {
316 			.sid = {
317 				.override = 0x6e8,
318 				.security = 0x6ec,
319 			},
320 		},
321 	}, {
322 		.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
323 		.name = "pcie3r",
324 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
325 		.type = TEGRA_ICC_NISO,
326 		.sid = TEGRA238_SID_PCIE3,
327 		.regs = {
328 			.sid = {
329 				.override = 0x6f0,
330 				.security = 0x6f4,
331 			},
332 		},
333 	}, {
334 		.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
335 		.name = "pcie3w",
336 		.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
337 		.type = TEGRA_ICC_NISO,
338 		.sid = TEGRA238_SID_PCIE3,
339 		.regs = {
340 			.sid = {
341 				.override = 0x6f8,
342 				.security = 0x6fc,
343 			},
344 		},
345 	}, {
346 		.id = TEGRA_ICC_MC_CPU_CLUSTER0,
347 		.name = "sw_cluster0",
348 		.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
349 		.type = TEGRA_ICC_NISO,
350 	}, {
351 		.id = TEGRA234_MEMORY_CLIENT_NVL1R,
352 		.name = "nvl1r",
353 		.bpmp_id = TEGRA_ICC_BPMP_GPU,
354 		.type = TEGRA_ICC_NISO,
355 	}, {
356 		.id = TEGRA234_MEMORY_CLIENT_NVL1W,
357 		.name = "nvl1w",
358 		.bpmp_id = TEGRA_ICC_BPMP_GPU,
359 		.type = TEGRA_ICC_NISO,
360 	}
361 };
362 
363 static const struct tegra_mc_intmask tegra238_mc_intmasks[] = {
364 	{
365 		.reg = MC_INTMASK,
366 		.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
367 			MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
368 			MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
369 	},
370 };
371 
372 const struct tegra_mc_soc tegra238_mc_soc = {
373 	.num_clients = ARRAY_SIZE(tegra238_mc_clients),
374 	.clients = tegra238_mc_clients,
375 	.num_address_bits = 40,
376 	.num_channels = 8,
377 	.client_id_mask = 0x1ff,
378 	.intmasks = tegra238_mc_intmasks,
379 	.num_intmasks = ARRAY_SIZE(tegra238_mc_intmasks),
380 	.has_addr_hi_reg = true,
381 	.ops = &tegra186_mc_ops,
382 	.icc_ops = &tegra234_mc_icc_ops,
383 	.ch_intmask = 0x0000ff00,
384 	.global_intstatus_channel_shift = 8,
385 	.num_carveouts = 32,
386 	.regs = &tegra20_mc_regs,
387 	.handle_irq = tegra30_mc_irq_handlers,
388 	.num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
389 	.mc_addr_hi_mask = 0x3,
390 	.mc_err_status_type_mask = (0x7 << 28),
391 };
392