1*687cac95SBiju Das /* SPDX-License-Identifier: GPL-2.0 */ 2*687cac95SBiju Das /* 3*687cac95SBiju Das * RZ xSPI Interface Registers Definitions 4*687cac95SBiju Das * 5*687cac95SBiju Das * Copyright (C) 2025 Renesas Electronics Corporation 6*687cac95SBiju Das */ 7*687cac95SBiju Das 8*687cac95SBiju Das #ifndef __RENESAS_XSPI_IF_REGS_H__ 9*687cac95SBiju Das #define __RENESAS_XSPI_IF_REGS_H__ 10*687cac95SBiju Das 11*687cac95SBiju Das #include <linux/bits.h> 12*687cac95SBiju Das 13*687cac95SBiju Das /* xSPI Wrapper Configuration Register */ 14*687cac95SBiju Das #define XSPI_WRAPCFG 0x0000 15*687cac95SBiju Das 16*687cac95SBiju Das /* xSPI Bridge Configuration Register */ 17*687cac95SBiju Das #define XSPI_BMCFG 0x0008 18*687cac95SBiju Das #define XSPI_BMCFG_WRMD BIT(0) 19*687cac95SBiju Das #define XSPI_BMCFG_MWRCOMB BIT(7) 20*687cac95SBiju Das #define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8) 21*687cac95SBiju Das #define XSPI_BMCFG_PREEN BIT(16) 22*687cac95SBiju Das 23*687cac95SBiju Das /* xSPI Command Map Configuration Register 0 CS0 */ 24*687cac95SBiju Das #define XSPI_CMCFG0CS0 0x0010 25*687cac95SBiju Das #define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0) 26*687cac95SBiju Das #define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2) 27*687cac95SBiju Das 28*687cac95SBiju Das /* xSPI Command Map Configuration Register 1 CS0 */ 29*687cac95SBiju Das #define XSPI_CMCFG1CS0 0x0014 30*687cac95SBiju Das #define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0) 31*687cac95SBiju Das #define XSPI_CMCFG1_RDCMD_UPPER_BYTE(val) (((val) & 0xff) << 8) 32*687cac95SBiju Das #define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16) 33*687cac95SBiju Das 34*687cac95SBiju Das /* xSPI Command Map Configuration Register 2 CS0 */ 35*687cac95SBiju Das #define XSPI_CMCFG2CS0 0x0018 36*687cac95SBiju Das #define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0) 37*687cac95SBiju Das #define XSPI_CMCFG2_WRCMD_UPPER(val) (((val) & 0xff) << 8) 38*687cac95SBiju Das #define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16) 39*687cac95SBiju Das 40*687cac95SBiju Das /* xSPI Link I/O Configuration Register CS0 */ 41*687cac95SBiju Das #define XSPI_LIOCFGCS0 0x0050 42*687cac95SBiju Das #define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0) 43*687cac95SBiju Das #define XSPI_LIOCFG_CSMIN(val) (((val) & 0x0f) << 16) 44*687cac95SBiju Das #define XSPI_LIOCFG_CSASTEX BIT(20) 45*687cac95SBiju Das #define XSPI_LIOCFG_CSNEGEX BIT(21) 46*687cac95SBiju Das 47*687cac95SBiju Das /* xSPI Bridge Map Control Register 0 */ 48*687cac95SBiju Das #define XSPI_BMCTL0 0x0060 49*687cac95SBiju Das #define XSPI_BMCTL0_CS0ACC(val) (((val) & 0x03) << 0) 50*687cac95SBiju Das 51*687cac95SBiju Das /* xSPI Bridge Map Control Register 1 */ 52*687cac95SBiju Das #define XSPI_BMCTL1 0x0064 53*687cac95SBiju Das #define XSPI_BMCTL1_MWRPUSH BIT(8) 54*687cac95SBiju Das 55*687cac95SBiju Das /* xSPI Command Manual Control Register 0 */ 56*687cac95SBiju Das #define XSPI_CDCTL0 0x0070 57*687cac95SBiju Das #define XSPI_CDCTL0_TRREQ BIT(0) 58*687cac95SBiju Das #define XSPI_CDCTL0_CSSEL BIT(3) 59*687cac95SBiju Das #define XSPI_CDCTL0_TRNUM(val) (((val) & 0x03) << 4) 60*687cac95SBiju Das 61*687cac95SBiju Das /* xSPI Command Manual Type Buf */ 62*687cac95SBiju Das #define XSPI_CDTBUF0 0x0080 63*687cac95SBiju Das #define XSPI_CDTBUF_CMDSIZE(val) (((val) & 0x03) << 0) 64*687cac95SBiju Das #define XSPI_CDTBUF_ADDSIZE(val) (((val) & 0x07) << 2) 65*687cac95SBiju Das #define XSPI_CDTBUF_DATASIZE(val) (((val) & 0x0f) << 5) 66*687cac95SBiju Das #define XSPI_CDTBUF_LATE(val) (((val) & 0x1f) << 9) 67*687cac95SBiju Das #define XSPI_CDTBUF_TRTYPE BIT(15) 68*687cac95SBiju Das #define XSPI_CDTBUF_CMD(val) (((val) & 0xffff) << 16) 69*687cac95SBiju Das #define XSPI_CDTBUF_CMD_FIELD(val) (((val) & 0xff) << 24) 70*687cac95SBiju Das 71*687cac95SBiju Das /* xSPI Command Manual Address Buff */ 72*687cac95SBiju Das #define XSPI_CDABUF0 0x0084 73*687cac95SBiju Das 74*687cac95SBiju Das /* xSPI Command Manual Data 0 Buf */ 75*687cac95SBiju Das #define XSPI_CDD0BUF0 0x0088 76*687cac95SBiju Das 77*687cac95SBiju Das /* xSPI Command Manual Data 1 Buf */ 78*687cac95SBiju Das #define XSPI_CDD1BUF0 0x008c 79*687cac95SBiju Das 80*687cac95SBiju Das /* xSPI Command Calibration Control Register 0 CS0 */ 81*687cac95SBiju Das #define XSPI_CCCTL0CS0 0x0130 82*687cac95SBiju Das #define XSPI_CCCTL0_CAEN BIT(0) 83*687cac95SBiju Das 84*687cac95SBiju Das /* xSPI Interrupt Status Register */ 85*687cac95SBiju Das #define XSPI_INTS 0x0190 86*687cac95SBiju Das #define XSPI_INTS_CMDCMP BIT(0) 87*687cac95SBiju Das 88*687cac95SBiju Das /* xSPI Interrupt Clear Register */ 89*687cac95SBiju Das #define XSPI_INTC 0x0194 90*687cac95SBiju Das #define XSPI_INTC_CMDCMPC BIT(0) 91*687cac95SBiju Das 92*687cac95SBiju Das /* xSPI Interrupt Enable Register */ 93*687cac95SBiju Das #define XSPI_INTE 0x0198 94*687cac95SBiju Das #define XSPI_INTE_CMDCMPE BIT(0) 95*687cac95SBiju Das 96*687cac95SBiju Das /* Maximum data size of MWRSIZE*/ 97*687cac95SBiju Das #define MWRSIZE_MAX 64 98*687cac95SBiju Das 99*687cac95SBiju Das /* xSPI Protocol mode */ 100*687cac95SBiju Das #define PROTO_1S_2S_2S 0x48 101*687cac95SBiju Das #define PROTO_2S_2S_2S 0x49 102*687cac95SBiju Das #define PROTO_1S_4S_4S 0x090 103*687cac95SBiju Das #define PROTO_4S_4S_4S 0x092 104*687cac95SBiju Das 105*687cac95SBiju Das #endif /* __RENESAS_XSPI_IF_REGS_H__ */ 106