1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * RZ xSPI Interface Registers Definitions 4 * 5 * Copyright (C) 2025 Renesas Electronics Corporation 6 */ 7 8 #ifndef __RENESAS_XSPI_IF_REGS_H__ 9 #define __RENESAS_XSPI_IF_REGS_H__ 10 11 #include <linux/bits.h> 12 13 /* xSPI Wrapper Configuration Register */ 14 #define XSPI_WRAPCFG 0x0000 15 16 /* xSPI Bridge Configuration Register */ 17 #define XSPI_BMCFG 0x0008 18 #define XSPI_BMCFG_WRMD BIT(0) 19 #define XSPI_BMCFG_MWRCOMB BIT(7) 20 #define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8) 21 #define XSPI_BMCFG_PREEN BIT(16) 22 23 /* xSPI Command Map Configuration Register 0 CS0 */ 24 #define XSPI_CMCFG0CS0 0x0010 25 #define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0) 26 #define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2) 27 28 /* xSPI Command Map Configuration Register 1 CS0 */ 29 #define XSPI_CMCFG1CS0 0x0014 30 #define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0) 31 #define XSPI_CMCFG1_RDCMD_UPPER_BYTE(val) (((val) & 0xff) << 8) 32 #define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16) 33 34 /* xSPI Command Map Configuration Register 2 CS0 */ 35 #define XSPI_CMCFG2CS0 0x0018 36 #define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0) 37 #define XSPI_CMCFG2_WRCMD_UPPER(val) (((val) & 0xff) << 8) 38 #define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16) 39 40 /* xSPI Link I/O Configuration Register CS0 */ 41 #define XSPI_LIOCFGCS0 0x0050 42 #define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0) 43 #define XSPI_LIOCFG_CSMIN(val) (((val) & 0x0f) << 16) 44 #define XSPI_LIOCFG_CSASTEX BIT(20) 45 #define XSPI_LIOCFG_CSNEGEX BIT(21) 46 47 /* xSPI Bridge Map Control Register 0 */ 48 #define XSPI_BMCTL0 0x0060 49 #define XSPI_BMCTL0_CS0ACC(val) (((val) & 0x03) << 0) 50 51 /* xSPI Bridge Map Control Register 1 */ 52 #define XSPI_BMCTL1 0x0064 53 #define XSPI_BMCTL1_MWRPUSH BIT(8) 54 55 /* xSPI Command Manual Control Register 0 */ 56 #define XSPI_CDCTL0 0x0070 57 #define XSPI_CDCTL0_TRREQ BIT(0) 58 #define XSPI_CDCTL0_CSSEL BIT(3) 59 #define XSPI_CDCTL0_TRNUM(val) (((val) & 0x03) << 4) 60 61 /* xSPI Command Manual Type Buf */ 62 #define XSPI_CDTBUF0 0x0080 63 #define XSPI_CDTBUF_CMDSIZE(val) (((val) & 0x03) << 0) 64 #define XSPI_CDTBUF_ADDSIZE(val) (((val) & 0x07) << 2) 65 #define XSPI_CDTBUF_DATASIZE(val) (((val) & 0x0f) << 5) 66 #define XSPI_CDTBUF_LATE(val) (((val) & 0x1f) << 9) 67 #define XSPI_CDTBUF_TRTYPE BIT(15) 68 #define XSPI_CDTBUF_CMD(val) (((val) & 0xffff) << 16) 69 #define XSPI_CDTBUF_CMD_FIELD(val) (((val) & 0xff) << 24) 70 71 /* xSPI Command Manual Address Buff */ 72 #define XSPI_CDABUF0 0x0084 73 74 /* xSPI Command Manual Data 0 Buf */ 75 #define XSPI_CDD0BUF0 0x0088 76 77 /* xSPI Command Manual Data 1 Buf */ 78 #define XSPI_CDD1BUF0 0x008c 79 80 /* xSPI Command Calibration Control Register 0 CS0 */ 81 #define XSPI_CCCTL0CS0 0x0130 82 #define XSPI_CCCTL0_CAEN BIT(0) 83 84 /* xSPI Interrupt Status Register */ 85 #define XSPI_INTS 0x0190 86 #define XSPI_INTS_CMDCMP BIT(0) 87 88 /* xSPI Interrupt Clear Register */ 89 #define XSPI_INTC 0x0194 90 #define XSPI_INTC_CMDCMPC BIT(0) 91 92 /* xSPI Interrupt Enable Register */ 93 #define XSPI_INTE 0x0198 94 #define XSPI_INTE_CMDCMPE BIT(0) 95 96 /* Maximum data size of MWRSIZE*/ 97 #define MWRSIZE_MAX 64 98 99 /* xSPI Protocol mode */ 100 #define PROTO_1S_2S_2S 0x48 101 #define PROTO_2S_2S_2S 0x49 102 #define PROTO_1S_4S_4S 0x090 103 #define PROTO_4S_4S_4S 0x092 104 105 #endif /* __RENESAS_XSPI_IF_REGS_H__ */ 106