1# 2# Memory devices 3# 4 5menuconfig MEMORY 6 bool "Memory Controller drivers" 7 8if MEMORY 9 10config ATMEL_SDRAMC 11 bool "Atmel (Multi-port DDR-)SDRAM Controller" 12 default y 13 depends on ARCH_AT91 && OF 14 help 15 This driver is for Atmel SDRAM Controller or Atmel Multi-port 16 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 17 Starting with the at91sam9g45, this controller supports SDR, DDR and 18 LP-DDR memories. 19 20config TI_AEMIF 21 tristate "Texas Instruments AEMIF driver" 22 depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF 23 help 24 This driver is for the AEMIF module available in Texas Instruments 25 SoCs. AEMIF stands for Asynchronous External Memory Interface and 26 is intended to provide a glue-less interface to a variety of 27 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 28 of 256M bytes of any of these memories can be accessed at a given 29 time via four chip selects with 64M byte access per chip select. 30 31config TI_EMIF 32 tristate "Texas Instruments EMIF driver" 33 depends on ARCH_OMAP2PLUS 34 select DDR 35 help 36 This driver is for the EMIF module available in Texas Instruments 37 SoCs. EMIF is an SDRAM controller that, based on its revision, 38 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 39 This driver takes care of only LPDDR2 memories presently. The 40 functions of the driver includes re-configuring AC timing 41 parameters and other settings during frequency, voltage and 42 temperature changes 43 44config OMAP_GPMC 45 bool 46 help 47 This driver is for the General Purpose Memory Controller (GPMC) 48 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 49 interfacing to a variety of asynchronous as well as synchronous 50 memory drives like NOR, NAND, OneNAND, SRAM. 51 52config MVEBU_DEVBUS 53 bool "Marvell EBU Device Bus Controller" 54 default y 55 depends on PLAT_ORION && OF 56 help 57 This driver is for the Device Bus controller available in some 58 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 59 Armada 370 and Armada XP. This controller allows to handle flash 60 devices such as NOR, NAND, SRAM, and FPGA. 61 62config TEGRA20_MC 63 bool "Tegra20 Memory Controller(MC) driver" 64 default y 65 depends on ARCH_TEGRA_2x_SOC 66 help 67 This driver is for the Memory Controller(MC) module available 68 in Tegra20 SoCs, mainly for a address translation fault 69 analysis, especially for IOMMU/GART(Graphics Address 70 Relocation Table) module. 71 72config TEGRA30_MC 73 bool "Tegra30 Memory Controller(MC) driver" 74 default y 75 depends on ARCH_TEGRA_3x_SOC 76 help 77 This driver is for the Memory Controller(MC) module available 78 in Tegra30 SoCs, mainly for a address translation fault 79 analysis, especially for IOMMU/SMMU(System Memory Management 80 Unit) module. 81 82config FSL_CORENET_CF 83 tristate "Freescale CoreNet Error Reporting" 84 depends on FSL_SOC_BOOKE 85 help 86 Say Y for reporting of errors from the Freescale CoreNet 87 Coherency Fabric. Errors reported include accesses to 88 physical addresses that mapped by no local access window 89 (LAW) or an invalid LAW, as well as bad cache state that 90 represents a coherency violation. 91 92config FSL_IFC 93 bool 94 depends on FSL_SOC 95 96endif 97