1ec8f24b7SThomas Gleixner# SPDX-License-Identifier: GPL-2.0-only 27ec94453SAneesh V# 37ec94453SAneesh V# Memory devices 47ec94453SAneesh V# 57ec94453SAneesh V 67ec94453SAneesh Vmenuconfig MEMORY 77ec94453SAneesh V bool "Memory Controller drivers" 82664a075SKrzysztof Kozlowski help 92664a075SKrzysztof Kozlowski This option allows to enable specific memory controller drivers, 102664a075SKrzysztof Kozlowski useful mostly on embedded systems. These could be controllers 112664a075SKrzysztof Kozlowski for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features 122664a075SKrzysztof Kozlowski vary from memory tuning and frequency scaling to enabling 132664a075SKrzysztof Kozlowski access to attached peripherals through memory bus. 147ec94453SAneesh V 157ec94453SAneesh Vif MEMORY 167ec94453SAneesh V 177b43b8fdSMasahiro Yamadaconfig DDR 187b43b8fdSMasahiro Yamada bool 197b43b8fdSMasahiro Yamada help 207b43b8fdSMasahiro Yamada Data from JEDEC specs for DDR SDRAM memories, 217b43b8fdSMasahiro Yamada particularly the AC timing parameters and addressing 227b43b8fdSMasahiro Yamada information. This data is useful for drivers handling 237b43b8fdSMasahiro Yamada DDR SDRAM controllers. 247b43b8fdSMasahiro Yamada 2517c50b70SJoachim Eastwoodconfig ARM_PL172_MPMC 2617c50b70SJoachim Eastwood tristate "ARM PL172 MPMC driver" 2717c50b70SJoachim Eastwood depends on ARM_AMBA && OF 2817c50b70SJoachim Eastwood help 2917c50b70SJoachim Eastwood This selects the ARM PrimeCell PL172 MultiPort Memory Controller. 3017c50b70SJoachim Eastwood If you have an embedded system with an AMBA bus and a PL172 3117c50b70SJoachim Eastwood controller, say Y or M here. 3217c50b70SJoachim Eastwood 33e81b6abeSAlexandre Belloniconfig ATMEL_SDRAMC 34e81b6abeSAlexandre Belloni bool "Atmel (Multi-port DDR-)SDRAM Controller" 35ea0c0ad6SKrzysztof Kozlowski default y if ARCH_AT91 36ea0c0ad6SKrzysztof Kozlowski depends on ARCH_AT91 || COMPILE_TEST 37ea0c0ad6SKrzysztof Kozlowski depends on OF 38e81b6abeSAlexandre Belloni help 39e81b6abeSAlexandre Belloni This driver is for Atmel SDRAM Controller or Atmel Multi-port 40e81b6abeSAlexandre Belloni DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs. 41e81b6abeSAlexandre Belloni Starting with the at91sam9g45, this controller supports SDR, DDR and 42e81b6abeSAlexandre Belloni LP-DDR memories. 43e81b6abeSAlexandre Belloni 446a4ec4cdSBoris Brezillonconfig ATMEL_EBI 456a4ec4cdSBoris Brezillon bool "Atmel EBI driver" 46ea0c0ad6SKrzysztof Kozlowski default y if ARCH_AT91 47ea0c0ad6SKrzysztof Kozlowski depends on ARCH_AT91 || COMPILE_TEST 48ea0c0ad6SKrzysztof Kozlowski depends on OF 496a4ec4cdSBoris Brezillon select MFD_SYSCON 508eb8c7d8SBoris Brezillon select MFD_ATMEL_SMC 516a4ec4cdSBoris Brezillon help 526a4ec4cdSBoris Brezillon Driver for Atmel EBI controller. 536a4ec4cdSBoris Brezillon Used to configure the EBI (external bus interface) when the device- 546a4ec4cdSBoris Brezillon tree is used. This bus supports NANDs, external ethernet controller, 556a4ec4cdSBoris Brezillon SRAMs, ATA devices, etc. 566a4ec4cdSBoris Brezillon 57904ffa81SKrzysztof Kozlowskiconfig BRCMSTB_DPFE 58904ffa81SKrzysztof Kozlowski bool "Broadcom STB DPFE driver" if COMPILE_TEST 59904ffa81SKrzysztof Kozlowski default y if ARCH_BRCMSTB 60904ffa81SKrzysztof Kozlowski depends on ARCH_BRCMSTB || COMPILE_TEST 61904ffa81SKrzysztof Kozlowski help 62904ffa81SKrzysztof Kozlowski This driver provides access to the DPFE interface of Broadcom 63904ffa81SKrzysztof Kozlowski STB SoCs. The firmware running on the DCPU inside the DDR PHY can 64904ffa81SKrzysztof Kozlowski provide current information about the system's RAM, for instance 65904ffa81SKrzysztof Kozlowski the DRAM refresh rate. This can be used as an indirect indicator 66904ffa81SKrzysztof Kozlowski for the DRAM's temperature. Slower refresh rate means cooler RAM, 67904ffa81SKrzysztof Kozlowski higher refresh rate means hotter RAM. 68904ffa81SKrzysztof Kozlowski 6983ca8b3eSSerge Seminconfig BT1_L2_CTL 7083ca8b3eSSerge Semin bool "Baikal-T1 CM2 L2-RAM Cache Control Block" 7183ca8b3eSSerge Semin depends on MIPS_BAIKAL_T1 || COMPILE_TEST 7283ca8b3eSSerge Semin select MFD_SYSCON 7383ca8b3eSSerge Semin help 7483ca8b3eSSerge Semin Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU 7583ca8b3eSSerge Semin resides Coherency Manager v2 with embedded 1MB L2-cache. It's 7683ca8b3eSSerge Semin possible to tune the L2 cache performance up by setting the data, 7783ca8b3eSSerge Semin tags and way-select latencies of RAM access. This driver provides a 7883ca8b3eSSerge Semin dt properties-based and sysfs interface for it. 7983ca8b3eSSerge Semin 805a7c8154SIvan Khoronzhukconfig TI_AEMIF 815a7c8154SIvan Khoronzhuk tristate "Texas Instruments AEMIF driver" 82ea0c0ad6SKrzysztof Kozlowski depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST 83ea0c0ad6SKrzysztof Kozlowski depends on OF 845a7c8154SIvan Khoronzhuk help 855a7c8154SIvan Khoronzhuk This driver is for the AEMIF module available in Texas Instruments 865a7c8154SIvan Khoronzhuk SoCs. AEMIF stands for Asynchronous External Memory Interface and 875a7c8154SIvan Khoronzhuk is intended to provide a glue-less interface to a variety of 885a7c8154SIvan Khoronzhuk asynchronuous memory devices like ASRAM, NOR and NAND memory. A total 895a7c8154SIvan Khoronzhuk of 256M bytes of any of these memories can be accessed at a given 905a7c8154SIvan Khoronzhuk time via four chip selects with 64M byte access per chip select. 915a7c8154SIvan Khoronzhuk 927ec94453SAneesh Vconfig TI_EMIF 937ec94453SAneesh V tristate "Texas Instruments EMIF driver" 94ea0c0ad6SKrzysztof Kozlowski depends on ARCH_OMAP2PLUS || COMPILE_TEST 957ec94453SAneesh V select DDR 967ec94453SAneesh V help 977ec94453SAneesh V This driver is for the EMIF module available in Texas Instruments 987ec94453SAneesh V SoCs. EMIF is an SDRAM controller that, based on its revision, 997ec94453SAneesh V supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols. 1007ec94453SAneesh V This driver takes care of only LPDDR2 memories presently. The 1017ec94453SAneesh V functions of the driver includes re-configuring AC timing 1027ec94453SAneesh V parameters and other settings during frequency, voltage and 1037ec94453SAneesh V temperature changes 1047ec94453SAneesh V 10518640193STony Lindgrenconfig OMAP_GPMC 106ea0c0ad6SKrzysztof Kozlowski bool "Texas Instruments OMAP SoC GPMC driver" if COMPILE_TEST 10726cb1d2fSKrzysztof Kozlowski depends on OF_ADDRESS 108d2d00862SRoger Quadros select GPIOLIB 10918640193STony Lindgren help 11018640193STony Lindgren This driver is for the General Purpose Memory Controller (GPMC) 11118640193STony Lindgren present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows 11218640193STony Lindgren interfacing to a variety of asynchronous as well as synchronous 11318640193STony Lindgren memory drives like NOR, NAND, OneNAND, SRAM. 11418640193STony Lindgren 11563aa945bSTony Lindgrenconfig OMAP_GPMC_DEBUG 116be59b619STony Lindgren bool "Enable GPMC debug output and skip reset of GPMC during init" 11763aa945bSTony Lindgren depends on OMAP_GPMC 11863aa945bSTony Lindgren help 11963aa945bSTony Lindgren Enables verbose debugging mostly to decode the bootloader provided 120be59b619STony Lindgren timings. To preserve the bootloader provided timings, the reset 121be59b619STony Lindgren of GPMC is skipped during init. Enable this during development to 122be59b619STony Lindgren configure devices connected to the GPMC bus. 123be59b619STony Lindgren 124be59b619STony Lindgren NOTE: In addition to matching the register setup with the bootloader 125be59b619STony Lindgren you also need to match the GPMC FCLK frequency used by the 126be59b619STony Lindgren bootloader or else the GPMC timings won't be identical with the 127be59b619STony Lindgren bootloader timings. 12863aa945bSTony Lindgren 1298428e5adSDave Gerlachconfig TI_EMIF_SRAM 1308428e5adSDave Gerlach tristate "Texas Instruments EMIF SRAM driver" 131d77d22d7SArnd Bergmann depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST) 132ea0c0ad6SKrzysztof Kozlowski depends on SRAM 1338428e5adSDave Gerlach help 1348428e5adSDave Gerlach This driver is for the EMIF module available on Texas Instruments 1358428e5adSDave Gerlach AM33XX and AM43XX SoCs and is required for PM. Certain parts of 1368428e5adSDave Gerlach the EMIF PM code must run from on-chip SRAM late in the suspend 1378428e5adSDave Gerlach sequence so this driver provides several relocatable PM functions 1388428e5adSDave Gerlach for the SoC PM code to use. 1398428e5adSDave Gerlach 140477dfdccSXu Yilunconfig FPGA_DFL_EMIF 141477dfdccSXu Yilun tristate "FPGA DFL EMIF Driver" 142477dfdccSXu Yilun depends on FPGA_DFL && HAS_IOMEM 143477dfdccSXu Yilun help 144477dfdccSXu Yilun This driver is for the EMIF private feature implemented under 145477dfdccSXu Yilun FPGA Device Feature List (DFL) framework. It is used to expose 146477dfdccSXu Yilun memory interface status information as well as memory clearing 147477dfdccSXu Yilun control. 148477dfdccSXu Yilun 1493edad321SEzequiel Garciaconfig MVEBU_DEVBUS 1503edad321SEzequiel Garcia bool "Marvell EBU Device Bus Controller" 151ea0c0ad6SKrzysztof Kozlowski default y if PLAT_ORION 152ea0c0ad6SKrzysztof Kozlowski depends on PLAT_ORION || COMPILE_TEST 153ea0c0ad6SKrzysztof Kozlowski depends on OF 1543edad321SEzequiel Garcia help 1553edad321SEzequiel Garcia This driver is for the Device Bus controller available in some 1563edad321SEzequiel Garcia Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and 1573edad321SEzequiel Garcia Armada 370 and Armada XP. This controller allows to handle flash 1583edad321SEzequiel Garcia devices such as NOR, NAND, SRAM, and FPGA. 1593edad321SEzequiel Garcia 16054afbec0SScott Woodconfig FSL_CORENET_CF 16154afbec0SScott Wood tristate "Freescale CoreNet Error Reporting" 162ea0c0ad6SKrzysztof Kozlowski depends on FSL_SOC_BOOKE || COMPILE_TEST 16354afbec0SScott Wood help 16454afbec0SScott Wood Say Y for reporting of errors from the Freescale CoreNet 16554afbec0SScott Wood Coherency Fabric. Errors reported include accesses to 16654afbec0SScott Wood physical addresses that mapped by no local access window 16754afbec0SScott Wood (LAW) or an invalid LAW, as well as bad cache state that 16854afbec0SScott Wood represents a coherency violation. 16954afbec0SScott Wood 17042d87b18SPaul Gortmakerconfig FSL_IFC 171ea0c0ad6SKrzysztof Kozlowski bool "Freescale IFC driver" if COMPILE_TEST 172b30a2bd4SBoris Brezillon depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST 173b30a2bd4SBoris Brezillon depends on HAS_IOMEM 17442d87b18SPaul Gortmaker 175911a8882SAlex Smithconfig JZ4780_NEMC 176911a8882SAlex Smith bool "Ingenic JZ4780 SoC NEMC driver" 17794b3a02cSPaul Cercueil depends on MIPS || COMPILE_TEST 17816909c81SAnders Roxell depends on HAS_IOMEM && OF 179911a8882SAlex Smith help 180911a8882SAlex Smith This driver is for the NAND/External Memory Controller (NEMC) in 181911a8882SAlex Smith the Ingenic JZ4780. This controller is used to handle external 182911a8882SAlex Smith memory devices such as NAND and SRAM. 183911a8882SAlex Smith 184cc8bbe1aSYong Wuconfig MTK_SMI 18550fc8d92SYong Wu tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST 186cc8bbe1aSYong Wu depends on ARCH_MEDIATEK || COMPILE_TEST 187cc8bbe1aSYong Wu help 188cc8bbe1aSYong Wu This driver is for the Memory Controller module in MediaTek SoCs, 189cc8bbe1aSYong Wu mainly help enable/disable iommu and control the power domain and 190cc8bbe1aSYong Wu clocks for each local arbiter. 191cc8bbe1aSYong Wu 19262a8a739SBartosz Golaszewskiconfig DA8XX_DDRCTL 19362a8a739SBartosz Golaszewski bool "Texas Instruments da8xx DDR2/mDDR driver" 194ea0c0ad6SKrzysztof Kozlowski depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST 19562a8a739SBartosz Golaszewski help 19662a8a739SBartosz Golaszewski This driver is for the DDR2/mDDR Memory Controller present on 19762a8a739SBartosz Golaszewski Texas Instruments da8xx SoCs. It's used to tweak various memory 19862a8a739SBartosz Golaszewski controller configuration options. 19962a8a739SBartosz Golaszewski 200fee10bd2SNaga Sureshkumar Relliconfig PL353_SMC 201fee10bd2SNaga Sureshkumar Relli tristate "ARM PL35X Static Memory Controller(SMC) driver" 202ea0c0ad6SKrzysztof Kozlowski default y if ARM 2035445a0c0SKrzysztof Kozlowski depends on ARM || COMPILE_TEST 2045445a0c0SKrzysztof Kozlowski depends on ARM_AMBA 205fee10bd2SNaga Sureshkumar Relli help 206fee10bd2SNaga Sureshkumar Relli This driver is for the ARM PL351/PL353 Static Memory 207fee10bd2SNaga Sureshkumar Relli Controller(SMC) module. 208fee10bd2SNaga Sureshkumar Relli 209ca7d8b98SSergei Shtylyovconfig RENESAS_RPCIF 210ca7d8b98SSergei Shtylyov tristate "Renesas RPC-IF driver" 211ea0c0ad6SKrzysztof Kozlowski depends on ARCH_RENESAS || COMPILE_TEST 212ca7d8b98SSergei Shtylyov select REGMAP_MMIO 213*4a26df8eSGeert Uytterhoeven select RESET_CONTROLLER 214ca7d8b98SSergei Shtylyov help 215409f9fe9SAdam Ford This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides 216409f9fe9SAdam Ford either SPI host or HyperFlash. You'll have to select individual 217409f9fe9SAdam Ford components under the corresponding menu. 218ca7d8b98SSergei Shtylyov 21966b8173aSChristophe Kerelloconfig STM32_FMC2_EBI 22066b8173aSChristophe Kerello tristate "Support for FMC2 External Bus Interface on STM32MP SoCs" 22166b8173aSChristophe Kerello depends on MACH_STM32MP157 || COMPILE_TEST 22266b8173aSChristophe Kerello select MFD_SYSCON 22366b8173aSChristophe Kerello help 22466b8173aSChristophe Kerello Select this option to enable the STM32 FMC2 External Bus Interface 22566b8173aSChristophe Kerello controller. This driver configures the transactions with external 22666b8173aSChristophe Kerello devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on 22766b8173aSChristophe Kerello SOCs containing the FMC2 External Bus Interface. 22866b8173aSChristophe Kerello 229a8aabb91SPankaj Dubeysource "drivers/memory/samsung/Kconfig" 23089184651SThierry Redingsource "drivers/memory/tegra/Kconfig" 23189184651SThierry Reding 2327ec94453SAneesh Vendif 233