1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * v4l2-dv-timings - dv-timings helper functions 4 * 5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/types.h> 10 #include <linux/kernel.h> 11 #include <linux/errno.h> 12 #include <linux/rational.h> 13 #include <linux/videodev2.h> 14 #include <linux/v4l2-dv-timings.h> 15 #include <media/v4l2-dv-timings.h> 16 #include <linux/math64.h> 17 #include <linux/hdmi.h> 18 #include <media/cec.h> 19 20 MODULE_AUTHOR("Hans Verkuil"); 21 MODULE_DESCRIPTION("V4L2 DV Timings Helper Functions"); 22 MODULE_LICENSE("GPL"); 23 24 const struct v4l2_dv_timings v4l2_dv_timings_presets[] = { 25 V4L2_DV_BT_CEA_640X480P59_94, 26 V4L2_DV_BT_CEA_720X480I59_94, 27 V4L2_DV_BT_CEA_720X480P59_94, 28 V4L2_DV_BT_CEA_720X576I50, 29 V4L2_DV_BT_CEA_720X576P50, 30 V4L2_DV_BT_CEA_1280X720P24, 31 V4L2_DV_BT_CEA_1280X720P25, 32 V4L2_DV_BT_CEA_1280X720P30, 33 V4L2_DV_BT_CEA_1280X720P50, 34 V4L2_DV_BT_CEA_1280X720P60, 35 V4L2_DV_BT_CEA_1920X1080P24, 36 V4L2_DV_BT_CEA_1920X1080P25, 37 V4L2_DV_BT_CEA_1920X1080P30, 38 V4L2_DV_BT_CEA_1920X1080I50, 39 V4L2_DV_BT_CEA_1920X1080P50, 40 V4L2_DV_BT_CEA_1920X1080I60, 41 V4L2_DV_BT_CEA_1920X1080P60, 42 V4L2_DV_BT_DMT_640X350P85, 43 V4L2_DV_BT_DMT_640X400P85, 44 V4L2_DV_BT_DMT_720X400P85, 45 V4L2_DV_BT_DMT_640X480P72, 46 V4L2_DV_BT_DMT_640X480P75, 47 V4L2_DV_BT_DMT_640X480P85, 48 V4L2_DV_BT_DMT_800X600P56, 49 V4L2_DV_BT_DMT_800X600P60, 50 V4L2_DV_BT_DMT_800X600P72, 51 V4L2_DV_BT_DMT_800X600P75, 52 V4L2_DV_BT_DMT_800X600P85, 53 V4L2_DV_BT_DMT_800X600P120_RB, 54 V4L2_DV_BT_DMT_848X480P60, 55 V4L2_DV_BT_DMT_1024X768I43, 56 V4L2_DV_BT_DMT_1024X768P60, 57 V4L2_DV_BT_DMT_1024X768P70, 58 V4L2_DV_BT_DMT_1024X768P75, 59 V4L2_DV_BT_DMT_1024X768P85, 60 V4L2_DV_BT_DMT_1024X768P120_RB, 61 V4L2_DV_BT_DMT_1152X864P75, 62 V4L2_DV_BT_DMT_1280X768P60_RB, 63 V4L2_DV_BT_DMT_1280X768P60, 64 V4L2_DV_BT_DMT_1280X768P75, 65 V4L2_DV_BT_DMT_1280X768P85, 66 V4L2_DV_BT_DMT_1280X768P120_RB, 67 V4L2_DV_BT_DMT_1280X800P60_RB, 68 V4L2_DV_BT_DMT_1280X800P60, 69 V4L2_DV_BT_DMT_1280X800P75, 70 V4L2_DV_BT_DMT_1280X800P85, 71 V4L2_DV_BT_DMT_1280X800P120_RB, 72 V4L2_DV_BT_DMT_1280X960P60, 73 V4L2_DV_BT_DMT_1280X960P85, 74 V4L2_DV_BT_DMT_1280X960P120_RB, 75 V4L2_DV_BT_DMT_1280X1024P60, 76 V4L2_DV_BT_DMT_1280X1024P75, 77 V4L2_DV_BT_DMT_1280X1024P85, 78 V4L2_DV_BT_DMT_1280X1024P120_RB, 79 V4L2_DV_BT_DMT_1360X768P60, 80 V4L2_DV_BT_DMT_1360X768P120_RB, 81 V4L2_DV_BT_DMT_1366X768P60, 82 V4L2_DV_BT_DMT_1366X768P60_RB, 83 V4L2_DV_BT_DMT_1400X1050P60_RB, 84 V4L2_DV_BT_DMT_1400X1050P60, 85 V4L2_DV_BT_DMT_1400X1050P75, 86 V4L2_DV_BT_DMT_1400X1050P85, 87 V4L2_DV_BT_DMT_1400X1050P120_RB, 88 V4L2_DV_BT_DMT_1440X900P60_RB, 89 V4L2_DV_BT_DMT_1440X900P60, 90 V4L2_DV_BT_DMT_1440X900P75, 91 V4L2_DV_BT_DMT_1440X900P85, 92 V4L2_DV_BT_DMT_1440X900P120_RB, 93 V4L2_DV_BT_DMT_1600X900P60_RB, 94 V4L2_DV_BT_DMT_1600X1200P60, 95 V4L2_DV_BT_DMT_1600X1200P65, 96 V4L2_DV_BT_DMT_1600X1200P70, 97 V4L2_DV_BT_DMT_1600X1200P75, 98 V4L2_DV_BT_DMT_1600X1200P85, 99 V4L2_DV_BT_DMT_1600X1200P120_RB, 100 V4L2_DV_BT_DMT_1680X1050P60_RB, 101 V4L2_DV_BT_DMT_1680X1050P60, 102 V4L2_DV_BT_DMT_1680X1050P75, 103 V4L2_DV_BT_DMT_1680X1050P85, 104 V4L2_DV_BT_DMT_1680X1050P120_RB, 105 V4L2_DV_BT_DMT_1792X1344P60, 106 V4L2_DV_BT_DMT_1792X1344P75, 107 V4L2_DV_BT_DMT_1792X1344P120_RB, 108 V4L2_DV_BT_DMT_1856X1392P60, 109 V4L2_DV_BT_DMT_1856X1392P75, 110 V4L2_DV_BT_DMT_1856X1392P120_RB, 111 V4L2_DV_BT_DMT_1920X1200P60_RB, 112 V4L2_DV_BT_DMT_1920X1200P60, 113 V4L2_DV_BT_DMT_1920X1200P75, 114 V4L2_DV_BT_DMT_1920X1200P85, 115 V4L2_DV_BT_DMT_1920X1200P120_RB, 116 V4L2_DV_BT_DMT_1920X1440P60, 117 V4L2_DV_BT_DMT_1920X1440P75, 118 V4L2_DV_BT_DMT_1920X1440P120_RB, 119 V4L2_DV_BT_DMT_2048X1152P60_RB, 120 V4L2_DV_BT_DMT_2560X1600P60_RB, 121 V4L2_DV_BT_DMT_2560X1600P60, 122 V4L2_DV_BT_DMT_2560X1600P75, 123 V4L2_DV_BT_DMT_2560X1600P85, 124 V4L2_DV_BT_DMT_2560X1600P120_RB, 125 V4L2_DV_BT_CEA_3840X2160P24, 126 V4L2_DV_BT_CEA_3840X2160P25, 127 V4L2_DV_BT_CEA_3840X2160P30, 128 V4L2_DV_BT_CEA_3840X2160P50, 129 V4L2_DV_BT_CEA_3840X2160P60, 130 V4L2_DV_BT_CEA_4096X2160P24, 131 V4L2_DV_BT_CEA_4096X2160P25, 132 V4L2_DV_BT_CEA_4096X2160P30, 133 V4L2_DV_BT_CEA_4096X2160P50, 134 V4L2_DV_BT_DMT_4096X2160P59_94_RB, 135 V4L2_DV_BT_CEA_4096X2160P60, 136 { } 137 }; 138 EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets); 139 140 bool v4l2_valid_dv_timings(const struct v4l2_dv_timings *t, 141 const struct v4l2_dv_timings_cap *dvcap, 142 v4l2_check_dv_timings_fnc fnc, 143 void *fnc_handle) 144 { 145 const struct v4l2_bt_timings *bt = &t->bt; 146 const struct v4l2_bt_timings_cap *cap = &dvcap->bt; 147 u32 caps = cap->capabilities; 148 149 if (t->type != V4L2_DV_BT_656_1120) 150 return false; 151 if (t->type != dvcap->type || 152 bt->height < cap->min_height || 153 bt->height > cap->max_height || 154 bt->width < cap->min_width || 155 bt->width > cap->max_width || 156 bt->pixelclock < cap->min_pixelclock || 157 bt->pixelclock > cap->max_pixelclock || 158 (!(caps & V4L2_DV_BT_CAP_CUSTOM) && 159 cap->standards && bt->standards && 160 !(bt->standards & cap->standards)) || 161 (bt->interlaced && !(caps & V4L2_DV_BT_CAP_INTERLACED)) || 162 (!bt->interlaced && !(caps & V4L2_DV_BT_CAP_PROGRESSIVE))) 163 return false; 164 165 /* sanity checks for the blanking timings */ 166 if (!bt->interlaced && 167 (bt->il_vbackporch || bt->il_vsync || bt->il_vfrontporch)) 168 return false; 169 if (bt->hfrontporch > 2 * bt->width || 170 bt->hsync > 1024 || bt->hbackporch > 1024) 171 return false; 172 if (bt->vfrontporch > 4096 || 173 bt->vsync > 128 || bt->vbackporch > 4096) 174 return false; 175 if (bt->interlaced && (bt->il_vfrontporch > 4096 || 176 bt->il_vsync > 128 || bt->il_vbackporch > 4096)) 177 return false; 178 return fnc == NULL || fnc(t, fnc_handle); 179 } 180 EXPORT_SYMBOL_GPL(v4l2_valid_dv_timings); 181 182 int v4l2_enum_dv_timings_cap(struct v4l2_enum_dv_timings *t, 183 const struct v4l2_dv_timings_cap *cap, 184 v4l2_check_dv_timings_fnc fnc, 185 void *fnc_handle) 186 { 187 u32 i, idx; 188 189 memset(t->reserved, 0, sizeof(t->reserved)); 190 for (i = idx = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 191 if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap, 192 fnc, fnc_handle) && 193 idx++ == t->index) { 194 t->timings = v4l2_dv_timings_presets[i]; 195 return 0; 196 } 197 } 198 return -EINVAL; 199 } 200 EXPORT_SYMBOL_GPL(v4l2_enum_dv_timings_cap); 201 202 bool v4l2_find_dv_timings_cap(struct v4l2_dv_timings *t, 203 const struct v4l2_dv_timings_cap *cap, 204 unsigned pclock_delta, 205 v4l2_check_dv_timings_fnc fnc, 206 void *fnc_handle) 207 { 208 int i; 209 210 if (!v4l2_valid_dv_timings(t, cap, fnc, fnc_handle)) 211 return false; 212 213 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 214 if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap, 215 fnc, fnc_handle) && 216 v4l2_match_dv_timings(t, v4l2_dv_timings_presets + i, 217 pclock_delta, false)) { 218 u32 flags = t->bt.flags & V4L2_DV_FL_REDUCED_FPS; 219 220 *t = v4l2_dv_timings_presets[i]; 221 if (can_reduce_fps(&t->bt)) 222 t->bt.flags |= flags; 223 224 return true; 225 } 226 } 227 return false; 228 } 229 EXPORT_SYMBOL_GPL(v4l2_find_dv_timings_cap); 230 231 bool v4l2_find_dv_timings_cea861_vic(struct v4l2_dv_timings *t, u8 vic) 232 { 233 unsigned int i; 234 235 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) { 236 const struct v4l2_bt_timings *bt = 237 &v4l2_dv_timings_presets[i].bt; 238 239 if ((bt->flags & V4L2_DV_FL_HAS_CEA861_VIC) && 240 bt->cea861_vic == vic) { 241 *t = v4l2_dv_timings_presets[i]; 242 return true; 243 } 244 } 245 return false; 246 } 247 EXPORT_SYMBOL_GPL(v4l2_find_dv_timings_cea861_vic); 248 249 /** 250 * v4l2_match_dv_timings - check if two timings match 251 * @t1: compare this v4l2_dv_timings struct... 252 * @t2: with this struct. 253 * @pclock_delta: the allowed pixelclock deviation. 254 * @match_reduced_fps: if true, then fail if V4L2_DV_FL_REDUCED_FPS does not 255 * match. 256 * 257 * Compare t1 with t2 with a given margin of error for the pixelclock. 258 */ 259 bool v4l2_match_dv_timings(const struct v4l2_dv_timings *t1, 260 const struct v4l2_dv_timings *t2, 261 unsigned pclock_delta, bool match_reduced_fps) 262 { 263 if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120) 264 return false; 265 if (t1->bt.width == t2->bt.width && 266 t1->bt.height == t2->bt.height && 267 t1->bt.interlaced == t2->bt.interlaced && 268 t1->bt.polarities == t2->bt.polarities && 269 t1->bt.pixelclock >= t2->bt.pixelclock - pclock_delta && 270 t1->bt.pixelclock <= t2->bt.pixelclock + pclock_delta && 271 t1->bt.hfrontporch == t2->bt.hfrontporch && 272 t1->bt.hsync == t2->bt.hsync && 273 t1->bt.hbackporch == t2->bt.hbackporch && 274 t1->bt.vfrontporch == t2->bt.vfrontporch && 275 t1->bt.vsync == t2->bt.vsync && 276 t1->bt.vbackporch == t2->bt.vbackporch && 277 (!match_reduced_fps || 278 (t1->bt.flags & V4L2_DV_FL_REDUCED_FPS) == 279 (t2->bt.flags & V4L2_DV_FL_REDUCED_FPS)) && 280 (!t1->bt.interlaced || 281 (t1->bt.il_vfrontporch == t2->bt.il_vfrontporch && 282 t1->bt.il_vsync == t2->bt.il_vsync && 283 t1->bt.il_vbackporch == t2->bt.il_vbackporch))) 284 return true; 285 return false; 286 } 287 EXPORT_SYMBOL_GPL(v4l2_match_dv_timings); 288 289 void v4l2_print_dv_timings(const char *dev_prefix, const char *prefix, 290 const struct v4l2_dv_timings *t, bool detailed) 291 { 292 const struct v4l2_bt_timings *bt = &t->bt; 293 u32 htot, vtot; 294 u32 fps; 295 296 if (t->type != V4L2_DV_BT_656_1120) 297 return; 298 299 htot = V4L2_DV_BT_FRAME_WIDTH(bt); 300 vtot = V4L2_DV_BT_FRAME_HEIGHT(bt); 301 if (bt->interlaced) 302 vtot /= 2; 303 304 fps = (htot * vtot) > 0 ? div_u64((100 * (u64)bt->pixelclock), 305 (htot * vtot)) : 0; 306 307 if (prefix == NULL) 308 prefix = ""; 309 310 pr_info("%s: %s%ux%u%s%u.%02u (%ux%u)\n", dev_prefix, prefix, 311 bt->width, bt->height, bt->interlaced ? "i" : "p", 312 fps / 100, fps % 100, htot, vtot); 313 314 if (!detailed) 315 return; 316 317 pr_info("%s: horizontal: fp = %u, %ssync = %u, bp = %u\n", 318 dev_prefix, bt->hfrontporch, 319 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-", 320 bt->hsync, bt->hbackporch); 321 pr_info("%s: vertical: fp = %u, %ssync = %u, bp = %u\n", 322 dev_prefix, bt->vfrontporch, 323 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", 324 bt->vsync, bt->vbackporch); 325 if (bt->interlaced) 326 pr_info("%s: vertical bottom field: fp = %u, %ssync = %u, bp = %u\n", 327 dev_prefix, bt->il_vfrontporch, 328 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-", 329 bt->il_vsync, bt->il_vbackporch); 330 pr_info("%s: pixelclock: %llu\n", dev_prefix, bt->pixelclock); 331 pr_info("%s: flags (0x%x):%s%s%s%s%s%s%s%s%s%s\n", 332 dev_prefix, bt->flags, 333 (bt->flags & V4L2_DV_FL_REDUCED_BLANKING) ? 334 " REDUCED_BLANKING" : "", 335 ((bt->flags & V4L2_DV_FL_REDUCED_BLANKING) && 336 bt->vsync == 8) ? " (V2)" : "", 337 (bt->flags & V4L2_DV_FL_CAN_REDUCE_FPS) ? 338 " CAN_REDUCE_FPS" : "", 339 (bt->flags & V4L2_DV_FL_REDUCED_FPS) ? 340 " REDUCED_FPS" : "", 341 (bt->flags & V4L2_DV_FL_HALF_LINE) ? 342 " HALF_LINE" : "", 343 (bt->flags & V4L2_DV_FL_IS_CE_VIDEO) ? 344 " CE_VIDEO" : "", 345 (bt->flags & V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) ? 346 " FIRST_FIELD_EXTRA_LINE" : "", 347 (bt->flags & V4L2_DV_FL_HAS_PICTURE_ASPECT) ? 348 " HAS_PICTURE_ASPECT" : "", 349 (bt->flags & V4L2_DV_FL_HAS_CEA861_VIC) ? 350 " HAS_CEA861_VIC" : "", 351 (bt->flags & V4L2_DV_FL_HAS_HDMI_VIC) ? 352 " HAS_HDMI_VIC" : ""); 353 pr_info("%s: standards (0x%x):%s%s%s%s%s\n", dev_prefix, bt->standards, 354 (bt->standards & V4L2_DV_BT_STD_CEA861) ? " CEA" : "", 355 (bt->standards & V4L2_DV_BT_STD_DMT) ? " DMT" : "", 356 (bt->standards & V4L2_DV_BT_STD_CVT) ? " CVT" : "", 357 (bt->standards & V4L2_DV_BT_STD_GTF) ? " GTF" : "", 358 (bt->standards & V4L2_DV_BT_STD_SDI) ? " SDI" : ""); 359 if (bt->flags & V4L2_DV_FL_HAS_PICTURE_ASPECT) 360 pr_info("%s: picture aspect (hor:vert): %u:%u\n", dev_prefix, 361 bt->picture_aspect.numerator, 362 bt->picture_aspect.denominator); 363 if (bt->flags & V4L2_DV_FL_HAS_CEA861_VIC) 364 pr_info("%s: CEA-861 VIC: %u\n", dev_prefix, bt->cea861_vic); 365 if (bt->flags & V4L2_DV_FL_HAS_HDMI_VIC) 366 pr_info("%s: HDMI VIC: %u\n", dev_prefix, bt->hdmi_vic); 367 } 368 EXPORT_SYMBOL_GPL(v4l2_print_dv_timings); 369 370 struct v4l2_fract v4l2_dv_timings_aspect_ratio(const struct v4l2_dv_timings *t) 371 { 372 struct v4l2_fract ratio = { 1, 1 }; 373 unsigned long n, d; 374 375 if (t->type != V4L2_DV_BT_656_1120) 376 return ratio; 377 if (!(t->bt.flags & V4L2_DV_FL_HAS_PICTURE_ASPECT)) 378 return ratio; 379 380 ratio.numerator = t->bt.width * t->bt.picture_aspect.denominator; 381 ratio.denominator = t->bt.height * t->bt.picture_aspect.numerator; 382 383 rational_best_approximation(ratio.numerator, ratio.denominator, 384 ratio.numerator, ratio.denominator, &n, &d); 385 ratio.numerator = n; 386 ratio.denominator = d; 387 return ratio; 388 } 389 EXPORT_SYMBOL_GPL(v4l2_dv_timings_aspect_ratio); 390 391 /** v4l2_calc_timeperframe - helper function to calculate timeperframe based 392 * v4l2_dv_timings fields. 393 * @t - Timings for the video mode. 394 * 395 * Calculates the expected timeperframe using the pixel clock value and 396 * horizontal/vertical measures. This means that v4l2_dv_timings structure 397 * must be correctly and fully filled. 398 */ 399 struct v4l2_fract v4l2_calc_timeperframe(const struct v4l2_dv_timings *t) 400 { 401 const struct v4l2_bt_timings *bt = &t->bt; 402 struct v4l2_fract fps_fract = { 1, 1 }; 403 unsigned long n, d; 404 u32 htot, vtot, fps; 405 u64 pclk; 406 407 if (t->type != V4L2_DV_BT_656_1120) 408 return fps_fract; 409 410 htot = V4L2_DV_BT_FRAME_WIDTH(bt); 411 vtot = V4L2_DV_BT_FRAME_HEIGHT(bt); 412 pclk = bt->pixelclock; 413 414 if ((bt->flags & V4L2_DV_FL_CAN_DETECT_REDUCED_FPS) && 415 (bt->flags & V4L2_DV_FL_REDUCED_FPS)) 416 pclk = div_u64(pclk * 1000ULL, 1001); 417 418 fps = (htot * vtot) > 0 ? div_u64((100 * pclk), (htot * vtot)) : 0; 419 if (!fps) 420 return fps_fract; 421 422 rational_best_approximation(fps, 100, fps, 100, &n, &d); 423 424 fps_fract.numerator = d; 425 fps_fract.denominator = n; 426 return fps_fract; 427 } 428 EXPORT_SYMBOL_GPL(v4l2_calc_timeperframe); 429 430 /* 431 * CVT defines 432 * Based on Coordinated Video Timings Standard 433 * version 1.1 September 10, 2003 434 */ 435 436 #define CVT_PXL_CLK_GRAN 250000 /* pixel clock granularity */ 437 #define CVT_PXL_CLK_GRAN_RB_V2 1000 /* granularity for reduced blanking v2*/ 438 439 /* Normal blanking */ 440 #define CVT_MIN_V_BPORCH 7 /* lines */ 441 #define CVT_MIN_V_PORCH_RND 3 /* lines */ 442 #define CVT_MIN_VSYNC_BP 550 /* min time of vsync + back porch (us) */ 443 #define CVT_HSYNC_PERCENT 8 /* nominal hsync as percentage of line */ 444 445 /* Normal blanking for CVT uses GTF to calculate horizontal blanking */ 446 #define CVT_CELL_GRAN 8 /* character cell granularity */ 447 #define CVT_M 600 /* blanking formula gradient */ 448 #define CVT_C 40 /* blanking formula offset */ 449 #define CVT_K 128 /* blanking formula scaling factor */ 450 #define CVT_J 20 /* blanking formula scaling factor */ 451 #define CVT_C_PRIME (((CVT_C - CVT_J) * CVT_K / 256) + CVT_J) 452 #define CVT_M_PRIME (CVT_K * CVT_M / 256) 453 454 /* Reduced Blanking */ 455 #define CVT_RB_MIN_V_BPORCH 7 /* lines */ 456 #define CVT_RB_V_FPORCH 3 /* lines */ 457 #define CVT_RB_MIN_V_BLANK 460 /* us */ 458 #define CVT_RB_H_SYNC 32 /* pixels */ 459 #define CVT_RB_H_BLANK 160 /* pixels */ 460 /* Reduce blanking Version 2 */ 461 #define CVT_RB_V2_H_BLANK 80 /* pixels */ 462 #define CVT_RB_MIN_V_FPORCH 3 /* lines */ 463 #define CVT_RB_V2_MIN_V_FPORCH 1 /* lines */ 464 #define CVT_RB_V_BPORCH 6 /* lines */ 465 466 /** v4l2_detect_cvt - detect if the given timings follow the CVT standard 467 * @frame_height - the total height of the frame (including blanking) in lines. 468 * @hfreq - the horizontal frequency in Hz. 469 * @vsync - the height of the vertical sync in lines. 470 * @active_width - active width of image (does not include blanking). This 471 * information is needed only in case of version 2 of reduced blanking. 472 * In other cases, this parameter does not have any effect on timings. 473 * @polarities - the horizontal and vertical polarities (same as struct 474 * v4l2_bt_timings polarities). 475 * @interlaced - if this flag is true, it indicates interlaced format 476 * @fmt - the resulting timings. 477 * 478 * This function will attempt to detect if the given values correspond to a 479 * valid CVT format. If so, then it will return true, and fmt will be filled 480 * in with the found CVT timings. 481 */ 482 bool v4l2_detect_cvt(unsigned frame_height, 483 unsigned hfreq, 484 unsigned vsync, 485 unsigned active_width, 486 u32 polarities, 487 bool interlaced, 488 struct v4l2_dv_timings *fmt) 489 { 490 int v_fp, v_bp, h_fp, h_bp, hsync; 491 int frame_width, image_height, image_width; 492 bool reduced_blanking; 493 bool rb_v2 = false; 494 unsigned pix_clk; 495 496 if (vsync < 4 || vsync > 8) 497 return false; 498 499 if (polarities == V4L2_DV_VSYNC_POS_POL) 500 reduced_blanking = false; 501 else if (polarities == V4L2_DV_HSYNC_POS_POL) 502 reduced_blanking = true; 503 else 504 return false; 505 506 if (reduced_blanking && vsync == 8) 507 rb_v2 = true; 508 509 if (rb_v2 && active_width == 0) 510 return false; 511 512 if (!rb_v2 && vsync > 7) 513 return false; 514 515 if (hfreq == 0) 516 return false; 517 518 /* Vertical */ 519 if (reduced_blanking) { 520 if (rb_v2) { 521 v_bp = CVT_RB_V_BPORCH; 522 v_fp = (CVT_RB_MIN_V_BLANK * hfreq) / 1000000 + 1; 523 v_fp -= vsync + v_bp; 524 525 if (v_fp < CVT_RB_V2_MIN_V_FPORCH) 526 v_fp = CVT_RB_V2_MIN_V_FPORCH; 527 } else { 528 v_fp = CVT_RB_V_FPORCH; 529 v_bp = (CVT_RB_MIN_V_BLANK * hfreq) / 1000000 + 1; 530 v_bp -= vsync + v_fp; 531 532 if (v_bp < CVT_RB_MIN_V_BPORCH) 533 v_bp = CVT_RB_MIN_V_BPORCH; 534 } 535 } else { 536 v_fp = CVT_MIN_V_PORCH_RND; 537 v_bp = (CVT_MIN_VSYNC_BP * hfreq) / 1000000 + 1 - vsync; 538 539 if (v_bp < CVT_MIN_V_BPORCH) 540 v_bp = CVT_MIN_V_BPORCH; 541 } 542 543 if (interlaced) 544 image_height = (frame_height - 2 * v_fp - 2 * vsync - 2 * v_bp) & ~0x1; 545 else 546 image_height = (frame_height - v_fp - vsync - v_bp + 1) & ~0x1; 547 548 if (image_height < 0) 549 return false; 550 551 /* Aspect ratio based on vsync */ 552 switch (vsync) { 553 case 4: 554 image_width = (image_height * 4) / 3; 555 break; 556 case 5: 557 image_width = (image_height * 16) / 9; 558 break; 559 case 6: 560 image_width = (image_height * 16) / 10; 561 break; 562 case 7: 563 /* special case */ 564 if (image_height == 1024) 565 image_width = (image_height * 5) / 4; 566 else if (image_height == 768) 567 image_width = (image_height * 15) / 9; 568 else 569 return false; 570 break; 571 case 8: 572 image_width = active_width; 573 break; 574 default: 575 return false; 576 } 577 578 if (!rb_v2) 579 image_width = image_width & ~7; 580 581 /* Horizontal */ 582 if (reduced_blanking) { 583 int h_blank; 584 int clk_gran; 585 586 h_blank = rb_v2 ? CVT_RB_V2_H_BLANK : CVT_RB_H_BLANK; 587 clk_gran = rb_v2 ? CVT_PXL_CLK_GRAN_RB_V2 : CVT_PXL_CLK_GRAN; 588 589 pix_clk = (image_width + h_blank) * hfreq; 590 pix_clk = (pix_clk / clk_gran) * clk_gran; 591 592 h_bp = h_blank / 2; 593 hsync = CVT_RB_H_SYNC; 594 h_fp = h_blank - h_bp - hsync; 595 596 frame_width = image_width + h_blank; 597 } else { 598 unsigned ideal_duty_cycle_per_myriad = 599 100 * CVT_C_PRIME - (CVT_M_PRIME * 100000) / hfreq; 600 int h_blank; 601 602 if (ideal_duty_cycle_per_myriad < 2000) 603 ideal_duty_cycle_per_myriad = 2000; 604 605 h_blank = image_width * ideal_duty_cycle_per_myriad / 606 (10000 - ideal_duty_cycle_per_myriad); 607 h_blank = (h_blank / (2 * CVT_CELL_GRAN)) * 2 * CVT_CELL_GRAN; 608 609 pix_clk = (image_width + h_blank) * hfreq; 610 pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN; 611 612 h_bp = h_blank / 2; 613 frame_width = image_width + h_blank; 614 615 hsync = frame_width * CVT_HSYNC_PERCENT / 100; 616 hsync = (hsync / CVT_CELL_GRAN) * CVT_CELL_GRAN; 617 h_fp = h_blank - hsync - h_bp; 618 } 619 620 fmt->type = V4L2_DV_BT_656_1120; 621 fmt->bt.polarities = polarities; 622 fmt->bt.width = image_width; 623 fmt->bt.height = image_height; 624 fmt->bt.hfrontporch = h_fp; 625 fmt->bt.vfrontporch = v_fp; 626 fmt->bt.hsync = hsync; 627 fmt->bt.vsync = vsync; 628 fmt->bt.hbackporch = frame_width - image_width - h_fp - hsync; 629 630 if (!interlaced) { 631 fmt->bt.vbackporch = frame_height - image_height - v_fp - vsync; 632 fmt->bt.interlaced = V4L2_DV_PROGRESSIVE; 633 } else { 634 fmt->bt.vbackporch = (frame_height - image_height - 2 * v_fp - 635 2 * vsync) / 2; 636 fmt->bt.il_vbackporch = frame_height - image_height - 2 * v_fp - 637 2 * vsync - fmt->bt.vbackporch; 638 fmt->bt.il_vfrontporch = v_fp; 639 fmt->bt.il_vsync = vsync; 640 fmt->bt.flags |= V4L2_DV_FL_HALF_LINE; 641 fmt->bt.interlaced = V4L2_DV_INTERLACED; 642 } 643 644 fmt->bt.pixelclock = pix_clk; 645 fmt->bt.standards = V4L2_DV_BT_STD_CVT; 646 647 if (reduced_blanking) 648 fmt->bt.flags |= V4L2_DV_FL_REDUCED_BLANKING; 649 650 return true; 651 } 652 EXPORT_SYMBOL_GPL(v4l2_detect_cvt); 653 654 /* 655 * GTF defines 656 * Based on Generalized Timing Formula Standard 657 * Version 1.1 September 2, 1999 658 */ 659 660 #define GTF_PXL_CLK_GRAN 250000 /* pixel clock granularity */ 661 662 #define GTF_MIN_VSYNC_BP 550 /* min time of vsync + back porch (us) */ 663 #define GTF_V_FP 1 /* vertical front porch (lines) */ 664 #define GTF_CELL_GRAN 8 /* character cell granularity */ 665 666 /* Default */ 667 #define GTF_D_M 600 /* blanking formula gradient */ 668 #define GTF_D_C 40 /* blanking formula offset */ 669 #define GTF_D_K 128 /* blanking formula scaling factor */ 670 #define GTF_D_J 20 /* blanking formula scaling factor */ 671 #define GTF_D_C_PRIME ((((GTF_D_C - GTF_D_J) * GTF_D_K) / 256) + GTF_D_J) 672 #define GTF_D_M_PRIME ((GTF_D_K * GTF_D_M) / 256) 673 674 /* Secondary */ 675 #define GTF_S_M 3600 /* blanking formula gradient */ 676 #define GTF_S_C 40 /* blanking formula offset */ 677 #define GTF_S_K 128 /* blanking formula scaling factor */ 678 #define GTF_S_J 35 /* blanking formula scaling factor */ 679 #define GTF_S_C_PRIME ((((GTF_S_C - GTF_S_J) * GTF_S_K) / 256) + GTF_S_J) 680 #define GTF_S_M_PRIME ((GTF_S_K * GTF_S_M) / 256) 681 682 /** v4l2_detect_gtf - detect if the given timings follow the GTF standard 683 * @frame_height - the total height of the frame (including blanking) in lines. 684 * @hfreq - the horizontal frequency in Hz. 685 * @vsync - the height of the vertical sync in lines. 686 * @polarities - the horizontal and vertical polarities (same as struct 687 * v4l2_bt_timings polarities). 688 * @interlaced - if this flag is true, it indicates interlaced format 689 * @aspect - preferred aspect ratio. GTF has no method of determining the 690 * aspect ratio in order to derive the image width from the 691 * image height, so it has to be passed explicitly. Usually 692 * the native screen aspect ratio is used for this. If it 693 * is not filled in correctly, then 16:9 will be assumed. 694 * @fmt - the resulting timings. 695 * 696 * This function will attempt to detect if the given values correspond to a 697 * valid GTF format. If so, then it will return true, and fmt will be filled 698 * in with the found GTF timings. 699 */ 700 bool v4l2_detect_gtf(unsigned frame_height, 701 unsigned hfreq, 702 unsigned vsync, 703 u32 polarities, 704 bool interlaced, 705 struct v4l2_fract aspect, 706 struct v4l2_dv_timings *fmt) 707 { 708 int pix_clk; 709 int v_fp, v_bp, h_fp, hsync; 710 int frame_width, image_height, image_width; 711 bool default_gtf; 712 int h_blank; 713 714 if (vsync != 3) 715 return false; 716 717 if (polarities == V4L2_DV_VSYNC_POS_POL) 718 default_gtf = true; 719 else if (polarities == V4L2_DV_HSYNC_POS_POL) 720 default_gtf = false; 721 else 722 return false; 723 724 if (hfreq == 0) 725 return false; 726 727 /* Vertical */ 728 v_fp = GTF_V_FP; 729 v_bp = (GTF_MIN_VSYNC_BP * hfreq + 500000) / 1000000 - vsync; 730 if (interlaced) 731 image_height = (frame_height - 2 * v_fp - 2 * vsync - 2 * v_bp) & ~0x1; 732 else 733 image_height = (frame_height - v_fp - vsync - v_bp + 1) & ~0x1; 734 735 if (image_height < 0) 736 return false; 737 738 if (aspect.numerator == 0 || aspect.denominator == 0) { 739 aspect.numerator = 16; 740 aspect.denominator = 9; 741 } 742 image_width = ((image_height * aspect.numerator) / aspect.denominator); 743 image_width = (image_width + GTF_CELL_GRAN/2) & ~(GTF_CELL_GRAN - 1); 744 745 /* Horizontal */ 746 if (default_gtf) { 747 u64 num; 748 u32 den; 749 750 num = ((image_width * GTF_D_C_PRIME * (u64)hfreq) - 751 ((u64)image_width * GTF_D_M_PRIME * 1000)); 752 den = (hfreq * (100 - GTF_D_C_PRIME) + GTF_D_M_PRIME * 1000) * 753 (2 * GTF_CELL_GRAN); 754 h_blank = div_u64((num + (den >> 1)), den); 755 h_blank *= (2 * GTF_CELL_GRAN); 756 } else { 757 u64 num; 758 u32 den; 759 760 num = ((image_width * GTF_S_C_PRIME * (u64)hfreq) - 761 ((u64)image_width * GTF_S_M_PRIME * 1000)); 762 den = (hfreq * (100 - GTF_S_C_PRIME) + GTF_S_M_PRIME * 1000) * 763 (2 * GTF_CELL_GRAN); 764 h_blank = div_u64((num + (den >> 1)), den); 765 h_blank *= (2 * GTF_CELL_GRAN); 766 } 767 768 frame_width = image_width + h_blank; 769 770 pix_clk = (image_width + h_blank) * hfreq; 771 pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN; 772 773 hsync = (frame_width * 8 + 50) / 100; 774 hsync = DIV_ROUND_CLOSEST(hsync, GTF_CELL_GRAN) * GTF_CELL_GRAN; 775 776 h_fp = h_blank / 2 - hsync; 777 778 fmt->type = V4L2_DV_BT_656_1120; 779 fmt->bt.polarities = polarities; 780 fmt->bt.width = image_width; 781 fmt->bt.height = image_height; 782 fmt->bt.hfrontporch = h_fp; 783 fmt->bt.vfrontporch = v_fp; 784 fmt->bt.hsync = hsync; 785 fmt->bt.vsync = vsync; 786 fmt->bt.hbackporch = frame_width - image_width - h_fp - hsync; 787 788 if (!interlaced) { 789 fmt->bt.vbackporch = frame_height - image_height - v_fp - vsync; 790 fmt->bt.interlaced = V4L2_DV_PROGRESSIVE; 791 } else { 792 fmt->bt.vbackporch = (frame_height - image_height - 2 * v_fp - 793 2 * vsync) / 2; 794 fmt->bt.il_vbackporch = frame_height - image_height - 2 * v_fp - 795 2 * vsync - fmt->bt.vbackporch; 796 fmt->bt.il_vfrontporch = v_fp; 797 fmt->bt.il_vsync = vsync; 798 fmt->bt.flags |= V4L2_DV_FL_HALF_LINE; 799 fmt->bt.interlaced = V4L2_DV_INTERLACED; 800 } 801 802 fmt->bt.pixelclock = pix_clk; 803 fmt->bt.standards = V4L2_DV_BT_STD_GTF; 804 805 if (!default_gtf) 806 fmt->bt.flags |= V4L2_DV_FL_REDUCED_BLANKING; 807 808 return true; 809 } 810 EXPORT_SYMBOL_GPL(v4l2_detect_gtf); 811 812 /** v4l2_calc_aspect_ratio - calculate the aspect ratio based on bytes 813 * 0x15 and 0x16 from the EDID. 814 * @hor_landscape - byte 0x15 from the EDID. 815 * @vert_portrait - byte 0x16 from the EDID. 816 * 817 * Determines the aspect ratio from the EDID. 818 * See VESA Enhanced EDID standard, release A, rev 2, section 3.6.2: 819 * "Horizontal and Vertical Screen Size or Aspect Ratio" 820 */ 821 struct v4l2_fract v4l2_calc_aspect_ratio(u8 hor_landscape, u8 vert_portrait) 822 { 823 struct v4l2_fract aspect = { 16, 9 }; 824 u8 ratio; 825 826 /* Nothing filled in, fallback to 16:9 */ 827 if (!hor_landscape && !vert_portrait) 828 return aspect; 829 /* Both filled in, so they are interpreted as the screen size in cm */ 830 if (hor_landscape && vert_portrait) { 831 aspect.numerator = hor_landscape; 832 aspect.denominator = vert_portrait; 833 return aspect; 834 } 835 /* Only one is filled in, so interpret them as a ratio: 836 (val + 99) / 100 */ 837 ratio = hor_landscape | vert_portrait; 838 /* Change some rounded values into the exact aspect ratio */ 839 if (ratio == 79) { 840 aspect.numerator = 16; 841 aspect.denominator = 9; 842 } else if (ratio == 34) { 843 aspect.numerator = 4; 844 aspect.denominator = 3; 845 } else if (ratio == 68) { 846 aspect.numerator = 15; 847 aspect.denominator = 9; 848 } else { 849 aspect.numerator = hor_landscape + 99; 850 aspect.denominator = 100; 851 } 852 if (hor_landscape) 853 return aspect; 854 /* The aspect ratio is for portrait, so swap numerator and denominator */ 855 swap(aspect.denominator, aspect.numerator); 856 return aspect; 857 } 858 EXPORT_SYMBOL_GPL(v4l2_calc_aspect_ratio); 859 860 /** v4l2_hdmi_rx_colorimetry - determine HDMI colorimetry information 861 * based on various InfoFrames. 862 * @avi: the AVI InfoFrame 863 * @hdmi: the HDMI Vendor InfoFrame, may be NULL 864 * @height: the frame height 865 * 866 * Determines the HDMI colorimetry information, i.e. how the HDMI 867 * pixel color data should be interpreted. 868 * 869 * Note that some of the newer features (DCI-P3, HDR) are not yet 870 * implemented: the hdmi.h header needs to be updated to the HDMI 2.0 871 * and CTA-861-G standards. 872 */ 873 struct v4l2_hdmi_colorimetry 874 v4l2_hdmi_rx_colorimetry(const struct hdmi_avi_infoframe *avi, 875 const struct hdmi_vendor_infoframe *hdmi, 876 unsigned int height) 877 { 878 struct v4l2_hdmi_colorimetry c = { 879 V4L2_COLORSPACE_SRGB, 880 V4L2_YCBCR_ENC_DEFAULT, 881 V4L2_QUANTIZATION_FULL_RANGE, 882 V4L2_XFER_FUNC_SRGB 883 }; 884 bool is_ce = avi->video_code || (hdmi && hdmi->vic); 885 bool is_sdtv = height <= 576; 886 bool default_is_lim_range_rgb = avi->video_code > 1; 887 888 switch (avi->colorspace) { 889 case HDMI_COLORSPACE_RGB: 890 /* RGB pixel encoding */ 891 switch (avi->colorimetry) { 892 case HDMI_COLORIMETRY_EXTENDED: 893 switch (avi->extended_colorimetry) { 894 case HDMI_EXTENDED_COLORIMETRY_OPRGB: 895 c.colorspace = V4L2_COLORSPACE_OPRGB; 896 c.xfer_func = V4L2_XFER_FUNC_OPRGB; 897 break; 898 case HDMI_EXTENDED_COLORIMETRY_BT2020: 899 c.colorspace = V4L2_COLORSPACE_BT2020; 900 c.xfer_func = V4L2_XFER_FUNC_709; 901 break; 902 default: 903 break; 904 } 905 break; 906 default: 907 break; 908 } 909 switch (avi->quantization_range) { 910 case HDMI_QUANTIZATION_RANGE_LIMITED: 911 c.quantization = V4L2_QUANTIZATION_LIM_RANGE; 912 break; 913 case HDMI_QUANTIZATION_RANGE_FULL: 914 break; 915 default: 916 if (default_is_lim_range_rgb) 917 c.quantization = V4L2_QUANTIZATION_LIM_RANGE; 918 break; 919 } 920 break; 921 922 default: 923 /* YCbCr pixel encoding */ 924 c.quantization = V4L2_QUANTIZATION_LIM_RANGE; 925 switch (avi->colorimetry) { 926 case HDMI_COLORIMETRY_NONE: 927 if (!is_ce) 928 break; 929 if (is_sdtv) { 930 c.colorspace = V4L2_COLORSPACE_SMPTE170M; 931 c.ycbcr_enc = V4L2_YCBCR_ENC_601; 932 } else { 933 c.colorspace = V4L2_COLORSPACE_REC709; 934 c.ycbcr_enc = V4L2_YCBCR_ENC_709; 935 } 936 c.xfer_func = V4L2_XFER_FUNC_709; 937 break; 938 case HDMI_COLORIMETRY_ITU_601: 939 c.colorspace = V4L2_COLORSPACE_SMPTE170M; 940 c.ycbcr_enc = V4L2_YCBCR_ENC_601; 941 c.xfer_func = V4L2_XFER_FUNC_709; 942 break; 943 case HDMI_COLORIMETRY_ITU_709: 944 c.colorspace = V4L2_COLORSPACE_REC709; 945 c.ycbcr_enc = V4L2_YCBCR_ENC_709; 946 c.xfer_func = V4L2_XFER_FUNC_709; 947 break; 948 case HDMI_COLORIMETRY_EXTENDED: 949 switch (avi->extended_colorimetry) { 950 case HDMI_EXTENDED_COLORIMETRY_XV_YCC_601: 951 c.colorspace = V4L2_COLORSPACE_REC709; 952 c.ycbcr_enc = V4L2_YCBCR_ENC_XV709; 953 c.xfer_func = V4L2_XFER_FUNC_709; 954 break; 955 case HDMI_EXTENDED_COLORIMETRY_XV_YCC_709: 956 c.colorspace = V4L2_COLORSPACE_REC709; 957 c.ycbcr_enc = V4L2_YCBCR_ENC_XV601; 958 c.xfer_func = V4L2_XFER_FUNC_709; 959 break; 960 case HDMI_EXTENDED_COLORIMETRY_S_YCC_601: 961 c.colorspace = V4L2_COLORSPACE_SRGB; 962 c.ycbcr_enc = V4L2_YCBCR_ENC_601; 963 c.xfer_func = V4L2_XFER_FUNC_SRGB; 964 break; 965 case HDMI_EXTENDED_COLORIMETRY_OPYCC_601: 966 c.colorspace = V4L2_COLORSPACE_OPRGB; 967 c.ycbcr_enc = V4L2_YCBCR_ENC_601; 968 c.xfer_func = V4L2_XFER_FUNC_OPRGB; 969 break; 970 case HDMI_EXTENDED_COLORIMETRY_BT2020: 971 c.colorspace = V4L2_COLORSPACE_BT2020; 972 c.ycbcr_enc = V4L2_YCBCR_ENC_BT2020; 973 c.xfer_func = V4L2_XFER_FUNC_709; 974 break; 975 case HDMI_EXTENDED_COLORIMETRY_BT2020_CONST_LUM: 976 c.colorspace = V4L2_COLORSPACE_BT2020; 977 c.ycbcr_enc = V4L2_YCBCR_ENC_BT2020_CONST_LUM; 978 c.xfer_func = V4L2_XFER_FUNC_709; 979 break; 980 default: /* fall back to ITU_709 */ 981 c.colorspace = V4L2_COLORSPACE_REC709; 982 c.ycbcr_enc = V4L2_YCBCR_ENC_709; 983 c.xfer_func = V4L2_XFER_FUNC_709; 984 break; 985 } 986 break; 987 default: 988 break; 989 } 990 /* 991 * YCC Quantization Range signaling is more-or-less broken, 992 * let's just ignore this. 993 */ 994 break; 995 } 996 return c; 997 } 998 EXPORT_SYMBOL_GPL(v4l2_hdmi_rx_colorimetry); 999 1000 /** 1001 * v4l2_get_edid_phys_addr() - find and return the physical address 1002 * 1003 * @edid: pointer to the EDID data 1004 * @size: size in bytes of the EDID data 1005 * @offset: If not %NULL then the location of the physical address 1006 * bytes in the EDID will be returned here. This is set to 0 1007 * if there is no physical address found. 1008 * 1009 * Return: the physical address or CEC_PHYS_ADDR_INVALID if there is none. 1010 */ 1011 u16 v4l2_get_edid_phys_addr(const u8 *edid, unsigned int size, 1012 unsigned int *offset) 1013 { 1014 unsigned int loc = cec_get_edid_spa_location(edid, size); 1015 1016 if (offset) 1017 *offset = loc; 1018 if (loc == 0) 1019 return CEC_PHYS_ADDR_INVALID; 1020 return (edid[loc] << 8) | edid[loc + 1]; 1021 } 1022 EXPORT_SYMBOL_GPL(v4l2_get_edid_phys_addr); 1023 1024 /** 1025 * v4l2_set_edid_phys_addr() - find and set the physical address 1026 * 1027 * @edid: pointer to the EDID data 1028 * @size: size in bytes of the EDID data 1029 * @phys_addr: the new physical address 1030 * 1031 * This function finds the location of the physical address in the EDID 1032 * and fills in the given physical address and updates the checksum 1033 * at the end of the EDID block. It does nothing if the EDID doesn't 1034 * contain a physical address. 1035 */ 1036 void v4l2_set_edid_phys_addr(u8 *edid, unsigned int size, u16 phys_addr) 1037 { 1038 unsigned int loc = cec_get_edid_spa_location(edid, size); 1039 u8 sum = 0; 1040 unsigned int i; 1041 1042 if (loc == 0) 1043 return; 1044 edid[loc] = phys_addr >> 8; 1045 edid[loc + 1] = phys_addr & 0xff; 1046 loc &= ~0x7f; 1047 1048 /* update the checksum */ 1049 for (i = loc; i < loc + 127; i++) 1050 sum += edid[i]; 1051 edid[i] = 256 - sum; 1052 } 1053 EXPORT_SYMBOL_GPL(v4l2_set_edid_phys_addr); 1054 1055 /** 1056 * v4l2_phys_addr_for_input() - calculate the PA for an input 1057 * 1058 * @phys_addr: the physical address of the parent 1059 * @input: the number of the input port, must be between 1 and 15 1060 * 1061 * This function calculates a new physical address based on the input 1062 * port number. For example: 1063 * 1064 * PA = 0.0.0.0 and input = 2 becomes 2.0.0.0 1065 * 1066 * PA = 3.0.0.0 and input = 1 becomes 3.1.0.0 1067 * 1068 * PA = 3.2.1.0 and input = 5 becomes 3.2.1.5 1069 * 1070 * PA = 3.2.1.3 and input = 5 becomes f.f.f.f since it maxed out the depth. 1071 * 1072 * Return: the new physical address or CEC_PHYS_ADDR_INVALID. 1073 */ 1074 u16 v4l2_phys_addr_for_input(u16 phys_addr, u8 input) 1075 { 1076 /* Check if input is sane */ 1077 if (WARN_ON(input == 0 || input > 0xf)) 1078 return CEC_PHYS_ADDR_INVALID; 1079 1080 if (phys_addr == 0) 1081 return input << 12; 1082 1083 if ((phys_addr & 0x0fff) == 0) 1084 return phys_addr | (input << 8); 1085 1086 if ((phys_addr & 0x00ff) == 0) 1087 return phys_addr | (input << 4); 1088 1089 if ((phys_addr & 0x000f) == 0) 1090 return phys_addr | input; 1091 1092 /* 1093 * All nibbles are used so no valid physical addresses can be assigned 1094 * to the input. 1095 */ 1096 return CEC_PHYS_ADDR_INVALID; 1097 } 1098 EXPORT_SYMBOL_GPL(v4l2_phys_addr_for_input); 1099 1100 /** 1101 * v4l2_phys_addr_validate() - validate a physical address from an EDID 1102 * 1103 * @phys_addr: the physical address to validate 1104 * @parent: if not %NULL, then this is filled with the parents PA. 1105 * @port: if not %NULL, then this is filled with the input port. 1106 * 1107 * This validates a physical address as read from an EDID. If the 1108 * PA is invalid (such as 1.0.1.0 since '0' is only allowed at the end), 1109 * then it will return -EINVAL. 1110 * 1111 * The parent PA is passed into %parent and the input port is passed into 1112 * %port. For example: 1113 * 1114 * PA = 0.0.0.0: has parent 0.0.0.0 and input port 0. 1115 * 1116 * PA = 1.0.0.0: has parent 0.0.0.0 and input port 1. 1117 * 1118 * PA = 3.2.0.0: has parent 3.0.0.0 and input port 2. 1119 * 1120 * PA = f.f.f.f: has parent f.f.f.f and input port 0. 1121 * 1122 * Return: 0 if the PA is valid, -EINVAL if not. 1123 */ 1124 int v4l2_phys_addr_validate(u16 phys_addr, u16 *parent, u16 *port) 1125 { 1126 int i; 1127 1128 if (parent) 1129 *parent = phys_addr; 1130 if (port) 1131 *port = 0; 1132 if (phys_addr == CEC_PHYS_ADDR_INVALID) 1133 return 0; 1134 for (i = 0; i < 16; i += 4) 1135 if (phys_addr & (0xf << i)) 1136 break; 1137 if (i == 16) 1138 return 0; 1139 if (parent) 1140 *parent = phys_addr & (0xfff0 << i); 1141 if (port) 1142 *port = (phys_addr >> i) & 0xf; 1143 for (i += 4; i < 16; i += 4) 1144 if ((phys_addr & (0xf << i)) == 0) 1145 return -EINVAL; 1146 return 0; 1147 } 1148 EXPORT_SYMBOL_GPL(v4l2_phys_addr_validate); 1149