xref: /linux/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Samsung S5P Multi Format Codec v 5.1
4  *
5  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
6  * Kamil Debski, <k.debski@samsung.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/videodev2.h>
18 #include <media/v4l2-event.h>
19 #include <linux/workqueue.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/of_reserved_mem.h>
23 #include <media/videobuf2-v4l2.h>
24 #include "s5p_mfc_common.h"
25 #include "s5p_mfc_ctrl.h"
26 #include "s5p_mfc_debug.h"
27 #include "s5p_mfc_dec.h"
28 #include "s5p_mfc_enc.h"
29 #include "s5p_mfc_intr.h"
30 #include "s5p_mfc_iommu.h"
31 #include "s5p_mfc_opr.h"
32 #include "s5p_mfc_cmd.h"
33 #include "s5p_mfc_pm.h"
34 
35 #define S5P_MFC_DEC_NAME	"s5p-mfc-dec"
36 #define S5P_MFC_ENC_NAME	"s5p-mfc-enc"
37 
38 int mfc_debug_level;
39 module_param_named(debug, mfc_debug_level, int, 0644);
40 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
41 
42 static char *mfc_mem_size;
43 module_param_named(mem, mfc_mem_size, charp, 0644);
44 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
45 
46 /* Helper functions for interrupt processing */
47 
48 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)49 void clear_work_bit(struct s5p_mfc_ctx *ctx)
50 {
51 	struct s5p_mfc_dev *dev = ctx->dev;
52 
53 	spin_lock(&dev->condlock);
54 	__clear_bit(ctx->num, &dev->ctx_work_bits);
55 	spin_unlock(&dev->condlock);
56 }
57 
58 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)59 void set_work_bit(struct s5p_mfc_ctx *ctx)
60 {
61 	struct s5p_mfc_dev *dev = ctx->dev;
62 
63 	spin_lock(&dev->condlock);
64 	__set_bit(ctx->num, &dev->ctx_work_bits);
65 	spin_unlock(&dev->condlock);
66 }
67 
68 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)69 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
70 {
71 	struct s5p_mfc_dev *dev = ctx->dev;
72 	unsigned long flags;
73 
74 	spin_lock_irqsave(&dev->condlock, flags);
75 	__clear_bit(ctx->num, &dev->ctx_work_bits);
76 	spin_unlock_irqrestore(&dev->condlock, flags);
77 }
78 
79 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)80 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
81 {
82 	struct s5p_mfc_dev *dev = ctx->dev;
83 	unsigned long flags;
84 
85 	spin_lock_irqsave(&dev->condlock, flags);
86 	__set_bit(ctx->num, &dev->ctx_work_bits);
87 	spin_unlock_irqrestore(&dev->condlock, flags);
88 }
89 
s5p_mfc_get_new_ctx(struct s5p_mfc_dev * dev)90 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
91 {
92 	unsigned long flags;
93 	int ctx;
94 
95 	spin_lock_irqsave(&dev->condlock, flags);
96 	ctx = dev->curr_ctx;
97 	do {
98 		ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
99 		if (ctx == dev->curr_ctx) {
100 			if (!test_bit(ctx, &dev->ctx_work_bits))
101 				ctx = -EAGAIN;
102 			break;
103 		}
104 	} while (!test_bit(ctx, &dev->ctx_work_bits));
105 	spin_unlock_irqrestore(&dev->condlock, flags);
106 
107 	return ctx;
108 }
109 
110 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)111 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
112 			unsigned int err)
113 {
114 	ctx->int_cond = 1;
115 	ctx->int_type = reason;
116 	ctx->int_err = err;
117 	wake_up(&ctx->queue);
118 }
119 
120 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)121 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
122 			unsigned int err)
123 {
124 	dev->int_cond = 1;
125 	dev->int_type = reason;
126 	dev->int_err = err;
127 	wake_up(&dev->queue);
128 }
129 
s5p_mfc_cleanup_queue(struct list_head * lh,struct vb2_queue * vq)130 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
131 {
132 	struct s5p_mfc_buf *b;
133 	int i;
134 
135 	while (!list_empty(lh)) {
136 		b = list_entry(lh->next, struct s5p_mfc_buf, list);
137 		for (i = 0; i < b->b->vb2_buf.num_planes; i++)
138 			vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
139 		vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
140 		list_del(&b->list);
141 	}
142 }
143 
s5p_mfc_watchdog(struct timer_list * t)144 static void s5p_mfc_watchdog(struct timer_list *t)
145 {
146 	struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
147 
148 	if (test_bit(0, &dev->hw_lock))
149 		atomic_inc(&dev->watchdog_cnt);
150 	if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
151 		/*
152 		 * This means that hw is busy and no interrupts were
153 		 * generated by hw for the Nth time of running this
154 		 * watchdog timer. This usually means a serious hw
155 		 * error. Now it is time to kill all instances and
156 		 * reset the MFC.
157 		 */
158 		mfc_err("Time out during waiting for HW\n");
159 		schedule_work(&dev->watchdog_work);
160 	}
161 	dev->watchdog_timer.expires = jiffies +
162 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
163 	add_timer(&dev->watchdog_timer);
164 }
165 
s5p_mfc_watchdog_worker(struct work_struct * work)166 static void s5p_mfc_watchdog_worker(struct work_struct *work)
167 {
168 	struct s5p_mfc_dev *dev;
169 	struct s5p_mfc_ctx *ctx;
170 	unsigned long flags;
171 	int mutex_locked;
172 	int i, ret;
173 
174 	dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
175 
176 	mfc_err("Driver timeout error handling\n");
177 	/*
178 	 * Lock the mutex that protects open and release.
179 	 * This is necessary as they may load and unload firmware.
180 	 */
181 	mutex_locked = mutex_trylock(&dev->mfc_mutex);
182 	if (!mutex_locked)
183 		mfc_err("Error: some instance may be closing/opening\n");
184 	spin_lock_irqsave(&dev->irqlock, flags);
185 
186 	s5p_mfc_clock_off(dev);
187 
188 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
189 		ctx = dev->ctx[i];
190 		if (!ctx)
191 			continue;
192 		ctx->state = MFCINST_ERROR;
193 		s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 		s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
195 		clear_work_bit(ctx);
196 		wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
197 	}
198 	clear_bit(0, &dev->hw_lock);
199 	spin_unlock_irqrestore(&dev->irqlock, flags);
200 
201 	/* De-init MFC */
202 	s5p_mfc_deinit_hw(dev);
203 
204 	/*
205 	 * Double check if there is at least one instance running.
206 	 * If no instance is in memory than no firmware should be present
207 	 */
208 	if (dev->num_inst > 0) {
209 		ret = s5p_mfc_load_firmware(dev);
210 		if (ret) {
211 			mfc_err("Failed to reload FW\n");
212 			goto unlock;
213 		}
214 		s5p_mfc_clock_on(dev);
215 		ret = s5p_mfc_init_hw(dev);
216 		s5p_mfc_clock_off(dev);
217 		if (ret)
218 			mfc_err("Failed to reinit FW\n");
219 	}
220 unlock:
221 	if (mutex_locked)
222 		mutex_unlock(&dev->mfc_mutex);
223 }
224 
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)225 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
226 {
227 	struct s5p_mfc_buf *dst_buf;
228 	struct s5p_mfc_dev *dev = ctx->dev;
229 
230 	ctx->state = MFCINST_FINISHED;
231 	ctx->sequence++;
232 	while (!list_empty(&ctx->dst_queue)) {
233 		dst_buf = list_entry(ctx->dst_queue.next,
234 				     struct s5p_mfc_buf, list);
235 		mfc_debug(2, "Cleaning up buffer: %d\n",
236 					  dst_buf->b->vb2_buf.index);
237 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
238 		vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
239 		list_del(&dst_buf->list);
240 		dst_buf->flags |= MFC_BUF_FLAG_EOS;
241 		ctx->dst_queue_cnt--;
242 		dst_buf->b->sequence = (ctx->sequence++);
243 
244 		if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
245 			s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
246 			dst_buf->b->field = V4L2_FIELD_NONE;
247 		else
248 			dst_buf->b->field = V4L2_FIELD_INTERLACED;
249 		dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
250 
251 		ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
252 		vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
253 	}
254 }
255 
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)256 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
257 {
258 	struct s5p_mfc_dev *dev = ctx->dev;
259 	struct s5p_mfc_buf *dst_buf, *src_buf;
260 	u32 dec_y_addr;
261 	unsigned int frame_type;
262 
263 	/* Make sure we actually have a new frame before continuing. */
264 	frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
265 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
266 		return;
267 	dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
268 
269 	/*
270 	 * Copy timestamp / timecode from decoded src to dst and set
271 	 * appropriate flags.
272 	 */
273 	src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
274 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
275 		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
276 
277 		if (addr == dec_y_addr) {
278 			dst_buf->b->timecode = src_buf->b->timecode;
279 			dst_buf->b->vb2_buf.timestamp =
280 						src_buf->b->vb2_buf.timestamp;
281 			dst_buf->b->flags &=
282 				~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
283 			dst_buf->b->flags |=
284 				src_buf->b->flags
285 				& V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
286 			switch (frame_type) {
287 			case S5P_FIMV_DECODE_FRAME_I_FRAME:
288 				dst_buf->b->flags |=
289 						V4L2_BUF_FLAG_KEYFRAME;
290 				break;
291 			case S5P_FIMV_DECODE_FRAME_P_FRAME:
292 				dst_buf->b->flags |=
293 						V4L2_BUF_FLAG_PFRAME;
294 				break;
295 			case S5P_FIMV_DECODE_FRAME_B_FRAME:
296 				dst_buf->b->flags |=
297 						V4L2_BUF_FLAG_BFRAME;
298 				break;
299 			default:
300 				/*
301 				 * Don't know how to handle
302 				 * S5P_FIMV_DECODE_FRAME_OTHER_FRAME.
303 				 */
304 				mfc_debug(2, "Unexpected frame type: %d\n",
305 						frame_type);
306 			}
307 			break;
308 		}
309 	}
310 }
311 
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)312 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
313 {
314 	struct s5p_mfc_dev *dev = ctx->dev;
315 	struct s5p_mfc_buf  *dst_buf;
316 	u32 dspl_y_addr;
317 	unsigned int frame_type;
318 
319 	dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
320 	if (IS_MFCV6_PLUS(dev))
321 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
322 			get_disp_frame_type, ctx);
323 	else
324 		frame_type = s5p_mfc_hw_call(dev->mfc_ops,
325 			get_dec_frame_type, dev);
326 
327 	/* If frame is same as previous then skip and do not dequeue */
328 	if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
329 		if (!ctx->after_packed_pb)
330 			ctx->sequence++;
331 		ctx->after_packed_pb = 0;
332 		return;
333 	}
334 	ctx->sequence++;
335 	/*
336 	 * The MFC returns address of the buffer, now we have to
337 	 * check which vb2_buffer does it correspond to
338 	 */
339 	list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
340 		u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
341 
342 		/* Check if this is the buffer we're looking for */
343 		if (addr == dspl_y_addr) {
344 			list_del(&dst_buf->list);
345 			ctx->dst_queue_cnt--;
346 			dst_buf->b->sequence = ctx->sequence;
347 			if (s5p_mfc_hw_call(dev->mfc_ops,
348 					get_pic_type_top, ctx) ==
349 				s5p_mfc_hw_call(dev->mfc_ops,
350 					get_pic_type_bot, ctx))
351 				dst_buf->b->field = V4L2_FIELD_NONE;
352 			else
353 				dst_buf->b->field =
354 							V4L2_FIELD_INTERLACED;
355 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
356 						ctx->luma_size);
357 			vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
358 						ctx->chroma_size);
359 			clear_bit(dst_buf->b->vb2_buf.index,
360 							&ctx->dec_dst_flag);
361 
362 			vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
363 				VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
364 
365 			break;
366 		}
367 	}
368 }
369 
370 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)371 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
372 					unsigned int reason, unsigned int err)
373 {
374 	struct s5p_mfc_dev *dev = ctx->dev;
375 	unsigned int dst_frame_status;
376 	unsigned int dec_frame_status;
377 	struct s5p_mfc_buf *src_buf;
378 	unsigned int res_change;
379 
380 	dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
381 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
382 	dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
383 				& S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
384 	res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
385 				& S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
386 				>> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
387 	mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
388 	if (ctx->state == MFCINST_RES_CHANGE_INIT)
389 		ctx->state = MFCINST_RES_CHANGE_FLUSH;
390 	if (res_change == S5P_FIMV_RES_INCREASE ||
391 		res_change == S5P_FIMV_RES_DECREASE) {
392 		ctx->state = MFCINST_RES_CHANGE_INIT;
393 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
394 		wake_up_ctx(ctx, reason, err);
395 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
396 		s5p_mfc_clock_off(dev);
397 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
398 		return;
399 	}
400 	if (ctx->dpb_flush_flag)
401 		ctx->dpb_flush_flag = 0;
402 
403 	/* All frames remaining in the buffer have been extracted  */
404 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
405 		if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
406 			static const struct v4l2_event ev_src_ch = {
407 				.type = V4L2_EVENT_SOURCE_CHANGE,
408 				.u.src_change.changes =
409 					V4L2_EVENT_SRC_CH_RESOLUTION,
410 			};
411 
412 			s5p_mfc_handle_frame_all_extracted(ctx);
413 			ctx->state = MFCINST_RES_CHANGE_END;
414 			v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
415 
416 			goto leave_handle_frame;
417 		} else {
418 			s5p_mfc_handle_frame_all_extracted(ctx);
419 		}
420 	}
421 
422 	if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
423 		s5p_mfc_handle_frame_copy_time(ctx);
424 
425 	/* A frame has been decoded and is in the buffer  */
426 	if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
427 	    dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
428 		s5p_mfc_handle_frame_new(ctx, err);
429 	} else {
430 		mfc_debug(2, "No frame decode\n");
431 	}
432 	/* Mark source buffer as complete */
433 	if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
434 		&& !list_empty(&ctx->src_queue)) {
435 		src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
436 								list);
437 		ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
438 						get_consumed_stream, dev);
439 		if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
440 			ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
441 			ctx->consumed_stream + STUFF_BYTE <
442 			src_buf->b->vb2_buf.planes[0].bytesused) {
443 			/* Run MFC again on the same buffer */
444 			mfc_debug(2, "Running again the same buffer\n");
445 			ctx->after_packed_pb = 1;
446 		} else {
447 			mfc_debug(2, "MFC needs next buffer\n");
448 			ctx->consumed_stream = 0;
449 			if (src_buf->flags & MFC_BUF_FLAG_EOS)
450 				ctx->state = MFCINST_FINISHING;
451 			list_del(&src_buf->list);
452 			ctx->src_queue_cnt--;
453 			if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
454 				vb2_buffer_done(&src_buf->b->vb2_buf,
455 						VB2_BUF_STATE_ERROR);
456 			else
457 				vb2_buffer_done(&src_buf->b->vb2_buf,
458 						VB2_BUF_STATE_DONE);
459 		}
460 	}
461 leave_handle_frame:
462 	if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
463 				    || ctx->dst_queue_cnt < ctx->pb_count)
464 		clear_work_bit(ctx);
465 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
466 	wake_up_ctx(ctx, reason, err);
467 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
468 	s5p_mfc_clock_off(dev);
469 	/* if suspending, wake up device and do not try_run again*/
470 	if (test_bit(0, &dev->enter_suspend))
471 		wake_up_dev(dev, reason, err);
472 	else
473 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
474 }
475 
476 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)477 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
478 		struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
479 {
480 	mfc_err("Interrupt Error: %08x\n", err);
481 
482 	if (ctx) {
483 		/* Error recovery is dependent on the state of context */
484 		switch (ctx->state) {
485 		case MFCINST_RES_CHANGE_INIT:
486 		case MFCINST_RES_CHANGE_FLUSH:
487 		case MFCINST_RES_CHANGE_END:
488 		case MFCINST_FINISHING:
489 		case MFCINST_FINISHED:
490 		case MFCINST_RUNNING:
491 			/*
492 			 * It is highly probable that an error occurred
493 			 * while decoding a frame
494 			 */
495 			clear_work_bit(ctx);
496 			ctx->state = MFCINST_ERROR;
497 			/* Mark all dst buffers as having an error */
498 			s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
499 			/* Mark all src buffers as having an error */
500 			s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
501 			wake_up_ctx(ctx, reason, err);
502 			break;
503 		default:
504 			clear_work_bit(ctx);
505 			ctx->state = MFCINST_ERROR;
506 			wake_up_ctx(ctx, reason, err);
507 			break;
508 		}
509 	}
510 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
511 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
512 	s5p_mfc_clock_off(dev);
513 	wake_up_dev(dev, reason, err);
514 }
515 
516 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)517 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
518 				 unsigned int reason, unsigned int err)
519 {
520 	struct s5p_mfc_dev *dev;
521 
522 	if (!ctx)
523 		return;
524 	dev = ctx->dev;
525 	if (ctx->c_ops->post_seq_start) {
526 		if (ctx->c_ops->post_seq_start(ctx))
527 			mfc_err("post_seq_start() failed\n");
528 	} else {
529 		ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
530 				dev);
531 		ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
532 				dev);
533 
534 		s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
535 
536 		ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
537 				dev);
538 		ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
539 				dev);
540 		if (FW_HAS_E_MIN_SCRATCH_BUF(dev))
541 			ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
542 						get_min_scratch_buf_size, dev);
543 		if (ctx->img_width == 0 || ctx->img_height == 0)
544 			ctx->state = MFCINST_ERROR;
545 		else
546 			ctx->state = MFCINST_HEAD_PARSED;
547 
548 		if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
549 			ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
550 				!list_empty(&ctx->src_queue)) {
551 			struct s5p_mfc_buf *src_buf;
552 
553 			src_buf = list_entry(ctx->src_queue.next,
554 					struct s5p_mfc_buf, list);
555 			if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
556 						dev) <
557 					src_buf->b->vb2_buf.planes[0].bytesused)
558 				ctx->head_processed = 0;
559 			else
560 				ctx->head_processed = 1;
561 		} else {
562 			ctx->head_processed = 1;
563 		}
564 	}
565 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
566 	clear_work_bit(ctx);
567 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
568 	s5p_mfc_clock_off(dev);
569 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
570 	wake_up_ctx(ctx, reason, err);
571 }
572 
573 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)574 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
575 				 unsigned int reason, unsigned int err)
576 {
577 	struct s5p_mfc_buf *src_buf;
578 	struct s5p_mfc_dev *dev;
579 
580 	if (!ctx)
581 		return;
582 	dev = ctx->dev;
583 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
584 	ctx->int_type = reason;
585 	ctx->int_err = err;
586 	ctx->int_cond = 1;
587 	clear_work_bit(ctx);
588 	if (err == 0) {
589 		ctx->state = MFCINST_RUNNING;
590 		if (!ctx->dpb_flush_flag && ctx->head_processed) {
591 			if (!list_empty(&ctx->src_queue)) {
592 				src_buf = list_entry(ctx->src_queue.next,
593 					     struct s5p_mfc_buf, list);
594 				list_del(&src_buf->list);
595 				ctx->src_queue_cnt--;
596 				vb2_buffer_done(&src_buf->b->vb2_buf,
597 						VB2_BUF_STATE_DONE);
598 			}
599 		} else {
600 			ctx->dpb_flush_flag = 0;
601 		}
602 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
603 
604 		s5p_mfc_clock_off(dev);
605 
606 		wake_up(&ctx->queue);
607 		if (ctx->src_queue_cnt >= 1 && ctx->dst_queue_cnt >= 1)
608 			set_work_bit_irqsave(ctx);
609 		s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
610 	} else {
611 		WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
612 
613 		s5p_mfc_clock_off(dev);
614 
615 		wake_up(&ctx->queue);
616 	}
617 }
618 
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx)619 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
620 {
621 	struct s5p_mfc_dev *dev = ctx->dev;
622 	struct s5p_mfc_buf *mb_entry;
623 
624 	mfc_debug(2, "Stream completed\n");
625 
626 	ctx->state = MFCINST_FINISHED;
627 
628 	if (!list_empty(&ctx->dst_queue)) {
629 		mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
630 									list);
631 		list_del(&mb_entry->list);
632 		ctx->dst_queue_cnt--;
633 		vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
634 		vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
635 	}
636 
637 	clear_work_bit(ctx);
638 
639 	WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
640 
641 	s5p_mfc_clock_off(dev);
642 	wake_up(&ctx->queue);
643 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
644 }
645 
646 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)647 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
648 {
649 	struct s5p_mfc_dev *dev = priv;
650 	struct s5p_mfc_ctx *ctx;
651 	unsigned int reason;
652 	unsigned int err;
653 
654 	mfc_debug_enter();
655 	/* Reset the timeout watchdog */
656 	atomic_set(&dev->watchdog_cnt, 0);
657 	spin_lock(&dev->irqlock);
658 	ctx = dev->ctx[dev->curr_ctx];
659 	/* Get the reason of interrupt and the error code */
660 	reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
661 	err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
662 	mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
663 	switch (reason) {
664 	case S5P_MFC_R2H_CMD_ERR_RET:
665 		/* An error has occurred */
666 		if (ctx->state == MFCINST_RUNNING &&
667 			(s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
668 				dev->warn_start ||
669 				err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
670 				err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
671 				err == S5P_FIMV_ERR_TIMEOUT))
672 			s5p_mfc_handle_frame(ctx, reason, err);
673 		else
674 			s5p_mfc_handle_error(dev, ctx, reason, err);
675 		clear_bit(0, &dev->enter_suspend);
676 		break;
677 
678 	case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
679 	case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
680 	case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
681 		if (ctx->c_ops->post_frame_start) {
682 			if (ctx->c_ops->post_frame_start(ctx))
683 				mfc_err("post_frame_start() failed\n");
684 
685 			if (ctx->state == MFCINST_FINISHING &&
686 						list_empty(&ctx->ref_queue)) {
687 				s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
688 				s5p_mfc_handle_stream_complete(ctx);
689 				break;
690 			}
691 			s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
692 			WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
693 			s5p_mfc_clock_off(dev);
694 			wake_up_ctx(ctx, reason, err);
695 			s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
696 		} else {
697 			s5p_mfc_handle_frame(ctx, reason, err);
698 		}
699 		break;
700 
701 	case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
702 		s5p_mfc_handle_seq_done(ctx, reason, err);
703 		break;
704 
705 	case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
706 		ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
707 		ctx->state = MFCINST_GOT_INST;
708 		goto irq_cleanup_hw;
709 
710 	case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
711 		ctx->inst_no = MFC_NO_INSTANCE_SET;
712 		ctx->state = MFCINST_FREE;
713 		goto irq_cleanup_hw;
714 
715 	case S5P_MFC_R2H_CMD_SYS_INIT_RET:
716 	case S5P_MFC_R2H_CMD_FW_STATUS_RET:
717 	case S5P_MFC_R2H_CMD_SLEEP_RET:
718 	case S5P_MFC_R2H_CMD_WAKEUP_RET:
719 		if (ctx)
720 			clear_work_bit(ctx);
721 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
722 		clear_bit(0, &dev->hw_lock);
723 		clear_bit(0, &dev->enter_suspend);
724 		wake_up_dev(dev, reason, err);
725 		break;
726 
727 	case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
728 		s5p_mfc_handle_init_buffers(ctx, reason, err);
729 		break;
730 
731 	case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
732 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
733 		ctx->int_type = reason;
734 		ctx->int_err = err;
735 		s5p_mfc_handle_stream_complete(ctx);
736 		break;
737 
738 	case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
739 		ctx->state = MFCINST_RUNNING;
740 		goto irq_cleanup_hw;
741 
742 	default:
743 		mfc_debug(2, "Unknown int reason\n");
744 		s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
745 	}
746 	spin_unlock(&dev->irqlock);
747 	mfc_debug_leave();
748 	return IRQ_HANDLED;
749 irq_cleanup_hw:
750 	s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
751 	ctx->int_type = reason;
752 	ctx->int_err = err;
753 	ctx->int_cond = 1;
754 	if (test_and_clear_bit(0, &dev->hw_lock) == 0)
755 		mfc_err("Failed to unlock hw\n");
756 
757 	s5p_mfc_clock_off(dev);
758 	clear_work_bit(ctx);
759 	wake_up(&ctx->queue);
760 
761 	s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
762 	spin_unlock(&dev->irqlock);
763 	mfc_debug(2, "Exit via irq_cleanup_hw\n");
764 	return IRQ_HANDLED;
765 }
766 
767 /* Open an MFC node */
s5p_mfc_open(struct file * file)768 static int s5p_mfc_open(struct file *file)
769 {
770 	struct video_device *vdev = video_devdata(file);
771 	struct s5p_mfc_dev *dev = video_drvdata(file);
772 	struct s5p_mfc_ctx *ctx = NULL;
773 	struct vb2_queue *q;
774 	int ret = 0;
775 
776 	mfc_debug_enter();
777 	if (mutex_lock_interruptible(&dev->mfc_mutex))
778 		return -ERESTARTSYS;
779 	dev->num_inst++;	/* It is guarded by mfc_mutex in vfd */
780 	/* Allocate memory for context */
781 	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
782 	if (!ctx) {
783 		ret = -ENOMEM;
784 		goto err_alloc;
785 	}
786 	init_waitqueue_head(&ctx->queue);
787 	v4l2_fh_init(&ctx->fh, vdev);
788 	file->private_data = &ctx->fh;
789 	v4l2_fh_add(&ctx->fh);
790 	ctx->dev = dev;
791 	INIT_LIST_HEAD(&ctx->src_queue);
792 	INIT_LIST_HEAD(&ctx->dst_queue);
793 	ctx->src_queue_cnt = 0;
794 	ctx->dst_queue_cnt = 0;
795 	ctx->is_422 = 0;
796 	ctx->is_10bit = 0;
797 	/* Get context number */
798 	ctx->num = 0;
799 	while (dev->ctx[ctx->num]) {
800 		ctx->num++;
801 		if (ctx->num >= MFC_NUM_CONTEXTS) {
802 			mfc_debug(2, "Too many open contexts\n");
803 			ret = -EBUSY;
804 			goto err_no_ctx;
805 		}
806 	}
807 	/* Mark context as idle */
808 	clear_work_bit_irqsave(ctx);
809 	dev->ctx[ctx->num] = ctx;
810 	if (vdev == dev->vfd_dec) {
811 		ctx->type = MFCINST_DECODER;
812 		ctx->c_ops = get_dec_codec_ops();
813 		s5p_mfc_dec_init(ctx);
814 		/* Setup ctrl handler */
815 		ret = s5p_mfc_dec_ctrls_setup(ctx);
816 		if (ret) {
817 			mfc_err("Failed to setup mfc controls\n");
818 			goto err_ctrls_setup;
819 		}
820 	} else if (vdev == dev->vfd_enc) {
821 		ctx->type = MFCINST_ENCODER;
822 		ctx->c_ops = get_enc_codec_ops();
823 		/* only for encoder */
824 		INIT_LIST_HEAD(&ctx->ref_queue);
825 		ctx->ref_queue_cnt = 0;
826 		s5p_mfc_enc_init(ctx);
827 		/* Setup ctrl handler */
828 		ret = s5p_mfc_enc_ctrls_setup(ctx);
829 		if (ret) {
830 			mfc_err("Failed to setup mfc controls\n");
831 			goto err_ctrls_setup;
832 		}
833 	} else {
834 		ret = -ENOENT;
835 		goto err_bad_node;
836 	}
837 	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
838 	ctx->inst_no = MFC_NO_INSTANCE_SET;
839 	/* Load firmware if this is the first instance */
840 	if (dev->num_inst == 1) {
841 		dev->watchdog_timer.expires = jiffies +
842 					msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
843 		add_timer(&dev->watchdog_timer);
844 		ret = s5p_mfc_power_on(dev);
845 		if (ret < 0) {
846 			mfc_err("power on failed\n");
847 			goto err_pwr_enable;
848 		}
849 		s5p_mfc_clock_on(dev);
850 		ret = s5p_mfc_load_firmware(dev);
851 		if (ret) {
852 			s5p_mfc_clock_off(dev);
853 			goto err_load_fw;
854 		}
855 		/* Init the FW */
856 		ret = s5p_mfc_init_hw(dev);
857 		s5p_mfc_clock_off(dev);
858 		if (ret)
859 			goto err_init_hw;
860 	}
861 	/* Init videobuf2 queue for CAPTURE */
862 	q = &ctx->vq_dst;
863 	q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
864 	q->drv_priv = &ctx->fh;
865 	q->lock = &dev->mfc_mutex;
866 	if (vdev == dev->vfd_dec) {
867 		q->io_modes = VB2_MMAP;
868 		q->ops = get_dec_queue_ops();
869 	} else if (vdev == dev->vfd_enc) {
870 		q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
871 		q->ops = get_enc_queue_ops();
872 	} else {
873 		ret = -ENOENT;
874 		goto err_queue_init;
875 	}
876 	/*
877 	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
878 	 * faster allocation.
879 	 */
880 	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
881 	q->mem_ops = &vb2_dma_contig_memops;
882 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
883 	ret = vb2_queue_init(q);
884 	if (ret) {
885 		mfc_err("Failed to initialize videobuf2 queue(capture)\n");
886 		goto err_queue_init;
887 	}
888 	/* Init videobuf2 queue for OUTPUT */
889 	q = &ctx->vq_src;
890 	q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
891 	q->drv_priv = &ctx->fh;
892 	q->lock = &dev->mfc_mutex;
893 	if (vdev == dev->vfd_dec) {
894 		q->io_modes = VB2_MMAP;
895 		q->ops = get_dec_queue_ops();
896 	} else if (vdev == dev->vfd_enc) {
897 		q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
898 		q->ops = get_enc_queue_ops();
899 	} else {
900 		ret = -ENOENT;
901 		goto err_queue_init;
902 	}
903 	/* One way to indicate end-of-stream for MFC is to set the
904 	 * bytesused == 0. However by default videobuf2 handles bytesused
905 	 * equal to 0 as a special case and changes its value to the size
906 	 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
907 	 * will keep the value of bytesused intact.
908 	 */
909 	q->allow_zero_bytesused = 1;
910 
911 	/*
912 	 * We'll do mostly sequential access, so sacrifice TLB efficiency for
913 	 * faster allocation.
914 	 */
915 	q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
916 	q->mem_ops = &vb2_dma_contig_memops;
917 	q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
918 	ret = vb2_queue_init(q);
919 	if (ret) {
920 		mfc_err("Failed to initialize videobuf2 queue(output)\n");
921 		goto err_queue_init;
922 	}
923 	mutex_unlock(&dev->mfc_mutex);
924 	mfc_debug_leave();
925 	return ret;
926 	/* Deinit when failure occurred */
927 err_queue_init:
928 	if (dev->num_inst == 1)
929 		s5p_mfc_deinit_hw(dev);
930 err_init_hw:
931 err_load_fw:
932 err_pwr_enable:
933 	if (dev->num_inst == 1) {
934 		if (s5p_mfc_power_off(dev) < 0)
935 			mfc_err("power off failed\n");
936 		del_timer_sync(&dev->watchdog_timer);
937 	}
938 err_ctrls_setup:
939 	s5p_mfc_dec_ctrls_delete(ctx);
940 err_bad_node:
941 	dev->ctx[ctx->num] = NULL;
942 err_no_ctx:
943 	v4l2_fh_del(&ctx->fh);
944 	v4l2_fh_exit(&ctx->fh);
945 	kfree(ctx);
946 err_alloc:
947 	dev->num_inst--;
948 	mutex_unlock(&dev->mfc_mutex);
949 	mfc_debug_leave();
950 	return ret;
951 }
952 
953 /* Release MFC context */
s5p_mfc_release(struct file * file)954 static int s5p_mfc_release(struct file *file)
955 {
956 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
957 	struct s5p_mfc_dev *dev = ctx->dev;
958 
959 	/* if dev is null, do cleanup that doesn't need dev */
960 	mfc_debug_enter();
961 	if (dev)
962 		mutex_lock(&dev->mfc_mutex);
963 	vb2_queue_release(&ctx->vq_src);
964 	vb2_queue_release(&ctx->vq_dst);
965 	if (dev) {
966 		s5p_mfc_clock_on(dev);
967 
968 		/* Mark context as idle */
969 		clear_work_bit_irqsave(ctx);
970 		/*
971 		 * If instance was initialised and not yet freed,
972 		 * return instance and free resources
973 		 */
974 		if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
975 			mfc_debug(2, "Has to free instance\n");
976 			s5p_mfc_close_mfc_inst(dev, ctx);
977 		}
978 		/* hardware locking scheme */
979 		if (dev->curr_ctx == ctx->num)
980 			clear_bit(0, &dev->hw_lock);
981 		dev->num_inst--;
982 		if (dev->num_inst == 0) {
983 			mfc_debug(2, "Last instance\n");
984 			s5p_mfc_deinit_hw(dev);
985 			del_timer_sync(&dev->watchdog_timer);
986 			s5p_mfc_clock_off(dev);
987 			if (s5p_mfc_power_off(dev) < 0)
988 				mfc_err("Power off failed\n");
989 		} else {
990 			mfc_debug(2, "Shutting down clock\n");
991 			s5p_mfc_clock_off(dev);
992 		}
993 	}
994 	if (dev)
995 		dev->ctx[ctx->num] = NULL;
996 	s5p_mfc_dec_ctrls_delete(ctx);
997 	v4l2_fh_del(&ctx->fh);
998 	/* vdev is gone if dev is null */
999 	if (dev)
1000 		v4l2_fh_exit(&ctx->fh);
1001 	kfree(ctx);
1002 	mfc_debug_leave();
1003 	if (dev)
1004 		mutex_unlock(&dev->mfc_mutex);
1005 
1006 	return 0;
1007 }
1008 
1009 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)1010 static __poll_t s5p_mfc_poll(struct file *file,
1011 				 struct poll_table_struct *wait)
1012 {
1013 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1014 	struct s5p_mfc_dev *dev = ctx->dev;
1015 	struct vb2_queue *src_q, *dst_q;
1016 	struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1017 	__poll_t rc = 0;
1018 	unsigned long flags;
1019 
1020 	mutex_lock(&dev->mfc_mutex);
1021 	src_q = &ctx->vq_src;
1022 	dst_q = &ctx->vq_dst;
1023 	/*
1024 	 * There has to be at least one buffer queued on each queued_list, which
1025 	 * means either in driver already or waiting for driver to claim it
1026 	 * and start processing.
1027 	 */
1028 	if ((!vb2_is_streaming(src_q) || list_empty(&src_q->queued_list)) &&
1029 	    (!vb2_is_streaming(dst_q) || list_empty(&dst_q->queued_list))) {
1030 		rc = EPOLLERR;
1031 		goto end;
1032 	}
1033 	mutex_unlock(&dev->mfc_mutex);
1034 	poll_wait(file, &ctx->fh.wait, wait);
1035 	poll_wait(file, &src_q->done_wq, wait);
1036 	poll_wait(file, &dst_q->done_wq, wait);
1037 	mutex_lock(&dev->mfc_mutex);
1038 	if (v4l2_event_pending(&ctx->fh))
1039 		rc |= EPOLLPRI;
1040 	spin_lock_irqsave(&src_q->done_lock, flags);
1041 	if (!list_empty(&src_q->done_list))
1042 		src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1043 								done_entry);
1044 	if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1045 				|| src_vb->state == VB2_BUF_STATE_ERROR))
1046 		rc |= EPOLLOUT | EPOLLWRNORM;
1047 	spin_unlock_irqrestore(&src_q->done_lock, flags);
1048 	spin_lock_irqsave(&dst_q->done_lock, flags);
1049 	if (!list_empty(&dst_q->done_list))
1050 		dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1051 								done_entry);
1052 	if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1053 				|| dst_vb->state == VB2_BUF_STATE_ERROR))
1054 		rc |= EPOLLIN | EPOLLRDNORM;
1055 	spin_unlock_irqrestore(&dst_q->done_lock, flags);
1056 end:
1057 	mutex_unlock(&dev->mfc_mutex);
1058 	return rc;
1059 }
1060 
1061 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)1062 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1063 {
1064 	struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1065 	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1066 	int ret;
1067 
1068 	if (offset < DST_QUEUE_OFF_BASE) {
1069 		mfc_debug(2, "mmapping source\n");
1070 		ret = vb2_mmap(&ctx->vq_src, vma);
1071 	} else {		/* capture */
1072 		mfc_debug(2, "mmapping destination\n");
1073 		vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1074 		ret = vb2_mmap(&ctx->vq_dst, vma);
1075 	}
1076 	return ret;
1077 }
1078 
1079 /* v4l2 ops */
1080 static const struct v4l2_file_operations s5p_mfc_fops = {
1081 	.owner = THIS_MODULE,
1082 	.open = s5p_mfc_open,
1083 	.release = s5p_mfc_release,
1084 	.poll = s5p_mfc_poll,
1085 	.unlocked_ioctl = video_ioctl2,
1086 	.mmap = s5p_mfc_mmap,
1087 };
1088 
1089 /* DMA memory related helper functions */
s5p_mfc_memdev_release(struct device * dev)1090 static void s5p_mfc_memdev_release(struct device *dev)
1091 {
1092 	of_reserved_mem_device_release(dev);
1093 }
1094 
s5p_mfc_alloc_memdev(struct device * dev,const char * name,unsigned int idx)1095 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1096 					   const char *name, unsigned int idx)
1097 {
1098 	struct device *child;
1099 	int ret;
1100 
1101 	child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1102 	if (!child)
1103 		return NULL;
1104 
1105 	device_initialize(child);
1106 	dev_set_name(child, "%s:%s", dev_name(dev), name);
1107 	child->parent = dev;
1108 	child->coherent_dma_mask = dev->coherent_dma_mask;
1109 	child->dma_mask = dev->dma_mask;
1110 	child->release = s5p_mfc_memdev_release;
1111 	child->dma_parms = devm_kzalloc(dev, sizeof(*child->dma_parms),
1112 					GFP_KERNEL);
1113 	if (!child->dma_parms)
1114 		goto err;
1115 
1116 	/*
1117 	 * The memdevs are not proper OF platform devices, so in order for them
1118 	 * to be treated as valid DMA masters we need a bit of a hack to force
1119 	 * them to inherit the MFC node's DMA configuration.
1120 	 */
1121 	of_dma_configure(child, dev->of_node, true);
1122 
1123 	if (device_add(child) == 0) {
1124 		ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1125 							 idx);
1126 		if (ret == 0)
1127 			return child;
1128 		device_del(child);
1129 	}
1130 err:
1131 	put_device(child);
1132 	return NULL;
1133 }
1134 
s5p_mfc_configure_2port_memory(struct s5p_mfc_dev * mfc_dev)1135 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1136 {
1137 	struct device *dev = &mfc_dev->plat_dev->dev;
1138 	void *bank2_virt;
1139 	dma_addr_t bank2_dma_addr;
1140 	unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1141 	int ret;
1142 
1143 	/*
1144 	 * Create and initialize virtual devices for accessing
1145 	 * reserved memory regions.
1146 	 */
1147 	mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1148 							   BANK_L_CTX);
1149 	if (!mfc_dev->mem_dev[BANK_L_CTX])
1150 		return -ENODEV;
1151 	mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1152 							   BANK_R_CTX);
1153 	if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1154 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1155 		return -ENODEV;
1156 	}
1157 
1158 	/* Allocate memory for firmware and initialize both banks addresses */
1159 	ret = s5p_mfc_alloc_firmware(mfc_dev);
1160 	if (ret) {
1161 		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1162 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1163 		return ret;
1164 	}
1165 
1166 	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1167 
1168 	bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1169 				       align_size, &bank2_dma_addr, GFP_KERNEL);
1170 	if (!bank2_virt) {
1171 		s5p_mfc_release_firmware(mfc_dev);
1172 		device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1173 		device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1174 		return -ENOMEM;
1175 	}
1176 
1177 	/* Valid buffers passed to MFC encoder with LAST_FRAME command
1178 	 * should not have address of bank2 - MFC will treat it as a null frame.
1179 	 * To avoid such situation we set bank2 address below the pool address.
1180 	 */
1181 	mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1182 
1183 	dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1184 			  bank2_dma_addr);
1185 
1186 	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1187 					DMA_BIT_MASK(32));
1188 	vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1189 					DMA_BIT_MASK(32));
1190 
1191 	return 0;
1192 }
1193 
s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev * mfc_dev)1194 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1195 {
1196 	device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1197 	device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1198 	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1199 	vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1200 }
1201 
s5p_mfc_configure_common_memory(struct s5p_mfc_dev * mfc_dev)1202 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1203 {
1204 	struct device *dev = &mfc_dev->plat_dev->dev;
1205 	unsigned long mem_size = SZ_4M;
1206 
1207 	if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1208 		mem_size = SZ_8M;
1209 
1210 	if (mfc_mem_size)
1211 		mem_size = memparse(mfc_mem_size, NULL);
1212 
1213 	mfc_dev->mem_bitmap = bitmap_zalloc(mem_size >> PAGE_SHIFT, GFP_KERNEL);
1214 	if (!mfc_dev->mem_bitmap)
1215 		return -ENOMEM;
1216 
1217 	mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1218 					       &mfc_dev->mem_base, GFP_KERNEL);
1219 	if (!mfc_dev->mem_virt) {
1220 		bitmap_free(mfc_dev->mem_bitmap);
1221 		dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1222 			(mem_size / SZ_1M));
1223 		return -ENOMEM;
1224 	}
1225 	mfc_dev->mem_size = mem_size;
1226 	mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1227 	mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1228 
1229 	/*
1230 	 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1231 	 * as used (to keep required base alignment) and adjust base address
1232 	 */
1233 	if (mfc_dev->mem_base == (dma_addr_t)0) {
1234 		unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1235 
1236 		bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1237 		mfc_dev->dma_base[BANK_L_CTX] += offset;
1238 		mfc_dev->dma_base[BANK_R_CTX] += offset;
1239 	}
1240 
1241 	/* Firmware allocation cannot fail in this case */
1242 	s5p_mfc_alloc_firmware(mfc_dev);
1243 
1244 	mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1245 	vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1246 
1247 	dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1248 		 (mem_size / SZ_1M));
1249 
1250 	return 0;
1251 }
1252 
s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev * mfc_dev)1253 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1254 {
1255 	struct device *dev = &mfc_dev->plat_dev->dev;
1256 
1257 	dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1258 			  mfc_dev->mem_base);
1259 	bitmap_free(mfc_dev->mem_bitmap);
1260 	vb2_dma_contig_clear_max_seg_size(dev);
1261 }
1262 
s5p_mfc_configure_dma_memory(struct s5p_mfc_dev * mfc_dev)1263 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1264 {
1265 	struct device *dev = &mfc_dev->plat_dev->dev;
1266 
1267 	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1268 		return s5p_mfc_configure_common_memory(mfc_dev);
1269 	else
1270 		return s5p_mfc_configure_2port_memory(mfc_dev);
1271 }
1272 
s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev * mfc_dev)1273 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1274 {
1275 	struct device *dev = &mfc_dev->plat_dev->dev;
1276 
1277 	s5p_mfc_release_firmware(mfc_dev);
1278 	if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1279 		s5p_mfc_unconfigure_common_memory(mfc_dev);
1280 	else
1281 		s5p_mfc_unconfigure_2port_memory(mfc_dev);
1282 }
1283 
1284 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1285 static int s5p_mfc_probe(struct platform_device *pdev)
1286 {
1287 	struct s5p_mfc_dev *dev;
1288 	struct video_device *vfd;
1289 	int ret;
1290 
1291 	pr_debug("%s++\n", __func__);
1292 	dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1293 	if (!dev)
1294 		return -ENOMEM;
1295 
1296 	spin_lock_init(&dev->irqlock);
1297 	spin_lock_init(&dev->condlock);
1298 	dev->plat_dev = pdev;
1299 	if (!dev->plat_dev) {
1300 		mfc_err("No platform data specified\n");
1301 		return -ENODEV;
1302 	}
1303 
1304 	dev->variant = of_device_get_match_data(&pdev->dev);
1305 	if (!dev->variant) {
1306 		dev_err(&pdev->dev, "Failed to get device MFC hardware variant information\n");
1307 		return -ENOENT;
1308 	}
1309 
1310 	dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
1311 	if (IS_ERR(dev->regs_base))
1312 		return PTR_ERR(dev->regs_base);
1313 
1314 	ret = platform_get_irq(pdev, 0);
1315 	if (ret < 0)
1316 		return ret;
1317 	dev->irq = ret;
1318 	ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1319 					0, pdev->name, dev);
1320 	if (ret) {
1321 		dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1322 		return ret;
1323 	}
1324 
1325 	ret = s5p_mfc_configure_dma_memory(dev);
1326 	if (ret < 0) {
1327 		dev_err(&pdev->dev, "failed to configure DMA memory\n");
1328 		return ret;
1329 	}
1330 
1331 	ret = s5p_mfc_init_pm(dev);
1332 	if (ret < 0) {
1333 		dev_err(&pdev->dev, "failed to get mfc clock source\n");
1334 		goto err_dma;
1335 	}
1336 
1337 	/*
1338 	 * Load fails if fs isn't mounted. Try loading anyway.
1339 	 * _open() will load it, it fails now. Ignore failure.
1340 	 */
1341 	s5p_mfc_load_firmware(dev);
1342 
1343 	mutex_init(&dev->mfc_mutex);
1344 	init_waitqueue_head(&dev->queue);
1345 	dev->hw_lock = 0;
1346 	INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1347 	atomic_set(&dev->watchdog_cnt, 0);
1348 	timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1349 
1350 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1351 	if (ret)
1352 		goto err_v4l2_dev_reg;
1353 
1354 	/* decoder */
1355 	vfd = video_device_alloc();
1356 	if (!vfd) {
1357 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1358 		ret = -ENOMEM;
1359 		goto err_dec_alloc;
1360 	}
1361 	vfd->fops	= &s5p_mfc_fops;
1362 	vfd->ioctl_ops	= get_dec_v4l2_ioctl_ops();
1363 	vfd->release	= video_device_release;
1364 	vfd->lock	= &dev->mfc_mutex;
1365 	vfd->v4l2_dev	= &dev->v4l2_dev;
1366 	vfd->vfl_dir	= VFL_DIR_M2M;
1367 	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1368 	set_bit(V4L2_FL_QUIRK_INVERTED_CROP, &vfd->flags);
1369 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1370 	dev->vfd_dec	= vfd;
1371 	video_set_drvdata(vfd, dev);
1372 
1373 	/* encoder */
1374 	vfd = video_device_alloc();
1375 	if (!vfd) {
1376 		v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1377 		ret = -ENOMEM;
1378 		goto err_enc_alloc;
1379 	}
1380 	vfd->fops	= &s5p_mfc_fops;
1381 	vfd->ioctl_ops	= get_enc_v4l2_ioctl_ops();
1382 	vfd->release	= video_device_release;
1383 	vfd->lock	= &dev->mfc_mutex;
1384 	vfd->v4l2_dev	= &dev->v4l2_dev;
1385 	vfd->vfl_dir	= VFL_DIR_M2M;
1386 	vfd->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1387 	snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1388 	dev->vfd_enc	= vfd;
1389 	video_set_drvdata(vfd, dev);
1390 	platform_set_drvdata(pdev, dev);
1391 
1392 	/* Initialize HW ops and commands based on MFC version */
1393 	s5p_mfc_init_hw_ops(dev);
1394 	s5p_mfc_init_hw_cmds(dev);
1395 	s5p_mfc_init_regs(dev);
1396 
1397 	/* Register decoder and encoder */
1398 	ret = video_register_device(dev->vfd_dec, VFL_TYPE_VIDEO, 0);
1399 	if (ret) {
1400 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1401 		goto err_dec_reg;
1402 	}
1403 	v4l2_info(&dev->v4l2_dev,
1404 		  "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1405 
1406 	ret = video_register_device(dev->vfd_enc, VFL_TYPE_VIDEO, 0);
1407 	if (ret) {
1408 		v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1409 		goto err_enc_reg;
1410 	}
1411 	v4l2_info(&dev->v4l2_dev,
1412 		  "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1413 
1414 	pr_debug("%s--\n", __func__);
1415 	return 0;
1416 
1417 /* Deinit MFC if probe had failed */
1418 err_enc_reg:
1419 	video_unregister_device(dev->vfd_dec);
1420 	dev->vfd_dec = NULL;
1421 err_dec_reg:
1422 	video_device_release(dev->vfd_enc);
1423 err_enc_alloc:
1424 	video_device_release(dev->vfd_dec);
1425 err_dec_alloc:
1426 	v4l2_device_unregister(&dev->v4l2_dev);
1427 err_v4l2_dev_reg:
1428 	s5p_mfc_final_pm(dev);
1429 err_dma:
1430 	s5p_mfc_unconfigure_dma_memory(dev);
1431 
1432 	pr_debug("%s-- with error\n", __func__);
1433 	return ret;
1434 
1435 }
1436 
1437 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1438 static void s5p_mfc_remove(struct platform_device *pdev)
1439 {
1440 	struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1441 	struct s5p_mfc_ctx *ctx;
1442 	int i;
1443 
1444 	v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1445 
1446 	/*
1447 	 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1448 	 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1449 	 * after s5p_mfc_remove() is run during unbind.
1450 	 */
1451 	mutex_lock(&dev->mfc_mutex);
1452 	for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1453 		ctx = dev->ctx[i];
1454 		if (!ctx)
1455 			continue;
1456 		/* clear ctx->dev */
1457 		ctx->dev = NULL;
1458 	}
1459 	mutex_unlock(&dev->mfc_mutex);
1460 
1461 	del_timer_sync(&dev->watchdog_timer);
1462 	flush_work(&dev->watchdog_work);
1463 
1464 	video_unregister_device(dev->vfd_enc);
1465 	video_unregister_device(dev->vfd_dec);
1466 	v4l2_device_unregister(&dev->v4l2_dev);
1467 	s5p_mfc_unconfigure_dma_memory(dev);
1468 
1469 	s5p_mfc_final_pm(dev);
1470 }
1471 
1472 #ifdef CONFIG_PM_SLEEP
1473 
s5p_mfc_suspend(struct device * dev)1474 static int s5p_mfc_suspend(struct device *dev)
1475 {
1476 	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1477 	int ret;
1478 
1479 	if (m_dev->num_inst == 0)
1480 		return 0;
1481 
1482 	if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1483 		mfc_err("Error: going to suspend for a second time\n");
1484 		return -EIO;
1485 	}
1486 
1487 	/* Check if we're processing then wait if it necessary. */
1488 	while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1489 		/* Try and lock the HW */
1490 		/* Wait on the interrupt waitqueue */
1491 		ret = wait_event_interruptible_timeout(m_dev->queue,
1492 			m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1493 		if (ret == 0) {
1494 			mfc_err("Waiting for hardware to finish timed out\n");
1495 			clear_bit(0, &m_dev->enter_suspend);
1496 			return -EIO;
1497 		}
1498 	}
1499 
1500 	ret = s5p_mfc_sleep(m_dev);
1501 	if (ret) {
1502 		clear_bit(0, &m_dev->enter_suspend);
1503 		clear_bit(0, &m_dev->hw_lock);
1504 	}
1505 	return ret;
1506 }
1507 
s5p_mfc_resume(struct device * dev)1508 static int s5p_mfc_resume(struct device *dev)
1509 {
1510 	struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1511 
1512 	if (m_dev->num_inst == 0)
1513 		return 0;
1514 	return s5p_mfc_wakeup(m_dev);
1515 }
1516 #endif
1517 
1518 /* Power management */
1519 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1520 	SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1521 };
1522 
1523 static const struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1524 	.h264_ctx	= MFC_H264_CTX_BUF_SIZE,
1525 	.non_h264_ctx	= MFC_CTX_BUF_SIZE,
1526 	.dsc		= DESC_BUF_SIZE,
1527 	.shm		= SHARED_BUF_SIZE,
1528 };
1529 
1530 static const struct s5p_mfc_buf_size buf_size_v5 = {
1531 	.fw	= MAX_FW_SIZE,
1532 	.cpb	= MAX_CPB_SIZE,
1533 	.priv	= &mfc_buf_size_v5,
1534 };
1535 
1536 static const struct s5p_mfc_variant mfc_drvdata_v5 = {
1537 	.version	= MFC_VERSION,
1538 	.version_bit	= MFC_V5_BIT,
1539 	.port_num	= MFC_NUM_PORTS,
1540 	.buf_size	= &buf_size_v5,
1541 	.fw_name[0]	= "s5p-mfc.fw",
1542 	.clk_names	= {"mfc", "sclk_mfc"},
1543 	.num_clocks	= 2,
1544 	.use_clock_gating = true,
1545 };
1546 
1547 static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1548 	.dev_ctx	= MFC_CTX_BUF_SIZE_V6,
1549 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V6,
1550 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1551 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V6,
1552 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1553 };
1554 
1555 static const struct s5p_mfc_buf_size buf_size_v6 = {
1556 	.fw	= MAX_FW_SIZE_V6,
1557 	.cpb	= MAX_CPB_SIZE_V6,
1558 	.priv	= &mfc_buf_size_v6,
1559 };
1560 
1561 static const struct s5p_mfc_variant mfc_drvdata_v6 = {
1562 	.version	= MFC_VERSION_V6,
1563 	.version_bit	= MFC_V6_BIT,
1564 	.port_num	= MFC_NUM_PORTS_V6,
1565 	.buf_size	= &buf_size_v6,
1566 	.fw_name[0]     = "s5p-mfc-v6.fw",
1567 	/*
1568 	 * v6-v2 firmware contains bug fixes and interface change
1569 	 * for init buffer command
1570 	 */
1571 	.fw_name[1]     = "s5p-mfc-v6-v2.fw",
1572 	.clk_names	= {"mfc"},
1573 	.num_clocks	= 1,
1574 };
1575 
1576 static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1577 	.dev_ctx	= MFC_CTX_BUF_SIZE_V7,
1578 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V7,
1579 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1580 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V7,
1581 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1582 };
1583 
1584 static const struct s5p_mfc_buf_size buf_size_v7 = {
1585 	.fw	= MAX_FW_SIZE_V7,
1586 	.cpb	= MAX_CPB_SIZE_V7,
1587 	.priv	= &mfc_buf_size_v7,
1588 };
1589 
1590 static const struct s5p_mfc_variant mfc_drvdata_v7 = {
1591 	.version	= MFC_VERSION_V7,
1592 	.version_bit	= MFC_V7_BIT,
1593 	.port_num	= MFC_NUM_PORTS_V7,
1594 	.buf_size	= &buf_size_v7,
1595 	.fw_name[0]     = "s5p-mfc-v7.fw",
1596 	.clk_names	= {"mfc"},
1597 	.num_clocks	= 1,
1598 };
1599 
1600 static const struct s5p_mfc_variant mfc_drvdata_v7_3250 = {
1601 	.version        = MFC_VERSION_V7,
1602 	.version_bit    = MFC_V7_BIT,
1603 	.port_num       = MFC_NUM_PORTS_V7,
1604 	.buf_size       = &buf_size_v7,
1605 	.fw_name[0]     = "s5p-mfc-v7.fw",
1606 	.clk_names      = {"mfc", "sclk_mfc"},
1607 	.num_clocks     = 2,
1608 };
1609 
1610 static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1611 	.dev_ctx	= MFC_CTX_BUF_SIZE_V8,
1612 	.h264_dec_ctx	= MFC_H264_DEC_CTX_BUF_SIZE_V8,
1613 	.other_dec_ctx	= MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1614 	.h264_enc_ctx	= MFC_H264_ENC_CTX_BUF_SIZE_V8,
1615 	.other_enc_ctx	= MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1616 };
1617 
1618 static const struct s5p_mfc_buf_size buf_size_v8 = {
1619 	.fw	= MAX_FW_SIZE_V8,
1620 	.cpb	= MAX_CPB_SIZE_V8,
1621 	.priv	= &mfc_buf_size_v8,
1622 };
1623 
1624 static const struct s5p_mfc_variant mfc_drvdata_v8 = {
1625 	.version	= MFC_VERSION_V8,
1626 	.version_bit	= MFC_V8_BIT,
1627 	.port_num	= MFC_NUM_PORTS_V8,
1628 	.buf_size	= &buf_size_v8,
1629 	.fw_name[0]     = "s5p-mfc-v8.fw",
1630 	.clk_names	= {"mfc"},
1631 	.num_clocks	= 1,
1632 };
1633 
1634 static const struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1635 	.version	= MFC_VERSION_V8,
1636 	.version_bit	= MFC_V8_BIT,
1637 	.port_num	= MFC_NUM_PORTS_V8,
1638 	.buf_size	= &buf_size_v8,
1639 	.fw_name[0]     = "s5p-mfc-v8.fw",
1640 	.clk_names	= {"pclk", "aclk", "aclk_xiu"},
1641 	.num_clocks	= 3,
1642 };
1643 
1644 static const struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1645 	.dev_ctx        = MFC_CTX_BUF_SIZE_V10,
1646 	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1647 	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1648 	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1649 	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1650 	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1651 };
1652 
1653 static const struct s5p_mfc_buf_size buf_size_v10 = {
1654 	.fw     = MAX_FW_SIZE_V10,
1655 	.cpb    = MAX_CPB_SIZE_V10,
1656 	.priv   = &mfc_buf_size_v10,
1657 };
1658 
1659 static const struct s5p_mfc_variant mfc_drvdata_v10 = {
1660 	.version        = MFC_VERSION_V10,
1661 	.version_bit    = MFC_V10_BIT,
1662 	.port_num       = MFC_NUM_PORTS_V10,
1663 	.buf_size       = &buf_size_v10,
1664 	.fw_name[0]     = "s5p-mfc-v10.fw",
1665 };
1666 
1667 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v12 = {
1668 	.dev_ctx        = MFC_CTX_BUF_SIZE_V12,
1669 	.h264_dec_ctx   = MFC_H264_DEC_CTX_BUF_SIZE_V12,
1670 	.other_dec_ctx  = MFC_OTHER_DEC_CTX_BUF_SIZE_V12,
1671 	.h264_enc_ctx   = MFC_H264_ENC_CTX_BUF_SIZE_V12,
1672 	.hevc_enc_ctx   = MFC_HEVC_ENC_CTX_BUF_SIZE_V12,
1673 	.other_enc_ctx  = MFC_OTHER_ENC_CTX_BUF_SIZE_V12,
1674 };
1675 
1676 static struct s5p_mfc_buf_size buf_size_v12 = {
1677 	.fw     = MAX_FW_SIZE_V12,
1678 	.cpb    = MAX_CPB_SIZE_V12,
1679 	.priv   = &mfc_buf_size_v12,
1680 };
1681 
1682 static struct s5p_mfc_variant mfc_drvdata_v12 = {
1683 	.version        = MFC_VERSION_V12,
1684 	.version_bit    = MFC_V12_BIT,
1685 	.port_num       = MFC_NUM_PORTS_V12,
1686 	.buf_size       = &buf_size_v12,
1687 	.fw_name[0]     = "s5p-mfc-v12.fw",
1688 	.clk_names	= {"mfc"},
1689 	.num_clocks	= 1,
1690 };
1691 
1692 static const struct of_device_id exynos_mfc_match[] = {
1693 	{
1694 		.compatible = "samsung,mfc-v5",
1695 		.data = &mfc_drvdata_v5,
1696 	}, {
1697 		.compatible = "samsung,mfc-v6",
1698 		.data = &mfc_drvdata_v6,
1699 	}, {
1700 		.compatible = "samsung,mfc-v7",
1701 		.data = &mfc_drvdata_v7,
1702 	}, {
1703 		.compatible = "samsung,exynos3250-mfc",
1704 		.data = &mfc_drvdata_v7_3250,
1705 	}, {
1706 		.compatible = "samsung,mfc-v8",
1707 		.data = &mfc_drvdata_v8,
1708 	}, {
1709 		.compatible = "samsung,exynos5433-mfc",
1710 		.data = &mfc_drvdata_v8_5433,
1711 	}, {
1712 		.compatible = "samsung,mfc-v10",
1713 		.data = &mfc_drvdata_v10,
1714 	}, {
1715 		.compatible = "tesla,fsd-mfc",
1716 		.data = &mfc_drvdata_v12,
1717 	},
1718 	{},
1719 };
1720 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1721 
1722 static struct platform_driver s5p_mfc_driver = {
1723 	.probe		= s5p_mfc_probe,
1724 	.remove_new	= s5p_mfc_remove,
1725 	.driver	= {
1726 		.name	= S5P_MFC_NAME,
1727 		.pm	= &s5p_mfc_pm_ops,
1728 		.of_match_table = exynos_mfc_match,
1729 	},
1730 };
1731 
1732 module_platform_driver(s5p_mfc_driver);
1733 
1734 MODULE_LICENSE("GPL");
1735 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1736 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1737 
1738