1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) Pengutronix e.K. 4 * Author: Sven Püschel <s.pueschel@pengutronix.de> 5 */ 6 #ifndef __RGA3_HW_H__ 7 #define __RGA3_HW_H__ 8 9 #include <linux/bits.h> 10 #include <linux/types.h> 11 12 #define RGA3_CMDBUF_SIZE 0xb8 13 14 #define RGA3_MIN_WIDTH 128 15 #define RGA3_MIN_HEIGHT 128 16 #define RGA3_MAX_INPUT_WIDTH (8192 - 16) 17 #define RGA3_MAX_INPUT_HEIGHT (8192 - 16) 18 #define RGA3_MAX_OUTPUT_WIDTH (8192 - 64) 19 #define RGA3_MAX_OUTPUT_HEIGHT (8192 - 64) 20 #define RGA3_MAX_SCALING_FACTOR 8 21 #define RGA3_RESET_TIMEOUT 1000 22 23 /* Registers address */ 24 /* sys reg */ 25 #define RGA3_SYS_CTRL 0x000 26 #define RGA3_CMD_CTRL 0x004 27 #define RGA3_CMD_ADDR 0x008 28 #define RGA3_MI_GROUP_CTRL 0x00c 29 #define RGA3_ARQOS_CTRL 0x010 30 #define RGA3_VERSION_NUM 0x018 31 #define RGA3_VERSION_TIM 0x01c 32 #define RGA3_INT_EN 0x020 33 #define RGA3_INT_RAW 0x024 34 #define RGA3_INT_MSK 0x028 35 #define RGA3_INT_CLR 0x02c 36 #define RGA3_RO_SRST 0x030 37 #define RGA3_STATUS0 0x034 38 #define RGA3_SCAN_CNT 0x038 39 #define RGA3_CMD_STATE 0x040 40 41 /* cmd reg */ 42 #define RGA3_WIN0_RD_CTRL 0x100 43 #define RGA3_FIRST_CMD_REG RGA3_WIN0_RD_CTRL 44 #define RGA3_WIN0_Y_BASE 0x110 45 #define RGA3_WIN0_U_BASE 0x114 46 #define RGA3_WIN0_V_BASE 0x118 47 #define RGA3_WIN0_VIR_STRIDE 0x11c 48 #define RGA3_WIN0_FBC_OFF 0x120 49 #define RGA3_WIN0_SRC_SIZE 0x124 50 #define RGA3_WIN0_ACT_OFF 0x128 51 #define RGA3_WIN0_ACT_SIZE 0x12c 52 #define RGA3_WIN0_DST_SIZE 0x130 53 #define RGA3_WIN0_SCL_FAC 0x134 54 #define RGA3_WIN0_UV_VIR_STRIDE 0x138 55 #define RGA3_WIN1_RD_CTRL 0x140 56 #define RGA3_WIN1_Y_BASE 0x150 57 #define RGA3_WIN1_U_BASE 0x154 58 #define RGA3_WIN1_V_BASE 0x158 59 #define RGA3_WIN1_VIR_STRIDE 0x15c 60 #define RGA3_WIN1_FBC_OFF 0x160 61 #define RGA3_WIN1_SRC_SIZE 0x164 62 #define RGA3_WIN1_ACT_OFF 0x168 63 #define RGA3_WIN1_ACT_SIZE 0x16c 64 #define RGA3_WIN1_DST_SIZE 0x170 65 #define RGA3_WIN1_SCL_FAC 0x174 66 #define RGA3_WIN1_UV_VIR_STRIDE 0x178 67 #define RGA3_OVLP_CTRL 0x180 68 #define RGA3_OVLP_OFF 0x184 69 #define RGA3_OVLP_TOP_KEY_MIN 0x188 70 #define RGA3_OVLP_TOP_KEY_MAX 0x18c 71 #define RGA3_OVLP_TOP_CTRL 0x190 72 #define RGA3_OVLP_BOT_CTRL 0x194 73 #define RGA3_OVLP_TOP_ALPHA 0x198 74 #define RGA3_OVLP_BOT_ALPHA 0x19c 75 #define RGA3_WR_CTRL 0x1a0 76 #define RGA3_WR_FBCE_CTRL 0x1a4 77 #define RGA3_WR_VIR_STRIDE 0x1a8 78 #define RGA3_WR_PL_VIR_STRIDE 0x1ac 79 #define RGA3_WR_Y_BASE 0x1b0 80 #define RGA3_WR_U_BASE 0x1b4 81 #define RGA3_WR_V_BASE 0x1b8 82 83 /* Registers value */ 84 #define RGA3_COLOR_FMT_YUV420 0x0 85 #define RGA3_COLOR_FMT_YUV422 0x1 86 #define RGA3_COLOR_FMT_YUV420_10B 0x2 87 #define RGA3_COLOR_FMT_YUV422_10B 0x3 88 /* 89 * Use memory ordering names 90 * instead of the datasheet naming RGB formats in big endian order 91 */ 92 #define RGA3_COLOR_FMT_BGR565 0x4 93 #define RGA3_COLOR_FMT_BGR888 0x5 94 #define RGA3_COLOR_FMT_FIRST_HAS_ALPHA RGA3_COLOR_FMT_BGRA8888 95 #define RGA3_COLOR_FMT_BGRA8888 0x6 96 #define RGA3_COLOR_FMT_LAST_OUTPUT RGA3_COLOR_FMT_BGRA8888 97 /* the following are only supported as inputs */ 98 #define RGA3_COLOR_FMT_ABGR8888 0x7 99 /* 100 * the following seem to be unnecessary, 101 * as they can be achieved with RB swaps 102 */ 103 #define RGA3_COLOR_FMT_RGBA8888 0x8 104 #define RGA3_COLOR_FMT_ARGB8888 0x9 105 106 #define RGA3_RDWR_FORMAT_SEMI_PLANAR 0x1 107 #define RGA3_RDWR_FORMAT_INTERLEAVED 0x2 108 109 #define RGA3_CMD_MODE_MASTER 0x1 110 111 #define RGA3_WIN_CSC_MODE_BT601_L 0x0 112 #define RGA3_WIN_CSC_MODE_BT709_L 0x1 113 #define RGA3_WIN_CSC_MODE_BT601_F 0x2 114 #define RGA3_WIN_CSC_MODE_BT2020_L 0x3 115 116 /* RGA masks */ 117 /* SYS_CTRL */ 118 #define RGA3_CCLK_SRESET BIT(4) 119 #define RGA3_ACLK_SRESET BIT(3) 120 #define RGA3_CMD_MODE BIT(1) 121 122 /* CMD_CTRL */ 123 #define RGA3_CMD_LINE_START_PULSE BIT(0) 124 125 /* VERSION_NUM */ 126 #define RGA3_VERSION_NUM_MAJOR GENMASK(31, 28) 127 #define RGA3_VERSION_NUM_MINOR GENMASK(27, 20) 128 129 /* INT_* */ 130 #define RGA3_INT_FRM_DONE BIT(0) 131 #define RGA3_INT_DMA_READ_BUS_ERR BIT(2) 132 #define RGA3_INT_WIN0_FBC_DEC_ERR BIT(5) 133 #define RGA3_INT_WIN0_HOR_ERR BIT(6) 134 #define RGA3_INT_WIN0_VER_ERR BIT(7) 135 #define RGA3_INT_WR_VER_ERR BIT(13) 136 #define RGA3_INT_WR_HOR_ERR BIT(14) 137 #define RGA3_INT_WR_BUS_ERR BIT(15) 138 #define RGA3_INT_WIN0_IN_FIFO_WR_ERR BIT(16) 139 #define RGA3_INT_WIN0_IN_FIFO_RD_ERR BIT(17) 140 #define RGA3_INT_WIN0_HOR_FIFO_WR_ERR BIT(18) 141 #define RGA3_INT_WIN0_HOR_FIFO_RD_ERR BIT(19) 142 #define RGA3_INT_WIN0_VER_FIFO_WR_ERR BIT(20) 143 #define RGA3_INT_WIN0_VER_FIFO_RD_ERR BIT(21) 144 145 /* RO_SRST */ 146 #define RGA3_RO_SRST_DONE GENMASK(5, 0) 147 148 /* *_SIZE */ 149 #define RGA3_HEIGHT GENMASK(28, 16) 150 #define RGA3_WIDTH GENMASK(12, 0) 151 152 /* SCL_FAC */ 153 #define RGA3_SCALE_VER_FAC GENMASK(31, 16) 154 #define RGA3_SCALE_HOR_FAC GENMASK(15, 0) 155 156 /* WINx_CTRL */ 157 #define RGA3_WIN_CSC_MODE GENMASK(27, 26) 158 #define RGA3_WIN_R2Y BIT(25) 159 #define RGA3_WIN_Y2R BIT(24) 160 #define RGA3_WIN_SCALE_VER_UP BIT(23) 161 #define RGA3_WIN_SCALE_VER_BYPASS BIT(22) 162 #define RGA3_WIN_SCALE_HOR_UP BIT(21) 163 #define RGA3_WIN_SCALE_HOR_BYPASS BIT(20) 164 #define RGA3_WIN_YC_SWAP BIT(13) 165 #define RGA3_WIN_RBUV_SWAP BIT(12) 166 #define RGA3_WIN_RD_FORMAT GENMASK(9, 8) 167 #define RGA3_WIN_PIC_FORMAT GENMASK(7, 4) 168 #define RGA3_WIN_ENABLE BIT(0) 169 170 /* COLOR_CTRL */ 171 #define RGA3_OVLP_GLOBAL_ALPHA GENMASK(23, 16) 172 #define RGA3_OVLP_COLOR_MODE BIT(0) 173 174 /* ALPHA_CTRL */ 175 #define RGA3_ALPHA_SELECT_MODE BIT(4) 176 #define RGA3_ALPHA_BLEND_MODE GENMASK(3, 2) 177 178 /* WR_CTRL */ 179 #define RGA3_WR_YC_SWAP BIT(20) 180 #define RGA3_WR_SW_OUTSTANDING_MAX GENMASK(18, 13) 181 #define RGA3_WR_RBUV_SWAP BIT(12) 182 #define RGA3_WR_FORMAT GENMASK(9, 8) 183 #define RGA3_WR_PIC_FORMAT GENMASK(7, 4) 184 185 struct rga3_fmt { 186 u32 fourcc; 187 u8 hw_format; 188 bool rbuv_swap; 189 bool yc_swap; 190 }; 191 192 #endif 193