1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/sys_soc.h> 19 #include <linux/units.h> 20 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-fwnode.h> 24 #include <media/v4l2-mc.h> 25 #include <media/v4l2-subdev.h> 26 27 /* LINK registers */ 28 /* Module Configuration Register */ 29 #define CSI2nMCG 0x0 30 #define CSI2nMCG_SDLN GENMASK(11, 8) 31 32 /* Module Control Register 0 */ 33 #define CSI2nMCT0 0x10 34 #define CSI2nMCT0_VDLN(x) ((x) << 0) 35 36 /* Module Control Register 2 */ 37 #define CSI2nMCT2 0x18 38 #define CSI2nMCT2_FRRSKW(x) ((x) << 16) 39 #define CSI2nMCT2_FRRCLK(x) ((x) << 0) 40 41 /* Module Control Register 3 */ 42 #define CSI2nMCT3 0x1c 43 #define CSI2nMCT3_RXEN BIT(0) 44 45 /* Reset Control Register */ 46 #define CSI2nRTCT 0x28 47 #define CSI2nRTCT_VSRST BIT(0) 48 49 /* Reset Status Register */ 50 #define CSI2nRTST 0x2c 51 #define CSI2nRTST_VSRSTS BIT(0) 52 53 /* Receive Data Type Enable Low Register */ 54 #define CSI2nDTEL 0x60 55 56 /* Receive Data Type Enable High Register */ 57 #define CSI2nDTEH 0x64 58 59 /* DPHY registers */ 60 /* D-PHY Control Register 0 */ 61 #define CSIDPHYCTRL0 0x400 62 #define CSIDPHYCTRL0_EN_LDO1200 BIT(1) 63 #define CSIDPHYCTRL0_EN_BGR BIT(0) 64 65 /* D-PHY Timing Register 0 */ 66 #define CSIDPHYTIM0 0x404 67 #define CSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) 68 #define CSIDPHYTIM0_T_INIT(x) ((x) << 0) 69 70 /* D-PHY Timing Register 1 */ 71 #define CSIDPHYTIM1 0x408 72 #define CSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) 73 #define CSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) 74 #define CSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) 75 #define CSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) 76 77 /* D-PHY Skew Adjustment Function */ 78 #define CSIDPHYSKW0 0x460 79 #define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) ((x) & 0x3) 80 #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4) 81 #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8) 82 #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12) 83 #define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \ 84 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \ 85 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \ 86 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)) 87 88 /* DPHY registers on RZ/V2H(P) SoC */ 89 #define CRUm_S_TIMCTL 0x41c 90 #define CRUm_S_TIMCTL_S_HSSETTLECTL(x) ((x) << 8) 91 92 #define CRUm_S_DPHYCTL_MSB 0x434 93 #define CRUm_S_DPHYCTL_MSB_DESKEW BIT(1) 94 95 #define CRUm_SWAPCTL 0x438 96 97 #define VSRSTS_RETRIES 20 98 99 #define RZG2L_CSI2_MIN_WIDTH 320 100 #define RZG2L_CSI2_MIN_HEIGHT 240 101 #define RZG2L_CSI2_MAX_WIDTH 2800 102 #define RZG2L_CSI2_MAX_HEIGHT 4095 103 104 #define RZG2L_CSI2_DEFAULT_WIDTH RZG2L_CSI2_MIN_WIDTH 105 #define RZG2L_CSI2_DEFAULT_HEIGHT RZG2L_CSI2_MIN_HEIGHT 106 #define RZG2L_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_UYVY8_1X16 107 108 enum rzg2l_csi2_pads { 109 RZG2L_CSI2_SINK = 0, 110 RZG2L_CSI2_SOURCE, 111 NR_OF_RZG2L_CSI2_PAD, 112 }; 113 114 struct rzg2l_csi2 { 115 struct device *dev; 116 void __iomem *base; 117 struct reset_control *presetn; 118 struct reset_control *cmn_rstb; 119 const struct rzg2l_csi2_info *info; 120 struct clk *sysclk; 121 struct clk *vclk; 122 unsigned long vclk_rate; 123 124 struct v4l2_subdev subdev; 125 struct media_pad pads[NR_OF_RZG2L_CSI2_PAD]; 126 127 struct v4l2_async_notifier notifier; 128 struct v4l2_subdev *remote_source; 129 130 unsigned short lanes; 131 unsigned long hsfreq; 132 133 bool dphy_enabled; 134 }; 135 136 struct rzg2l_csi2_info { 137 int (*dphy_enable)(struct rzg2l_csi2 *csi2); 138 int (*dphy_disable)(struct rzg2l_csi2 *csi2); 139 bool has_system_clk; 140 }; 141 142 struct rzg2l_csi2_timings { 143 u32 t_init; 144 u32 tclk_miss; 145 u32 tclk_settle; 146 u32 ths_settle; 147 u32 tclk_prepare; 148 u32 ths_prepare; 149 u32 max_hsfreq; 150 }; 151 152 struct rzv2h_csi2_s_hssettlectl { 153 unsigned int hsfreq; 154 u16 s_hssettlectl; 155 }; 156 157 static const struct rzv2h_csi2_s_hssettlectl rzv2h_s_hssettlectl[] = { 158 { 90, 1 }, { 130, 2 }, { 180, 3 }, 159 { 220, 4 }, { 270, 5 }, { 310, 6 }, 160 { 360, 7 }, { 400, 8 }, { 450, 9 }, 161 { 490, 10 }, { 540, 11 }, { 580, 12 }, 162 { 630, 13 }, { 670, 14 }, { 720, 15 }, 163 { 760, 16 }, { 810, 17 }, { 850, 18 }, 164 { 900, 19 }, { 940, 20 }, { 990, 21 }, 165 { 1030, 22 }, { 1080, 23 }, { 1120, 24 }, 166 { 1170, 25 }, { 1220, 26 }, { 1260, 27 }, 167 { 1310, 28 }, { 1350, 29 }, { 1400, 30 }, 168 { 1440, 31 }, { 1490, 32 }, { 1530, 33 }, 169 { 1580, 34 }, { 1620, 35 }, { 1670, 36 }, 170 { 1710, 37 }, { 1760, 38 }, { 1800, 39 }, 171 { 1850, 40 }, { 1890, 41 }, { 1940, 42 }, 172 { 1980, 43 }, { 2030, 44 }, { 2070, 45 }, 173 { 2100, 46 }, 174 }; 175 176 static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = { 177 { 178 .max_hsfreq = 80, 179 .t_init = 79801, 180 .tclk_miss = 4, 181 .tclk_settle = 23, 182 .ths_settle = 31, 183 .tclk_prepare = 10, 184 .ths_prepare = 19, 185 }, 186 { 187 .max_hsfreq = 125, 188 .t_init = 79801, 189 .tclk_miss = 4, 190 .tclk_settle = 23, 191 .ths_settle = 28, 192 .tclk_prepare = 10, 193 .ths_prepare = 19, 194 }, 195 { 196 .max_hsfreq = 250, 197 .t_init = 79801, 198 .tclk_miss = 4, 199 .tclk_settle = 23, 200 .ths_settle = 22, 201 .tclk_prepare = 10, 202 .ths_prepare = 16, 203 }, 204 { 205 .max_hsfreq = 360, 206 .t_init = 79801, 207 .tclk_miss = 4, 208 .tclk_settle = 18, 209 .ths_settle = 19, 210 .tclk_prepare = 10, 211 .ths_prepare = 10, 212 }, 213 { 214 .max_hsfreq = 1500, 215 .t_init = 79801, 216 .tclk_miss = 4, 217 .tclk_settle = 18, 218 .ths_settle = 18, 219 .tclk_prepare = 10, 220 .ths_prepare = 10, 221 }, 222 }; 223 224 struct rzg2l_csi2_format { 225 u32 code; 226 unsigned int bpp; 227 }; 228 229 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = { 230 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16 }, 231 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, }, 232 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, }, 233 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, }, 234 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, }, 235 }; 236 237 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 238 { 239 return container_of(sd, struct rzg2l_csi2, subdev); 240 } 241 242 static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code) 243 { 244 unsigned int i; 245 246 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++) 247 if (rzg2l_csi2_formats[i].code == code) 248 return &rzg2l_csi2_formats[i]; 249 250 return NULL; 251 } 252 253 static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 254 { 255 return container_of(n, struct rzg2l_csi2, notifier); 256 } 257 258 static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg) 259 { 260 return ioread32(csi2->base + reg); 261 } 262 263 static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg, 264 u32 data) 265 { 266 iowrite32(data, csi2->base + reg); 267 } 268 269 static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set) 270 { 271 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set); 272 } 273 274 static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr) 275 { 276 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr); 277 } 278 279 static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2) 280 { 281 struct v4l2_subdev *source = csi2->remote_source; 282 const struct rzg2l_csi2_format *format; 283 const struct v4l2_mbus_framefmt *fmt; 284 struct v4l2_subdev_state *state; 285 struct v4l2_ctrl *ctrl; 286 u64 mbps; 287 288 /* Read the pixel rate control from remote. */ 289 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 290 if (!ctrl) { 291 dev_err(csi2->dev, "no pixel rate control in subdev %s\n", 292 source->name); 293 return -EINVAL; 294 } 295 296 state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev); 297 fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK); 298 format = rzg2l_csi2_code_to_fmt(fmt->code); 299 v4l2_subdev_unlock_state(state); 300 301 /* 302 * Calculate hsfreq in Mbps 303 * hsfreq = (pixel_rate * bits_per_sample) / number_of_lanes 304 */ 305 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * format->bpp; 306 do_div(mbps, csi2->lanes * 1000000); 307 308 return mbps; 309 } 310 311 /* ----------------------------------------------------------------------------- 312 * DPHY setting 313 */ 314 315 static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2) 316 { 317 int ret; 318 319 /* Reset the CRU (D-PHY) */ 320 ret = reset_control_assert(csi2->cmn_rstb); 321 if (ret) 322 return ret; 323 324 /* Stop the D-PHY clock */ 325 clk_disable_unprepare(csi2->sysclk); 326 327 /* Cancel the EN_LDO1200 register setting */ 328 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 329 330 /* Cancel the EN_BGR register setting */ 331 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 332 333 csi2->dphy_enabled = false; 334 335 return 0; 336 } 337 338 static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2) 339 { 340 const struct rzg2l_csi2_timings *dphy_timing; 341 u32 dphytim0, dphytim1; 342 unsigned int i; 343 int mbps; 344 int ret; 345 346 mbps = rzg2l_csi2_calc_mbps(csi2); 347 if (mbps < 0) 348 return mbps; 349 350 csi2->hsfreq = mbps; 351 352 /* Set DPHY timing parameters */ 353 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) { 354 dphy_timing = &rzg2l_csi2_global_timings[i]; 355 356 if (csi2->hsfreq <= dphy_timing->max_hsfreq) 357 break; 358 } 359 360 if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings)) 361 return -EINVAL; 362 363 /* Set D-PHY timing parameters */ 364 dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) | 365 CSIDPHYTIM0_T_INIT(dphy_timing->t_init); 366 dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) | 367 CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) | 368 CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) | 369 CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle); 370 rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0); 371 rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1); 372 373 /* Enable D-PHY power control 0 */ 374 rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW); 375 376 /* Set the EN_BGR bit */ 377 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 378 379 /* Delay 20us to be stable */ 380 usleep_range(20, 40); 381 382 /* Enable D-PHY power control 1 */ 383 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 384 385 /* Delay 10us to be stable */ 386 usleep_range(10, 20); 387 388 /* Start supplying the internal clock for the D-PHY block */ 389 ret = clk_prepare_enable(csi2->sysclk); 390 if (ret) 391 rzg2l_csi2_dphy_disable(csi2); 392 393 csi2->dphy_enabled = true; 394 395 return ret; 396 } 397 398 static const struct rzg2l_csi2_info rzg2l_csi2_info = { 399 .dphy_enable = rzg2l_csi2_dphy_enable, 400 .dphy_disable = rzg2l_csi2_dphy_disable, 401 .has_system_clk = true, 402 }; 403 404 static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on) 405 { 406 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 407 408 if (on) 409 return csi2->info->dphy_enable(csi2); 410 411 return csi2->info->dphy_disable(csi2); 412 } 413 414 static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2) 415 { 416 unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ; 417 u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff; 418 419 /* Select data lanes */ 420 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes)); 421 422 frrskw_coeff = 3 * vclk_rate * 8; 423 frrclk_coeff = frrskw_coeff / 2; 424 frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq); 425 frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq); 426 rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) | 427 CSI2nMCT2_FRRCLK(frrclk)); 428 429 /* 430 * Select data type. 431 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8, 432 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit, 433 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit 434 * data types 1 to 8 435 */ 436 rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f); 437 rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f); 438 439 clk_disable_unprepare(csi2->vclk); 440 441 /* Enable LINK reception */ 442 rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 443 444 return clk_prepare_enable(csi2->vclk); 445 } 446 447 static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2) 448 { 449 unsigned int timeout = VSRSTS_RETRIES; 450 451 /* Stop LINK reception */ 452 rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 453 454 /* Request a software reset of the LINK Video Pixel Interface */ 455 rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST); 456 457 /* Make sure CSI2nRTST.VSRSTS bit is cleared */ 458 while (--timeout) { 459 if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS)) 460 break; 461 usleep_range(100, 200); 462 } 463 464 if (!timeout) 465 dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n"); 466 467 return 0; 468 } 469 470 static int rzv2h_csi2_dphy_disable(struct rzg2l_csi2 *csi2) 471 { 472 int ret; 473 474 /* Reset the CRU (D-PHY) */ 475 ret = reset_control_assert(csi2->cmn_rstb); 476 if (ret) 477 return ret; 478 479 csi2->dphy_enabled = false; 480 481 return 0; 482 } 483 484 static int rzv2h_csi2_dphy_enable(struct rzg2l_csi2 *csi2) 485 { 486 unsigned int i; 487 u16 hssettle; 488 int mbps; 489 490 mbps = rzg2l_csi2_calc_mbps(csi2); 491 if (mbps < 0) 492 return mbps; 493 494 csi2->hsfreq = mbps; 495 496 for (i = 0; i < ARRAY_SIZE(rzv2h_s_hssettlectl); i++) { 497 if (csi2->hsfreq <= rzv2h_s_hssettlectl[i].hsfreq) 498 break; 499 } 500 501 if (i == ARRAY_SIZE(rzv2h_s_hssettlectl)) 502 return -EINVAL; 503 504 rzg2l_csi2_write(csi2, CRUm_SWAPCTL, 0); 505 506 hssettle = rzv2h_s_hssettlectl[i].s_hssettlectl; 507 rzg2l_csi2_write(csi2, CRUm_S_TIMCTL, 508 CRUm_S_TIMCTL_S_HSSETTLECTL(hssettle)); 509 510 if (csi2->hsfreq > 1500) 511 rzg2l_csi2_set(csi2, CRUm_S_DPHYCTL_MSB, 512 CRUm_S_DPHYCTL_MSB_DESKEW); 513 else 514 rzg2l_csi2_clr(csi2, CRUm_S_DPHYCTL_MSB, 515 CRUm_S_DPHYCTL_MSB_DESKEW); 516 517 csi2->dphy_enabled = true; 518 519 return 0; 520 } 521 522 static const struct rzg2l_csi2_info rzv2h_csi2_info = { 523 .dphy_enable = rzv2h_csi2_dphy_enable, 524 .dphy_disable = rzv2h_csi2_dphy_disable, 525 .has_system_clk = false, 526 }; 527 528 static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on) 529 { 530 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 531 int ret; 532 533 if (on) 534 ret = rzg2l_csi2_mipi_link_enable(csi2); 535 else 536 ret = rzg2l_csi2_mipi_link_disable(csi2); 537 538 return ret; 539 } 540 541 static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable) 542 { 543 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 544 int s_stream_ret = 0; 545 int ret; 546 547 if (enable) { 548 ret = pm_runtime_resume_and_get(csi2->dev); 549 if (ret) 550 return ret; 551 552 ret = rzg2l_csi2_mipi_link_setting(sd, 1); 553 if (ret) 554 goto err_pm_put; 555 556 ret = reset_control_deassert(csi2->cmn_rstb); 557 if (ret) 558 goto err_mipi_link_disable; 559 } 560 561 ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable); 562 if (ret) 563 s_stream_ret = ret; 564 565 if (enable && ret) 566 goto err_assert_rstb; 567 568 if (!enable) { 569 ret = rzg2l_csi2_dphy_setting(sd, 0); 570 if (ret && !s_stream_ret) 571 s_stream_ret = ret; 572 ret = rzg2l_csi2_mipi_link_setting(sd, 0); 573 if (ret && !s_stream_ret) 574 s_stream_ret = ret; 575 576 pm_runtime_put_sync(csi2->dev); 577 } 578 579 return s_stream_ret; 580 581 err_assert_rstb: 582 reset_control_assert(csi2->cmn_rstb); 583 err_mipi_link_disable: 584 rzg2l_csi2_mipi_link_setting(sd, 0); 585 err_pm_put: 586 pm_runtime_put_sync(csi2->dev); 587 return ret; 588 } 589 590 static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags) 591 { 592 return rzg2l_csi2_dphy_setting(sd, 1); 593 } 594 595 static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd) 596 { 597 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 598 599 /* 600 * In ideal case D-PHY will be disabled in s_stream(0) callback 601 * as mentioned in the HW manual. The below will only happen when 602 * pre_streamon succeeds and further down the line s_stream(1) 603 * fails so we need to undo things in post_streamoff. 604 */ 605 if (csi2->dphy_enabled) 606 return rzg2l_csi2_dphy_setting(sd, 0); 607 608 return 0; 609 } 610 611 static int rzg2l_csi2_set_format(struct v4l2_subdev *sd, 612 struct v4l2_subdev_state *state, 613 struct v4l2_subdev_format *fmt) 614 { 615 struct v4l2_mbus_framefmt *src_format; 616 struct v4l2_mbus_framefmt *sink_format; 617 618 src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE); 619 if (fmt->pad == RZG2L_CSI2_SOURCE) { 620 fmt->format = *src_format; 621 return 0; 622 } 623 624 sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK); 625 626 if (!rzg2l_csi2_code_to_fmt(fmt->format.code)) 627 sink_format->code = rzg2l_csi2_formats[0].code; 628 else 629 sink_format->code = fmt->format.code; 630 631 sink_format->field = V4L2_FIELD_NONE; 632 sink_format->colorspace = fmt->format.colorspace; 633 sink_format->xfer_func = fmt->format.xfer_func; 634 sink_format->ycbcr_enc = fmt->format.ycbcr_enc; 635 sink_format->quantization = fmt->format.quantization; 636 sink_format->width = clamp_t(u32, fmt->format.width, 637 RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH); 638 sink_format->height = clamp_t(u32, fmt->format.height, 639 RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT); 640 fmt->format = *sink_format; 641 642 /* propagate format to source pad */ 643 *src_format = *sink_format; 644 645 return 0; 646 } 647 648 static int rzg2l_csi2_init_state(struct v4l2_subdev *sd, 649 struct v4l2_subdev_state *sd_state) 650 { 651 struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, }; 652 653 fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH; 654 fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT; 655 fmt.format.field = V4L2_FIELD_NONE; 656 fmt.format.code = RZG2L_CSI2_DEFAULT_FMT; 657 fmt.format.colorspace = V4L2_COLORSPACE_SRGB; 658 fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 659 fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT; 660 fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT; 661 662 return rzg2l_csi2_set_format(sd, sd_state, &fmt); 663 } 664 665 static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd, 666 struct v4l2_subdev_state *sd_state, 667 struct v4l2_subdev_mbus_code_enum *code) 668 { 669 if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats)) 670 return -EINVAL; 671 672 code->code = rzg2l_csi2_formats[code->index].code; 673 674 return 0; 675 } 676 677 static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd, 678 struct v4l2_subdev_state *sd_state, 679 struct v4l2_subdev_frame_size_enum *fse) 680 { 681 if (fse->index != 0) 682 return -EINVAL; 683 684 if (!rzg2l_csi2_code_to_fmt(fse->code)) 685 return -EINVAL; 686 687 fse->min_width = RZG2L_CSI2_MIN_WIDTH; 688 fse->min_height = RZG2L_CSI2_MIN_HEIGHT; 689 fse->max_width = RZG2L_CSI2_MAX_WIDTH; 690 fse->max_height = RZG2L_CSI2_MAX_HEIGHT; 691 692 return 0; 693 } 694 695 static int rzg2l_csi2_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 696 struct v4l2_mbus_frame_desc *fd) 697 { 698 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 699 struct media_pad *remote_pad; 700 701 if (!csi2->remote_source) 702 return -ENODEV; 703 704 remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]); 705 if (IS_ERR(remote_pad)) { 706 dev_err(csi2->dev, "can't get source pad of %s (%ld)\n", 707 csi2->remote_source->name, PTR_ERR(remote_pad)); 708 return PTR_ERR(remote_pad); 709 } 710 return v4l2_subdev_call(csi2->remote_source, pad, get_frame_desc, 711 remote_pad->index, fd); 712 } 713 714 static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = { 715 .s_stream = rzg2l_csi2_s_stream, 716 .pre_streamon = rzg2l_csi2_pre_streamon, 717 .post_streamoff = rzg2l_csi2_post_streamoff, 718 }; 719 720 static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = { 721 .enum_mbus_code = rzg2l_csi2_enum_mbus_code, 722 .enum_frame_size = rzg2l_csi2_enum_frame_size, 723 .set_fmt = rzg2l_csi2_set_format, 724 .get_fmt = v4l2_subdev_get_fmt, 725 .get_frame_desc = rzg2l_csi2_get_frame_desc, 726 }; 727 728 static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = { 729 .video = &rzg2l_csi2_video_ops, 730 .pad = &rzg2l_csi2_pad_ops, 731 }; 732 733 static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = { 734 .init_state = rzg2l_csi2_init_state, 735 }; 736 737 /* ----------------------------------------------------------------------------- 738 * Async handling and registration of subdevices and links. 739 */ 740 741 static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier, 742 struct v4l2_subdev *subdev, 743 struct v4l2_async_connection *asd) 744 { 745 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 746 747 csi2->remote_source = subdev; 748 749 dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name); 750 751 return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK, 752 &csi2->subdev.entity, 0, 753 MEDIA_LNK_FL_ENABLED | 754 MEDIA_LNK_FL_IMMUTABLE); 755 } 756 757 static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier, 758 struct v4l2_subdev *subdev, 759 struct v4l2_async_connection *asd) 760 { 761 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 762 763 csi2->remote_source = NULL; 764 765 dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name); 766 } 767 768 static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = { 769 .bound = rzg2l_csi2_notify_bound, 770 .unbind = rzg2l_csi2_notify_unbind, 771 }; 772 773 static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2, 774 struct v4l2_fwnode_endpoint *vep) 775 { 776 /* Only port 0 endpoint 0 is valid. */ 777 if (vep->base.port || vep->base.id) 778 return -ENOTCONN; 779 780 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes; 781 782 return 0; 783 } 784 785 static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2) 786 { 787 struct v4l2_fwnode_endpoint v4l2_ep = { 788 .bus_type = V4L2_MBUS_CSI2_DPHY 789 }; 790 struct v4l2_async_connection *asd; 791 struct fwnode_handle *fwnode; 792 struct fwnode_handle *ep; 793 int ret; 794 795 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0); 796 if (!ep) { 797 dev_err(csi2->dev, "Not connected to subdevice\n"); 798 return -EINVAL; 799 } 800 801 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 802 if (ret) { 803 dev_err(csi2->dev, "Could not parse v4l2 endpoint\n"); 804 fwnode_handle_put(ep); 805 return -EINVAL; 806 } 807 808 ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep); 809 if (ret) { 810 fwnode_handle_put(ep); 811 return ret; 812 } 813 814 fwnode = fwnode_graph_get_remote_endpoint(ep); 815 fwnode_handle_put(ep); 816 817 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev); 818 csi2->notifier.ops = &rzg2l_csi2_notify_ops; 819 820 asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode, 821 struct v4l2_async_connection); 822 fwnode_handle_put(fwnode); 823 if (IS_ERR(asd)) 824 return PTR_ERR(asd); 825 826 ret = v4l2_async_nf_register(&csi2->notifier); 827 if (ret) 828 v4l2_async_nf_cleanup(&csi2->notifier); 829 830 return ret; 831 } 832 833 static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2) 834 { 835 int lanes; 836 int ret; 837 838 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) { 839 dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n", 840 csi2->lanes); 841 return -EINVAL; 842 } 843 844 ret = pm_runtime_resume_and_get(csi2->dev); 845 if (ret) 846 return ret; 847 848 /* Checking the maximum lanes support for CSI-2 module */ 849 lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8; 850 if (lanes < csi2->lanes) { 851 dev_err(csi2->dev, 852 "Failed to support %d data lanes\n", csi2->lanes); 853 ret = -EINVAL; 854 } 855 856 pm_runtime_put_sync(csi2->dev); 857 858 return ret; 859 } 860 861 /* ----------------------------------------------------------------------------- 862 * Platform Device Driver. 863 */ 864 865 static const struct media_entity_operations rzg2l_csi2_entity_ops = { 866 .link_validate = v4l2_subdev_link_validate, 867 }; 868 869 static int rzg2l_csi2_probe(struct platform_device *pdev) 870 { 871 struct device *dev = &pdev->dev; 872 struct rzg2l_csi2 *csi2; 873 int ret; 874 875 csi2 = devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL); 876 if (!csi2) 877 return -ENOMEM; 878 879 csi2->info = of_device_get_match_data(dev); 880 if (!csi2->info) 881 return dev_err_probe(dev, -EINVAL, "Failed to get OF match data\n"); 882 883 csi2->base = devm_platform_ioremap_resource(pdev, 0); 884 if (IS_ERR(csi2->base)) 885 return PTR_ERR(csi2->base); 886 887 csi2->cmn_rstb = devm_reset_control_get_exclusive(dev, "cmn-rstb"); 888 if (IS_ERR(csi2->cmn_rstb)) 889 return dev_err_probe(dev, PTR_ERR(csi2->cmn_rstb), 890 "Failed to get cpg cmn-rstb\n"); 891 892 csi2->presetn = devm_reset_control_get_shared(dev, "presetn"); 893 if (IS_ERR(csi2->presetn)) 894 return dev_err_probe(dev, PTR_ERR(csi2->presetn), 895 "Failed to get cpg presetn\n"); 896 897 if (csi2->info->has_system_clk) { 898 csi2->sysclk = devm_clk_get(dev, "system"); 899 if (IS_ERR(csi2->sysclk)) 900 return dev_err_probe(dev, PTR_ERR(csi2->sysclk), 901 "Failed to get system clk\n"); 902 } 903 904 csi2->vclk = devm_clk_get(dev, "video"); 905 if (IS_ERR(csi2->vclk)) 906 return dev_err_probe(dev, PTR_ERR(csi2->vclk), 907 "Failed to get video clock\n"); 908 csi2->vclk_rate = clk_get_rate(csi2->vclk); 909 910 csi2->dev = dev; 911 912 platform_set_drvdata(pdev, csi2); 913 914 ret = rzg2l_csi2_parse_dt(csi2); 915 if (ret) 916 return ret; 917 918 ret = devm_pm_runtime_enable(dev); 919 if (ret) 920 return ret; 921 922 ret = rzg2l_validate_csi2_lanes(csi2); 923 if (ret) 924 return ret; 925 926 csi2->subdev.dev = dev; 927 v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops); 928 csi2->subdev.internal_ops = &rzg2l_csi2_internal_ops; 929 v4l2_set_subdevdata(&csi2->subdev, dev); 930 snprintf(csi2->subdev.name, sizeof(csi2->subdev.name), 931 "csi-%s", dev_name(dev)); 932 csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 933 934 csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 935 csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops; 936 937 csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK | 938 MEDIA_PAD_FL_MUST_CONNECT; 939 /* 940 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual 941 * channels should be implemented by streams API which is under 942 * development lets hardcode to VC0 for now. 943 */ 944 csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE | 945 MEDIA_PAD_FL_MUST_CONNECT; 946 ret = media_entity_pads_init(&csi2->subdev.entity, ARRAY_SIZE(csi2->pads), 947 csi2->pads); 948 if (ret) 949 return ret; 950 951 ret = v4l2_subdev_init_finalize(&csi2->subdev); 952 if (ret < 0) 953 goto error_async; 954 955 ret = v4l2_async_register_subdev(&csi2->subdev); 956 if (ret < 0) 957 goto error_subdev; 958 959 return 0; 960 961 error_subdev: 962 v4l2_subdev_cleanup(&csi2->subdev); 963 error_async: 964 v4l2_async_nf_unregister(&csi2->notifier); 965 v4l2_async_nf_cleanup(&csi2->notifier); 966 media_entity_cleanup(&csi2->subdev.entity); 967 968 return ret; 969 } 970 971 static void rzg2l_csi2_remove(struct platform_device *pdev) 972 { 973 struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev); 974 975 v4l2_async_nf_unregister(&csi2->notifier); 976 v4l2_async_nf_cleanup(&csi2->notifier); 977 v4l2_async_unregister_subdev(&csi2->subdev); 978 v4l2_subdev_cleanup(&csi2->subdev); 979 media_entity_cleanup(&csi2->subdev.entity); 980 } 981 982 static int rzg2l_csi2_pm_runtime_suspend(struct device *dev) 983 { 984 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 985 986 reset_control_assert(csi2->presetn); 987 988 return 0; 989 } 990 991 static int rzg2l_csi2_pm_runtime_resume(struct device *dev) 992 { 993 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 994 995 return reset_control_deassert(csi2->presetn); 996 } 997 998 static const struct dev_pm_ops rzg2l_csi2_pm_ops = { 999 RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend, 1000 rzg2l_csi2_pm_runtime_resume, NULL) 1001 }; 1002 1003 static const struct of_device_id rzg2l_csi2_of_table[] = { 1004 { 1005 .compatible = "renesas,r9a09g057-csi2", 1006 .data = &rzv2h_csi2_info, 1007 }, 1008 { 1009 .compatible = "renesas,rzg2l-csi2", 1010 .data = &rzg2l_csi2_info, 1011 }, 1012 { /* sentinel */ } 1013 }; 1014 MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table); 1015 1016 static struct platform_driver rzg2l_csi2_pdrv = { 1017 .remove = rzg2l_csi2_remove, 1018 .probe = rzg2l_csi2_probe, 1019 .driver = { 1020 .name = "rzg2l-csi2", 1021 .of_match_table = rzg2l_csi2_of_table, 1022 .pm = pm_ptr(&rzg2l_csi2_pm_ops), 1023 }, 1024 }; 1025 1026 module_platform_driver(rzg2l_csi2_pdrv); 1027 1028 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1029 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver"); 1030 MODULE_LICENSE("GPL"); 1031