1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/sys_soc.h> 19 #include <linux/units.h> 20 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-fwnode.h> 24 #include <media/v4l2-mc.h> 25 #include <media/v4l2-subdev.h> 26 27 /* LINK registers */ 28 /* Module Configuration Register */ 29 #define CSI2nMCG 0x0 30 #define CSI2nMCG_SDLN GENMASK(11, 8) 31 32 /* Module Control Register 0 */ 33 #define CSI2nMCT0 0x10 34 #define CSI2nMCT0_VDLN(x) ((x) << 0) 35 36 /* Module Control Register 2 */ 37 #define CSI2nMCT2 0x18 38 #define CSI2nMCT2_FRRSKW(x) ((x) << 16) 39 #define CSI2nMCT2_FRRCLK(x) ((x) << 0) 40 41 /* Module Control Register 3 */ 42 #define CSI2nMCT3 0x1c 43 #define CSI2nMCT3_RXEN BIT(0) 44 45 /* Reset Control Register */ 46 #define CSI2nRTCT 0x28 47 #define CSI2nRTCT_VSRST BIT(0) 48 49 /* Reset Status Register */ 50 #define CSI2nRTST 0x2c 51 #define CSI2nRTST_VSRSTS BIT(0) 52 53 /* Receive Data Type Enable Low Register */ 54 #define CSI2nDTEL 0x60 55 56 /* Receive Data Type Enable High Register */ 57 #define CSI2nDTEH 0x64 58 59 /* DPHY registers */ 60 /* D-PHY Control Register 0 */ 61 #define CSIDPHYCTRL0 0x400 62 #define CSIDPHYCTRL0_EN_LDO1200 BIT(1) 63 #define CSIDPHYCTRL0_EN_BGR BIT(0) 64 65 /* D-PHY Timing Register 0 */ 66 #define CSIDPHYTIM0 0x404 67 #define CSIDPHYTIM0_TCLK_MISS(x) ((x) << 24) 68 #define CSIDPHYTIM0_T_INIT(x) ((x) << 0) 69 70 /* D-PHY Timing Register 1 */ 71 #define CSIDPHYTIM1 0x408 72 #define CSIDPHYTIM1_THS_PREPARE(x) ((x) << 24) 73 #define CSIDPHYTIM1_TCLK_PREPARE(x) ((x) << 16) 74 #define CSIDPHYTIM1_THS_SETTLE(x) ((x) << 8) 75 #define CSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0) 76 77 /* D-PHY Skew Adjustment Function */ 78 #define CSIDPHYSKW0 0x460 79 #define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) ((x) & 0x3) 80 #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) (((x) & 0x3) << 4) 81 #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) (((x) & 0x3) << 8) 82 #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) (((x) & 0x3) << 12) 83 #define CSIDPHYSKW0_DEFAULT_SKW (CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \ 84 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \ 85 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \ 86 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1)) 87 88 /* DPHY registers on RZ/V2H(P) SoC */ 89 #define CRUm_S_TIMCTL 0x41c 90 #define CRUm_S_TIMCTL_S_HSSETTLECTL(x) ((x) << 8) 91 92 #define CRUm_S_DPHYCTL_MSB 0x434 93 #define CRUm_S_DPHYCTL_MSB_DESKEW BIT(1) 94 95 #define CRUm_SWAPCTL 0x438 96 97 #define VSRSTS_RETRIES 20 98 99 #define RZG2L_CSI2_MIN_WIDTH 320 100 #define RZG2L_CSI2_MIN_HEIGHT 240 101 #define RZG2L_CSI2_MAX_WIDTH 2800 102 #define RZG2L_CSI2_MAX_HEIGHT 4095 103 104 #define RZG2L_CSI2_DEFAULT_WIDTH RZG2L_CSI2_MIN_WIDTH 105 #define RZG2L_CSI2_DEFAULT_HEIGHT RZG2L_CSI2_MIN_HEIGHT 106 #define RZG2L_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_UYVY8_1X16 107 108 enum rzg2l_csi2_pads { 109 RZG2L_CSI2_SINK = 0, 110 RZG2L_CSI2_SOURCE, 111 NR_OF_RZG2L_CSI2_PAD, 112 }; 113 114 struct rzg2l_csi2 { 115 struct device *dev; 116 void __iomem *base; 117 struct reset_control *presetn; 118 struct reset_control *cmn_rstb; 119 const struct rzg2l_csi2_info *info; 120 struct clk *sysclk; 121 struct clk *vclk; 122 unsigned long vclk_rate; 123 124 struct v4l2_subdev subdev; 125 struct media_pad pads[NR_OF_RZG2L_CSI2_PAD]; 126 127 struct v4l2_async_notifier notifier; 128 struct v4l2_subdev *remote_source; 129 130 unsigned short lanes; 131 unsigned long hsfreq; 132 133 bool dphy_enabled; 134 }; 135 136 struct rzg2l_csi2_info { 137 int (*dphy_enable)(struct rzg2l_csi2 *csi2); 138 int (*dphy_disable)(struct rzg2l_csi2 *csi2); 139 bool has_system_clk; 140 }; 141 142 struct rzg2l_csi2_timings { 143 u32 t_init; 144 u32 tclk_miss; 145 u32 tclk_settle; 146 u32 ths_settle; 147 u32 tclk_prepare; 148 u32 ths_prepare; 149 u32 max_hsfreq; 150 }; 151 152 struct rzv2h_csi2_s_hssettlectl { 153 unsigned int hsfreq; 154 u16 s_hssettlectl; 155 }; 156 157 static const struct rzv2h_csi2_s_hssettlectl rzv2h_s_hssettlectl[] = { 158 { 90, 1 }, { 130, 2 }, { 180, 3 }, 159 { 220, 4 }, { 270, 5 }, { 310, 6 }, 160 { 360, 7 }, { 400, 8 }, { 450, 9 }, 161 { 490, 10 }, { 540, 11 }, { 580, 12 }, 162 { 630, 13 }, { 670, 14 }, { 720, 15 }, 163 { 760, 16 }, { 810, 17 }, { 850, 18 }, 164 { 900, 19 }, { 940, 20 }, { 990, 21 }, 165 { 1030, 22 }, { 1080, 23 }, { 1120, 24 }, 166 { 1170, 25 }, { 1220, 26 }, { 1260, 27 }, 167 { 1310, 28 }, { 1350, 29 }, { 1400, 30 }, 168 { 1440, 31 }, { 1490, 32 }, { 1530, 33 }, 169 { 1580, 34 }, { 1620, 35 }, { 1670, 36 }, 170 { 1710, 37 }, { 1760, 38 }, { 1800, 39 }, 171 { 1850, 40 }, { 1890, 41 }, { 1940, 42 }, 172 { 1980, 43 }, { 2030, 44 }, { 2070, 45 }, 173 { 2100, 46 }, 174 }; 175 176 static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = { 177 { 178 .max_hsfreq = 80, 179 .t_init = 79801, 180 .tclk_miss = 4, 181 .tclk_settle = 23, 182 .ths_settle = 31, 183 .tclk_prepare = 10, 184 .ths_prepare = 19, 185 }, 186 { 187 .max_hsfreq = 125, 188 .t_init = 79801, 189 .tclk_miss = 4, 190 .tclk_settle = 23, 191 .ths_settle = 28, 192 .tclk_prepare = 10, 193 .ths_prepare = 19, 194 }, 195 { 196 .max_hsfreq = 250, 197 .t_init = 79801, 198 .tclk_miss = 4, 199 .tclk_settle = 23, 200 .ths_settle = 22, 201 .tclk_prepare = 10, 202 .ths_prepare = 16, 203 }, 204 { 205 .max_hsfreq = 360, 206 .t_init = 79801, 207 .tclk_miss = 4, 208 .tclk_settle = 18, 209 .ths_settle = 19, 210 .tclk_prepare = 10, 211 .ths_prepare = 10, 212 }, 213 { 214 .max_hsfreq = 1500, 215 .t_init = 79801, 216 .tclk_miss = 4, 217 .tclk_settle = 18, 218 .ths_settle = 18, 219 .tclk_prepare = 10, 220 .ths_prepare = 10, 221 }, 222 }; 223 224 struct rzg2l_csi2_format { 225 u32 code; 226 unsigned int bpp; 227 }; 228 229 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = { 230 { .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16 }, 231 { .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, }, 232 { .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, }, 233 { .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, }, 234 { .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, }, 235 { .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, }, 236 { .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, }, 237 { .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, }, 238 { .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, }, 239 { .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, }, 240 { .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, }, 241 { .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, }, 242 { .code = MEDIA_BUS_FMT_SRGGB12_1X12, .bpp = 12, }, 243 { .code = MEDIA_BUS_FMT_SBGGR14_1X14, .bpp = 14, }, 244 { .code = MEDIA_BUS_FMT_SGBRG14_1X14, .bpp = 14, }, 245 { .code = MEDIA_BUS_FMT_SGRBG14_1X14, .bpp = 14, }, 246 { .code = MEDIA_BUS_FMT_SRGGB14_1X14, .bpp = 14, }, 247 }; 248 249 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 250 { 251 return container_of(sd, struct rzg2l_csi2, subdev); 252 } 253 254 static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code) 255 { 256 unsigned int i; 257 258 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++) 259 if (rzg2l_csi2_formats[i].code == code) 260 return &rzg2l_csi2_formats[i]; 261 262 return NULL; 263 } 264 265 static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 266 { 267 return container_of(n, struct rzg2l_csi2, notifier); 268 } 269 270 static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg) 271 { 272 return ioread32(csi2->base + reg); 273 } 274 275 static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg, 276 u32 data) 277 { 278 iowrite32(data, csi2->base + reg); 279 } 280 281 static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set) 282 { 283 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set); 284 } 285 286 static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr) 287 { 288 rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr); 289 } 290 291 static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2) 292 { 293 struct v4l2_subdev *source = csi2->remote_source; 294 const struct rzg2l_csi2_format *format; 295 const struct v4l2_mbus_framefmt *fmt; 296 struct v4l2_subdev_state *state; 297 struct media_pad *remote_pad; 298 u64 mbps; 299 s64 ret; 300 301 if (!csi2->remote_source) 302 return -ENODEV; 303 304 remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]); 305 if (IS_ERR(remote_pad)) { 306 dev_err(csi2->dev, "can't get source pad of %s (%ld)\n", 307 csi2->remote_source->name, PTR_ERR(remote_pad)); 308 return PTR_ERR(remote_pad); 309 } 310 311 state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev); 312 fmt = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK); 313 format = rzg2l_csi2_code_to_fmt(fmt->code); 314 v4l2_subdev_unlock_state(state); 315 316 /* Read the link frequency from remote subdevice. */ 317 ret = v4l2_get_link_freq(remote_pad, format->bpp, csi2->lanes * 2); 318 if (ret < 0) { 319 dev_err(csi2->dev, "can't retrieve link freq from subdev %s\n", 320 source->name); 321 return -EINVAL; 322 } 323 324 mbps = ret * 2; 325 do_div(mbps, 1000000); 326 327 return mbps; 328 } 329 330 /* ----------------------------------------------------------------------------- 331 * DPHY setting 332 */ 333 334 static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2) 335 { 336 int ret; 337 338 /* Reset the CRU (D-PHY) */ 339 ret = reset_control_assert(csi2->cmn_rstb); 340 if (ret) 341 return ret; 342 343 /* Stop the D-PHY clock */ 344 clk_disable_unprepare(csi2->sysclk); 345 346 /* Cancel the EN_LDO1200 register setting */ 347 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 348 349 /* Cancel the EN_BGR register setting */ 350 rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 351 352 csi2->dphy_enabled = false; 353 354 return 0; 355 } 356 357 static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2) 358 { 359 const struct rzg2l_csi2_timings *dphy_timing; 360 u32 dphytim0, dphytim1; 361 unsigned int i; 362 int mbps; 363 int ret; 364 365 mbps = rzg2l_csi2_calc_mbps(csi2); 366 if (mbps < 0) 367 return mbps; 368 369 csi2->hsfreq = mbps; 370 371 /* Set DPHY timing parameters */ 372 for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) { 373 dphy_timing = &rzg2l_csi2_global_timings[i]; 374 375 if (csi2->hsfreq <= dphy_timing->max_hsfreq) 376 break; 377 } 378 379 if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings)) 380 return -EINVAL; 381 382 /* Set D-PHY timing parameters */ 383 dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) | 384 CSIDPHYTIM0_T_INIT(dphy_timing->t_init); 385 dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) | 386 CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) | 387 CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) | 388 CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle); 389 rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0); 390 rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1); 391 392 /* Enable D-PHY power control 0 */ 393 rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW); 394 395 /* Set the EN_BGR bit */ 396 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR); 397 398 /* Delay 20us to be stable */ 399 usleep_range(20, 40); 400 401 /* Enable D-PHY power control 1 */ 402 rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200); 403 404 /* Delay 10us to be stable */ 405 usleep_range(10, 20); 406 407 /* Start supplying the internal clock for the D-PHY block */ 408 ret = clk_prepare_enable(csi2->sysclk); 409 if (ret) 410 rzg2l_csi2_dphy_disable(csi2); 411 412 csi2->dphy_enabled = true; 413 414 return ret; 415 } 416 417 static const struct rzg2l_csi2_info rzg2l_csi2_info = { 418 .dphy_enable = rzg2l_csi2_dphy_enable, 419 .dphy_disable = rzg2l_csi2_dphy_disable, 420 .has_system_clk = true, 421 }; 422 423 static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on) 424 { 425 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 426 427 if (on) 428 return csi2->info->dphy_enable(csi2); 429 430 return csi2->info->dphy_disable(csi2); 431 } 432 433 static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2) 434 { 435 unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ; 436 u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff; 437 438 /* Select data lanes */ 439 rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes)); 440 441 frrskw_coeff = 3 * vclk_rate * 8; 442 frrclk_coeff = frrskw_coeff / 2; 443 frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq); 444 frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq); 445 rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) | 446 CSI2nMCT2_FRRCLK(frrclk)); 447 448 /* 449 * Select data type. 450 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8, 451 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit, 452 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit 453 * data types 1 to 8 454 */ 455 rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f); 456 rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f); 457 458 clk_disable_unprepare(csi2->vclk); 459 460 /* Enable LINK reception */ 461 rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 462 463 return clk_prepare_enable(csi2->vclk); 464 } 465 466 static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2) 467 { 468 unsigned int timeout = VSRSTS_RETRIES; 469 470 /* Stop LINK reception */ 471 rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN); 472 473 /* Request a software reset of the LINK Video Pixel Interface */ 474 rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST); 475 476 /* Make sure CSI2nRTST.VSRSTS bit is cleared */ 477 while (--timeout) { 478 if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS)) 479 break; 480 usleep_range(100, 200); 481 } 482 483 if (!timeout) 484 dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n"); 485 486 return 0; 487 } 488 489 static int rzv2h_csi2_dphy_disable(struct rzg2l_csi2 *csi2) 490 { 491 int ret; 492 493 /* Reset the CRU (D-PHY) */ 494 ret = reset_control_assert(csi2->cmn_rstb); 495 if (ret) 496 return ret; 497 498 csi2->dphy_enabled = false; 499 500 return 0; 501 } 502 503 static int rzv2h_csi2_dphy_enable(struct rzg2l_csi2 *csi2) 504 { 505 unsigned int i; 506 u16 hssettle; 507 int mbps; 508 509 mbps = rzg2l_csi2_calc_mbps(csi2); 510 if (mbps < 0) 511 return mbps; 512 513 csi2->hsfreq = mbps; 514 515 for (i = 0; i < ARRAY_SIZE(rzv2h_s_hssettlectl); i++) { 516 if (csi2->hsfreq <= rzv2h_s_hssettlectl[i].hsfreq) 517 break; 518 } 519 520 if (i == ARRAY_SIZE(rzv2h_s_hssettlectl)) 521 return -EINVAL; 522 523 rzg2l_csi2_write(csi2, CRUm_SWAPCTL, 0); 524 525 hssettle = rzv2h_s_hssettlectl[i].s_hssettlectl; 526 rzg2l_csi2_write(csi2, CRUm_S_TIMCTL, 527 CRUm_S_TIMCTL_S_HSSETTLECTL(hssettle)); 528 529 if (csi2->hsfreq > 1500) 530 rzg2l_csi2_set(csi2, CRUm_S_DPHYCTL_MSB, 531 CRUm_S_DPHYCTL_MSB_DESKEW); 532 else 533 rzg2l_csi2_clr(csi2, CRUm_S_DPHYCTL_MSB, 534 CRUm_S_DPHYCTL_MSB_DESKEW); 535 536 csi2->dphy_enabled = true; 537 538 return 0; 539 } 540 541 static const struct rzg2l_csi2_info rzv2h_csi2_info = { 542 .dphy_enable = rzv2h_csi2_dphy_enable, 543 .dphy_disable = rzv2h_csi2_dphy_disable, 544 .has_system_clk = false, 545 }; 546 547 static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on) 548 { 549 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 550 int ret; 551 552 if (on) 553 ret = rzg2l_csi2_mipi_link_enable(csi2); 554 else 555 ret = rzg2l_csi2_mipi_link_disable(csi2); 556 557 return ret; 558 } 559 560 static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable) 561 { 562 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 563 int s_stream_ret = 0; 564 int ret; 565 566 if (enable) { 567 ret = pm_runtime_resume_and_get(csi2->dev); 568 if (ret) 569 return ret; 570 571 ret = rzg2l_csi2_mipi_link_setting(sd, 1); 572 if (ret) 573 goto err_pm_put; 574 575 ret = reset_control_deassert(csi2->cmn_rstb); 576 if (ret) 577 goto err_mipi_link_disable; 578 } 579 580 ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable); 581 if (ret) 582 s_stream_ret = ret; 583 584 if (enable && ret) 585 goto err_assert_rstb; 586 587 if (!enable) { 588 ret = rzg2l_csi2_dphy_setting(sd, 0); 589 if (ret && !s_stream_ret) 590 s_stream_ret = ret; 591 ret = rzg2l_csi2_mipi_link_setting(sd, 0); 592 if (ret && !s_stream_ret) 593 s_stream_ret = ret; 594 595 pm_runtime_put_sync(csi2->dev); 596 } 597 598 return s_stream_ret; 599 600 err_assert_rstb: 601 reset_control_assert(csi2->cmn_rstb); 602 err_mipi_link_disable: 603 rzg2l_csi2_mipi_link_setting(sd, 0); 604 err_pm_put: 605 pm_runtime_put_sync(csi2->dev); 606 return ret; 607 } 608 609 static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags) 610 { 611 return rzg2l_csi2_dphy_setting(sd, 1); 612 } 613 614 static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd) 615 { 616 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 617 618 /* 619 * In ideal case D-PHY will be disabled in s_stream(0) callback 620 * as mentioned in the HW manual. The below will only happen when 621 * pre_streamon succeeds and further down the line s_stream(1) 622 * fails so we need to undo things in post_streamoff. 623 */ 624 if (csi2->dphy_enabled) 625 return rzg2l_csi2_dphy_setting(sd, 0); 626 627 return 0; 628 } 629 630 static int rzg2l_csi2_set_format(struct v4l2_subdev *sd, 631 struct v4l2_subdev_state *state, 632 struct v4l2_subdev_format *fmt) 633 { 634 struct v4l2_mbus_framefmt *src_format; 635 struct v4l2_mbus_framefmt *sink_format; 636 637 src_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SOURCE); 638 if (fmt->pad == RZG2L_CSI2_SOURCE) { 639 fmt->format = *src_format; 640 return 0; 641 } 642 643 sink_format = v4l2_subdev_state_get_format(state, RZG2L_CSI2_SINK); 644 645 if (!rzg2l_csi2_code_to_fmt(fmt->format.code)) 646 sink_format->code = rzg2l_csi2_formats[0].code; 647 else 648 sink_format->code = fmt->format.code; 649 650 sink_format->field = V4L2_FIELD_NONE; 651 sink_format->colorspace = fmt->format.colorspace; 652 sink_format->xfer_func = fmt->format.xfer_func; 653 sink_format->ycbcr_enc = fmt->format.ycbcr_enc; 654 sink_format->quantization = fmt->format.quantization; 655 sink_format->width = clamp_t(u32, fmt->format.width, 656 RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH); 657 sink_format->height = clamp_t(u32, fmt->format.height, 658 RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT); 659 fmt->format = *sink_format; 660 661 /* propagate format to source pad */ 662 *src_format = *sink_format; 663 664 return 0; 665 } 666 667 static int rzg2l_csi2_init_state(struct v4l2_subdev *sd, 668 struct v4l2_subdev_state *sd_state) 669 { 670 struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, }; 671 672 fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH; 673 fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT; 674 fmt.format.field = V4L2_FIELD_NONE; 675 fmt.format.code = RZG2L_CSI2_DEFAULT_FMT; 676 fmt.format.colorspace = V4L2_COLORSPACE_SRGB; 677 fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 678 fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT; 679 fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT; 680 681 return rzg2l_csi2_set_format(sd, sd_state, &fmt); 682 } 683 684 static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd, 685 struct v4l2_subdev_state *sd_state, 686 struct v4l2_subdev_mbus_code_enum *code) 687 { 688 if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats)) 689 return -EINVAL; 690 691 code->code = rzg2l_csi2_formats[code->index].code; 692 693 return 0; 694 } 695 696 static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd, 697 struct v4l2_subdev_state *sd_state, 698 struct v4l2_subdev_frame_size_enum *fse) 699 { 700 if (fse->index != 0) 701 return -EINVAL; 702 703 if (!rzg2l_csi2_code_to_fmt(fse->code)) 704 return -EINVAL; 705 706 fse->min_width = RZG2L_CSI2_MIN_WIDTH; 707 fse->min_height = RZG2L_CSI2_MIN_HEIGHT; 708 fse->max_width = RZG2L_CSI2_MAX_WIDTH; 709 fse->max_height = RZG2L_CSI2_MAX_HEIGHT; 710 711 return 0; 712 } 713 714 static int rzg2l_csi2_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 715 struct v4l2_mbus_frame_desc *fd) 716 { 717 struct rzg2l_csi2 *csi2 = sd_to_csi2(sd); 718 struct media_pad *remote_pad; 719 720 if (!csi2->remote_source) 721 return -ENODEV; 722 723 remote_pad = media_pad_remote_pad_unique(&csi2->pads[RZG2L_CSI2_SINK]); 724 if (IS_ERR(remote_pad)) { 725 dev_err(csi2->dev, "can't get source pad of %s (%ld)\n", 726 csi2->remote_source->name, PTR_ERR(remote_pad)); 727 return PTR_ERR(remote_pad); 728 } 729 return v4l2_subdev_call(csi2->remote_source, pad, get_frame_desc, 730 remote_pad->index, fd); 731 } 732 733 static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = { 734 .s_stream = rzg2l_csi2_s_stream, 735 .pre_streamon = rzg2l_csi2_pre_streamon, 736 .post_streamoff = rzg2l_csi2_post_streamoff, 737 }; 738 739 static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = { 740 .enum_mbus_code = rzg2l_csi2_enum_mbus_code, 741 .enum_frame_size = rzg2l_csi2_enum_frame_size, 742 .set_fmt = rzg2l_csi2_set_format, 743 .get_fmt = v4l2_subdev_get_fmt, 744 .get_frame_desc = rzg2l_csi2_get_frame_desc, 745 }; 746 747 static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = { 748 .video = &rzg2l_csi2_video_ops, 749 .pad = &rzg2l_csi2_pad_ops, 750 }; 751 752 static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = { 753 .init_state = rzg2l_csi2_init_state, 754 }; 755 756 /* ----------------------------------------------------------------------------- 757 * Async handling and registration of subdevices and links. 758 */ 759 760 static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier, 761 struct v4l2_subdev *subdev, 762 struct v4l2_async_connection *asd) 763 { 764 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 765 766 csi2->remote_source = subdev; 767 768 dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name); 769 770 return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK, 771 &csi2->subdev.entity, 0, 772 MEDIA_LNK_FL_ENABLED | 773 MEDIA_LNK_FL_IMMUTABLE); 774 } 775 776 static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier, 777 struct v4l2_subdev *subdev, 778 struct v4l2_async_connection *asd) 779 { 780 struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier); 781 782 csi2->remote_source = NULL; 783 784 dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name); 785 } 786 787 static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = { 788 .bound = rzg2l_csi2_notify_bound, 789 .unbind = rzg2l_csi2_notify_unbind, 790 }; 791 792 static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2, 793 struct v4l2_fwnode_endpoint *vep) 794 { 795 /* Only port 0 endpoint 0 is valid. */ 796 if (vep->base.port || vep->base.id) 797 return -ENOTCONN; 798 799 csi2->lanes = vep->bus.mipi_csi2.num_data_lanes; 800 801 return 0; 802 } 803 804 static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2) 805 { 806 struct v4l2_fwnode_endpoint v4l2_ep = { 807 .bus_type = V4L2_MBUS_CSI2_DPHY 808 }; 809 struct v4l2_async_connection *asd; 810 struct fwnode_handle *fwnode; 811 struct fwnode_handle *ep; 812 int ret; 813 814 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0); 815 if (!ep) { 816 dev_err(csi2->dev, "Not connected to subdevice\n"); 817 return -EINVAL; 818 } 819 820 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 821 if (ret) { 822 dev_err(csi2->dev, "Could not parse v4l2 endpoint\n"); 823 fwnode_handle_put(ep); 824 return -EINVAL; 825 } 826 827 ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep); 828 if (ret) { 829 fwnode_handle_put(ep); 830 return ret; 831 } 832 833 fwnode = fwnode_graph_get_remote_endpoint(ep); 834 fwnode_handle_put(ep); 835 836 v4l2_async_subdev_nf_init(&csi2->notifier, &csi2->subdev); 837 csi2->notifier.ops = &rzg2l_csi2_notify_ops; 838 839 asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode, 840 struct v4l2_async_connection); 841 fwnode_handle_put(fwnode); 842 if (IS_ERR(asd)) 843 return PTR_ERR(asd); 844 845 ret = v4l2_async_nf_register(&csi2->notifier); 846 if (ret) 847 v4l2_async_nf_cleanup(&csi2->notifier); 848 849 return ret; 850 } 851 852 static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2) 853 { 854 int lanes; 855 int ret; 856 857 if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) { 858 dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n", 859 csi2->lanes); 860 return -EINVAL; 861 } 862 863 ret = pm_runtime_resume_and_get(csi2->dev); 864 if (ret) 865 return ret; 866 867 /* Checking the maximum lanes support for CSI-2 module */ 868 lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8; 869 if (lanes < csi2->lanes) { 870 dev_err(csi2->dev, 871 "Failed to support %d data lanes\n", csi2->lanes); 872 ret = -EINVAL; 873 } 874 875 pm_runtime_put_sync(csi2->dev); 876 877 return ret; 878 } 879 880 /* ----------------------------------------------------------------------------- 881 * Platform Device Driver. 882 */ 883 884 static const struct media_entity_operations rzg2l_csi2_entity_ops = { 885 .link_validate = v4l2_subdev_link_validate, 886 }; 887 888 static int rzg2l_csi2_probe(struct platform_device *pdev) 889 { 890 struct device *dev = &pdev->dev; 891 struct rzg2l_csi2 *csi2; 892 int ret; 893 894 csi2 = devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL); 895 if (!csi2) 896 return -ENOMEM; 897 898 csi2->info = of_device_get_match_data(dev); 899 if (!csi2->info) 900 return dev_err_probe(dev, -EINVAL, "Failed to get OF match data\n"); 901 902 csi2->base = devm_platform_ioremap_resource(pdev, 0); 903 if (IS_ERR(csi2->base)) 904 return PTR_ERR(csi2->base); 905 906 csi2->cmn_rstb = devm_reset_control_get_exclusive(dev, "cmn-rstb"); 907 if (IS_ERR(csi2->cmn_rstb)) 908 return dev_err_probe(dev, PTR_ERR(csi2->cmn_rstb), 909 "Failed to get cpg cmn-rstb\n"); 910 911 csi2->presetn = devm_reset_control_get_shared(dev, "presetn"); 912 if (IS_ERR(csi2->presetn)) 913 return dev_err_probe(dev, PTR_ERR(csi2->presetn), 914 "Failed to get cpg presetn\n"); 915 916 if (csi2->info->has_system_clk) { 917 csi2->sysclk = devm_clk_get(dev, "system"); 918 if (IS_ERR(csi2->sysclk)) 919 return dev_err_probe(dev, PTR_ERR(csi2->sysclk), 920 "Failed to get system clk\n"); 921 } 922 923 csi2->vclk = devm_clk_get(dev, "video"); 924 if (IS_ERR(csi2->vclk)) 925 return dev_err_probe(dev, PTR_ERR(csi2->vclk), 926 "Failed to get video clock\n"); 927 csi2->vclk_rate = clk_get_rate(csi2->vclk); 928 929 csi2->dev = dev; 930 931 platform_set_drvdata(pdev, csi2); 932 933 ret = rzg2l_csi2_parse_dt(csi2); 934 if (ret) 935 return ret; 936 937 ret = devm_pm_runtime_enable(dev); 938 if (ret) 939 return ret; 940 941 ret = rzg2l_validate_csi2_lanes(csi2); 942 if (ret) 943 return ret; 944 945 csi2->subdev.dev = dev; 946 v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops); 947 csi2->subdev.internal_ops = &rzg2l_csi2_internal_ops; 948 v4l2_set_subdevdata(&csi2->subdev, dev); 949 snprintf(csi2->subdev.name, sizeof(csi2->subdev.name), 950 "csi-%s", dev_name(dev)); 951 csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 952 953 csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 954 csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops; 955 956 csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK | 957 MEDIA_PAD_FL_MUST_CONNECT; 958 /* 959 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual 960 * channels should be implemented by streams API which is under 961 * development lets hardcode to VC0 for now. 962 */ 963 csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE | 964 MEDIA_PAD_FL_MUST_CONNECT; 965 ret = media_entity_pads_init(&csi2->subdev.entity, ARRAY_SIZE(csi2->pads), 966 csi2->pads); 967 if (ret) 968 return ret; 969 970 ret = v4l2_subdev_init_finalize(&csi2->subdev); 971 if (ret < 0) 972 goto error_async; 973 974 ret = v4l2_async_register_subdev(&csi2->subdev); 975 if (ret < 0) 976 goto error_subdev; 977 978 return 0; 979 980 error_subdev: 981 v4l2_subdev_cleanup(&csi2->subdev); 982 error_async: 983 v4l2_async_nf_unregister(&csi2->notifier); 984 v4l2_async_nf_cleanup(&csi2->notifier); 985 media_entity_cleanup(&csi2->subdev.entity); 986 987 return ret; 988 } 989 990 static void rzg2l_csi2_remove(struct platform_device *pdev) 991 { 992 struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev); 993 994 v4l2_async_nf_unregister(&csi2->notifier); 995 v4l2_async_nf_cleanup(&csi2->notifier); 996 v4l2_async_unregister_subdev(&csi2->subdev); 997 v4l2_subdev_cleanup(&csi2->subdev); 998 media_entity_cleanup(&csi2->subdev.entity); 999 } 1000 1001 static int rzg2l_csi2_pm_runtime_suspend(struct device *dev) 1002 { 1003 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 1004 1005 reset_control_assert(csi2->presetn); 1006 1007 return 0; 1008 } 1009 1010 static int rzg2l_csi2_pm_runtime_resume(struct device *dev) 1011 { 1012 struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev); 1013 1014 return reset_control_deassert(csi2->presetn); 1015 } 1016 1017 static const struct dev_pm_ops rzg2l_csi2_pm_ops = { 1018 RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend, 1019 rzg2l_csi2_pm_runtime_resume, NULL) 1020 }; 1021 1022 static const struct of_device_id rzg2l_csi2_of_table[] = { 1023 { 1024 .compatible = "renesas,r9a09g057-csi2", 1025 .data = &rzv2h_csi2_info, 1026 }, 1027 { 1028 .compatible = "renesas,rzg2l-csi2", 1029 .data = &rzg2l_csi2_info, 1030 }, 1031 { /* sentinel */ } 1032 }; 1033 MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table); 1034 1035 static struct platform_driver rzg2l_csi2_pdrv = { 1036 .remove = rzg2l_csi2_remove, 1037 .probe = rzg2l_csi2_probe, 1038 .driver = { 1039 .name = "rzg2l-csi2", 1040 .of_match_table = rzg2l_csi2_of_table, 1041 .pm = pm_ptr(&rzg2l_csi2_pm_ops), 1042 }, 1043 }; 1044 1045 module_platform_driver(rzg2l_csi2_pdrv); 1046 1047 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1048 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver"); 1049 MODULE_LICENSE("GPL"); 1050