1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2025 Linaro Ltd 5 */ 6 7 #include "iris_core.h" 8 #include "iris_ctrls.h" 9 #include "iris_hfi_gen2.h" 10 #include "iris_hfi_gen2_defines.h" 11 #include "iris_platform_common.h" 12 #include "iris_vpu_buffer.h" 13 #include "iris_vpu_common.h" 14 15 #include "iris_platform_qcs8300.h" 16 #include "iris_platform_sm8550.h" 17 #include "iris_platform_sm8650.h" 18 #include "iris_platform_sm8750.h" 19 #include "iris_platform_x1p42100.h" 20 21 static const struct iris_firmware_desc iris_vpu30_p4_s6_gen2_desc = { 22 .firmware_data = &iris_hfi_gen2_data, 23 .get_vpu_buffer_size = iris_vpu_buf_size, 24 .fwname = "qcom/vpu/vpu30_p4_s6.mbn", 25 }; 26 27 static const struct iris_firmware_desc iris_vpu30_p4_gen2_desc = { 28 .firmware_data = &iris_hfi_gen2_data, 29 .get_vpu_buffer_size = iris_vpu_buf_size, 30 .fwname = "qcom/vpu/vpu30_p4.mbn", 31 }; 32 33 static const struct iris_firmware_desc iris_vpu30_p1_gen2_desc = { 34 .firmware_data = &iris_hfi_gen2_data, 35 .get_vpu_buffer_size = iris_vpu_buf_size, 36 .fwname = "qcom/vpu/vpu30_p1_s7.mbn", 37 }; 38 39 static const struct iris_firmware_desc iris_vpu33_p4_gen2_desc = { 40 .firmware_data = &iris_hfi_gen2_data, 41 .get_vpu_buffer_size = iris_vpu33_buf_size, 42 .fwname = "qcom/vpu/vpu33_p4.mbn", 43 }; 44 45 static const struct iris_firmware_desc iris_vpu35_p4_gen2_desc = { 46 .firmware_data = &iris_hfi_gen2_data, 47 .get_vpu_buffer_size = iris_vpu33_buf_size, 48 .fwname = "qcom/vpu/vpu35_p4.mbn", 49 }; 50 51 static const u32 iris_fmts_vpu3x_dec[] = { 52 [IRIS_FMT_H264] = V4L2_PIX_FMT_H264, 53 [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC, 54 [IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9, 55 [IRIS_FMT_AV1] = V4L2_PIX_FMT_AV1, 56 }; 57 58 static const struct icc_info iris_icc_info_vpu3x[] = { 59 { "cpu-cfg", 1000, 1000 }, 60 { "video-mem", 1000, 15000000 }, 61 }; 62 63 static const struct bw_info iris_bw_table_dec_vpu3x[] = { 64 { ((4096 * 2160) / 256) * 60, 1608000 }, 65 { ((4096 * 2160) / 256) * 30, 826000 }, 66 { ((1920 * 1080) / 256) * 60, 567000 }, 67 { ((1920 * 1080) / 256) * 30, 294000 }, 68 }; 69 70 static const char * const iris_pmdomain_table_vpu3x[] = { "venus", "vcodec0" }; 71 72 static const char * const iris_opp_pd_table_vpu3x[] = { "mxc", "mmcx" }; 73 74 static const char * const iris_opp_clk_table_vpu3x[] = { 75 "vcodec0_core", 76 NULL, 77 }; 78 79 static const struct tz_cp_config tz_cp_config_vpu3[] = { 80 { 81 .cp_start = 0, 82 .cp_size = 0x25800000, 83 .cp_nonpixel_start = 0x01000000, 84 .cp_nonpixel_size = 0x24800000, 85 }, 86 }; 87 88 /* 89 * Shares most of SM8550 data except: 90 * - inst_caps to platform_inst_cap_qcs8300 91 */ 92 const struct iris_platform_data qcs8300_data = { 93 .firmware_desc = &iris_vpu30_p4_s6_gen2_desc, 94 .vpu_ops = &iris_vpu3_ops, 95 .icc_tbl = iris_icc_info_vpu3x, 96 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), 97 .clk_rst_tbl = sm8550_clk_reset_table, 98 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), 99 .bw_tbl_dec = iris_bw_table_dec_vpu3x, 100 .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), 101 .pmdomain_tbl = iris_pmdomain_table_vpu3x, 102 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), 103 .opp_pd_tbl = iris_opp_pd_table_vpu3x, 104 .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), 105 .clk_tbl = sm8550_clk_table, 106 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), 107 .opp_clk_tbl = iris_opp_clk_table_vpu3x, 108 /* Upper bound of DMA address range */ 109 .dma_mask = 0xe0000000 - 1, 110 .inst_iris_fmts = iris_fmts_vpu3x_dec, 111 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), 112 .inst_caps = &platform_inst_cap_qcs8300, 113 .tz_cp_config_data = tz_cp_config_vpu3, 114 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), 115 .num_vpp_pipe = 2, 116 .max_session_count = 16, 117 .max_core_mbpf = ((4096 * 2176) / 256) * 4, 118 .max_core_mbps = (((3840 * 2176) / 256) * 120), 119 }; 120 121 const struct iris_platform_data sm8550_data = { 122 .firmware_desc = &iris_vpu30_p4_gen2_desc, 123 .vpu_ops = &iris_vpu3_ops, 124 .icc_tbl = iris_icc_info_vpu3x, 125 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), 126 .clk_rst_tbl = sm8550_clk_reset_table, 127 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), 128 .bw_tbl_dec = iris_bw_table_dec_vpu3x, 129 .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), 130 .pmdomain_tbl = iris_pmdomain_table_vpu3x, 131 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), 132 .opp_pd_tbl = iris_opp_pd_table_vpu3x, 133 .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), 134 .clk_tbl = sm8550_clk_table, 135 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), 136 .opp_clk_tbl = iris_opp_clk_table_vpu3x, 137 /* Upper bound of DMA address range */ 138 .dma_mask = 0xe0000000 - 1, 139 .inst_iris_fmts = iris_fmts_vpu3x_dec, 140 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), 141 .inst_caps = &platform_inst_cap_sm8550, 142 .tz_cp_config_data = tz_cp_config_vpu3, 143 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), 144 .num_vpp_pipe = 4, 145 .max_session_count = 16, 146 .max_core_mbpf = NUM_MBS_8K * 2, 147 .max_core_mbps = ((7680 * 4320) / 256) * 60, 148 }; 149 150 /* 151 * Shares most of SM8550 data except: 152 * - vpu_ops to iris_vpu33_ops 153 * - clk_rst_tbl to sm8650_clk_reset_table 154 * - controller_rst_tbl to sm8650_controller_reset_table 155 */ 156 const struct iris_platform_data sm8650_data = { 157 .firmware_desc = &iris_vpu33_p4_gen2_desc, 158 .vpu_ops = &iris_vpu33_ops, 159 .icc_tbl = iris_icc_info_vpu3x, 160 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), 161 .clk_rst_tbl = sm8650_clk_reset_table, 162 .clk_rst_tbl_size = ARRAY_SIZE(sm8650_clk_reset_table), 163 .controller_rst_tbl = sm8650_controller_reset_table, 164 .controller_rst_tbl_size = ARRAY_SIZE(sm8650_controller_reset_table), 165 .bw_tbl_dec = iris_bw_table_dec_vpu3x, 166 .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), 167 .pmdomain_tbl = iris_pmdomain_table_vpu3x, 168 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), 169 .opp_pd_tbl = iris_opp_pd_table_vpu3x, 170 .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), 171 .clk_tbl = sm8550_clk_table, 172 .clk_tbl_size = ARRAY_SIZE(sm8550_clk_table), 173 .opp_clk_tbl = iris_opp_clk_table_vpu3x, 174 /* Upper bound of DMA address range */ 175 .dma_mask = 0xe0000000 - 1, 176 .inst_iris_fmts = iris_fmts_vpu3x_dec, 177 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), 178 .inst_caps = &platform_inst_cap_sm8550, 179 .tz_cp_config_data = tz_cp_config_vpu3, 180 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), 181 .num_vpp_pipe = 4, 182 .max_session_count = 16, 183 .max_core_mbpf = NUM_MBS_8K * 2, 184 .max_core_mbps = ((7680 * 4320) / 256) * 60, 185 }; 186 187 const struct iris_platform_data sm8750_data = { 188 .firmware_desc = &iris_vpu35_p4_gen2_desc, 189 .vpu_ops = &iris_vpu35_ops, 190 .icc_tbl = iris_icc_info_vpu3x, 191 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), 192 .clk_rst_tbl = sm8750_clk_reset_table, 193 .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), 194 .bw_tbl_dec = iris_bw_table_dec_vpu3x, 195 .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), 196 .pmdomain_tbl = iris_pmdomain_table_vpu3x, 197 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), 198 .opp_pd_tbl = iris_opp_pd_table_vpu3x, 199 .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), 200 .clk_tbl = sm8750_clk_table, 201 .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), 202 .opp_clk_tbl = iris_opp_clk_table_vpu3x, 203 /* Upper bound of DMA address range */ 204 .dma_mask = 0xe0000000 - 1, 205 .inst_iris_fmts = iris_fmts_vpu3x_dec, 206 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), 207 .inst_caps = &platform_inst_cap_sm8550, 208 .tz_cp_config_data = tz_cp_config_vpu3, 209 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), 210 .num_vpp_pipe = 4, 211 .max_session_count = 16, 212 .max_core_mbpf = NUM_MBS_8K * 2, 213 .max_core_mbps = ((7680 * 4320) / 256) * 60, 214 }; 215 216 /* 217 * Shares most of SM8550 data except: 218 * - clk_tbl and opp_clk_tbl for x1p42100 219 * - different firmware 220 * - different num_vpp_pipe 221 */ 222 const struct iris_platform_data x1p42100_data = { 223 .firmware_desc = &iris_vpu30_p1_gen2_desc, 224 .vpu_ops = &iris_vpu3_ops, 225 .icc_tbl = iris_icc_info_vpu3x, 226 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu3x), 227 .clk_rst_tbl = sm8550_clk_reset_table, 228 .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), 229 .bw_tbl_dec = iris_bw_table_dec_vpu3x, 230 .bw_tbl_dec_size = ARRAY_SIZE(iris_bw_table_dec_vpu3x), 231 .pmdomain_tbl = iris_pmdomain_table_vpu3x, 232 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu3x), 233 .opp_pd_tbl = iris_opp_pd_table_vpu3x, 234 .opp_pd_tbl_size = ARRAY_SIZE(iris_opp_pd_table_vpu3x), 235 .clk_tbl = x1p42100_clk_table, 236 .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table), 237 .opp_clk_tbl = x1p42100_opp_clk_table, 238 /* Upper bound of DMA address range */ 239 .dma_mask = 0xe0000000 - 1, 240 .inst_iris_fmts = iris_fmts_vpu3x_dec, 241 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu3x_dec), 242 .inst_caps = &platform_inst_cap_sm8550, 243 .tz_cp_config_data = tz_cp_config_vpu3, 244 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu3), 245 .num_vpp_pipe = 1, 246 .max_session_count = 16, 247 .max_core_mbpf = NUM_MBS_8K * 2, 248 .max_core_mbps = ((7680 * 4320) / 256) * 60, 249 }; 250