1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #include "iris_core.h" 7 #include "iris_ctrls.h" 8 #include "iris_platform_common.h" 9 #include "iris_resources.h" 10 #include "iris_hfi_gen1.h" 11 #include "iris_hfi_gen1_defines.h" 12 #include "iris_vpu_buffer.h" 13 #include "iris_vpu_common.h" 14 #include "iris_instance.h" 15 16 #include "iris_platform_sc7280.h" 17 #include "iris_platform_sm8250.h" 18 19 static const struct iris_firmware_desc iris_vpu20_p1_gen1_desc = { 20 .firmware_data = &iris_hfi_gen1_data, 21 .get_vpu_buffer_size = iris_vpu_buf_size, 22 .fwname = "qcom/vpu/vpu20_p1.mbn", 23 }; 24 25 static const struct iris_firmware_desc iris_vpu20_p4_gen1_desc = { 26 .firmware_data = &iris_hfi_gen1_data, 27 .get_vpu_buffer_size = iris_vpu_buf_size, 28 .fwname = "qcom/vpu/vpu20_p4.mbn", 29 }; 30 31 static const u32 iris_fmts_vpu2_dec[] = { 32 [IRIS_FMT_H264] = V4L2_PIX_FMT_H264, 33 [IRIS_FMT_HEVC] = V4L2_PIX_FMT_HEVC, 34 [IRIS_FMT_VP9] = V4L2_PIX_FMT_VP9, 35 }; 36 37 static struct platform_inst_caps platform_inst_cap_vpu2 = { 38 .min_frame_width = 128, 39 .max_frame_width = 8192, 40 .min_frame_height = 128, 41 .max_frame_height = 8192, 42 .max_mbpf = 138240, 43 .mb_cycles_vsp = 25, 44 .mb_cycles_vpp = 200, 45 .max_frame_rate = MAXIMUM_FPS, 46 .max_operating_rate = MAXIMUM_FPS, 47 }; 48 49 static const struct icc_info iris_icc_info_vpu2[] = { 50 { "cpu-cfg", 1000, 1000 }, 51 { "video-mem", 1000, 15000000 }, 52 }; 53 54 static const char * const iris_clk_reset_table_vpu2[] = { "bus", "core" }; 55 56 static const char * const iris_pmdomain_table_vpu2[] = { "venus", "vcodec0" }; 57 58 static const struct tz_cp_config tz_cp_config_vpu2[] = { 59 { 60 .cp_start = 0, 61 .cp_size = 0x25800000, 62 .cp_nonpixel_start = 0x01000000, 63 .cp_nonpixel_size = 0x24800000, 64 }, 65 }; 66 67 const struct iris_platform_data sc7280_data = { 68 .firmware_desc = &iris_vpu20_p1_gen1_desc, 69 .vpu_ops = &iris_vpu2_ops, 70 .icc_tbl = iris_icc_info_vpu2, 71 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), 72 .bw_tbl_dec = sc7280_bw_table_dec, 73 .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), 74 .pmdomain_tbl = iris_pmdomain_table_vpu2, 75 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), 76 .opp_pd_tbl = sc7280_opp_pd_table, 77 .opp_pd_tbl_size = ARRAY_SIZE(sc7280_opp_pd_table), 78 .clk_tbl = sc7280_clk_table, 79 .clk_tbl_size = ARRAY_SIZE(sc7280_clk_table), 80 .opp_clk_tbl = sc7280_opp_clk_table, 81 /* Upper bound of DMA address range */ 82 .dma_mask = 0xe0000000 - 1, 83 .inst_iris_fmts = iris_fmts_vpu2_dec, 84 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), 85 .inst_caps = &platform_inst_cap_vpu2, 86 .tz_cp_config_data = tz_cp_config_vpu2, 87 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), 88 .num_vpp_pipe = 1, 89 .no_aon = true, 90 .max_session_count = 16, 91 .max_core_mbpf = 4096 * 2176 / 256 * 2 + 1920 * 1088 / 256, 92 /* max spec for SC7280 is 4096x2176@60fps */ 93 .max_core_mbps = 4096 * 2176 / 256 * 60, 94 }; 95 96 const struct iris_platform_data sm8250_data = { 97 .firmware_desc = &iris_vpu20_p4_gen1_desc, 98 .vpu_ops = &iris_vpu2_ops, 99 .icc_tbl = iris_icc_info_vpu2, 100 .icc_tbl_size = ARRAY_SIZE(iris_icc_info_vpu2), 101 .clk_rst_tbl = iris_clk_reset_table_vpu2, 102 .clk_rst_tbl_size = ARRAY_SIZE(iris_clk_reset_table_vpu2), 103 .bw_tbl_dec = sm8250_bw_table_dec, 104 .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), 105 .pmdomain_tbl = iris_pmdomain_table_vpu2, 106 .pmdomain_tbl_size = ARRAY_SIZE(iris_pmdomain_table_vpu2), 107 .opp_pd_tbl = sm8250_opp_pd_table, 108 .opp_pd_tbl_size = ARRAY_SIZE(sm8250_opp_pd_table), 109 .clk_tbl = sm8250_clk_table, 110 .clk_tbl_size = ARRAY_SIZE(sm8250_clk_table), 111 .opp_clk_tbl = sm8250_opp_clk_table, 112 /* Upper bound of DMA address range */ 113 .dma_mask = 0xe0000000 - 1, 114 .inst_iris_fmts = iris_fmts_vpu2_dec, 115 .inst_iris_fmts_size = ARRAY_SIZE(iris_fmts_vpu2_dec), 116 .inst_caps = &platform_inst_cap_vpu2, 117 .tz_cp_config_data = tz_cp_config_vpu2, 118 .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_vpu2), 119 .num_vpp_pipe = 4, 120 .max_session_count = 16, 121 .max_core_mbpf = NUM_MBS_8K, 122 .max_core_mbps = ((7680 * 4320) / 256) * 60, 123 }; 124