1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * camss-tpg.h 4 * 5 * Qualcomm MSM Camera Subsystem - TPG Module 6 * 7 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 8 */ 9 #ifndef QC_MSM_CAMSS_TPG_H 10 #define QC_MSM_CAMSS_TPG_H 11 12 #include <linux/clk.h> 13 #include <linux/bitfield.h> 14 #include <media/media-entity.h> 15 #include <media/v4l2-ctrls.h> 16 #include <media/v4l2-device.h> 17 #include <media/v4l2-mediabus.h> 18 #include <media/v4l2-subdev.h> 19 20 #define ENCODE_FORMAT_UNCOMPRESSED_8_BIT 0x1 21 #define ENCODE_FORMAT_UNCOMPRESSED_10_BIT 0x2 22 #define ENCODE_FORMAT_UNCOMPRESSED_12_BIT 0x3 23 #define ENCODE_FORMAT_UNCOMPRESSED_14_BIT 0x4 24 #define ENCODE_FORMAT_UNCOMPRESSED_16_BIT 0x5 25 #define ENCODE_FORMAT_UNCOMPRESSED_20_BIT 0x6 26 #define ENCODE_FORMAT_UNCOMPRESSED_24_BIT 0x7 27 28 #define MSM_TPG_PAD_SRC 0 29 #define MSM_TPG_ACTIVE_VC 0 30 #define MSM_TPG_ACTIVE_DT 0 31 32 #define TPG_MIN_WIDTH 1 33 #define TPG_MIN_HEIGHT 1 34 #define TPG_MAX_WIDTH 8191 35 #define TPG_MAX_HEIGHT 8191 36 37 #define TPG_GRP_ID 0 38 39 enum tpg_testgen_mode { 40 TPG_PAYLOAD_MODE_DISABLED = 0, 41 TPG_PAYLOAD_MODE_INCREMENTING = 1, 42 TPG_PAYLOAD_MODE_ALTERNATING_55_AA = 2, 43 TPG_PAYLOAD_MODE_RANDOM = 5, 44 TPG_PAYLOAD_MODE_USER_SPECIFIED = 6, 45 TPG_PAYLOAD_MODE_COLOR_BARS = 9, 46 TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1 = 9, 47 }; 48 49 struct tpg_testgen_config { 50 enum tpg_testgen_mode mode; 51 const char * const*modes; 52 u8 nmodes; 53 }; 54 55 struct tpg_format_info { 56 u32 code; 57 u8 data_type; 58 u8 encode_format; 59 u8 bpp; 60 }; 61 62 struct tpg_formats { 63 unsigned int nformats; 64 const struct tpg_format_info *formats; 65 }; 66 67 struct tpg_device; 68 69 struct tpg_hw_ops { 70 int (*configure_stream)(struct tpg_device *tpg, u8 enable); 71 int (*configure_testgen_pattern)(struct tpg_device *tpg, s32 val); 72 u32 (*hw_version)(struct tpg_device *tpg); 73 int (*reset)(struct tpg_device *tpg); 74 void (*subdev_init)(struct tpg_device *tpg); 75 }; 76 77 struct tpg_subdev_resources { 78 u8 lane_cnt; 79 const struct tpg_formats *formats; 80 const struct tpg_hw_ops *hw_ops; 81 }; 82 83 struct tpg_device { 84 struct camss *camss; 85 u8 id; 86 struct v4l2_subdev subdev; 87 struct media_pad pad; 88 void __iomem *base; 89 struct camss_clock *clock; 90 int nclocks; 91 struct tpg_testgen_config testgen; 92 struct v4l2_mbus_framefmt fmt; 93 struct v4l2_ctrl_handler ctrls; 94 struct v4l2_ctrl *testgen_mode; 95 const struct tpg_subdev_resources *res; 96 u32 hw_version; 97 }; 98 99 struct camss_subdev_resources; 100 101 const struct tpg_format_info *tpg_get_fmt_entry(const struct tpg_format_info *formats, 102 unsigned int nformats, 103 u32 code); 104 105 int msm_tpg_subdev_init(struct camss *camss, 106 struct tpg_device *tpg, 107 const struct camss_subdev_resources *res, u8 id); 108 109 int msm_tpg_register_entity(struct tpg_device *tpg, 110 struct v4l2_device *v4l2_dev); 111 112 void msm_tpg_unregister_entity(struct tpg_device *tpg); 113 114 extern const struct tpg_formats tpg_formats_gen1; 115 116 extern const struct tpg_hw_ops tpg_ops_gen1; 117 118 #endif /* QC_MSM_CAMSS_TPG_H */ 119