1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * 4 * Qualcomm MSM Camera Subsystem - TPG (Test Pattern Generator) Module 5 * 6 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 7 */ 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 11 #include "camss-tpg.h" 12 #include "camss.h" 13 14 /* TPG global registers */ 15 #define TPG_HW_VERSION 0x0 16 # define HW_VERSION_STEPPING GENMASK(15, 0) 17 # define HW_VERSION_REVISION GENMASK(27, 16) 18 # define HW_VERSION_GENERATION GENMASK(31, 28) 19 20 #define TPG_HW_VER(gen, rev, step) \ 21 (((u32)(gen) << 28) | ((u32)(rev) << 16) | (u32)(step)) 22 23 #define TPG_HW_VER_2_0_0 TPG_HW_VER(2, 0, 0) 24 #define TPG_HW_VER_2_1_0 TPG_HW_VER(2, 1, 0) 25 26 #define TPG_HW_STATUS 0x4 27 28 #define TPG_CTRL 0x64 29 # define TPG_CTRL_TEST_EN BIT(0) 30 # define TPG_CTRL_PHY_SEL BIT(3) 31 # define TPG_CTRL_NUM_ACTIVE_LANES GENMASK(5, 4) 32 # define TPG_CTRL_VC_DT_PATTERN_ID GENMASK(8, 6) 33 # define TPG_CTRL_OVERLAP_SHDR_EN BIT(10) 34 # define TPG_CTRL_NUM_ACTIVE_VC GENMASK(31, 30) 35 36 #define TPG_CLEAR 0x1F4 37 38 /* TPG VC-based registers */ 39 #define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) 40 41 #define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) 42 # define TPG_VC_n_CFG0_VC_NUM GENMASK(4, 0) 43 # define TPG_VC_n_CFG0_NUM_ACTIVE_DT GENMASK(9, 8) 44 # define TPG_VC_n_CFG0_NUM_BATCH GENMASK(15, 12) 45 # define TPG_VC_n_CFG0_NUM_FRAMES GENMASK(31, 16) 46 47 #define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) 48 #define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) 49 #define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) 50 51 #define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) 52 # define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN GENMASK(2, 0) 53 # define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN BIT(3) 54 # define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN BIT(4) 55 # define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN BIT(5) 56 # define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD GENMASK(13, 8) 57 # define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN BIT(16) 58 # define TPG_VC_n_COLOR_BARS_CFG_SIZE_X GENMASK(26, 24) 59 # define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y GENMASK(30, 28) 60 61 /* TPG DT-based registers */ 62 #define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) 63 # define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT GENMASK(15, 0) 64 # define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH GENMASK(31, 16) 65 66 #define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) 67 # define TPG_VC_m_DT_n_CFG_1_DATA_TYPE GENMASK(5, 0) 68 # define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK GENMASK(13, 8) 69 # define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK GENMASK(31, 16) 70 71 #define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) 72 # define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE GENMASK(3, 0) 73 /* v2.0.0: USER[19:4], ENC[23:20] */ 74 # define TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(19, 4) 75 # define TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(23, 20) 76 /* v2.1.0: USER[27:4], ENC[31:28] */ 77 # define TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD GENMASK(27, 4) 78 # define TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT GENMASK(31, 28) 79 80 #define TPG_HBI_PCT_DEFAULT 545 /* 545% */ 81 #define TPG_VBI_PCT_DEFAULT 10 /* 10% */ 82 #define PERCENT_BASE 100 83 84 /* Default user-specified payload for TPG test generator. 85 * Keep consistent with CSID TPG default: 0xBE. 86 */ 87 #define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE 88 #define TPG_LFSR_SEED_DEFAULT 0x12345678 89 #define TPG_COLOR_BARS_CFG_STANDARD \ 90 FIELD_PREP(TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD, 0xA) 91 92 static const char * const testgen_payload_modes[] = { 93 [TPG_PAYLOAD_MODE_DISABLED] = "Disabled", 94 [TPG_PAYLOAD_MODE_INCREMENTING] = "Incrementing", 95 [TPG_PAYLOAD_MODE_ALTERNATING_55_AA] = "Alternating 0x55/0xAA", 96 [TPG_PAYLOAD_MODE_RANDOM] = "Pseudo-random Data", 97 [TPG_PAYLOAD_MODE_USER_SPECIFIED] = "User Specified", 98 [TPG_PAYLOAD_MODE_COLOR_BARS] = "Color bars", 99 }; 100 101 static int tpg_stream_on(struct tpg_device *tpg) 102 { 103 struct tpg_testgen_config *tg = &tpg->testgen; 104 struct v4l2_mbus_framefmt *input_format; 105 const struct tpg_format_info *format; 106 u8 payload_mode = (tg->mode > TPG_PAYLOAD_MODE_DISABLED) ? 107 tg->mode - 1 : 0; 108 u8 lane_cnt = tpg->res->lane_cnt; 109 u8 vc, dt, last_vc = 0; 110 u32 val; 111 112 for (vc = 0; vc <= MSM_TPG_ACTIVE_VC; vc++) { 113 last_vc = vc; 114 115 input_format = &tpg->fmt; 116 format = tpg_get_fmt_entry(tpg->res->formats->formats, 117 tpg->res->formats->nformats, 118 input_format->code); 119 if (IS_ERR(format)) 120 return -EINVAL; 121 122 /* VC configuration */ 123 val = FIELD_PREP(TPG_VC_n_CFG0_NUM_ACTIVE_DT, MSM_TPG_ACTIVE_DT) | 124 FIELD_PREP(TPG_VC_n_CFG0_NUM_FRAMES, 0); 125 writel(val, tpg->base + TPG_VC_n_CFG0(vc)); 126 127 writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(vc)); 128 129 val = DIV_ROUND_UP(input_format->width * format->bpp * TPG_HBI_PCT_DEFAULT, 130 BITS_PER_BYTE * lane_cnt * PERCENT_BASE); 131 writel(val, tpg->base + TPG_VC_n_HBI_CFG(vc)); 132 133 val = input_format->height * TPG_VBI_PCT_DEFAULT / PERCENT_BASE; 134 writel(val, tpg->base + TPG_VC_n_VBI_CFG(vc)); 135 136 writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(vc)); 137 138 /* DT configuration */ 139 for (dt = 0; dt <= MSM_TPG_ACTIVE_DT; dt++) { 140 val = FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT, 141 input_format->height & 0xffff) | 142 FIELD_PREP(TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH, 143 input_format->width & 0xffff); 144 writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(vc, dt)); 145 146 val = FIELD_PREP(TPG_VC_m_DT_n_CFG_1_DATA_TYPE, format->data_type); 147 writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(vc, dt)); 148 149 if (tpg->hw_version == TPG_HW_VER_2_0_0) { 150 val = FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | 151 FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, 152 TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | 153 FIELD_PREP(TPG_V2_0_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, 154 format->encode_format); 155 } else if (tpg->hw_version >= TPG_HW_VER_2_1_0) { 156 val = FIELD_PREP(TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE, payload_mode) | 157 FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD, 158 TPG_USER_SPECIFIED_PAYLOAD_DEFAULT) | 159 FIELD_PREP(TPG_V2_1_0_VC_m_DT_n_CFG_2_ENCODE_FORMAT, 160 format->encode_format); 161 } 162 writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(vc, dt)); 163 } 164 } 165 166 /* Global TPG control */ 167 val = FIELD_PREP(TPG_CTRL_TEST_EN, 1) | 168 FIELD_PREP(TPG_CTRL_NUM_ACTIVE_LANES, lane_cnt - 1) | 169 FIELD_PREP(TPG_CTRL_NUM_ACTIVE_VC, last_vc); 170 writel(val, tpg->base + TPG_CTRL); 171 172 return 0; 173 } 174 175 static int tpg_reset(struct tpg_device *tpg) 176 { 177 writel(0, tpg->base + TPG_CTRL); 178 writel(1, tpg->base + TPG_CLEAR); 179 180 return 0; 181 } 182 183 static void tpg_stream_off(struct tpg_device *tpg) 184 { 185 tpg_reset(tpg); 186 } 187 188 static int tpg_configure_stream(struct tpg_device *tpg, u8 enable) 189 { 190 if (enable) 191 return tpg_stream_on(tpg); 192 193 tpg_stream_off(tpg); 194 195 return 0; 196 } 197 198 static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) 199 { 200 if (val >= 0 && val <= TPG_PAYLOAD_MODE_COLOR_BARS) 201 tpg->testgen.mode = val; 202 203 return 0; 204 } 205 206 static u32 tpg_hw_version(struct tpg_device *tpg) 207 { 208 u32 hw_version = readl(tpg->base + TPG_HW_VERSION); 209 210 tpg->hw_version = hw_version; 211 dev_dbg(tpg->camss->dev, "tpg HW Version = %u.%u.%u\n", 212 (u32)FIELD_GET(HW_VERSION_GENERATION, hw_version), 213 (u32)FIELD_GET(HW_VERSION_REVISION, hw_version), 214 (u32)FIELD_GET(HW_VERSION_STEPPING, hw_version)); 215 216 return hw_version; 217 } 218 219 static void tpg_subdev_init(struct tpg_device *tpg) 220 { 221 tpg->testgen.modes = testgen_payload_modes; 222 tpg->testgen.nmodes = TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; 223 } 224 225 const struct tpg_hw_ops tpg_ops_gen1 = { 226 .configure_stream = tpg_configure_stream, 227 .configure_testgen_pattern = tpg_configure_testgen_pattern, 228 .hw_version = tpg_hw_version, 229 .reset = tpg_reset, 230 .subdev_init = tpg_subdev_init, 231 }; 232