1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2026 Renesas Electronics Corp. 4 * Copyright (C) 2026 Ideas on Board Oy 5 * Copyright (C) 2026 Ragnatech AB 6 */ 7 8 #include "rpp_module.h" 9 10 #define DPCC_VERSION_REG 0x0000 11 12 #define DPCC_MODE_REG 0x0004 13 #define DPCC_MODE_STAGE1_ENABLE BIT(2) 14 #define DPCC_MODE_GRAYSCALE_MODE BIT(1) 15 #define DPCC_MODE_DPCC_ENABLE BIT(0) 16 17 #define DPCC_OUTPUT_MODE_REG 0x0008 18 #define DPCC_SET_USE_REG 0x000c 19 #define DPCC_METHODS_SET_1_REG 0x0010 20 #define DPCC_METHODS_SET_2_REG 0x0014 21 #define DPCC_METHODS_SET_3_REG 0x0018 22 #define DPCC_LINE_THRESH_1_REG 0x001c 23 #define DPCC_LINE_MAD_FAC_1_REG 0x0020 24 #define DPCC_PG_FAC_1_REG 0x0024 25 #define DPCC_RND_THRESH_1_REG 0x0028 26 #define DPCC_RG_FAC_1_REG 0x002c 27 #define DPCC_LINE_THRESH_2_REG 0x0030 28 #define DPCC_LINE_MAD_FAC_2_REG 0x0034 29 #define DPCC_PG_FAC_2_REG 0x0038 30 #define DPCC_RND_THRESH_2_REG 0x003c 31 #define DPCC_RG_FAC_2_REG 0x0040 32 #define DPCC_LINE_THRESH_3_REG 0x0044 33 #define DPCC_LINE_MAD_FAC_3_REG 0x0048 34 #define DPCC_PG_FAC_3_REG 0x004c 35 #define DPCC_RND_THRESH_3_REG 0x0050 36 #define DPCC_RG_FAC_3_REG 0x0054 37 #define DPCC_RO_LIMITS_REG 0x0058 38 #define DPCC_RND_OFFS_REG 0x005c 39 #define DPCC_BPT_CTRL_REG 0x0060 40 #define DPCC_BP_NUMBER_REG 0x0064 41 #define DPCC_BP_TADDR_REG 0x0068 42 #define DPCC_BP_POSITION_REG 0x006c 43 44 static int rppx1_dpcc_probe(struct rpp_module *mod) 45 { 46 /* Version check. */ 47 switch (rpp_module_read(mod, DPCC_VERSION_REG)) { 48 case 2: 49 case 4: 50 case 6: 51 /* 12-bit. */ 52 break; 53 case 3: 54 case 5: 55 case 7: 56 /* 24-bit. */ 57 break; 58 default: 59 return -EINVAL; 60 } 61 62 return 0; 63 } 64 65 static int rppx1_dpcc_start(struct rpp_module *mod, 66 const struct v4l2_mbus_framefmt *fmt) 67 { 68 /* Bypass stage1 and DPCC. */ 69 rpp_module_write(mod, DPCC_MODE_REG, 0); 70 71 return 0; 72 } 73 74 const struct rpp_module_ops rppx1_dpcc_ops = { 75 .probe = rppx1_dpcc_probe, 76 .start = rppx1_dpcc_start, 77 }; 78