1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2026 Renesas Electronics Corp. 4 * Copyright (C) 2026 Ideas on Board Oy 5 * Copyright (C) 2026 Ragnatech AB 6 */ 7 8 #include "rpp_module.h" 9 10 #define AWB_GAIN_VERSION_REG 0x0000 11 12 #define AWB_ENABLE_REG 0x0004 13 #define AWB_ENABLE_AWB_GAIN_EN BIT(0) 14 15 #define AWB_GAIN_GR_REG 0x0008 16 #define AWB_GAIN_GB_REG 0x000c 17 #define AWB_GAIN_R_REG 0x0010 18 #define AWB_GAIN_B_REG 0x0014 19 20 static int rppx1_awbg_probe(struct rpp_module *mod) 21 { 22 /* Version check. */ 23 if (rpp_module_read(mod, AWB_GAIN_VERSION_REG) != 3) 24 return -EINVAL; 25 26 return 0; 27 } 28 29 static int 30 rppx1_awbg_fill_params(struct rpp_module *mod, 31 const union rppx1_params_block *block, 32 rppx1_reg_write write, void *priv) 33 { 34 const struct rppx1_awbg_params *cfg = &block->awbg; 35 36 /* If the modules is disabled, simply bypass it. */ 37 if (cfg->header.flags & V4L2_ISP_PARAMS_FL_BLOCK_DISABLE) { 38 write(priv, mod->base + AWB_ENABLE_REG, 0); 39 return 0; 40 } 41 42 /* 43 * RPP gains are 18-bit with 12 bit fractional part and 0x1000 = 1.0, 44 * giving a possible range of 0.0 to 64.0. NOTE: RPP documentation is 45 * contradictory this is the register definition, the function 46 * description states 0x400 = 1.0 AND 18-bit with 12 fractional bits, 47 * which is not possible... 48 */ 49 50 write(priv, mod->base + AWB_GAIN_GR_REG, cfg->gain_green_r); 51 write(priv, mod->base + AWB_GAIN_GB_REG, cfg->gain_green_b); 52 write(priv, mod->base + AWB_GAIN_R_REG, cfg->gain_red); 53 write(priv, mod->base + AWB_GAIN_B_REG, cfg->gain_blue); 54 55 write(priv, mod->base + AWB_ENABLE_REG, AWB_ENABLE_AWB_GAIN_EN); 56 57 return 0; 58 } 59 60 const struct rpp_module_ops rppx1_awbg_ops = { 61 .probe = rppx1_awbg_probe, 62 .fill_params = rppx1_awbg_fill_params, 63 }; 64