1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * ARM Mali-C55 ISP Driver - Common definitions 4 * 5 * Copyright (C) 2025 Ideas on Board Oy 6 */ 7 8 #ifndef _MALI_C55_COMMON_H 9 #define _MALI_C55_COMMON_H 10 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/list.h> 14 #include <linux/mutex.h> 15 #include <linux/reset.h> 16 #include <linux/spinlock.h> 17 #include <linux/videodev2.h> 18 19 #include <media/media-device.h> 20 #include <media/v4l2-async.h> 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-dev.h> 23 #include <media/v4l2-device.h> 24 #include <media/v4l2-isp.h> 25 #include <media/v4l2-subdev.h> 26 #include <media/videobuf2-core.h> 27 #include <media/videobuf2-v4l2.h> 28 29 #define MALI_C55_DRIVER_NAME "mali-c55" 30 31 /* min and max values for the image sizes */ 32 #define MALI_C55_MIN_WIDTH 640U 33 #define MALI_C55_MIN_HEIGHT 480U 34 #define MALI_C55_MAX_WIDTH 8192U 35 #define MALI_C55_MAX_HEIGHT 8192U 36 #define MALI_C55_DEFAULT_WIDTH 1920U 37 #define MALI_C55_DEFAULT_HEIGHT 1080U 38 39 #define MALI_C55_DEFAULT_MEDIA_BUS_FMT MEDIA_BUS_FMT_RGB121212_1X36 40 41 #define MALI_C55_NUM_CLKS 3 42 #define MALI_C55_NUM_RESETS 3 43 44 struct device; 45 struct mali_c55; 46 struct mali_c55_cap_dev; 47 struct media_pipeline; 48 struct mali_c55_params_buffer; 49 struct platform_device; 50 struct resource; 51 52 enum mali_c55_isp_pads { 53 MALI_C55_ISP_PAD_SINK_VIDEO, 54 MALI_C55_ISP_PAD_SOURCE_VIDEO, 55 MALI_C55_ISP_PAD_SOURCE_BYPASS, 56 MALI_C55_ISP_PAD_SOURCE_STATS, 57 MALI_C55_ISP_PAD_SINK_PARAMS, 58 MALI_C55_ISP_NUM_PADS, 59 }; 60 61 struct mali_c55_tpg { 62 struct mali_c55 *mali_c55; 63 struct v4l2_subdev sd; 64 struct media_pad pad; 65 struct mali_c55_tpg_ctrls { 66 struct v4l2_ctrl_handler handler; 67 struct v4l2_ctrl *vblank; 68 } ctrls; 69 }; 70 71 struct mali_c55_isp { 72 struct mali_c55 *mali_c55; 73 struct v4l2_subdev sd; 74 struct media_pad pads[MALI_C55_ISP_NUM_PADS]; 75 struct v4l2_ctrl_handler handler; 76 struct media_pad *remote_src; 77 /* Mutex to guard vb2 start/stop streaming */ 78 struct mutex capture_lock; 79 unsigned int frame_sequence; 80 }; 81 82 enum mali_c55_resizer_ids { 83 MALI_C55_RSZ_FR, 84 MALI_C55_RSZ_DS, 85 MALI_C55_NUM_RSZS, 86 }; 87 88 enum mali_c55_rsz_pads { 89 MALI_C55_RSZ_SINK_PAD, 90 MALI_C55_RSZ_SOURCE_PAD, 91 MALI_C55_RSZ_SINK_BYPASS_PAD, 92 MALI_C55_RSZ_NUM_PADS 93 }; 94 95 struct mali_c55_resizer { 96 struct mali_c55 *mali_c55; 97 struct mali_c55_cap_dev *cap_dev; 98 enum mali_c55_resizer_ids id; 99 struct v4l2_subdev sd; 100 struct media_pad pads[MALI_C55_RSZ_NUM_PADS]; 101 unsigned int num_routes; 102 }; 103 104 enum mali_c55_cap_devs { 105 MALI_C55_CAP_DEV_FR, 106 MALI_C55_CAP_DEV_DS, 107 MALI_C55_NUM_CAP_DEVS 108 }; 109 110 struct mali_c55_format_info { 111 u32 fourcc; 112 /* 113 * The output formats can be produced by a couple of different media bus 114 * formats, depending on how the ISP is configured. 115 */ 116 unsigned int mbus_codes[2]; 117 bool is_raw; 118 struct { 119 u32 base_mode; 120 u32 uv_plane; 121 } registers; 122 }; 123 124 struct mali_c55_isp_format_info { 125 u32 code; 126 u32 shifted_code; 127 bool bypass; 128 u32 order; 129 }; 130 131 enum mali_c55_planes { 132 MALI_C55_PLANE_Y, 133 MALI_C55_PLANE_UV, 134 MALI_C55_NUM_PLANES 135 }; 136 137 struct mali_c55_buffer { 138 struct vb2_v4l2_buffer vb; 139 unsigned int planes_pending; 140 struct list_head queue; 141 dma_addr_t addrs[MALI_C55_NUM_PLANES]; 142 }; 143 144 struct mali_c55_cap_dev { 145 struct mali_c55 *mali_c55; 146 struct mali_c55_resizer *rsz; 147 struct video_device vdev; 148 struct media_pad pad; 149 struct vb2_queue queue; 150 /* Mutex to provide to vb2 */ 151 struct mutex lock; 152 unsigned int reg_offset; 153 154 struct { 155 const struct mali_c55_format_info *info; 156 struct v4l2_pix_format_mplane format; 157 } format; 158 159 struct { 160 /* Spinlock to guard buffer queue */ 161 spinlock_t lock; 162 /* Spinlock to guard the queue of buffers being processed */ 163 spinlock_t processing_lock; 164 struct list_head input; 165 struct list_head processing; 166 } buffers; 167 }; 168 169 struct mali_c55_stats_buf { 170 struct vb2_v4l2_buffer vb; 171 unsigned int segments_remaining; 172 struct list_head queue; 173 bool failed; 174 }; 175 176 struct mali_c55_params_buf { 177 struct vb2_v4l2_buffer vb; 178 struct list_head queue; 179 struct v4l2_isp_params_buffer *config; 180 }; 181 182 struct mali_c55_stats { 183 struct mali_c55 *mali_c55; 184 struct video_device vdev; 185 struct vb2_queue queue; 186 struct media_pad pad; 187 /* Mutex to provide to vb2 */ 188 struct mutex lock; 189 190 struct { 191 /* Spinlock to guard buffer queue */ 192 spinlock_t lock; 193 struct list_head queue; 194 } buffers; 195 }; 196 197 struct mali_c55_params { 198 struct mali_c55 *mali_c55; 199 struct video_device vdev; 200 struct vb2_queue queue; 201 struct media_pad pad; 202 /* Mutex to provide to vb2 */ 203 struct mutex lock; 204 205 struct { 206 /* Spinlock to guard buffer queue */ 207 spinlock_t lock; 208 struct list_head queue; 209 } buffers; 210 }; 211 212 enum mali_c55_config_spaces { 213 MALI_C55_CONFIG_PONG, 214 MALI_C55_CONFIG_PING, 215 }; 216 217 /** 218 * struct mali_c55_context - Fields relating to a single camera context 219 * 220 * @mali_c55: Pointer to the main struct mali_c55 221 * @registers: A pointer to some allocated memory holding register 222 * values to be written to the hardware at frame interrupt 223 * @base: Base address of the config space in the hardware 224 * @lock: A spinlock to protect against writes to @registers whilst that 225 * space is being copied to the hardware 226 * @list: A list head to facilitate a context queue 227 */ 228 struct mali_c55_context { 229 struct mali_c55 *mali_c55; 230 u32 *registers; 231 phys_addr_t base; 232 /* Spinlock to prevent simultaneous access of register space */ 233 spinlock_t lock; 234 struct list_head list; 235 }; 236 237 struct mali_c55 { 238 struct device *dev; 239 void __iomem *base; 240 struct clk_bulk_data clks[MALI_C55_NUM_CLKS]; 241 struct reset_control_bulk_data resets[MALI_C55_NUM_RESETS]; 242 int irqnum; 243 244 u16 capabilities; 245 bool inline_mode; 246 struct media_device media_dev; 247 struct v4l2_device v4l2_dev; 248 struct v4l2_async_notifier notifier; 249 struct media_pipeline pipe; 250 251 struct mali_c55_tpg tpg; 252 struct mali_c55_isp isp; 253 struct mali_c55_resizer resizers[MALI_C55_NUM_RSZS]; 254 struct mali_c55_cap_dev cap_devs[MALI_C55_NUM_CAP_DEVS]; 255 struct mali_c55_params params; 256 struct mali_c55_stats stats; 257 258 struct mali_c55_context context; 259 u32 next_config; 260 }; 261 262 void mali_c55_write(struct mali_c55 *mali_c55, unsigned int addr, u32 val); 263 void mali_c55_cap_dev_write(struct mali_c55_cap_dev *cap_dev, unsigned int addr, 264 u32 val); 265 void mali_c55_update_bits(struct mali_c55 *mali_c55, unsigned int addr, 266 u32 mask, u32 val); 267 u32 mali_c55_read(struct mali_c55 *mali_c55, unsigned int addr); 268 void mali_c55_ctx_write(struct mali_c55 *mali_c55, unsigned int addr, u32 val); 269 u32 mali_c55_ctx_read(struct mali_c55 *mali_c55, unsigned int addr); 270 void mali_c55_ctx_update_bits(struct mali_c55 *mali_c55, unsigned int addr, 271 u32 mask, u32 val); 272 273 int mali_c55_config_write(struct mali_c55_context *ctx, 274 enum mali_c55_config_spaces cfg_space, 275 bool force_synchronous); 276 277 int mali_c55_register_isp(struct mali_c55 *mali_c55); 278 int mali_c55_register_tpg(struct mali_c55 *mali_c55); 279 void mali_c55_unregister_tpg(struct mali_c55 *mali_c55); 280 void mali_c55_unregister_isp(struct mali_c55 *mali_c55); 281 int mali_c55_register_resizers(struct mali_c55 *mali_c55); 282 void mali_c55_unregister_resizers(struct mali_c55 *mali_c55); 283 int mali_c55_register_capture_devs(struct mali_c55 *mali_c55); 284 void mali_c55_unregister_capture_devs(struct mali_c55 *mali_c55); 285 int mali_c55_register_stats(struct mali_c55 *mali_c55); 286 void mali_c55_unregister_stats(struct mali_c55 *mali_c55); 287 int mali_c55_register_params(struct mali_c55 *mali_c55); 288 void mali_c55_unregister_params(struct mali_c55 *mali_c55); 289 struct mali_c55_context *mali_c55_get_active_context(struct mali_c55 *mali_c55); 290 void mali_c55_set_plane_done(struct mali_c55_cap_dev *cap_dev, 291 enum mali_c55_planes plane); 292 void mali_c55_set_next_buffer(struct mali_c55_cap_dev *cap_dev); 293 void mali_c55_isp_queue_event_sof(struct mali_c55 *mali_c55); 294 295 bool mali_c55_format_is_raw(unsigned int mbus_code); 296 297 const struct mali_c55_isp_format_info * 298 mali_c55_isp_fmt_next(const struct mali_c55_isp_format_info *fmt); 299 const struct mali_c55_isp_format_info * 300 mali_c55_isp_get_mbus_config_by_code(u32 code); 301 const struct mali_c55_isp_format_info * 302 mali_c55_isp_get_mbus_config_by_shifted_code(u32 code); 303 const struct mali_c55_isp_format_info * 304 mali_c55_isp_get_mbus_config_by_index(u32 index); 305 bool mali_c55_pipeline_ready(struct mali_c55 *mali_c55); 306 void mali_c55_stats_fill_buffer(struct mali_c55 *mali_c55, 307 enum mali_c55_config_spaces cfg_space); 308 void mali_c55_params_write_config(struct mali_c55 *mali_c55); 309 310 #endif /* _MALI_C55_COMMON_H */ 311