1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 /* 3 * Copyright (C) 2024 Amlogic, Inc. All rights reserved 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/device.h> 8 #include <linux/math.h> 9 #include <linux/module.h> 10 #include <linux/mutex.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 14 #include <media/v4l2-async.h> 15 #include <media/v4l2-common.h> 16 #include <media/v4l2-device.h> 17 #include <media/v4l2-fwnode.h> 18 #include <media/v4l2-mc.h> 19 #include <media/v4l2-subdev.h> 20 21 /* C3 CSI-2 submodule definition */ 22 enum { 23 SUBMD_APHY, 24 SUBMD_DPHY, 25 SUBMD_HOST, 26 }; 27 28 #define CSI2_SUBMD_MASK GENMASK(17, 16) 29 #define CSI2_SUBMD_SHIFT 16 30 #define CSI2_SUBMD(x) (((x) & (CSI2_SUBMD_MASK)) >> (CSI2_SUBMD_SHIFT)) 31 #define CSI2_REG_ADDR_MASK GENMASK(15, 0) 32 #define CSI2_REG_ADDR(x) ((x) & (CSI2_REG_ADDR_MASK)) 33 #define CSI2_REG_A(x) ((SUBMD_APHY << CSI2_SUBMD_SHIFT) | (x)) 34 #define CSI2_REG_D(x) ((SUBMD_DPHY << CSI2_SUBMD_SHIFT) | (x)) 35 #define CSI2_REG_H(x) ((SUBMD_HOST << CSI2_SUBMD_SHIFT) | (x)) 36 37 #define MIPI_CSI2_CLOCK_NUM_MAX 3 38 #define MIPI_CSI2_SUBDEV_NAME "c3-mipi-csi2" 39 40 /* C3 CSI-2 APHY register */ 41 #define CSI_PHY_CNTL0 CSI2_REG_A(0x44) 42 #define CSI_PHY_CNTL0_HS_LP_BIAS_EN BIT(10) 43 #define CSI_PHY_CNTL0_HS_RX_TRIM_11 (11 << 11) 44 #define CSI_PHY_CNTL0_LP_LOW_VTH_2 (2 << 16) 45 #define CSI_PHY_CNTL0_LP_HIGH_VTH_4 (4 << 20) 46 #define CSI_PHY_CNTL0_DATA_LANE0_HS_DIG_EN BIT(24) 47 #define CSI_PHY_CNTL0_DATA_LANE1_HS_DIG_EN BIT(25) 48 #define CSI_PHY_CNTL0_CLK0_LANE_HS_DIG_EN BIT(26) 49 #define CSI_PHY_CNTL0_DATA_LANE2_HS_DIG_EN BIT(27) 50 #define CSI_PHY_CNTL0_DATA_LANE3_HS_DIG_EN BIT(28) 51 52 #define CSI_PHY_CNTL1 CSI2_REG_A(0x48) 53 #define CSI_PHY_CNTL1_HS_EQ_CAP_SMALL (2 << 16) 54 #define CSI_PHY_CNTL1_HS_EQ_CAP_BIG (3 << 16) 55 #define CSI_PHY_CNTL1_HS_EQ_RES_MIN (3 << 18) 56 #define CSI_PHY_CNTL1_HS_EQ_RES_MED (2 << 18) 57 #define CSI_PHY_CNTL1_HS_EQ_RES_MAX BIT(18) 58 #define CSI_PHY_CNTL1_CLK_CHN_EQ_MAX_GAIN BIT(20) 59 #define CSI_PHY_CNTL1_DATA_CHN_EQ_MAX_GAIN BIT(21) 60 #define CSI_PHY_CNTL1_COM_BG_EN BIT(24) 61 #define CSI_PHY_CNTL1_HS_SYNC_EN BIT(25) 62 63 /* C3 CSI-2 DPHY register */ 64 #define MIPI_PHY_CTRL CSI2_REG_D(0x00) 65 #define MIPI_PHY_CTRL_DATA_LANE0_EN (0 << 0) 66 #define MIPI_PHY_CTRL_DATA_LANE0_DIS BIT(0) 67 #define MIPI_PHY_CTRL_DATA_LANE1_EN (0 << 1) 68 #define MIPI_PHY_CTRL_DATA_LANE1_DIS BIT(1) 69 #define MIPI_PHY_CTRL_DATA_LANE2_EN (0 << 2) 70 #define MIPI_PHY_CTRL_DATA_LANE2_DIS BIT(2) 71 #define MIPI_PHY_CTRL_DATA_LANE3_EN (0 << 3) 72 #define MIPI_PHY_CTRL_DATA_LANE3_DIS BIT(3) 73 #define MIPI_PHY_CTRL_CLOCK_LANE_EN (0 << 4) 74 #define MIPI_PHY_CTRL_CLOCK_LANE_DIS BIT(4) 75 76 #define MIPI_PHY_CLK_LANE_CTRL CSI2_REG_D(0x04) 77 #define MIPI_PHY_CLK_LANE_CTRL_FORCE_ULPS_ENTER BIT(0) 78 #define MIPI_PHY_CLK_LANE_CTRL_FORCE_ULPS_EXIT BIT(1) 79 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS (0 << 3) 80 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_2 BIT(3) 81 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_4 (2 << 3) 82 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_8 (3 << 3) 83 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_16 (4 << 3) 84 #define MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_EN BIT(6) 85 #define MIPI_PHY_CLK_LANE_CTRL_LPEN_DIS BIT(7) 86 #define MIPI_PHY_CLK_LANE_CTRL_END_EN BIT(8) 87 #define MIPI_PHY_CLK_LANE_CTRL_HS_RX_EN BIT(9) 88 89 #define MIPI_PHY_DATA_LANE_CTRL1 CSI2_REG_D(0x0c) 90 #define MIPI_PHY_DATA_LANE_CTRL1_INSERT_ERRESC BIT(0) 91 #define MIPI_PHY_DATA_LANE_CTRL1_HS_SYNC_CHK_EN BIT(1) 92 #define MIPI_PHY_DATA_LANE_CTRL1_PIPE_MASK GENMASK(6, 2) 93 #define MIPI_PHY_DATA_LANE_CTRL1_PIPE_ALL_EN (0x1f << 2) 94 #define MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_MASK GENMASK(9, 7) 95 #define MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_3 (3 << 7) 96 97 #define MIPI_PHY_TCLK_MISS CSI2_REG_D(0x10) 98 #define MIPI_PHY_TCLK_MISS_CYCLES_MASK GENMASK(7, 0) 99 #define MIPI_PHY_TCLK_MISS_CYCLES_9 (9 << 0) 100 101 #define MIPI_PHY_TCLK_SETTLE CSI2_REG_D(0x14) 102 #define MIPI_PHY_TCLK_SETTLE_CYCLES_MASK GENMASK(7, 0) 103 #define MIPI_PHY_TCLK_SETTLE_CYCLES_31 (31 << 0) 104 105 #define MIPI_PHY_THS_EXIT CSI2_REG_D(0x18) 106 #define MIPI_PHY_THS_EXIT_CYCLES_MASK GENMASK(7, 0) 107 #define MIPI_PHY_THS_EXIT_CYCLES_8 (8 << 0) 108 109 #define MIPI_PHY_THS_SKIP CSI2_REG_D(0x1c) 110 #define MIPI_PHY_THS_SKIP_CYCLES_MASK GENMASK(7, 0) 111 #define MIPI_PHY_THS_SKIP_CYCLES_10 (10 << 0) 112 113 #define MIPI_PHY_THS_SETTLE CSI2_REG_D(0x20) 114 #define MIPI_PHY_THS_SETTLE_CYCLES_MASK GENMASK(7, 0) 115 116 #define MIPI_PHY_TINIT CSI2_REG_D(0x24) 117 #define MIPI_PHY_TINIT_CYCLES_MASK GENMASK(31, 0) 118 #define MIPI_PHY_TINIT_CYCLES_20000 (20000 << 0) 119 120 #define MIPI_PHY_TULPS_C CSI2_REG_D(0x28) 121 #define MIPI_PHY_TULPS_C_CYCLES_MASK GENMASK(31, 0) 122 #define MIPI_PHY_TULPS_C_CYCLES_4096 (4096 << 0) 123 124 #define MIPI_PHY_TULPS_S CSI2_REG_D(0x2c) 125 #define MIPI_PHY_TULPS_S_CYCLES_MASK GENMASK(31, 0) 126 #define MIPI_PHY_TULPS_S_CYCLES_256 (256 << 0) 127 128 #define MIPI_PHY_TMBIAS CSI2_REG_D(0x30) 129 #define MIPI_PHY_TMBIAS_CYCLES_MASK GENMASK(31, 0) 130 #define MIPI_PHY_TMBIAS_CYCLES_256 (256 << 0) 131 132 #define MIPI_PHY_TLP_EN_W CSI2_REG_D(0x34) 133 #define MIPI_PHY_TLP_EN_W_CYCLES_MASK GENMASK(31, 0) 134 #define MIPI_PHY_TLP_EN_W_CYCLES_12 (12 << 0) 135 136 #define MIPI_PHY_TLPOK CSI2_REG_D(0x38) 137 #define MIPI_PHY_TLPOK_CYCLES_MASK GENMASK(31, 0) 138 #define MIPI_PHY_TLPOK_CYCLES_256 (256 << 0) 139 140 #define MIPI_PHY_TWD_INIT CSI2_REG_D(0x3c) 141 #define MIPI_PHY_TWD_INIT_DOG_MASK GENMASK(31, 0) 142 #define MIPI_PHY_TWD_INIT_DOG_0X400000 (0x400000 << 0) 143 144 #define MIPI_PHY_TWD_HS CSI2_REG_D(0x40) 145 #define MIPI_PHY_TWD_HS_DOG_MASK GENMASK(31, 0) 146 #define MIPI_PHY_TWD_HS_DOG_0X400000 (0x400000 << 0) 147 148 #define MIPI_PHY_MUX_CTRL0 CSI2_REG_D(0x284) 149 #define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_MASK GENMASK(3, 0) 150 #define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE0 (0 << 0) 151 #define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE1 BIT(0) 152 #define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE2 (2 << 0) 153 #define MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE3 (3 << 0) 154 #define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_MASK GENMASK(7, 4) 155 #define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE0 (0 << 4) 156 #define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE1 BIT(4) 157 #define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE2 (2 << 4) 158 #define MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE3 (3 << 4) 159 #define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_MASK GENMASK(11, 8) 160 #define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE0 (0 << 8) 161 #define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE1 BIT(8) 162 #define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE2 (2 << 8) 163 #define MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE3 (3 << 8) 164 #define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_MASK GENMASK(14, 12) 165 #define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE0 (0 << 12) 166 #define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE1 BIT(12) 167 #define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE2 (2 << 12) 168 #define MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE3 (3 << 12) 169 170 #define MIPI_PHY_MUX_CTRL1 CSI2_REG_D(0x288) 171 #define MIPI_PHY_MUX_CTRL1_LANE3_SRC_MASK GENMASK(3, 0) 172 #define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN0 (0 << 0) 173 #define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN1 BIT(0) 174 #define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN2 (2 << 0) 175 #define MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN3 (3 << 0) 176 #define MIPI_PHY_MUX_CTRL1_LANE2_SRC_MASK GENMASK(7, 4) 177 #define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN0 (0 << 4) 178 #define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN1 BIT(4) 179 #define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN2 (2 << 4) 180 #define MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN3 (3 << 4) 181 #define MIPI_PHY_MUX_CTRL1_LANE1_SRC_MASK GENMASK(11, 8) 182 #define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN0 (0 << 8) 183 #define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN1 BIT(8) 184 #define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN2 (2 << 8) 185 #define MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN3 (3 << 8) 186 #define MIPI_PHY_MUX_CTRL1_LANE0_SRC_MASK GENMASK(14, 12) 187 #define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN0 (0 << 12) 188 #define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN1 BIT(12) 189 #define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN2 (2 << 12) 190 #define MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN3 (3 << 12) 191 192 /* C3 CSI-2 HOST register */ 193 #define CSI2_HOST_N_LANES CSI2_REG_H(0x04) 194 #define CSI2_HOST_N_LANES_MASK GENMASK(1, 0) 195 #define CSI2_HOST_N_LANES_1 (0 << 0) 196 #define CSI2_HOST_N_LANES_2 BIT(0) 197 #define CSI2_HOST_N_LANES_3 (2 << 0) 198 #define CSI2_HOST_N_LANES_4 (3 << 0) 199 200 #define CSI2_HOST_CSI2_RESETN CSI2_REG_H(0x10) 201 #define CSI2_HOST_CSI2_RESETN_MASK BIT(0) 202 #define CSI2_HOST_CSI2_RESETN_ACTIVE (0 << 0) 203 #define CSI2_HOST_CSI2_RESETN_EXIT BIT(0) 204 205 #define C3_MIPI_CSI2_MAX_WIDTH 2888 206 #define C3_MIPI_CSI2_MIN_WIDTH 160 207 #define C3_MIPI_CSI2_MAX_HEIGHT 2240 208 #define C3_MIPI_CSI2_MIN_HEIGHT 120 209 #define C3_MIPI_CSI2_DEFAULT_WIDTH 1920 210 #define C3_MIPI_CSI2_DEFAULT_HEIGHT 1080 211 #define C3_MIPI_CSI2_DEFAULT_FMT MEDIA_BUS_FMT_SRGGB10_1X10 212 213 /* C3 CSI-2 pad list */ 214 enum { 215 C3_MIPI_CSI2_PAD_SINK, 216 C3_MIPI_CSI2_PAD_SRC, 217 C3_MIPI_CSI2_PAD_MAX 218 }; 219 220 /* 221 * struct c3_csi_info - MIPI CSI2 information 222 * 223 * @clocks: array of MIPI CSI2 clock names 224 * @clock_num: actual clock number 225 */ 226 struct c3_csi_info { 227 char *clocks[MIPI_CSI2_CLOCK_NUM_MAX]; 228 u32 clock_num; 229 }; 230 231 /* 232 * struct c3_csi_device - MIPI CSI2 platform device 233 * 234 * @dev: pointer to the struct device 235 * @aphy: MIPI CSI2 aphy register address 236 * @dphy: MIPI CSI2 dphy register address 237 * @host: MIPI CSI2 host register address 238 * @clks: array of MIPI CSI2 clocks 239 * @sd: MIPI CSI2 sub-device 240 * @pads: MIPI CSI2 sub-device pads 241 * @notifier: notifier to register on the v4l2-async API 242 * @src_pad: source sub-device pad 243 * @bus: MIPI CSI2 bus information 244 * @info: version-specific MIPI CSI2 information 245 */ 246 struct c3_csi_device { 247 struct device *dev; 248 void __iomem *aphy; 249 void __iomem *dphy; 250 void __iomem *host; 251 struct clk_bulk_data clks[MIPI_CSI2_CLOCK_NUM_MAX]; 252 253 struct v4l2_subdev sd; 254 struct media_pad pads[C3_MIPI_CSI2_PAD_MAX]; 255 struct v4l2_async_notifier notifier; 256 struct media_pad *src_pad; 257 struct v4l2_mbus_config_mipi_csi2 bus; 258 259 const struct c3_csi_info *info; 260 }; 261 262 static const u32 c3_mipi_csi_formats[] = { 263 MEDIA_BUS_FMT_SBGGR10_1X10, 264 MEDIA_BUS_FMT_SGBRG10_1X10, 265 MEDIA_BUS_FMT_SGRBG10_1X10, 266 MEDIA_BUS_FMT_SRGGB10_1X10, 267 MEDIA_BUS_FMT_SBGGR12_1X12, 268 MEDIA_BUS_FMT_SGBRG12_1X12, 269 MEDIA_BUS_FMT_SGRBG12_1X12, 270 MEDIA_BUS_FMT_SRGGB12_1X12, 271 }; 272 273 /* Hardware configuration */ 274 275 static void c3_mipi_csi_write(struct c3_csi_device *csi, u32 reg, u32 val) 276 { 277 void __iomem *addr; 278 279 switch (CSI2_SUBMD(reg)) { 280 case SUBMD_APHY: 281 addr = csi->aphy + CSI2_REG_ADDR(reg); 282 break; 283 case SUBMD_DPHY: 284 addr = csi->dphy + CSI2_REG_ADDR(reg); 285 break; 286 case SUBMD_HOST: 287 addr = csi->host + CSI2_REG_ADDR(reg); 288 break; 289 default: 290 dev_err(csi->dev, "Invalid sub-module: %lu\n", CSI2_SUBMD(reg)); 291 return; 292 } 293 294 writel(val, addr); 295 } 296 297 static void c3_mipi_csi_cfg_aphy(struct c3_csi_device *csi) 298 { 299 c3_mipi_csi_write(csi, CSI_PHY_CNTL0, 300 CSI_PHY_CNTL0_HS_LP_BIAS_EN | 301 CSI_PHY_CNTL0_HS_RX_TRIM_11 | 302 CSI_PHY_CNTL0_LP_LOW_VTH_2 | 303 CSI_PHY_CNTL0_LP_HIGH_VTH_4 | 304 CSI_PHY_CNTL0_DATA_LANE0_HS_DIG_EN | 305 CSI_PHY_CNTL0_DATA_LANE1_HS_DIG_EN | 306 CSI_PHY_CNTL0_CLK0_LANE_HS_DIG_EN | 307 CSI_PHY_CNTL0_DATA_LANE2_HS_DIG_EN | 308 CSI_PHY_CNTL0_DATA_LANE3_HS_DIG_EN); 309 310 c3_mipi_csi_write(csi, CSI_PHY_CNTL1, 311 CSI_PHY_CNTL1_HS_EQ_CAP_SMALL | 312 CSI_PHY_CNTL1_HS_EQ_RES_MED | 313 CSI_PHY_CNTL1_CLK_CHN_EQ_MAX_GAIN | 314 CSI_PHY_CNTL1_DATA_CHN_EQ_MAX_GAIN | 315 CSI_PHY_CNTL1_COM_BG_EN | 316 CSI_PHY_CNTL1_HS_SYNC_EN); 317 } 318 319 static void c3_mipi_csi_cfg_dphy(struct c3_csi_device *csi, s64 rate) 320 { 321 u32 val; 322 u32 settle; 323 324 /* Calculate the high speed settle */ 325 val = DIV_ROUND_UP_ULL(1000000000, rate); 326 settle = (16 * val + 230) / 10; 327 328 c3_mipi_csi_write(csi, MIPI_PHY_CLK_LANE_CTRL, 329 MIPI_PHY_CLK_LANE_CTRL_HS_RX_EN | 330 MIPI_PHY_CLK_LANE_CTRL_END_EN | 331 MIPI_PHY_CLK_LANE_CTRL_LPEN_DIS | 332 MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_EN | 333 MIPI_PHY_CLK_LANE_CTRL_TCLK_ZERO_HS_8); 334 335 c3_mipi_csi_write(csi, MIPI_PHY_TCLK_MISS, MIPI_PHY_TCLK_MISS_CYCLES_9); 336 c3_mipi_csi_write(csi, MIPI_PHY_TCLK_SETTLE, 337 MIPI_PHY_TCLK_SETTLE_CYCLES_31); 338 c3_mipi_csi_write(csi, MIPI_PHY_THS_EXIT, MIPI_PHY_THS_EXIT_CYCLES_8); 339 c3_mipi_csi_write(csi, MIPI_PHY_THS_SKIP, MIPI_PHY_THS_SKIP_CYCLES_10); 340 c3_mipi_csi_write(csi, MIPI_PHY_THS_SETTLE, settle); 341 c3_mipi_csi_write(csi, MIPI_PHY_TINIT, MIPI_PHY_TINIT_CYCLES_20000); 342 c3_mipi_csi_write(csi, MIPI_PHY_TMBIAS, MIPI_PHY_TMBIAS_CYCLES_256); 343 c3_mipi_csi_write(csi, MIPI_PHY_TULPS_C, MIPI_PHY_TULPS_C_CYCLES_4096); 344 c3_mipi_csi_write(csi, MIPI_PHY_TULPS_S, MIPI_PHY_TULPS_S_CYCLES_256); 345 c3_mipi_csi_write(csi, MIPI_PHY_TLP_EN_W, MIPI_PHY_TLP_EN_W_CYCLES_12); 346 c3_mipi_csi_write(csi, MIPI_PHY_TLPOK, MIPI_PHY_TLPOK_CYCLES_256); 347 c3_mipi_csi_write(csi, MIPI_PHY_TWD_INIT, 348 MIPI_PHY_TWD_INIT_DOG_0X400000); 349 c3_mipi_csi_write(csi, MIPI_PHY_TWD_HS, MIPI_PHY_TWD_HS_DOG_0X400000); 350 351 c3_mipi_csi_write(csi, MIPI_PHY_DATA_LANE_CTRL1, 352 MIPI_PHY_DATA_LANE_CTRL1_INSERT_ERRESC | 353 MIPI_PHY_DATA_LANE_CTRL1_HS_SYNC_CHK_EN | 354 MIPI_PHY_DATA_LANE_CTRL1_PIPE_ALL_EN | 355 MIPI_PHY_DATA_LANE_CTRL1_PIPE_DELAY_3); 356 357 /* Set the order of lanes */ 358 c3_mipi_csi_write(csi, MIPI_PHY_MUX_CTRL0, 359 MIPI_PHY_MUX_CTRL0_SFEN3_SRC_LANE3 | 360 MIPI_PHY_MUX_CTRL0_SFEN2_SRC_LANE2 | 361 MIPI_PHY_MUX_CTRL0_SFEN1_SRC_LANE1 | 362 MIPI_PHY_MUX_CTRL0_SFEN0_SRC_LANE0); 363 364 c3_mipi_csi_write(csi, MIPI_PHY_MUX_CTRL1, 365 MIPI_PHY_MUX_CTRL1_LANE3_SRC_SFEN3 | 366 MIPI_PHY_MUX_CTRL1_LANE2_SRC_SFEN2 | 367 MIPI_PHY_MUX_CTRL1_LANE1_SRC_SFEN1 | 368 MIPI_PHY_MUX_CTRL1_LANE0_SRC_SFEN0); 369 370 /* Enable digital data and clock lanes */ 371 c3_mipi_csi_write(csi, MIPI_PHY_CTRL, 372 MIPI_PHY_CTRL_DATA_LANE0_EN | 373 MIPI_PHY_CTRL_DATA_LANE1_EN | 374 MIPI_PHY_CTRL_DATA_LANE2_EN | 375 MIPI_PHY_CTRL_DATA_LANE3_EN | 376 MIPI_PHY_CTRL_CLOCK_LANE_EN); 377 } 378 379 static void c3_mipi_csi_cfg_host(struct c3_csi_device *csi) 380 { 381 /* Reset CSI-2 controller output */ 382 c3_mipi_csi_write(csi, CSI2_HOST_CSI2_RESETN, 383 CSI2_HOST_CSI2_RESETN_ACTIVE); 384 c3_mipi_csi_write(csi, CSI2_HOST_CSI2_RESETN, 385 CSI2_HOST_CSI2_RESETN_EXIT); 386 387 /* Set data lane number */ 388 c3_mipi_csi_write(csi, CSI2_HOST_N_LANES, csi->bus.num_data_lanes - 1); 389 } 390 391 static int c3_mipi_csi_start_stream(struct c3_csi_device *csi, 392 struct v4l2_subdev *src_sd) 393 { 394 s64 link_freq; 395 s64 lane_rate; 396 397 link_freq = v4l2_get_link_freq(src_sd->ctrl_handler, 0, 0); 398 if (link_freq < 0) { 399 dev_err(csi->dev, 400 "Unable to obtain link frequency: %lld\n", link_freq); 401 return link_freq; 402 } 403 404 lane_rate = link_freq * 2; 405 if (lane_rate > 1500000000) { 406 dev_err(csi->dev, "Invalid lane rate: %lld\n", lane_rate); 407 return -EINVAL; 408 } 409 410 c3_mipi_csi_cfg_aphy(csi); 411 c3_mipi_csi_cfg_dphy(csi, lane_rate); 412 c3_mipi_csi_cfg_host(csi); 413 414 return 0; 415 } 416 417 static int c3_mipi_csi_enable_streams(struct v4l2_subdev *sd, 418 struct v4l2_subdev_state *state, 419 u32 pad, u64 streams_mask) 420 { 421 struct c3_csi_device *csi = v4l2_get_subdevdata(sd); 422 struct media_pad *sink_pad; 423 struct v4l2_subdev *src_sd; 424 int ret; 425 426 sink_pad = &csi->pads[C3_MIPI_CSI2_PAD_SINK]; 427 csi->src_pad = media_pad_remote_pad_unique(sink_pad); 428 if (IS_ERR(csi->src_pad)) { 429 dev_dbg(csi->dev, "Failed to get source pad for MIPI CSI-2\n"); 430 return -EPIPE; 431 } 432 433 src_sd = media_entity_to_v4l2_subdev(csi->src_pad->entity); 434 435 pm_runtime_resume_and_get(csi->dev); 436 437 c3_mipi_csi_start_stream(csi, src_sd); 438 439 ret = v4l2_subdev_enable_streams(src_sd, csi->src_pad->index, BIT(0)); 440 if (ret) { 441 pm_runtime_put(csi->dev); 442 return ret; 443 } 444 445 return 0; 446 } 447 448 static int c3_mipi_csi_disable_streams(struct v4l2_subdev *sd, 449 struct v4l2_subdev_state *state, 450 u32 pad, u64 streams_mask) 451 { 452 struct c3_csi_device *csi = v4l2_get_subdevdata(sd); 453 struct v4l2_subdev *src_sd; 454 455 if (csi->src_pad) { 456 src_sd = media_entity_to_v4l2_subdev(csi->src_pad->entity); 457 v4l2_subdev_disable_streams(src_sd, csi->src_pad->index, 458 BIT(0)); 459 } 460 csi->src_pad = NULL; 461 462 pm_runtime_put(csi->dev); 463 464 return 0; 465 } 466 467 static int c3_mipi_csi_enum_mbus_code(struct v4l2_subdev *sd, 468 struct v4l2_subdev_state *state, 469 struct v4l2_subdev_mbus_code_enum *code) 470 { 471 struct v4l2_mbus_framefmt *fmt; 472 473 switch (code->pad) { 474 case C3_MIPI_CSI2_PAD_SINK: 475 if (code->index >= ARRAY_SIZE(c3_mipi_csi_formats)) 476 return -EINVAL; 477 478 code->code = c3_mipi_csi_formats[code->index]; 479 break; 480 case C3_MIPI_CSI2_PAD_SRC: 481 if (code->index) 482 return -EINVAL; 483 484 fmt = v4l2_subdev_state_get_format(state, code->pad); 485 code->code = fmt->code; 486 break; 487 default: 488 return -EINVAL; 489 } 490 491 return 0; 492 } 493 494 static int c3_mipi_csi_set_fmt(struct v4l2_subdev *sd, 495 struct v4l2_subdev_state *state, 496 struct v4l2_subdev_format *format) 497 { 498 struct v4l2_mbus_framefmt *fmt; 499 unsigned int i; 500 501 if (format->pad != C3_MIPI_CSI2_PAD_SINK) 502 return v4l2_subdev_get_fmt(sd, state, format); 503 504 fmt = v4l2_subdev_state_get_format(state, format->pad); 505 506 for (i = 0; i < ARRAY_SIZE(c3_mipi_csi_formats); i++) { 507 if (format->format.code == c3_mipi_csi_formats[i]) { 508 fmt->code = c3_mipi_csi_formats[i]; 509 break; 510 } 511 } 512 513 if (i == ARRAY_SIZE(c3_mipi_csi_formats)) 514 fmt->code = c3_mipi_csi_formats[0]; 515 516 fmt->width = clamp_t(u32, format->format.width, 517 C3_MIPI_CSI2_MIN_WIDTH, C3_MIPI_CSI2_MAX_WIDTH); 518 fmt->height = clamp_t(u32, format->format.height, 519 C3_MIPI_CSI2_MIN_HEIGHT, C3_MIPI_CSI2_MAX_HEIGHT); 520 fmt->colorspace = V4L2_COLORSPACE_RAW; 521 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 522 fmt->ycbcr_enc = V4L2_YCBCR_ENC_601; 523 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 524 525 format->format = *fmt; 526 527 /* Synchronize the format to source pad */ 528 fmt = v4l2_subdev_state_get_format(state, C3_MIPI_CSI2_PAD_SRC); 529 *fmt = format->format; 530 531 return 0; 532 } 533 534 static int c3_mipi_csi_init_state(struct v4l2_subdev *sd, 535 struct v4l2_subdev_state *state) 536 { 537 struct v4l2_mbus_framefmt *sink_fmt; 538 struct v4l2_mbus_framefmt *src_fmt; 539 540 sink_fmt = v4l2_subdev_state_get_format(state, C3_MIPI_CSI2_PAD_SINK); 541 src_fmt = v4l2_subdev_state_get_format(state, C3_MIPI_CSI2_PAD_SRC); 542 543 sink_fmt->width = C3_MIPI_CSI2_DEFAULT_WIDTH; 544 sink_fmt->height = C3_MIPI_CSI2_DEFAULT_HEIGHT; 545 sink_fmt->field = V4L2_FIELD_NONE; 546 sink_fmt->code = C3_MIPI_CSI2_DEFAULT_FMT; 547 sink_fmt->colorspace = V4L2_COLORSPACE_RAW; 548 sink_fmt->xfer_func = V4L2_XFER_FUNC_NONE; 549 sink_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601; 550 sink_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 551 552 *src_fmt = *sink_fmt; 553 554 return 0; 555 } 556 557 static const struct v4l2_subdev_pad_ops c3_mipi_csi_pad_ops = { 558 .enum_mbus_code = c3_mipi_csi_enum_mbus_code, 559 .get_fmt = v4l2_subdev_get_fmt, 560 .set_fmt = c3_mipi_csi_set_fmt, 561 .enable_streams = c3_mipi_csi_enable_streams, 562 .disable_streams = c3_mipi_csi_disable_streams, 563 }; 564 565 static const struct v4l2_subdev_ops c3_mipi_csi_subdev_ops = { 566 .pad = &c3_mipi_csi_pad_ops, 567 }; 568 569 static const struct v4l2_subdev_internal_ops c3_mipi_csi_internal_ops = { 570 .init_state = c3_mipi_csi_init_state, 571 }; 572 573 /* Media entity operations */ 574 static const struct media_entity_operations c3_mipi_csi_entity_ops = { 575 .link_validate = v4l2_subdev_link_validate, 576 }; 577 578 /* PM runtime */ 579 580 static int c3_mipi_csi_runtime_suspend(struct device *dev) 581 { 582 struct c3_csi_device *csi = dev_get_drvdata(dev); 583 584 clk_bulk_disable_unprepare(csi->info->clock_num, csi->clks); 585 586 return 0; 587 } 588 589 static int c3_mipi_csi_runtime_resume(struct device *dev) 590 { 591 struct c3_csi_device *csi = dev_get_drvdata(dev); 592 593 return clk_bulk_prepare_enable(csi->info->clock_num, csi->clks); 594 } 595 596 static const struct dev_pm_ops c3_mipi_csi_pm_ops = { 597 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 598 pm_runtime_force_resume) 599 RUNTIME_PM_OPS(c3_mipi_csi_runtime_suspend, 600 c3_mipi_csi_runtime_resume, NULL) 601 }; 602 603 /* Probe/remove & platform driver */ 604 605 static int c3_mipi_csi_subdev_init(struct c3_csi_device *csi) 606 { 607 struct v4l2_subdev *sd = &csi->sd; 608 int ret; 609 610 v4l2_subdev_init(sd, &c3_mipi_csi_subdev_ops); 611 sd->owner = THIS_MODULE; 612 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 613 sd->internal_ops = &c3_mipi_csi_internal_ops; 614 snprintf(sd->name, sizeof(sd->name), "%s", MIPI_CSI2_SUBDEV_NAME); 615 616 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 617 sd->entity.ops = &c3_mipi_csi_entity_ops; 618 619 sd->dev = csi->dev; 620 v4l2_set_subdevdata(sd, csi); 621 622 csi->pads[C3_MIPI_CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 623 csi->pads[C3_MIPI_CSI2_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 624 ret = media_entity_pads_init(&sd->entity, C3_MIPI_CSI2_PAD_MAX, 625 csi->pads); 626 if (ret) 627 return ret; 628 629 ret = v4l2_subdev_init_finalize(sd); 630 if (ret) { 631 media_entity_cleanup(&sd->entity); 632 return ret; 633 } 634 635 return 0; 636 } 637 638 static void c3_mipi_csi_subdev_deinit(struct c3_csi_device *csi) 639 { 640 v4l2_subdev_cleanup(&csi->sd); 641 media_entity_cleanup(&csi->sd.entity); 642 } 643 644 /* Subdev notifier register */ 645 static int c3_mipi_csi_notify_bound(struct v4l2_async_notifier *notifier, 646 struct v4l2_subdev *sd, 647 struct v4l2_async_connection *asc) 648 { 649 struct c3_csi_device *csi = v4l2_get_subdevdata(notifier->sd); 650 struct media_pad *sink = &csi->sd.entity.pads[C3_MIPI_CSI2_PAD_SINK]; 651 652 return v4l2_create_fwnode_links_to_pad(sd, sink, MEDIA_LNK_FL_ENABLED | 653 MEDIA_LNK_FL_IMMUTABLE); 654 } 655 656 static const struct v4l2_async_notifier_operations c3_mipi_csi_notify_ops = { 657 .bound = c3_mipi_csi_notify_bound, 658 }; 659 660 static int c3_mipi_csi_async_register(struct c3_csi_device *csi) 661 { 662 struct v4l2_fwnode_endpoint vep = { 663 .bus_type = V4L2_MBUS_CSI2_DPHY, 664 }; 665 struct v4l2_async_connection *asc; 666 struct fwnode_handle *ep; 667 int ret; 668 669 v4l2_async_subdev_nf_init(&csi->notifier, &csi->sd); 670 671 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0, 672 FWNODE_GRAPH_ENDPOINT_NEXT); 673 if (!ep) 674 return -ENOTCONN; 675 676 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 677 if (ret) 678 goto err_put_handle; 679 680 csi->bus = vep.bus.mipi_csi2; 681 682 asc = v4l2_async_nf_add_fwnode_remote(&csi->notifier, ep, 683 struct v4l2_async_connection); 684 if (IS_ERR(asc)) { 685 ret = PTR_ERR(asc); 686 goto err_put_handle; 687 } 688 689 csi->notifier.ops = &c3_mipi_csi_notify_ops; 690 ret = v4l2_async_nf_register(&csi->notifier); 691 if (ret) 692 goto err_cleanup_nf; 693 694 ret = v4l2_async_register_subdev(&csi->sd); 695 if (ret) 696 goto err_unregister_nf; 697 698 fwnode_handle_put(ep); 699 700 return 0; 701 702 err_unregister_nf: 703 v4l2_async_nf_unregister(&csi->notifier); 704 err_cleanup_nf: 705 v4l2_async_nf_cleanup(&csi->notifier); 706 err_put_handle: 707 fwnode_handle_put(ep); 708 return ret; 709 } 710 711 static void c3_mipi_csi_async_unregister(struct c3_csi_device *csi) 712 { 713 v4l2_async_unregister_subdev(&csi->sd); 714 v4l2_async_nf_unregister(&csi->notifier); 715 v4l2_async_nf_cleanup(&csi->notifier); 716 } 717 718 static int c3_mipi_csi_ioremap_resource(struct c3_csi_device *csi) 719 { 720 struct device *dev = csi->dev; 721 struct platform_device *pdev = to_platform_device(dev); 722 723 csi->aphy = devm_platform_ioremap_resource_byname(pdev, "aphy"); 724 if (IS_ERR(csi->aphy)) 725 return PTR_ERR(csi->aphy); 726 727 csi->dphy = devm_platform_ioremap_resource_byname(pdev, "dphy"); 728 if (IS_ERR(csi->dphy)) 729 return PTR_ERR(csi->dphy); 730 731 csi->host = devm_platform_ioremap_resource_byname(pdev, "host"); 732 if (IS_ERR(csi->host)) 733 return PTR_ERR(csi->host); 734 735 return 0; 736 } 737 738 static int c3_mipi_csi_get_clocks(struct c3_csi_device *csi) 739 { 740 const struct c3_csi_info *info = csi->info; 741 742 for (unsigned int i = 0; i < info->clock_num; i++) 743 csi->clks[i].id = info->clocks[i]; 744 745 return devm_clk_bulk_get(csi->dev, info->clock_num, csi->clks); 746 } 747 748 static int c3_mipi_csi_probe(struct platform_device *pdev) 749 { 750 struct device *dev = &pdev->dev; 751 struct c3_csi_device *csi; 752 int ret; 753 754 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL); 755 if (!csi) 756 return -ENOMEM; 757 758 csi->info = of_device_get_match_data(dev); 759 csi->dev = dev; 760 761 ret = c3_mipi_csi_ioremap_resource(csi); 762 if (ret) 763 return dev_err_probe(dev, ret, "Failed to ioremap resource\n"); 764 765 ret = c3_mipi_csi_get_clocks(csi); 766 if (ret) 767 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 768 769 platform_set_drvdata(pdev, csi); 770 771 pm_runtime_enable(dev); 772 773 ret = c3_mipi_csi_subdev_init(csi); 774 if (ret) 775 goto err_disable_runtime_pm; 776 777 ret = c3_mipi_csi_async_register(csi); 778 if (ret) 779 goto err_deinit_subdev; 780 781 return 0; 782 783 err_deinit_subdev: 784 c3_mipi_csi_subdev_deinit(csi); 785 err_disable_runtime_pm: 786 pm_runtime_disable(dev); 787 return ret; 788 }; 789 790 static void c3_mipi_csi_remove(struct platform_device *pdev) 791 { 792 struct c3_csi_device *csi = platform_get_drvdata(pdev); 793 794 c3_mipi_csi_async_unregister(csi); 795 c3_mipi_csi_subdev_deinit(csi); 796 797 pm_runtime_disable(&pdev->dev); 798 }; 799 800 static const struct c3_csi_info c3_mipi_csi_info = { 801 .clocks = {"vapb", "phy0"}, 802 .clock_num = 2 803 }; 804 805 static const struct of_device_id c3_mipi_csi_of_match[] = { 806 { 807 .compatible = "amlogic,c3-mipi-csi2", 808 .data = &c3_mipi_csi_info, 809 }, 810 { }, 811 }; 812 MODULE_DEVICE_TABLE(of, c3_mipi_csi_of_match); 813 814 static struct platform_driver c3_mipi_csi_driver = { 815 .probe = c3_mipi_csi_probe, 816 .remove = c3_mipi_csi_remove, 817 .driver = { 818 .name = "c3-mipi-csi2", 819 .of_match_table = c3_mipi_csi_of_match, 820 .pm = pm_ptr(&c3_mipi_csi_pm_ops), 821 }, 822 }; 823 824 module_platform_driver(c3_mipi_csi_driver); 825 826 MODULE_AUTHOR("Keke Li <keke.li@amlogic.com>"); 827 MODULE_DESCRIPTION("Amlogic C3 MIPI CSI-2 receiver"); 828 MODULE_LICENSE("GPL"); 829