1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef _HWS_PCIE_REG_H 3 #define _HWS_PCIE_REG_H 4 5 #include <linux/bits.h> 6 #include <linux/sizes.h> 7 8 #define XDMA_CHANNEL_NUM_MAX (1) 9 #define MAX_NUM_ENGINES (XDMA_CHANNEL_NUM_MAX * 2) 10 11 #define PCIE_BARADDROFSIZE 4u 12 13 #define PCI_BUS_ACCESS_BASE 0x00000000U 14 #define INT_EN_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0134U) 15 #define PCIEBR_EN_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0148U) 16 #define PCIE_INT_DEC_REG_BASE (PCI_BUS_ACCESS_BASE + 0x0138U) 17 18 #define HWS_INT_EN_MASK 0x0003FFFFU 19 20 #define PCIEBAR_AXI_BASE 0x20000000U 21 22 #define CTL_REG_ACC_BASE 0x0 23 #define PCI_ADDR_TABLE_BASE CTL_REG_ACC_BASE 24 25 #define CVBS_IN_BASE 0x00004000U 26 #define CVBS_IN_BUF_BASE (CVBS_IN_BASE + (16U * PCIE_BARADDROFSIZE)) 27 #define CVBS_IN_BUF_BASE2 (CVBS_IN_BASE + (50U * PCIE_BARADDROFSIZE)) 28 29 /* 2 Mib */ 30 #define MAX_L_VIDEO_SIZE 0x200000U 31 32 #define PCI_E_BAR_PAGE_SIZE 0x20000000 33 #define PCI_E_BAR_ADD_MASK 0xE0000000 34 #define PCI_E_BAR_ADD_LOWMASK 0x1FFFFFFF 35 36 #define MAX_VID_CHANNELS 4 37 38 #define MAX_MM_VIDEO_SIZE SZ_4M 39 40 #define MAX_VIDEO_HW_W 1920 41 #define MAX_VIDEO_HW_H 1080 42 #define MAX_VIDEO_SCALER_SIZE (1920U * 1080U * 2U) 43 44 #define MIN_VAMP_BRIGHTNESS_UNITS 0 45 #define MAX_VAMP_BRIGHTNESS_UNITS 0xff 46 47 #define MIN_VAMP_CONTRAST_UNITS 0 48 #define MAX_VAMP_CONTRAST_UNITS 0xff 49 50 #define MIN_VAMP_SATURATION_UNITS 0 51 #define MAX_VAMP_SATURATION_UNITS 0xff 52 53 #define MIN_VAMP_HUE_UNITS 0 54 #define MAX_VAMP_HUE_UNITS 0xff 55 56 #define HWS_BRIGHTNESS_DEFAULT 0x80 57 #define HWS_CONTRAST_DEFAULT 0x80 58 #define HWS_SATURATION_DEFAULT 0x80 59 #define HWS_HUE_DEFAULT 0x00 60 61 /* Core/global status. */ 62 #define HWS_REG_SYS_STATUS (CVBS_IN_BASE + 0 * PCIE_BARADDROFSIZE) 63 /* bit3: DMA busy, bit2: int, ... */ 64 65 #define HWS_SYS_DMA_BUSY_BIT BIT(3) /* 0x08 = DMA busy flag */ 66 67 #define HWS_REG_DEC_MODE (CVBS_IN_BASE + 0 * PCIE_BARADDROFSIZE) 68 /* Main control register */ 69 #define HWS_REG_CTL (CVBS_IN_BASE + 4 * PCIE_BARADDROFSIZE) 70 #define HWS_CTL_IRQ_ENABLE_BIT BIT(0) /* Global interrupt enable bit */ 71 /* Write 0x00 to fully reset decoder, 72 * set bit 31=1 to "start run", 73 * low byte=0x13 selects YUYV/BT.709/etc, 74 * in ReadChipId() we also write 0x00 and 0x10 here for chip-ID sequencing. 75 */ 76 77 /* Per-channel done flags. */ 78 #define HWS_REG_INT_STATUS (CVBS_IN_BASE + 1 * PCIE_BARADDROFSIZE) 79 #define HWS_SYS_BUSY_BIT BIT(2) /* matches old 0x04 test */ 80 81 /* Capture enable switches. */ 82 /* bit0-3: CH0-CH3 video enable */ 83 #define HWS_REG_VCAP_ENABLE (CVBS_IN_BASE + 2 * PCIE_BARADDROFSIZE) 84 /* bits0-3: signal present, bits8-11: interlace */ 85 #define HWS_REG_ACTIVE_STATUS (CVBS_IN_BASE + 5 * PCIE_BARADDROFSIZE) 86 /* bits0-3: HDCP detected */ 87 #define HWS_REG_HDCP_STATUS (CVBS_IN_BASE + 8 * PCIE_BARADDROFSIZE) 88 #define HWS_REG_DMA_MAX_SIZE (CVBS_IN_BASE + 9 * PCIE_BARADDROFSIZE) 89 90 /* Buffer addresses (written once during init/reset). */ 91 /* Base of host-visible buffer. */ 92 #define HWS_REG_VBUF1_ADDR (CVBS_IN_BASE + 25 * PCIE_BARADDROFSIZE) 93 /* Per-channel DMA address. */ 94 #define HWS_REG_DMA_ADDR(ch) (CVBS_IN_BASE + (26 + (ch)) * PCIE_BARADDROFSIZE) 95 96 /* Per-channel live buffer toggles (read-only). */ 97 #define HWS_REG_VBUF_TOGGLE(ch) (CVBS_IN_BASE + (32 + (ch)) * PCIE_BARADDROFSIZE) 98 /* 99 * Returns 0 or 1 = which half of the video ring the DMA engine is 100 * currently filling for channel *ch* (0-3). 101 */ 102 103 /* Per-interrupt bits (video 0-3). */ 104 #define HWS_INT_VDONE_BIT(ch) BIT(ch) /* 0x01,0x02,0x04,0x08 */ 105 106 #define HWS_REG_INT_ACK (CVBS_IN_BASE + 0x4000 + 1 * PCIE_BARADDROFSIZE) 107 108 /* 16-bit W | 16-bit H. */ 109 #define HWS_REG_IN_RES(ch) (CVBS_IN_BASE + (90 + (ch) * 2) * PCIE_BARADDROFSIZE) 110 /* B|C|H|S packed bytes. */ 111 #define HWS_REG_BCHS(ch) (CVBS_IN_BASE + (91 + (ch) * 2) * PCIE_BARADDROFSIZE) 112 113 /* Input fps. */ 114 #define HWS_REG_FRAME_RATE(ch) (CVBS_IN_BASE + (110 + (ch)) * PCIE_BARADDROFSIZE) 115 /* Programmed out W|H. */ 116 #define HWS_REG_OUT_RES(ch) (CVBS_IN_BASE + (120 + (ch)) * PCIE_BARADDROFSIZE) 117 /* Programmed out fps. */ 118 #define HWS_REG_OUT_FRAME_RATE(ch) (CVBS_IN_BASE + (130 + (ch)) * PCIE_BARADDROFSIZE) 119 120 /* Device version/port ID/subversion register. */ 121 #define HWS_REG_DEVICE_INFO (CVBS_IN_BASE + 88 * PCIE_BARADDROFSIZE) 122 /* 123 * Reading this 32-bit word returns: 124 * bits 7:0 = "device version" 125 * bits 15:8 = "device sub-version" 126 * bits 23:24 = "HW key / port ID" etc. 127 * bits 31:28 = "support YV12" flags 128 */ 129 130 /* Convenience aliases for individual channels. */ 131 #define HWS_REG_VBUF_TOGGLE_CH0 HWS_REG_VBUF_TOGGLE(0) 132 #define HWS_REG_VBUF_TOGGLE_CH1 HWS_REG_VBUF_TOGGLE(1) 133 #define HWS_REG_VBUF_TOGGLE_CH2 HWS_REG_VBUF_TOGGLE(2) 134 #define HWS_REG_VBUF_TOGGLE_CH3 HWS_REG_VBUF_TOGGLE(3) 135 136 #endif /* _HWS_PCIE_REG_H */ 137