1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2025 Linaro Ltd 3 4 #include <linux/clk.h> 5 #include <linux/delay.h> 6 #include <linux/gpio/consumer.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/pm_runtime.h> 10 #include <linux/regulator/consumer.h> 11 #include <linux/units.h> 12 #include <media/v4l2-cci.h> 13 #include <media/v4l2-ctrls.h> 14 #include <media/v4l2-device.h> 15 #include <media/v4l2-fwnode.h> 16 17 #define S5KJN1_LINK_FREQ_700MHZ (700ULL * HZ_PER_MHZ) 18 #define S5KJN1_MCLK_FREQ_24MHZ (24 * HZ_PER_MHZ) 19 #define S5KJN1_DATA_LANES 4 20 21 /* Register map is similar to MIPI CCS compliant camera sensors */ 22 #define S5KJN1_REG_CHIP_ID CCI_REG16(0x0000) 23 #define S5KJN1_CHIP_ID 0x38e1 24 25 #define S5KJN1_REG_CTRL_MODE CCI_REG8(0x0100) 26 #define S5KJN1_MODE_STREAMING BIT(0) 27 28 #define S5KJN1_REG_ORIENTATION CCI_REG8(0x0101) 29 #define S5KJN1_VFLIP BIT(1) 30 #define S5KJN1_HFLIP BIT(0) 31 32 #define S5KJN1_REG_EXPOSURE CCI_REG16(0x0202) 33 #define S5KJN1_EXPOSURE_MIN 8 34 #define S5KJN1_EXPOSURE_STEP 1 35 36 #define S5KJN1_REG_AGAIN CCI_REG16(0x0204) 37 #define S5KJN1_AGAIN_MIN 1 38 #define S5KJN1_AGAIN_MAX 64 39 #define S5KJN1_AGAIN_STEP 1 40 #define S5KJN1_AGAIN_DEFAULT 6 41 #define S5KJN1_AGAIN_SHIFT 5 42 43 #define S5KJN1_REG_VTS CCI_REG16(0x0340) 44 #define S5KJN1_VTS_MAX 0xffff 45 46 #define S5KJN1_REG_HTS CCI_REG16(0x0342) 47 #define S5KJN1_REG_X_ADDR_START CCI_REG16(0x0344) 48 #define S5KJN1_REG_Y_ADDR_START CCI_REG16(0x0346) 49 #define S5KJN1_REG_X_ADDR_END CCI_REG16(0x0348) 50 #define S5KJN1_REG_Y_ADDR_END CCI_REG16(0x034a) 51 #define S5KJN1_REG_X_OUTPUT_SIZE CCI_REG16(0x034c) 52 #define S5KJN1_REG_Y_OUTPUT_SIZE CCI_REG16(0x034e) 53 54 #define S5KJN1_REG_TEST_PATTERN CCI_REG16(0x0600) 55 56 #define to_s5kjn1(_sd) container_of(_sd, struct s5kjn1, sd) 57 58 static const s64 s5kjn1_link_freq_menu[] = { 59 S5KJN1_LINK_FREQ_700MHZ, 60 }; 61 62 /* List of supported formats to cover horizontal and vertical flip controls */ 63 static const u32 s5kjn1_mbus_formats[] = { 64 MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10, 65 MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10, 66 }; 67 68 struct s5kjn1_reg_list { 69 const struct cci_reg_sequence *regs; 70 unsigned int num_regs; 71 }; 72 73 struct s5kjn1_mode { 74 u32 width; /* Frame width in pixels */ 75 u32 height; /* Frame height in pixels */ 76 u32 hts; /* Horizontal timing size */ 77 u32 vts; /* Default vertical timing size */ 78 u32 exposure; /* Default exposure value */ 79 u32 exposure_margin; /* Exposure margin */ 80 81 const struct s5kjn1_reg_list reg_list; /* Sensor register setting */ 82 }; 83 84 static const char * const s5kjn1_test_pattern_menu[] = { 85 "Disabled", 86 "Solid color", 87 "Color bars", 88 "Fade to grey color bars", 89 "PN9", 90 }; 91 92 struct s5kjn1 { 93 struct device *dev; 94 struct regmap *regmap; 95 struct clk *mclk; 96 struct gpio_desc *reset_gpio; 97 struct regulator *afvdd; /* Autofocus actuator power */ 98 struct regulator *vdda; /* Analog power */ 99 struct regulator *vddd; /* Digital core power */ 100 struct regulator *vddio; /* Digital I/O power */ 101 102 struct v4l2_subdev sd; 103 struct media_pad pad; 104 105 struct v4l2_ctrl_handler ctrl_handler; 106 struct v4l2_ctrl *link_freq; 107 struct v4l2_ctrl *pixel_rate; 108 struct v4l2_ctrl *hblank; 109 struct v4l2_ctrl *vblank; 110 struct v4l2_ctrl *exposure; 111 struct v4l2_ctrl *vflip; 112 struct v4l2_ctrl *hflip; 113 114 const struct s5kjn1_mode *mode; 115 }; 116 117 static const struct cci_reg_sequence init_array_setting[] = { 118 { CCI_REG16(0x6028), 0x2400 }, 119 { CCI_REG16(0x602a), 0x1354 }, 120 { CCI_REG16(0x6f12), 0x0100 }, 121 { CCI_REG16(0x6f12), 0x7017 }, 122 { CCI_REG16(0x602a), 0x13b2 }, 123 { CCI_REG16(0x6f12), 0x0000 }, 124 { CCI_REG16(0x602a), 0x1236 }, 125 { CCI_REG16(0x6f12), 0x0000 }, 126 { CCI_REG16(0x602a), 0x1a0a }, 127 { CCI_REG16(0x6f12), 0x4c0a }, 128 { CCI_REG16(0x602a), 0x2210 }, 129 { CCI_REG16(0x6f12), 0x3401 }, 130 { CCI_REG16(0x602a), 0x2176 }, 131 { CCI_REG16(0x6f12), 0x6400 }, 132 { CCI_REG16(0x602a), 0x222e }, 133 { CCI_REG16(0x6f12), 0x0001 }, 134 { CCI_REG16(0x602a), 0x06b6 }, 135 { CCI_REG16(0x6f12), 0x0a00 }, 136 { CCI_REG16(0x602a), 0x06bc }, 137 { CCI_REG16(0x6f12), 0x1001 }, 138 { CCI_REG16(0x602a), 0x2140 }, 139 { CCI_REG16(0x6f12), 0x0101 }, 140 { CCI_REG16(0x602a), 0x1a0e }, 141 { CCI_REG16(0x6f12), 0x9600 }, 142 { CCI_REG16(0x6028), 0x4000 }, 143 { CCI_REG16(0xf44e), 0x0011 }, 144 { CCI_REG16(0xf44c), 0x0b0b }, 145 { CCI_REG16(0xf44a), 0x0006 }, 146 { CCI_REG16(0x0118), 0x0002 }, 147 { CCI_REG16(0x011a), 0x0001 }, 148 }; 149 150 static const struct cci_reg_sequence s5kjn1_4080x3072_30fps_mode[] = { 151 { CCI_REG16(0x6028), 0x2400 }, 152 { CCI_REG16(0x602a), 0x1a28 }, 153 { CCI_REG16(0x6f12), 0x4c00 }, 154 { CCI_REG16(0x602a), 0x065a }, 155 { CCI_REG16(0x6f12), 0x0000 }, 156 { CCI_REG16(0x602a), 0x139e }, 157 { CCI_REG16(0x6f12), 0x0100 }, 158 { CCI_REG16(0x602a), 0x139c }, 159 { CCI_REG16(0x6f12), 0x0000 }, 160 { CCI_REG16(0x602a), 0x13a0 }, 161 { CCI_REG16(0x6f12), 0x0a00 }, 162 { CCI_REG16(0x6f12), 0x0120 }, 163 { CCI_REG16(0x602a), 0x2072 }, 164 { CCI_REG16(0x6f12), 0x0000 }, 165 { CCI_REG16(0x602a), 0x1a64 }, 166 { CCI_REG16(0x6f12), 0x0301 }, 167 { CCI_REG16(0x6f12), 0xff00 }, 168 { CCI_REG16(0x602a), 0x19e6 }, 169 { CCI_REG16(0x6f12), 0x0200 }, 170 { CCI_REG16(0x602a), 0x1a30 }, 171 { CCI_REG16(0x6f12), 0x3401 }, 172 { CCI_REG16(0x602a), 0x19fc }, 173 { CCI_REG16(0x6f12), 0x0b00 }, 174 { CCI_REG16(0x602a), 0x19f4 }, 175 { CCI_REG16(0x6f12), 0x0606 }, 176 { CCI_REG16(0x602a), 0x19f8 }, 177 { CCI_REG16(0x6f12), 0x1010 }, 178 { CCI_REG16(0x602a), 0x1b26 }, 179 { CCI_REG16(0x6f12), 0x6f80 }, 180 { CCI_REG16(0x6f12), 0xa060 }, 181 { CCI_REG16(0x602a), 0x1a3c }, 182 { CCI_REG16(0x6f12), 0x6207 }, 183 { CCI_REG16(0x602a), 0x1a48 }, 184 { CCI_REG16(0x6f12), 0x6207 }, 185 { CCI_REG16(0x602a), 0x1444 }, 186 { CCI_REG16(0x6f12), 0x2000 }, 187 { CCI_REG16(0x6f12), 0x2000 }, 188 { CCI_REG16(0x602a), 0x144c }, 189 { CCI_REG16(0x6f12), 0x3f00 }, 190 { CCI_REG16(0x6f12), 0x3f00 }, 191 { CCI_REG16(0x602a), 0x7f6c }, 192 { CCI_REG16(0x6f12), 0x0100 }, 193 { CCI_REG16(0x6f12), 0x2f00 }, 194 { CCI_REG16(0x6f12), 0xfa00 }, 195 { CCI_REG16(0x6f12), 0x2400 }, 196 { CCI_REG16(0x6f12), 0xe500 }, 197 { CCI_REG16(0x602a), 0x0650 }, 198 { CCI_REG16(0x6f12), 0x0600 }, 199 { CCI_REG16(0x602a), 0x0654 }, 200 { CCI_REG16(0x6f12), 0x0000 }, 201 { CCI_REG16(0x602a), 0x1a46 }, 202 { CCI_REG16(0x6f12), 0x8a00 }, 203 { CCI_REG16(0x602a), 0x1a52 }, 204 { CCI_REG16(0x6f12), 0xbf00 }, 205 { CCI_REG16(0x602a), 0x0674 }, 206 { CCI_REG16(0x6f12), 0x0500 }, 207 { CCI_REG16(0x6f12), 0x0500 }, 208 { CCI_REG16(0x6f12), 0x0500 }, 209 { CCI_REG16(0x6f12), 0x0500 }, 210 { CCI_REG16(0x602a), 0x0668 }, 211 { CCI_REG16(0x6f12), 0x0800 }, 212 { CCI_REG16(0x6f12), 0x0800 }, 213 { CCI_REG16(0x6f12), 0x0800 }, 214 { CCI_REG16(0x6f12), 0x0800 }, 215 { CCI_REG16(0x602a), 0x0684 }, 216 { CCI_REG16(0x6f12), 0x4001 }, 217 { CCI_REG16(0x602a), 0x0688 }, 218 { CCI_REG16(0x6f12), 0x4001 }, 219 { CCI_REG16(0x602a), 0x147c }, 220 { CCI_REG16(0x6f12), 0x1000 }, 221 { CCI_REG16(0x602a), 0x1480 }, 222 { CCI_REG16(0x6f12), 0x1000 }, 223 { CCI_REG16(0x602a), 0x19f6 }, 224 { CCI_REG16(0x6f12), 0x0904 }, 225 { CCI_REG16(0x602a), 0x0812 }, 226 { CCI_REG16(0x6f12), 0x0000 }, 227 { CCI_REG16(0x602a), 0x1a02 }, 228 { CCI_REG16(0x6f12), 0x1800 }, 229 { CCI_REG16(0x602a), 0x2148 }, 230 { CCI_REG16(0x6f12), 0x0100 }, 231 { CCI_REG16(0x602a), 0x2042 }, 232 { CCI_REG16(0x6f12), 0x1a00 }, 233 { CCI_REG16(0x602a), 0x0874 }, 234 { CCI_REG16(0x6f12), 0x0100 }, 235 { CCI_REG16(0x602a), 0x09c0 }, 236 { CCI_REG16(0x6f12), 0x2008 }, 237 { CCI_REG16(0x602a), 0x09c4 }, 238 { CCI_REG16(0x6f12), 0x2000 }, 239 { CCI_REG16(0x602a), 0x19fe }, 240 { CCI_REG16(0x6f12), 0x0e1c }, 241 { CCI_REG16(0x602a), 0x4d92 }, 242 { CCI_REG16(0x6f12), 0x0100 }, 243 { CCI_REG16(0x602a), 0x84c8 }, 244 { CCI_REG16(0x6f12), 0x0100 }, 245 { CCI_REG16(0x602a), 0x4d94 }, 246 { CCI_REG16(0x6f12), 0x0005 }, 247 { CCI_REG16(0x6f12), 0x000a }, 248 { CCI_REG16(0x6f12), 0x0010 }, 249 { CCI_REG16(0x6f12), 0x0810 }, 250 { CCI_REG16(0x6f12), 0x000a }, 251 { CCI_REG16(0x6f12), 0x0040 }, 252 { CCI_REG16(0x6f12), 0x0810 }, 253 { CCI_REG16(0x6f12), 0x0810 }, 254 { CCI_REG16(0x6f12), 0x8002 }, 255 { CCI_REG16(0x6f12), 0xfd03 }, 256 { CCI_REG16(0x6f12), 0x0010 }, 257 { CCI_REG16(0x6f12), 0x1510 }, 258 { CCI_REG16(0x602a), 0x3570 }, 259 { CCI_REG16(0x6f12), 0x0000 }, 260 { CCI_REG16(0x602a), 0x3574 }, 261 { CCI_REG16(0x6f12), 0x1201 }, 262 { CCI_REG16(0x602a), 0x21e4 }, 263 { CCI_REG16(0x6f12), 0x0400 }, 264 { CCI_REG16(0x602a), 0x21ec }, 265 { CCI_REG16(0x6f12), 0x1f04 }, 266 { CCI_REG16(0x602a), 0x2080 }, 267 { CCI_REG16(0x6f12), 0x0101 }, 268 { CCI_REG16(0x6f12), 0xff00 }, 269 { CCI_REG16(0x6f12), 0x7f01 }, 270 { CCI_REG16(0x6f12), 0x0001 }, 271 { CCI_REG16(0x6f12), 0x8001 }, 272 { CCI_REG16(0x6f12), 0xd244 }, 273 { CCI_REG16(0x6f12), 0xd244 }, 274 { CCI_REG16(0x6f12), 0x14f4 }, 275 { CCI_REG16(0x6f12), 0x0000 }, 276 { CCI_REG16(0x6f12), 0x0000 }, 277 { CCI_REG16(0x6f12), 0x0000 }, 278 { CCI_REG16(0x602a), 0x20ba }, 279 { CCI_REG16(0x6f12), 0x141c }, 280 { CCI_REG16(0x6f12), 0x111c }, 281 { CCI_REG16(0x6f12), 0x54f4 }, 282 { CCI_REG16(0x602a), 0x120e }, 283 { CCI_REG16(0x6f12), 0x1000 }, 284 { CCI_REG16(0x602a), 0x212e }, 285 { CCI_REG16(0x6f12), 0x0200 }, 286 { CCI_REG16(0x602a), 0x13ae }, 287 { CCI_REG16(0x6f12), 0x0101 }, 288 { CCI_REG16(0x602a), 0x0718 }, 289 { CCI_REG16(0x6f12), 0x0001 }, 290 { CCI_REG16(0x602a), 0x0710 }, 291 { CCI_REG16(0x6f12), 0x0002 }, 292 { CCI_REG16(0x6f12), 0x0804 }, 293 { CCI_REG16(0x6f12), 0x0100 }, 294 { CCI_REG16(0x602a), 0x1b5c }, 295 { CCI_REG16(0x6f12), 0x0000 }, 296 { CCI_REG16(0x602a), 0x0786 }, 297 { CCI_REG16(0x6f12), 0x7701 }, 298 { CCI_REG16(0x602a), 0x2022 }, 299 { CCI_REG16(0x6f12), 0x0500 }, 300 { CCI_REG16(0x6f12), 0x0500 }, 301 { CCI_REG16(0x602a), 0x1360 }, 302 { CCI_REG16(0x6f12), 0x0100 }, 303 { CCI_REG16(0x602a), 0x1376 }, 304 { CCI_REG16(0x6f12), 0x0100 }, 305 { CCI_REG16(0x6f12), 0x6038 }, 306 { CCI_REG16(0x6f12), 0x7038 }, 307 { CCI_REG16(0x6f12), 0x8038 }, 308 { CCI_REG16(0x602a), 0x1386 }, 309 { CCI_REG16(0x6f12), 0x0b00 }, 310 { CCI_REG16(0x602a), 0x06fa }, 311 { CCI_REG16(0x6f12), 0x1000 }, 312 { CCI_REG16(0x602a), 0x4a94 }, 313 { CCI_REG16(0x6f12), 0x0900 }, 314 { CCI_REG16(0x6f12), 0x0000 }, 315 { CCI_REG16(0x6f12), 0x0300 }, 316 { CCI_REG16(0x6f12), 0x0000 }, 317 { CCI_REG16(0x6f12), 0x0000 }, 318 { CCI_REG16(0x6f12), 0x0000 }, 319 { CCI_REG16(0x6f12), 0x0000 }, 320 { CCI_REG16(0x6f12), 0x0000 }, 321 { CCI_REG16(0x6f12), 0x0300 }, 322 { CCI_REG16(0x6f12), 0x0000 }, 323 { CCI_REG16(0x6f12), 0x0900 }, 324 { CCI_REG16(0x6f12), 0x0000 }, 325 { CCI_REG16(0x6f12), 0x0000 }, 326 { CCI_REG16(0x6f12), 0x0000 }, 327 { CCI_REG16(0x6f12), 0x0000 }, 328 { CCI_REG16(0x6f12), 0x0000 }, 329 { CCI_REG16(0x602a), 0x0a76 }, 330 { CCI_REG16(0x6f12), 0x1000 }, 331 { CCI_REG16(0x602a), 0x0aee }, 332 { CCI_REG16(0x6f12), 0x1000 }, 333 { CCI_REG16(0x602a), 0x0b66 }, 334 { CCI_REG16(0x6f12), 0x1000 }, 335 { CCI_REG16(0x602a), 0x0bde }, 336 { CCI_REG16(0x6f12), 0x1000 }, 337 { CCI_REG16(0x602a), 0x0be8 }, 338 { CCI_REG16(0x6f12), 0x3000 }, 339 { CCI_REG16(0x6f12), 0x3000 }, 340 { CCI_REG16(0x602a), 0x0c56 }, 341 { CCI_REG16(0x6f12), 0x1000 }, 342 { CCI_REG16(0x602a), 0x0c60 }, 343 { CCI_REG16(0x6f12), 0x3000 }, 344 { CCI_REG16(0x6f12), 0x3000 }, 345 { CCI_REG16(0x602a), 0x0cb6 }, 346 { CCI_REG16(0x6f12), 0x0100 }, 347 { CCI_REG16(0x602a), 0x0cf2 }, 348 { CCI_REG16(0x6f12), 0x0001 }, 349 { CCI_REG16(0x602a), 0x0cf0 }, 350 { CCI_REG16(0x6f12), 0x0101 }, 351 { CCI_REG16(0x602a), 0x11b8 }, 352 { CCI_REG16(0x6f12), 0x0100 }, 353 { CCI_REG16(0x602a), 0x11f6 }, 354 { CCI_REG16(0x6f12), 0x0020 }, 355 { CCI_REG16(0x602a), 0x4a74 }, 356 { CCI_REG16(0x6f12), 0x0000 }, 357 { CCI_REG16(0x6f12), 0x0000 }, 358 { CCI_REG16(0x6f12), 0xd8ff }, 359 { CCI_REG16(0x6f12), 0x0000 }, 360 { CCI_REG16(0x6f12), 0x0000 }, 361 { CCI_REG16(0x6f12), 0x0000 }, 362 { CCI_REG16(0x6f12), 0x0000 }, 363 { CCI_REG16(0x6f12), 0x0000 }, 364 { CCI_REG16(0x6f12), 0xd8ff }, 365 { CCI_REG16(0x6f12), 0x0000 }, 366 { CCI_REG16(0x6f12), 0x0000 }, 367 { CCI_REG16(0x6f12), 0x0000 }, 368 { CCI_REG16(0x6f12), 0x0000 }, 369 { CCI_REG16(0x6f12), 0x0000 }, 370 { CCI_REG16(0x6f12), 0x0000 }, 371 { CCI_REG16(0x6f12), 0x0000 }, 372 { CCI_REG16(0x602a), 0x218e }, 373 { CCI_REG16(0x6f12), 0x0000 }, 374 { CCI_REG16(0x602a), 0x2268 }, 375 { CCI_REG16(0x6f12), 0xf279 }, 376 { CCI_REG16(0x602a), 0x5006 }, 377 { CCI_REG16(0x6f12), 0x0000 }, 378 { CCI_REG16(0x602a), 0x500e }, 379 { CCI_REG16(0x6f12), 0x0100 }, 380 { CCI_REG16(0x602a), 0x4e70 }, 381 { CCI_REG16(0x6f12), 0x2062 }, 382 { CCI_REG16(0x6f12), 0x5501 }, 383 { CCI_REG16(0x602a), 0x06dc }, 384 { CCI_REG16(0x6f12), 0x0000 }, 385 { CCI_REG16(0x6f12), 0x0000 }, 386 { CCI_REG16(0x6f12), 0x0000 }, 387 { CCI_REG16(0x6f12), 0x0000 }, 388 { CCI_REG16(0x6028), 0x4000 }, 389 { CCI_REG16(0xf46a), 0xae80 }, 390 { S5KJN1_REG_X_ADDR_START, 0x0000 }, 391 { S5KJN1_REG_Y_ADDR_START, 0x0000 }, 392 { S5KJN1_REG_X_ADDR_END, 0x1fff }, 393 { S5KJN1_REG_Y_ADDR_END, 0x181f }, 394 { S5KJN1_REG_X_OUTPUT_SIZE, 0x0ff0 }, 395 { S5KJN1_REG_Y_OUTPUT_SIZE, 0x0c00 }, 396 { CCI_REG16(0x0350), 0x0008 }, 397 { CCI_REG16(0x0352), 0x0008 }, 398 { CCI_REG16(0x0900), 0x0122 }, 399 { CCI_REG16(0x0380), 0x0002 }, 400 { CCI_REG16(0x0382), 0x0002 }, 401 { CCI_REG16(0x0384), 0x0002 }, 402 { CCI_REG16(0x0386), 0x0002 }, 403 { CCI_REG16(0x0110), 0x1002 }, 404 { CCI_REG16(0x0114), 0x0301 }, 405 { CCI_REG16(0x0116), 0x3000 }, 406 407 /* Clock settings */ 408 { CCI_REG16(0x0136), 0x1800 }, 409 { CCI_REG16(0x013e), 0x0000 }, 410 { CCI_REG16(0x0300), 0x0006 }, 411 { CCI_REG16(0x0302), 0x0001 }, 412 { CCI_REG16(0x0304), 0x0004 }, 413 { CCI_REG16(0x0306), 0x008c }, 414 { CCI_REG16(0x0308), 0x0008 }, 415 { CCI_REG16(0x030a), 0x0001 }, 416 { CCI_REG16(0x030c), 0x0000 }, 417 { CCI_REG16(0x030e), 0x0004 }, 418 { CCI_REG16(0x0310), 0x0092 }, 419 { CCI_REG16(0x0312), 0x0000 }, 420 421 { CCI_REG16(0x080e), 0x0000 }, 422 { S5KJN1_REG_VTS, 0x10c0 }, 423 { S5KJN1_REG_HTS, 0x1100 }, 424 { CCI_REG16(0x0702), 0x0000 }, 425 { S5KJN1_REG_EXPOSURE, 0x0100 }, 426 { CCI_REG16(0x0200), 0x0100 }, 427 { CCI_REG16(0x0d00), 0x0101 }, 428 { CCI_REG16(0x0d02), 0x0101 }, 429 { CCI_REG16(0x0d04), 0x0102 }, 430 { CCI_REG16(0x6226), 0x0000 }, 431 { CCI_REG16(0x0816), 0x1c00 }, 432 }; 433 434 static const struct cci_reg_sequence s5kjn1_8160x6144_10fps_mode[] = { 435 { CCI_REG16(0x6028), 0x2400 }, 436 { CCI_REG16(0x602a), 0x1a28 }, 437 { CCI_REG16(0x6f12), 0x4c00 }, 438 { CCI_REG16(0x602a), 0x065a }, 439 { CCI_REG16(0x6f12), 0x0000 }, 440 { CCI_REG16(0x602a), 0x139e }, 441 { CCI_REG16(0x6f12), 0x0400 }, 442 { CCI_REG16(0x602a), 0x139c }, 443 { CCI_REG16(0x6f12), 0x0100 }, 444 { CCI_REG16(0x602a), 0x13a0 }, 445 { CCI_REG16(0x6f12), 0x0500 }, 446 { CCI_REG16(0x6f12), 0x0120 }, 447 { CCI_REG16(0x602a), 0x2072 }, 448 { CCI_REG16(0x6f12), 0x0101 }, 449 { CCI_REG16(0x602a), 0x1a64 }, 450 { CCI_REG16(0x6f12), 0x0001 }, 451 { CCI_REG16(0x6f12), 0x0000 }, 452 { CCI_REG16(0x602a), 0x19e6 }, 453 { CCI_REG16(0x6f12), 0x0200 }, 454 { CCI_REG16(0x602a), 0x1a30 }, 455 { CCI_REG16(0x6f12), 0x3403 }, 456 { CCI_REG16(0x602a), 0x19fc }, 457 { CCI_REG16(0x6f12), 0x0700 }, 458 { CCI_REG16(0x602a), 0x19f4 }, 459 { CCI_REG16(0x6f12), 0x0707 }, 460 { CCI_REG16(0x602a), 0x19f8 }, 461 { CCI_REG16(0x6f12), 0x0b0b }, 462 { CCI_REG16(0x602a), 0x1b26 }, 463 { CCI_REG16(0x6f12), 0x6f80 }, 464 { CCI_REG16(0x6f12), 0xa060 }, 465 { CCI_REG16(0x602a), 0x1a3c }, 466 { CCI_REG16(0x6f12), 0x8207 }, 467 { CCI_REG16(0x602a), 0x1a48 }, 468 { CCI_REG16(0x6f12), 0x8207 }, 469 { CCI_REG16(0x602a), 0x1444 }, 470 { CCI_REG16(0x6f12), 0x2000 }, 471 { CCI_REG16(0x6f12), 0x2000 }, 472 { CCI_REG16(0x602a), 0x144c }, 473 { CCI_REG16(0x6f12), 0x3f00 }, 474 { CCI_REG16(0x6f12), 0x3f00 }, 475 { CCI_REG16(0x602a), 0x7f6c }, 476 { CCI_REG16(0x6f12), 0x0100 }, 477 { CCI_REG16(0x6f12), 0x2f00 }, 478 { CCI_REG16(0x6f12), 0xfa00 }, 479 { CCI_REG16(0x6f12), 0x2400 }, 480 { CCI_REG16(0x6f12), 0xe500 }, 481 { CCI_REG16(0x602a), 0x0650 }, 482 { CCI_REG16(0x6f12), 0x0600 }, 483 { CCI_REG16(0x602a), 0x0654 }, 484 { CCI_REG16(0x6f12), 0x0000 }, 485 { CCI_REG16(0x602a), 0x1a46 }, 486 { CCI_REG16(0x6f12), 0x8500 }, 487 { CCI_REG16(0x602a), 0x1a52 }, 488 { CCI_REG16(0x6f12), 0x9800 }, 489 { CCI_REG16(0x602a), 0x0674 }, 490 { CCI_REG16(0x6f12), 0x0500 }, 491 { CCI_REG16(0x6f12), 0x0500 }, 492 { CCI_REG16(0x6f12), 0x0500 }, 493 { CCI_REG16(0x6f12), 0x0500 }, 494 { CCI_REG16(0x602a), 0x0668 }, 495 { CCI_REG16(0x6f12), 0x0800 }, 496 { CCI_REG16(0x6f12), 0x0800 }, 497 { CCI_REG16(0x6f12), 0x0800 }, 498 { CCI_REG16(0x6f12), 0x0800 }, 499 { CCI_REG16(0x602a), 0x0684 }, 500 { CCI_REG16(0x6f12), 0x4001 }, 501 { CCI_REG16(0x602a), 0x0688 }, 502 { CCI_REG16(0x6f12), 0x4001 }, 503 { CCI_REG16(0x602a), 0x147c }, 504 { CCI_REG16(0x6f12), 0x0400 }, 505 { CCI_REG16(0x602a), 0x1480 }, 506 { CCI_REG16(0x6f12), 0x0400 }, 507 { CCI_REG16(0x602a), 0x19f6 }, 508 { CCI_REG16(0x6f12), 0x0404 }, 509 { CCI_REG16(0x602a), 0x0812 }, 510 { CCI_REG16(0x6f12), 0x0000 }, 511 { CCI_REG16(0x602a), 0x1a02 }, 512 { CCI_REG16(0x6f12), 0x1800 }, 513 { CCI_REG16(0x602a), 0x2148 }, 514 { CCI_REG16(0x6f12), 0x0100 }, 515 { CCI_REG16(0x602a), 0x2042 }, 516 { CCI_REG16(0x6f12), 0x1a00 }, 517 { CCI_REG16(0x602a), 0x0874 }, 518 { CCI_REG16(0x6f12), 0x0106 }, 519 { CCI_REG16(0x602a), 0x09c0 }, 520 { CCI_REG16(0x6f12), 0x4000 }, 521 { CCI_REG16(0x602a), 0x09c4 }, 522 { CCI_REG16(0x6f12), 0x4000 }, 523 { CCI_REG16(0x602a), 0x19fe }, 524 { CCI_REG16(0x6f12), 0x0c1c }, 525 { CCI_REG16(0x602a), 0x4d92 }, 526 { CCI_REG16(0x6f12), 0x0000 }, 527 { CCI_REG16(0x602a), 0x84c8 }, 528 { CCI_REG16(0x6f12), 0x0000 }, 529 { CCI_REG16(0x602a), 0x4d94 }, 530 { CCI_REG16(0x6f12), 0x0000 }, 531 { CCI_REG16(0x6f12), 0x0000 }, 532 { CCI_REG16(0x6f12), 0x0000 }, 533 { CCI_REG16(0x6f12), 0x0000 }, 534 { CCI_REG16(0x6f12), 0x0000 }, 535 { CCI_REG16(0x6f12), 0x0000 }, 536 { CCI_REG16(0x6f12), 0x0000 }, 537 { CCI_REG16(0x6f12), 0x0000 }, 538 { CCI_REG16(0x6f12), 0x0000 }, 539 { CCI_REG16(0x6f12), 0x0000 }, 540 { CCI_REG16(0x6f12), 0x0000 }, 541 { CCI_REG16(0x6f12), 0x0000 }, 542 { CCI_REG16(0x602a), 0x3570 }, 543 { CCI_REG16(0x6f12), 0x0000 }, 544 { CCI_REG16(0x602a), 0x3574 }, 545 { CCI_REG16(0x6f12), 0x7306 }, 546 { CCI_REG16(0x602a), 0x21e4 }, 547 { CCI_REG16(0x6f12), 0x0400 }, 548 { CCI_REG16(0x602a), 0x21ec }, 549 { CCI_REG16(0x6f12), 0x6902 }, 550 { CCI_REG16(0x602a), 0x2080 }, 551 { CCI_REG16(0x6f12), 0x0100 }, 552 { CCI_REG16(0x6f12), 0xff00 }, 553 { CCI_REG16(0x6f12), 0x0002 }, 554 { CCI_REG16(0x6f12), 0x0001 }, 555 { CCI_REG16(0x6f12), 0x0002 }, 556 { CCI_REG16(0x6f12), 0xd244 }, 557 { CCI_REG16(0x6f12), 0xd244 }, 558 { CCI_REG16(0x6f12), 0x14f4 }, 559 { CCI_REG16(0x6f12), 0x101c }, 560 { CCI_REG16(0x6f12), 0x0d1c }, 561 { CCI_REG16(0x6f12), 0x54f4 }, 562 { CCI_REG16(0x602a), 0x20ba }, 563 { CCI_REG16(0x6f12), 0x0000 }, 564 { CCI_REG16(0x6f12), 0x0000 }, 565 { CCI_REG16(0x6f12), 0x0000 }, 566 { CCI_REG16(0x602a), 0x120e }, 567 { CCI_REG16(0x6f12), 0x1000 }, 568 { CCI_REG16(0x602a), 0x212e }, 569 { CCI_REG16(0x6f12), 0x0200 }, 570 { CCI_REG16(0x602a), 0x13ae }, 571 { CCI_REG16(0x6f12), 0x0100 }, 572 { CCI_REG16(0x602a), 0x0718 }, 573 { CCI_REG16(0x6f12), 0x0000 }, 574 { CCI_REG16(0x602a), 0x0710 }, 575 { CCI_REG16(0x6f12), 0x0010 }, 576 { CCI_REG16(0x6f12), 0x0201 }, 577 { CCI_REG16(0x6f12), 0x0800 }, 578 { CCI_REG16(0x602a), 0x1b5c }, 579 { CCI_REG16(0x6f12), 0x0000 }, 580 { CCI_REG16(0x602a), 0x0786 }, 581 { CCI_REG16(0x6f12), 0x1401 }, 582 { CCI_REG16(0x602a), 0x2022 }, 583 { CCI_REG16(0x6f12), 0x0500 }, 584 { CCI_REG16(0x6f12), 0x0500 }, 585 { CCI_REG16(0x602a), 0x1360 }, 586 { CCI_REG16(0x6f12), 0x0000 }, 587 { CCI_REG16(0x602a), 0x1376 }, 588 { CCI_REG16(0x6f12), 0x0000 }, 589 { CCI_REG16(0x6f12), 0x6038 }, 590 { CCI_REG16(0x6f12), 0x7038 }, 591 { CCI_REG16(0x6f12), 0x8038 }, 592 { CCI_REG16(0x602a), 0x1386 }, 593 { CCI_REG16(0x6f12), 0x0b00 }, 594 { CCI_REG16(0x602a), 0x06fa }, 595 { CCI_REG16(0x6f12), 0x1000 }, 596 { CCI_REG16(0x602a), 0x4a94 }, 597 { CCI_REG16(0x6f12), 0x0400 }, 598 { CCI_REG16(0x6f12), 0x0400 }, 599 { CCI_REG16(0x6f12), 0x0400 }, 600 { CCI_REG16(0x6f12), 0x0400 }, 601 { CCI_REG16(0x6f12), 0x0800 }, 602 { CCI_REG16(0x6f12), 0x0800 }, 603 { CCI_REG16(0x6f12), 0x0800 }, 604 { CCI_REG16(0x6f12), 0x0800 }, 605 { CCI_REG16(0x6f12), 0x0400 }, 606 { CCI_REG16(0x6f12), 0x0400 }, 607 { CCI_REG16(0x6f12), 0x0400 }, 608 { CCI_REG16(0x6f12), 0x0400 }, 609 { CCI_REG16(0x6f12), 0x0800 }, 610 { CCI_REG16(0x6f12), 0x0800 }, 611 { CCI_REG16(0x6f12), 0x0800 }, 612 { CCI_REG16(0x6f12), 0x0800 }, 613 { CCI_REG16(0x602a), 0x0a76 }, 614 { CCI_REG16(0x6f12), 0x1000 }, 615 { CCI_REG16(0x602a), 0x0aee }, 616 { CCI_REG16(0x6f12), 0x1000 }, 617 { CCI_REG16(0x602a), 0x0b66 }, 618 { CCI_REG16(0x6f12), 0x1000 }, 619 { CCI_REG16(0x602a), 0x0bde }, 620 { CCI_REG16(0x6f12), 0x1000 }, 621 { CCI_REG16(0x602a), 0x0be8 }, 622 { CCI_REG16(0x6f12), 0x5000 }, 623 { CCI_REG16(0x6f12), 0x5000 }, 624 { CCI_REG16(0x602a), 0x0c56 }, 625 { CCI_REG16(0x6f12), 0x1000 }, 626 { CCI_REG16(0x602a), 0x0c60 }, 627 { CCI_REG16(0x6f12), 0x5000 }, 628 { CCI_REG16(0x6f12), 0x5000 }, 629 { CCI_REG16(0x602a), 0x0cb6 }, 630 { CCI_REG16(0x6f12), 0x0000 }, 631 { CCI_REG16(0x602a), 0x0cf2 }, 632 { CCI_REG16(0x6f12), 0x0001 }, 633 { CCI_REG16(0x602a), 0x0cf0 }, 634 { CCI_REG16(0x6f12), 0x0101 }, 635 { CCI_REG16(0x602a), 0x11b8 }, 636 { CCI_REG16(0x6f12), 0x0000 }, 637 { CCI_REG16(0x602a), 0x11f6 }, 638 { CCI_REG16(0x6f12), 0x0010 }, 639 { CCI_REG16(0x602a), 0x4a74 }, 640 { CCI_REG16(0x6f12), 0x0000 }, 641 { CCI_REG16(0x6f12), 0x0000 }, 642 { CCI_REG16(0x6f12), 0x0000 }, 643 { CCI_REG16(0x6f12), 0x0000 }, 644 { CCI_REG16(0x6f12), 0x0000 }, 645 { CCI_REG16(0x6f12), 0x0000 }, 646 { CCI_REG16(0x6f12), 0x0000 }, 647 { CCI_REG16(0x6f12), 0x0000 }, 648 { CCI_REG16(0x6f12), 0x0000 }, 649 { CCI_REG16(0x6f12), 0x0000 }, 650 { CCI_REG16(0x6f12), 0x0000 }, 651 { CCI_REG16(0x6f12), 0x0000 }, 652 { CCI_REG16(0x6f12), 0x0000 }, 653 { CCI_REG16(0x6f12), 0x0000 }, 654 { CCI_REG16(0x6f12), 0x0000 }, 655 { CCI_REG16(0x6f12), 0x0000 }, 656 { CCI_REG16(0x602a), 0x218e }, 657 { CCI_REG16(0x6f12), 0x0000 }, 658 { CCI_REG16(0x602a), 0x2268 }, 659 { CCI_REG16(0x6f12), 0xf279 }, 660 { CCI_REG16(0x602a), 0x5006 }, 661 { CCI_REG16(0x6f12), 0x0000 }, 662 { CCI_REG16(0x602a), 0x500e }, 663 { CCI_REG16(0x6f12), 0x0100 }, 664 { CCI_REG16(0x602a), 0x4e70 }, 665 { CCI_REG16(0x6f12), 0x2062 }, 666 { CCI_REG16(0x6f12), 0x5501 }, 667 { CCI_REG16(0x602a), 0x06dc }, 668 { CCI_REG16(0x6f12), 0x0000 }, 669 { CCI_REG16(0x6f12), 0x0000 }, 670 { CCI_REG16(0x6f12), 0x0000 }, 671 { CCI_REG16(0x6f12), 0x0000 }, 672 { CCI_REG16(0x6028), 0x4000 }, 673 { CCI_REG16(0xf46a), 0xae80 }, 674 { S5KJN1_REG_X_ADDR_START, 0x0000 }, 675 { S5KJN1_REG_Y_ADDR_START, 0x0000 }, 676 { S5KJN1_REG_X_ADDR_END, 0x1fff }, 677 { S5KJN1_REG_Y_ADDR_END, 0x181f }, 678 { S5KJN1_REG_X_OUTPUT_SIZE, 0x1fe0 }, 679 { S5KJN1_REG_Y_OUTPUT_SIZE, 0x1800 }, 680 { CCI_REG16(0x0350), 0x0010 }, 681 { CCI_REG16(0x0352), 0x0010 }, 682 { CCI_REG16(0x0900), 0x0111 }, 683 { CCI_REG16(0x0380), 0x0001 }, 684 { CCI_REG16(0x0382), 0x0001 }, 685 { CCI_REG16(0x0384), 0x0001 }, 686 { CCI_REG16(0x0386), 0x0001 }, 687 { CCI_REG16(0x0110), 0x1002 }, 688 { CCI_REG16(0x0114), 0x0300 }, 689 { CCI_REG16(0x0116), 0x3000 }, 690 691 /* Clock settings */ 692 { CCI_REG16(0x0136), 0x1800 }, 693 { CCI_REG16(0x013e), 0x0000 }, 694 { CCI_REG16(0x0300), 0x0006 }, 695 { CCI_REG16(0x0302), 0x0001 }, 696 { CCI_REG16(0x0304), 0x0004 }, 697 { CCI_REG16(0x0306), 0x008c }, 698 { CCI_REG16(0x0308), 0x0008 }, 699 { CCI_REG16(0x030a), 0x0001 }, 700 { CCI_REG16(0x030c), 0x0000 }, 701 { CCI_REG16(0x030e), 0x0004 }, 702 { CCI_REG16(0x0310), 0x0074 }, 703 { CCI_REG16(0x0312), 0x0000 }, 704 705 { CCI_REG16(0x080e), 0x0000 }, 706 { S5KJN1_REG_VTS, 0x1900 }, 707 { S5KJN1_REG_HTS, 0x21f0 }, 708 { CCI_REG16(0x0702), 0x0000 }, 709 { S5KJN1_REG_EXPOSURE, 0x0100 }, 710 { CCI_REG16(0x0200), 0x0100 }, 711 { CCI_REG16(0x0d00), 0x0100 }, 712 { CCI_REG16(0x0d02), 0x0001 }, 713 { CCI_REG16(0x0d04), 0x0002 }, 714 { CCI_REG16(0x6226), 0x0000 }, 715 }; 716 717 static const struct s5kjn1_mode s5kjn1_supported_modes[] = { 718 { 719 .width = 4080, 720 .height = 3072, 721 .hts = 4352, 722 .vts = 4288, 723 .exposure = 3840, 724 .exposure_margin = 22, 725 .reg_list = { 726 .regs = s5kjn1_4080x3072_30fps_mode, 727 .num_regs = ARRAY_SIZE(s5kjn1_4080x3072_30fps_mode), 728 }, 729 }, 730 { 731 .width = 8160, 732 .height = 6144, 733 .hts = 8688, 734 .vts = 6400, 735 .exposure = 6144, 736 .exposure_margin = 44, 737 .reg_list = { 738 .regs = s5kjn1_8160x6144_10fps_mode, 739 .num_regs = ARRAY_SIZE(s5kjn1_8160x6144_10fps_mode), 740 }, 741 }, 742 }; 743 744 static int s5kjn1_set_ctrl(struct v4l2_ctrl *ctrl) 745 { 746 struct s5kjn1 *s5kjn1 = container_of(ctrl->handler, struct s5kjn1, 747 ctrl_handler); 748 const struct s5kjn1_mode *mode = s5kjn1->mode; 749 s64 exposure_max; 750 int ret; 751 752 /* Propagate change of current control to all related controls */ 753 switch (ctrl->id) { 754 case V4L2_CID_VBLANK: 755 /* Update max exposure while meeting expected vblanking */ 756 exposure_max = mode->height + ctrl->val - mode->exposure_margin; 757 __v4l2_ctrl_modify_range(s5kjn1->exposure, 758 s5kjn1->exposure->minimum, 759 exposure_max, 760 s5kjn1->exposure->step, 761 s5kjn1->exposure->default_value); 762 break; 763 } 764 765 /* V4L2 controls are applied, when sensor is powered up for streaming */ 766 if (!pm_runtime_get_if_active(s5kjn1->dev)) 767 return 0; 768 769 switch (ctrl->id) { 770 case V4L2_CID_ANALOGUE_GAIN: 771 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_AGAIN, 772 ctrl->val << S5KJN1_AGAIN_SHIFT, NULL); 773 break; 774 case V4L2_CID_EXPOSURE: 775 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_EXPOSURE, 776 ctrl->val, NULL); 777 break; 778 case V4L2_CID_VBLANK: 779 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_VTS, 780 ctrl->val + mode->height, NULL); 781 break; 782 case V4L2_CID_VFLIP: 783 case V4L2_CID_HFLIP: 784 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_ORIENTATION, 785 (s5kjn1->vflip->val ? S5KJN1_VFLIP : 0) | 786 (s5kjn1->hflip->val ? S5KJN1_HFLIP : 0), NULL); 787 break; 788 case V4L2_CID_TEST_PATTERN: 789 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_TEST_PATTERN, 790 ctrl->val, NULL); 791 break; 792 default: 793 ret = -EINVAL; 794 break; 795 } 796 797 pm_runtime_put(s5kjn1->dev); 798 799 return ret; 800 } 801 802 static const struct v4l2_ctrl_ops s5kjn1_ctrl_ops = { 803 .s_ctrl = s5kjn1_set_ctrl, 804 }; 805 806 static inline u64 s5kjn1_freq_to_pixel_rate(const u64 freq) 807 { 808 return div_u64(freq * 2 * S5KJN1_DATA_LANES, 10); 809 } 810 811 static int s5kjn1_init_controls(struct s5kjn1 *s5kjn1) 812 { 813 struct v4l2_ctrl_handler *ctrl_hdlr = &s5kjn1->ctrl_handler; 814 const struct s5kjn1_mode *mode = s5kjn1->mode; 815 s64 pixel_rate, hblank, vblank, exposure_max; 816 struct v4l2_fwnode_device_properties props; 817 int ret; 818 819 v4l2_ctrl_handler_init(ctrl_hdlr, 9); 820 821 s5kjn1->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &s5kjn1_ctrl_ops, 822 V4L2_CID_LINK_FREQ, 823 ARRAY_SIZE(s5kjn1_link_freq_menu) - 1, 824 0, s5kjn1_link_freq_menu); 825 if (s5kjn1->link_freq) 826 s5kjn1->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY; 827 828 pixel_rate = s5kjn1_freq_to_pixel_rate(s5kjn1_link_freq_menu[0]); 829 s5kjn1->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 830 V4L2_CID_PIXEL_RATE, 831 0, pixel_rate, 1, pixel_rate); 832 833 hblank = mode->hts - mode->width; 834 s5kjn1->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 835 V4L2_CID_HBLANK, hblank, 836 hblank, 1, hblank); 837 if (s5kjn1->hblank) 838 s5kjn1->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; 839 840 vblank = mode->vts - mode->height; 841 s5kjn1->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 842 V4L2_CID_VBLANK, vblank, 843 S5KJN1_VTS_MAX - mode->height, 1, 844 vblank); 845 846 v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 847 S5KJN1_AGAIN_MIN, S5KJN1_AGAIN_MAX, 848 S5KJN1_AGAIN_STEP, S5KJN1_AGAIN_DEFAULT); 849 850 exposure_max = mode->vts - mode->exposure_margin; 851 s5kjn1->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 852 V4L2_CID_EXPOSURE, 853 S5KJN1_EXPOSURE_MIN, 854 exposure_max, 855 S5KJN1_EXPOSURE_STEP, 856 mode->exposure); 857 858 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &s5kjn1_ctrl_ops, 859 V4L2_CID_TEST_PATTERN, 860 ARRAY_SIZE(s5kjn1_test_pattern_menu) - 1, 861 0, 0, s5kjn1_test_pattern_menu); 862 863 s5kjn1->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 864 V4L2_CID_HFLIP, 0, 1, 1, 0); 865 if (s5kjn1->hflip) 866 s5kjn1->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 867 868 s5kjn1->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &s5kjn1_ctrl_ops, 869 V4L2_CID_VFLIP, 0, 1, 1, 0); 870 if (s5kjn1->vflip) 871 s5kjn1->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; 872 873 ret = v4l2_fwnode_device_parse(s5kjn1->dev, &props); 874 if (ret) 875 goto error_free_hdlr; 876 877 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &s5kjn1_ctrl_ops, 878 &props); 879 if (ret) 880 goto error_free_hdlr; 881 882 s5kjn1->sd.ctrl_handler = ctrl_hdlr; 883 884 return 0; 885 886 error_free_hdlr: 887 v4l2_ctrl_handler_free(ctrl_hdlr); 888 889 return ret; 890 } 891 892 static int s5kjn1_enable_streams(struct v4l2_subdev *sd, 893 struct v4l2_subdev_state *state, u32 pad, 894 u64 streams_mask) 895 { 896 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 897 const struct s5kjn1_reg_list *reg_list = &s5kjn1->mode->reg_list; 898 int ret; 899 900 ret = pm_runtime_resume_and_get(s5kjn1->dev); 901 if (ret) 902 return ret; 903 904 /* Page pointer */ 905 cci_write(s5kjn1->regmap, CCI_REG16(0x6028), 0x4000, &ret); 906 907 /* Set version */ 908 cci_write(s5kjn1->regmap, CCI_REG16(0x0000), 0x0003, &ret); 909 cci_write(s5kjn1->regmap, CCI_REG16(0x0000), S5KJN1_CHIP_ID, &ret); 910 cci_write(s5kjn1->regmap, CCI_REG16(0x001e), 0x0007, &ret); 911 cci_write(s5kjn1->regmap, CCI_REG16(0x6028), 0x4000, &ret); 912 cci_write(s5kjn1->regmap, CCI_REG16(0x6010), 0x0001, &ret); 913 if (ret) 914 goto error; 915 916 usleep_range(5 * USEC_PER_MSEC, 6 * USEC_PER_MSEC); 917 918 cci_write(s5kjn1->regmap, CCI_REG16(0x6226), 0x0001, &ret); 919 if (ret) 920 goto error; 921 922 usleep_range(10 * USEC_PER_MSEC, 11 * USEC_PER_MSEC); 923 924 /* Sensor init settings */ 925 cci_multi_reg_write(s5kjn1->regmap, init_array_setting, 926 ARRAY_SIZE(init_array_setting), &ret); 927 cci_multi_reg_write(s5kjn1->regmap, reg_list->regs, 928 reg_list->num_regs, &ret); 929 if (ret) 930 goto error; 931 932 ret = __v4l2_ctrl_handler_setup(s5kjn1->sd.ctrl_handler); 933 934 cci_write(s5kjn1->regmap, S5KJN1_REG_CTRL_MODE, 935 S5KJN1_MODE_STREAMING, &ret); 936 if (ret) 937 goto error; 938 939 return 0; 940 941 error: 942 dev_err(s5kjn1->dev, "failed to start streaming: %d\n", ret); 943 pm_runtime_put_autosuspend(s5kjn1->dev); 944 945 return ret; 946 } 947 948 static int s5kjn1_disable_streams(struct v4l2_subdev *sd, 949 struct v4l2_subdev_state *state, u32 pad, 950 u64 streams_mask) 951 { 952 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 953 int ret; 954 955 ret = cci_write(s5kjn1->regmap, S5KJN1_REG_CTRL_MODE, 0x0, NULL); 956 if (ret) 957 dev_err(s5kjn1->dev, "failed to stop streaming: %d\n", ret); 958 959 pm_runtime_put_autosuspend(s5kjn1->dev); 960 961 return ret; 962 } 963 964 static u32 s5kjn1_get_format_code(struct s5kjn1 *s5kjn1) 965 { 966 unsigned int i; 967 968 i = (s5kjn1->vflip->val ? 2 : 0) | (s5kjn1->hflip->val ? 1 : 0); 969 970 return s5kjn1_mbus_formats[i]; 971 } 972 973 static void s5kjn1_update_pad_format(struct s5kjn1 *s5kjn1, 974 const struct s5kjn1_mode *mode, 975 struct v4l2_mbus_framefmt *fmt) 976 { 977 fmt->code = s5kjn1_get_format_code(s5kjn1); 978 fmt->width = mode->width; 979 fmt->height = mode->height; 980 fmt->field = V4L2_FIELD_NONE; 981 fmt->colorspace = V4L2_COLORSPACE_SRGB; 982 fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 983 fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 984 fmt->xfer_func = V4L2_XFER_FUNC_NONE; 985 } 986 987 static int s5kjn1_set_pad_format(struct v4l2_subdev *sd, 988 struct v4l2_subdev_state *state, 989 struct v4l2_subdev_format *fmt) 990 { 991 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 992 s64 hblank, vblank, exposure_max; 993 const struct s5kjn1_mode *mode; 994 995 mode = v4l2_find_nearest_size(s5kjn1_supported_modes, 996 ARRAY_SIZE(s5kjn1_supported_modes), 997 width, height, 998 fmt->format.width, fmt->format.height); 999 1000 s5kjn1_update_pad_format(s5kjn1, mode, &fmt->format); 1001 1002 /* Format code could be updated with respect to flip controls */ 1003 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY || s5kjn1->mode == mode) 1004 goto set_format; 1005 1006 /* Update limits and set FPS and exposure to default values */ 1007 hblank = mode->hts - mode->width; 1008 __v4l2_ctrl_modify_range(s5kjn1->hblank, hblank, hblank, 1, hblank); 1009 1010 vblank = mode->vts - mode->height; 1011 __v4l2_ctrl_modify_range(s5kjn1->vblank, vblank, 1012 S5KJN1_VTS_MAX - mode->height, 1, vblank); 1013 __v4l2_ctrl_s_ctrl(s5kjn1->vblank, vblank); 1014 1015 exposure_max = mode->vts - mode->exposure_margin; 1016 __v4l2_ctrl_modify_range(s5kjn1->exposure, S5KJN1_EXPOSURE_MIN, 1017 exposure_max, S5KJN1_EXPOSURE_STEP, 1018 mode->exposure); 1019 __v4l2_ctrl_s_ctrl(s5kjn1->exposure, mode->exposure); 1020 1021 if (s5kjn1->sd.ctrl_handler->error) 1022 return s5kjn1->sd.ctrl_handler->error; 1023 1024 s5kjn1->mode = mode; 1025 1026 set_format: 1027 *v4l2_subdev_state_get_format(state, 0) = fmt->format; 1028 1029 return 0; 1030 } 1031 1032 static int s5kjn1_enum_mbus_code(struct v4l2_subdev *sd, 1033 struct v4l2_subdev_state *sd_state, 1034 struct v4l2_subdev_mbus_code_enum *code) 1035 { 1036 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1037 1038 /* Media bus code index is constant, but code formats are not */ 1039 if (code->index > 0) 1040 return -EINVAL; 1041 1042 code->code = s5kjn1_get_format_code(s5kjn1); 1043 1044 return 0; 1045 } 1046 1047 static int s5kjn1_enum_frame_size(struct v4l2_subdev *sd, 1048 struct v4l2_subdev_state *sd_state, 1049 struct v4l2_subdev_frame_size_enum *fse) 1050 { 1051 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1052 1053 if (fse->index >= ARRAY_SIZE(s5kjn1_supported_modes)) 1054 return -EINVAL; 1055 1056 if (fse->code != s5kjn1_get_format_code(s5kjn1)) 1057 return -EINVAL; 1058 1059 fse->min_width = s5kjn1_supported_modes[fse->index].width; 1060 fse->max_width = fse->min_width; 1061 fse->min_height = s5kjn1_supported_modes[fse->index].height; 1062 fse->max_height = fse->min_height; 1063 1064 return 0; 1065 } 1066 1067 static int s5kjn1_get_selection(struct v4l2_subdev *sd, 1068 struct v4l2_subdev_state *sd_state, 1069 struct v4l2_subdev_selection *sel) 1070 { 1071 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1072 1073 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 1074 return -EINVAL; 1075 1076 switch (sel->target) { 1077 case V4L2_SEL_TGT_CROP: 1078 case V4L2_SEL_TGT_CROP_BOUNDS: 1079 sel->r.left = 0; 1080 sel->r.top = 0; 1081 sel->r.width = s5kjn1->mode->width; 1082 sel->r.height = s5kjn1->mode->width; 1083 return 0; 1084 default: 1085 return -EINVAL; 1086 } 1087 1088 return 0; 1089 } 1090 1091 static int s5kjn1_init_state(struct v4l2_subdev *sd, 1092 struct v4l2_subdev_state *state) 1093 { 1094 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1095 struct v4l2_subdev_format fmt = { 1096 .which = V4L2_SUBDEV_FORMAT_TRY, 1097 .pad = 0, 1098 .format = { 1099 /* Media bus code depends on current flip controls */ 1100 .width = s5kjn1->mode->width, 1101 .height = s5kjn1->mode->height, 1102 }, 1103 }; 1104 1105 s5kjn1_set_pad_format(sd, state, &fmt); 1106 1107 return 0; 1108 } 1109 1110 static const struct v4l2_subdev_video_ops s5kjn1_video_ops = { 1111 .s_stream = v4l2_subdev_s_stream_helper, 1112 }; 1113 1114 static const struct v4l2_subdev_pad_ops s5kjn1_pad_ops = { 1115 .set_fmt = s5kjn1_set_pad_format, 1116 .get_fmt = v4l2_subdev_get_fmt, 1117 .get_selection = s5kjn1_get_selection, 1118 .enum_mbus_code = s5kjn1_enum_mbus_code, 1119 .enum_frame_size = s5kjn1_enum_frame_size, 1120 .enable_streams = s5kjn1_enable_streams, 1121 .disable_streams = s5kjn1_disable_streams, 1122 }; 1123 1124 static const struct v4l2_subdev_ops s5kjn1_subdev_ops = { 1125 .video = &s5kjn1_video_ops, 1126 .pad = &s5kjn1_pad_ops, 1127 }; 1128 1129 static const struct v4l2_subdev_internal_ops s5kjn1_internal_ops = { 1130 .init_state = s5kjn1_init_state, 1131 }; 1132 1133 static const struct media_entity_operations s5kjn1_subdev_entity_ops = { 1134 .link_validate = v4l2_subdev_link_validate, 1135 }; 1136 1137 static int s5kjn1_identify_sensor(struct s5kjn1 *s5kjn1) 1138 { 1139 u64 val; 1140 int ret; 1141 1142 ret = cci_read(s5kjn1->regmap, S5KJN1_REG_CHIP_ID, &val, NULL); 1143 if (ret) { 1144 dev_err(s5kjn1->dev, "failed to read chip id: %d\n", ret); 1145 return ret; 1146 } 1147 1148 if (val != S5KJN1_CHIP_ID) { 1149 dev_err(s5kjn1->dev, "chip id mismatch: %x!=%llx\n", 1150 S5KJN1_CHIP_ID, val); 1151 return -ENODEV; 1152 } 1153 1154 return 0; 1155 } 1156 1157 static int s5kjn1_check_hwcfg(struct s5kjn1 *s5kjn1) 1158 { 1159 struct fwnode_handle *fwnode = dev_fwnode(s5kjn1->dev), *ep; 1160 struct v4l2_fwnode_endpoint bus_cfg = { 1161 .bus = { 1162 .mipi_csi2 = { 1163 .num_data_lanes = S5KJN1_DATA_LANES, 1164 }, 1165 }, 1166 .bus_type = V4L2_MBUS_CSI2_DPHY, 1167 }; 1168 unsigned long freq_bitmap; 1169 int ret; 1170 1171 if (!fwnode) 1172 return -ENODEV; 1173 1174 ep = fwnode_graph_get_next_endpoint(fwnode, NULL); 1175 if (!ep) 1176 return -EINVAL; 1177 1178 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); 1179 fwnode_handle_put(ep); 1180 if (ret) 1181 return ret; 1182 1183 if (bus_cfg.bus.mipi_csi2.num_data_lanes != S5KJN1_DATA_LANES) { 1184 dev_err(s5kjn1->dev, "Invalid number of data lanes: %u\n", 1185 bus_cfg.bus.mipi_csi2.num_data_lanes); 1186 ret = -EINVAL; 1187 goto endpoint_free; 1188 } 1189 1190 ret = v4l2_link_freq_to_bitmap(s5kjn1->dev, bus_cfg.link_frequencies, 1191 bus_cfg.nr_of_link_frequencies, 1192 s5kjn1_link_freq_menu, 1193 ARRAY_SIZE(s5kjn1_link_freq_menu), 1194 &freq_bitmap); 1195 1196 endpoint_free: 1197 v4l2_fwnode_endpoint_free(&bus_cfg); 1198 1199 return ret; 1200 } 1201 1202 static int s5kjn1_power_on(struct device *dev) 1203 { 1204 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1205 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1206 int ret; 1207 1208 if (s5kjn1->vddd) { 1209 ret = regulator_enable(s5kjn1->vddd); 1210 if (ret) 1211 return ret; 1212 1213 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 1214 } 1215 1216 if (s5kjn1->vdda) { 1217 ret = regulator_enable(s5kjn1->vdda); 1218 if (ret) 1219 goto disable_vddd; 1220 } 1221 1222 if (s5kjn1->vddio) { 1223 ret = regulator_enable(s5kjn1->vddio); 1224 if (ret) 1225 goto disable_vdda; 1226 } 1227 1228 if (s5kjn1->afvdd) { 1229 ret = regulator_enable(s5kjn1->afvdd); 1230 if (ret) 1231 goto disable_vddio; 1232 } 1233 1234 ret = clk_prepare_enable(s5kjn1->mclk); 1235 if (ret) 1236 goto disable_regulators; 1237 1238 gpiod_set_value_cansleep(s5kjn1->reset_gpio, 0); 1239 usleep_range(10 * USEC_PER_MSEC, 15 * USEC_PER_MSEC); 1240 1241 return 0; 1242 1243 disable_regulators: 1244 if (s5kjn1->afvdd) 1245 regulator_disable(s5kjn1->afvdd); 1246 1247 disable_vddio: 1248 if (s5kjn1->vddio) 1249 regulator_disable(s5kjn1->vddio); 1250 1251 disable_vdda: 1252 if (s5kjn1->vdda) 1253 regulator_disable(s5kjn1->vdda); 1254 1255 disable_vddd: 1256 if (s5kjn1->vddd) { 1257 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 1258 regulator_disable(s5kjn1->vddd); 1259 } 1260 1261 return ret; 1262 } 1263 1264 static int s5kjn1_power_off(struct device *dev) 1265 { 1266 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1267 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1268 1269 gpiod_set_value_cansleep(s5kjn1->reset_gpio, 1); 1270 1271 clk_disable_unprepare(s5kjn1->mclk); 1272 1273 if (s5kjn1->afvdd) 1274 regulator_disable(s5kjn1->afvdd); 1275 1276 if (s5kjn1->vddio) 1277 regulator_disable(s5kjn1->vddio); 1278 1279 if (s5kjn1->vdda) 1280 regulator_disable(s5kjn1->vdda); 1281 1282 if (s5kjn1->vddd) { 1283 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC); 1284 regulator_disable(s5kjn1->vddd); 1285 } 1286 1287 return 0; 1288 } 1289 1290 static int s5kjn1_probe(struct i2c_client *client) 1291 { 1292 struct s5kjn1 *s5kjn1; 1293 unsigned long freq; 1294 int ret; 1295 1296 s5kjn1 = devm_kzalloc(&client->dev, sizeof(*s5kjn1), GFP_KERNEL); 1297 if (!s5kjn1) 1298 return -ENOMEM; 1299 1300 s5kjn1->dev = &client->dev; 1301 v4l2_i2c_subdev_init(&s5kjn1->sd, client, &s5kjn1_subdev_ops); 1302 1303 s5kjn1->regmap = devm_cci_regmap_init_i2c(client, 16); 1304 if (IS_ERR(s5kjn1->regmap)) 1305 return dev_err_probe(s5kjn1->dev, PTR_ERR(s5kjn1->regmap), 1306 "failed to init CCI\n"); 1307 1308 s5kjn1->mclk = devm_v4l2_sensor_clk_get(s5kjn1->dev, NULL); 1309 if (IS_ERR(s5kjn1->mclk)) 1310 return dev_err_probe(s5kjn1->dev, PTR_ERR(s5kjn1->mclk), 1311 "failed to get MCLK clock\n"); 1312 1313 freq = clk_get_rate(s5kjn1->mclk); 1314 if (freq != S5KJN1_MCLK_FREQ_24MHZ) 1315 return dev_err_probe(s5kjn1->dev, -EINVAL, 1316 "MCLK clock frequency %lu is not supported\n", 1317 freq); 1318 1319 ret = s5kjn1_check_hwcfg(s5kjn1); 1320 if (ret) 1321 return dev_err_probe(s5kjn1->dev, ret, 1322 "failed to check HW configuration\n"); 1323 1324 s5kjn1->reset_gpio = devm_gpiod_get_optional(s5kjn1->dev, "reset", 1325 GPIOD_OUT_HIGH); 1326 if (IS_ERR(s5kjn1->reset_gpio)) 1327 return dev_err_probe(s5kjn1->dev, PTR_ERR(s5kjn1->reset_gpio), 1328 "cannot get reset GPIO\n"); 1329 1330 s5kjn1->afvdd = devm_regulator_get_optional(s5kjn1->dev, "afvdd"); 1331 if (IS_ERR(s5kjn1->afvdd)) { 1332 ret = PTR_ERR(s5kjn1->afvdd); 1333 if (ret != -ENODEV) { 1334 return dev_err_probe(s5kjn1->dev, ret, 1335 "Failed to get 'afvdd' regulator\n"); 1336 } 1337 1338 s5kjn1->afvdd = NULL; 1339 } 1340 1341 s5kjn1->vdda = devm_regulator_get_optional(s5kjn1->dev, "vdda"); 1342 if (IS_ERR(s5kjn1->vdda)) { 1343 ret = PTR_ERR(s5kjn1->vdda); 1344 if (ret != -ENODEV) { 1345 return dev_err_probe(s5kjn1->dev, ret, 1346 "Failed to get 'vdda' regulator\n"); 1347 } 1348 1349 s5kjn1->vdda = NULL; 1350 } 1351 1352 s5kjn1->vddd = devm_regulator_get_optional(s5kjn1->dev, "vddd"); 1353 if (IS_ERR(s5kjn1->vddd)) { 1354 ret = PTR_ERR(s5kjn1->vddd); 1355 if (ret != -ENODEV) { 1356 return dev_err_probe(s5kjn1->dev, ret, 1357 "Failed to get 'vddd' regulator\n"); 1358 } 1359 1360 s5kjn1->vddd = NULL; 1361 } 1362 1363 s5kjn1->vddio = devm_regulator_get_optional(s5kjn1->dev, "vddio"); 1364 if (IS_ERR(s5kjn1->vddio)) { 1365 ret = PTR_ERR(s5kjn1->vddio); 1366 if (ret != -ENODEV) { 1367 return dev_err_probe(s5kjn1->dev, ret, 1368 "Failed to get 'vddio' regulator\n"); 1369 } 1370 1371 s5kjn1->vddio = NULL; 1372 } 1373 1374 /* The sensor must be powered on to read the CHIP_ID register */ 1375 ret = s5kjn1_power_on(s5kjn1->dev); 1376 if (ret) 1377 return ret; 1378 1379 ret = s5kjn1_identify_sensor(s5kjn1); 1380 if (ret) { 1381 dev_err_probe(s5kjn1->dev, ret, "failed to find sensor\n"); 1382 goto power_off; 1383 } 1384 1385 s5kjn1->mode = &s5kjn1_supported_modes[0]; 1386 ret = s5kjn1_init_controls(s5kjn1); 1387 if (ret) { 1388 dev_err_probe(s5kjn1->dev, ret, "failed to init controls\n"); 1389 goto power_off; 1390 } 1391 1392 s5kjn1->sd.state_lock = s5kjn1->ctrl_handler.lock; 1393 s5kjn1->sd.internal_ops = &s5kjn1_internal_ops; 1394 s5kjn1->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1395 s5kjn1->sd.entity.ops = &s5kjn1_subdev_entity_ops; 1396 s5kjn1->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; 1397 s5kjn1->pad.flags = MEDIA_PAD_FL_SOURCE; 1398 1399 ret = media_entity_pads_init(&s5kjn1->sd.entity, 1, &s5kjn1->pad); 1400 if (ret) { 1401 dev_err_probe(s5kjn1->dev, ret, 1402 "failed to init media entity pads\n"); 1403 goto v4l2_ctrl_handler_free; 1404 } 1405 1406 ret = v4l2_subdev_init_finalize(&s5kjn1->sd); 1407 if (ret < 0) { 1408 dev_err_probe(s5kjn1->dev, ret, 1409 "failed to init media entity pads\n"); 1410 goto media_entity_cleanup; 1411 } 1412 1413 pm_runtime_set_active(s5kjn1->dev); 1414 pm_runtime_enable(s5kjn1->dev); 1415 1416 ret = v4l2_async_register_subdev_sensor(&s5kjn1->sd); 1417 if (ret < 0) { 1418 dev_err_probe(s5kjn1->dev, ret, 1419 "failed to register V4L2 subdev\n"); 1420 goto subdev_cleanup; 1421 } 1422 1423 pm_runtime_set_autosuspend_delay(s5kjn1->dev, 1000); 1424 pm_runtime_use_autosuspend(s5kjn1->dev); 1425 pm_runtime_idle(s5kjn1->dev); 1426 1427 return 0; 1428 1429 subdev_cleanup: 1430 v4l2_subdev_cleanup(&s5kjn1->sd); 1431 pm_runtime_disable(s5kjn1->dev); 1432 pm_runtime_set_suspended(s5kjn1->dev); 1433 1434 media_entity_cleanup: 1435 media_entity_cleanup(&s5kjn1->sd.entity); 1436 1437 v4l2_ctrl_handler_free: 1438 v4l2_ctrl_handler_free(s5kjn1->sd.ctrl_handler); 1439 1440 power_off: 1441 s5kjn1_power_off(s5kjn1->dev); 1442 1443 return ret; 1444 } 1445 1446 static void s5kjn1_remove(struct i2c_client *client) 1447 { 1448 struct v4l2_subdev *sd = i2c_get_clientdata(client); 1449 struct s5kjn1 *s5kjn1 = to_s5kjn1(sd); 1450 1451 v4l2_async_unregister_subdev(sd); 1452 v4l2_subdev_cleanup(sd); 1453 media_entity_cleanup(&sd->entity); 1454 v4l2_ctrl_handler_free(sd->ctrl_handler); 1455 pm_runtime_disable(s5kjn1->dev); 1456 1457 if (!pm_runtime_status_suspended(s5kjn1->dev)) { 1458 s5kjn1_power_off(s5kjn1->dev); 1459 pm_runtime_set_suspended(s5kjn1->dev); 1460 } 1461 } 1462 1463 static const struct dev_pm_ops s5kjn1_pm_ops = { 1464 SET_RUNTIME_PM_OPS(s5kjn1_power_off, s5kjn1_power_on, NULL) 1465 }; 1466 1467 static const struct of_device_id s5kjn1_of_match[] = { 1468 { .compatible = "samsung,s5kjn1" }, 1469 { /* sentinel */ } 1470 }; 1471 MODULE_DEVICE_TABLE(of, s5kjn1_of_match); 1472 1473 static struct i2c_driver s5kjn1_i2c_driver = { 1474 .driver = { 1475 .name = "s5kjn1", 1476 .pm = &s5kjn1_pm_ops, 1477 .of_match_table = s5kjn1_of_match, 1478 }, 1479 .probe = s5kjn1_probe, 1480 .remove = s5kjn1_remove, 1481 }; 1482 1483 module_i2c_driver(s5kjn1_i2c_driver); 1484 1485 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>"); 1486 MODULE_DESCRIPTION("Samsung S5KJN1 image sensor driver"); 1487 MODULE_LICENSE("GPL"); 1488