1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ov4689 driver 4 * 5 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 6 * Copyright (C) 2022, 2024 Mikhail Rudenko 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <media/media-entity.h> 17 #include <media/v4l2-async.h> 18 #include <media/v4l2-cci.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-subdev.h> 21 #include <media/v4l2-fwnode.h> 22 23 #define OV4689_REG_CTRL_MODE CCI_REG8(0x0100) 24 #define OV4689_MODE_SW_STANDBY 0x0 25 #define OV4689_MODE_STREAMING BIT(0) 26 27 #define OV4689_REG_CHIP_ID CCI_REG16(0x300a) 28 #define CHIP_ID 0x004688 29 30 #define OV4689_REG_EXPOSURE CCI_REG24(0x3500) 31 #define OV4689_EXPOSURE_MIN 4 32 #define OV4689_EXPOSURE_STEP 1 33 34 #define OV4689_REG_GAIN CCI_REG16(0x3508) 35 #define OV4689_GAIN_STEP 1 36 #define OV4689_GAIN_DEFAULT 0x80 37 38 #define OV4689_REG_DIG_GAIN CCI_REG16(0x352a) 39 #define OV4689_DIG_GAIN_MIN 1 40 #define OV4689_DIG_GAIN_MAX 0x7fff 41 #define OV4689_DIG_GAIN_STEP 1 42 #define OV4689_DIG_GAIN_DEFAULT 0x800 43 44 #define OV4689_REG_HTS CCI_REG16(0x380c) 45 #define OV4689_HTS_DIVIDER 4 46 #define OV4689_HTS_MAX 0x7fff 47 48 #define OV4689_REG_VTS CCI_REG16(0x380e) 49 #define OV4689_VTS_MAX 0x7fff 50 51 #define OV4689_REG_TIMING_FORMAT1 CCI_REG8(0x3820) /* Vertical */ 52 #define OV4689_REG_TIMING_FORMAT2 CCI_REG8(0x3821) /* Horizontal */ 53 #define OV4689_TIMING_FLIP_MASK GENMASK(2, 1) 54 #define OV4689_TIMING_FLIP_ARRAY BIT(1) 55 #define OV4689_TIMING_FLIP_DIGITAL BIT(2) 56 #define OV4689_TIMING_FLIP_BOTH (OV4689_TIMING_FLIP_ARRAY |\ 57 OV4689_TIMING_FLIP_DIGITAL) 58 59 #define OV4689_REG_WB_GAIN_RED CCI_REG16(0x500c) 60 #define OV4689_REG_WB_GAIN_BLUE CCI_REG16(0x5010) 61 #define OV4689_WB_GAIN_MIN 1 62 #define OV4689_WB_GAIN_MAX 0xfff 63 #define OV4689_WB_GAIN_STEP 1 64 #define OV4689_WB_GAIN_DEFAULT 0x400 65 66 #define OV4689_REG_TEST_PATTERN CCI_REG8(0x5040) 67 #define OV4689_TEST_PATTERN_ENABLE 0x80 68 #define OV4689_TEST_PATTERN_DISABLE 0x0 69 70 #define OV4689_LANES 4 71 #define OV4689_XVCLK_FREQ 24000000 72 73 static const char *const ov4689_supply_names[] = { 74 "avdd", /* Analog power */ 75 "dovdd", /* Digital I/O power */ 76 "dvdd", /* Digital core power */ 77 }; 78 79 enum ov4689_mode_id { 80 OV4689_MODE_2688_1520 = 0, 81 OV4689_NUM_MODES, 82 }; 83 84 struct ov4689_mode { 85 enum ov4689_mode_id id; 86 u32 width; 87 u32 height; 88 u32 hts_def; 89 u32 hts_min; 90 u32 vts_def; 91 u32 exp_def; 92 u32 pixel_rate; 93 u32 sensor_width; 94 u32 sensor_height; 95 u32 crop_top; 96 u32 crop_left; 97 const struct cci_reg_sequence *reg_list; 98 unsigned int num_regs; 99 }; 100 101 struct ov4689 { 102 struct device *dev; 103 struct regmap *regmap; 104 struct clk *xvclk; 105 struct gpio_desc *reset_gpio; 106 struct gpio_desc *pwdn_gpio; 107 struct regulator_bulk_data supplies[ARRAY_SIZE(ov4689_supply_names)]; 108 109 struct v4l2_subdev subdev; 110 struct media_pad pad; 111 112 u32 clock_rate; 113 114 struct v4l2_ctrl_handler ctrl_handler; 115 struct v4l2_ctrl *exposure; 116 117 const struct ov4689_mode *cur_mode; 118 }; 119 120 #define to_ov4689(sd) container_of(sd, struct ov4689, subdev) 121 122 struct ov4689_gain_range { 123 u32 logical_min; 124 u32 logical_max; 125 u32 offset; 126 u32 divider; 127 u32 physical_min; 128 u32 physical_max; 129 }; 130 131 /* 132 * Xclk 24Mhz 133 * max_framerate 90fps 134 * mipi_datarate per lane 1008Mbps 135 */ 136 static const struct cci_reg_sequence ov4689_2688x1520_regs[] = { 137 /* System control*/ 138 { CCI_REG8(0x0103), 0x01 }, /* SC_CTRL0103 software_reset = 1 */ 139 { CCI_REG8(0x3000), 0x20 }, /* SC_CMMN_PAD_OEN0 FSIN_output_enable = 1 */ 140 { CCI_REG8(0x3021), 0x03 }, /* 141 * SC_CMMN_MISC_CTRL fst_stby_ctr = 0, 142 * sleep_no_latch_enable = 0 143 */ 144 145 /* AEC PK */ 146 { CCI_REG8(0x3503), 0x04 }, /* AEC_MANUAL gain_input_as_sensor_gain_format = 1 */ 147 148 /* ADC and analog control*/ 149 { CCI_REG8(0x3603), 0x40 }, 150 { CCI_REG8(0x3604), 0x02 }, 151 { CCI_REG8(0x3609), 0x12 }, 152 { CCI_REG8(0x360c), 0x08 }, 153 { CCI_REG8(0x360f), 0xe5 }, 154 { CCI_REG8(0x3608), 0x8f }, 155 { CCI_REG8(0x3611), 0x00 }, 156 { CCI_REG8(0x3613), 0xf7 }, 157 { CCI_REG8(0x3616), 0x58 }, 158 { CCI_REG8(0x3619), 0x99 }, 159 { CCI_REG8(0x361b), 0x60 }, 160 { CCI_REG8(0x361e), 0x79 }, 161 { CCI_REG8(0x3634), 0x10 }, 162 { CCI_REG8(0x3635), 0x10 }, 163 { CCI_REG8(0x3636), 0x15 }, 164 { CCI_REG8(0x3646), 0x86 }, 165 { CCI_REG8(0x364a), 0x0b }, 166 167 /* Sensor control */ 168 { CCI_REG8(0x3700), 0x17 }, 169 { CCI_REG8(0x3701), 0x22 }, 170 { CCI_REG8(0x3703), 0x10 }, 171 { CCI_REG8(0x370a), 0x37 }, 172 { CCI_REG8(0x3706), 0x63 }, 173 { CCI_REG8(0x3709), 0x3c }, 174 { CCI_REG8(0x370c), 0x30 }, 175 { CCI_REG8(0x3710), 0x24 }, 176 { CCI_REG8(0x3720), 0x28 }, 177 { CCI_REG8(0x3729), 0x7b }, 178 { CCI_REG8(0x372b), 0xbd }, 179 { CCI_REG8(0x372c), 0xbc }, 180 { CCI_REG8(0x372e), 0x52 }, 181 { CCI_REG8(0x373c), 0x0e }, 182 { CCI_REG8(0x373e), 0x33 }, 183 { CCI_REG8(0x3743), 0x10 }, 184 { CCI_REG8(0x3744), 0x88 }, 185 { CCI_REG8(0x3745), 0xc0 }, 186 { CCI_REG8(0x374c), 0x00 }, 187 { CCI_REG8(0x374e), 0x23 }, 188 { CCI_REG8(0x3751), 0x7b }, 189 { CCI_REG8(0x3753), 0xbd }, 190 { CCI_REG8(0x3754), 0xbc }, 191 { CCI_REG8(0x3756), 0x52 }, 192 { CCI_REG8(0x376b), 0x20 }, 193 { CCI_REG8(0x3774), 0x51 }, 194 { CCI_REG8(0x3776), 0xbd }, 195 { CCI_REG8(0x3777), 0xbd }, 196 { CCI_REG8(0x3781), 0x18 }, 197 { CCI_REG8(0x3783), 0x25 }, 198 { CCI_REG8(0x3798), 0x1b }, 199 200 /* Timing control */ 201 { CCI_REG8(0x3801), 0x08 }, /* H_CROP_START_L h_crop_start[7:0] = 0x08 */ 202 { CCI_REG8(0x3805), 0x97 }, /* H_CROP_END_L h_crop_end[7:0] = 0x97 */ 203 { CCI_REG8(0x3811), 0x08 }, /* H_WIN_OFF_L h_win_off[7:0] = 0x08*/ 204 { CCI_REG8(0x3813), 0x04 }, /* V_WIN_OFF_L v_win_off[7:0] = 0x04 */ 205 { CCI_REG8(0x3819), 0x01 }, /* VSYNC_END_L vsync_end_point[7:0] = 0x01 */ 206 207 /* OTP control */ 208 { CCI_REG8(0x3d85), 0x36 }, /* OTP_REG85 OTP_power_up_load_setting_enable = 1, 209 * OTP_power_up_load_data_enable = 1, 210 * OTP_bist_select = 1 (compare with zero) 211 */ 212 { CCI_REG8(0x3d8c), 0x71 }, /* OTP_SETTING_STT_ADDRESS_H */ 213 { CCI_REG8(0x3d8d), 0xcb }, /* OTP_SETTING_STT_ADDRESS_L */ 214 215 /* BLC registers*/ 216 { CCI_REG8(0x4001), 0x40 }, /* DEBUG_MODE */ 217 { CCI_REG8(0x401b), 0x00 }, /* DEBUG_MODE */ 218 { CCI_REG8(0x401d), 0x00 }, /* DEBUG_MODE */ 219 { CCI_REG8(0x401f), 0x00 }, /* DEBUG_MODE */ 220 { CCI_REG8(0x4020), 0x00 }, /* ANCHOR_LEFT_START_H anchor_left_start[11:8] = 0 */ 221 { CCI_REG8(0x4021), 0x10 }, /* ANCHOR_LEFT_START_L anchor_left_start[7:0] = 0x10 */ 222 { CCI_REG8(0x4022), 0x07 }, /* ANCHOR_LEFT_END_H anchor_left_end[11:8] = 0x07 */ 223 { CCI_REG8(0x4023), 0xcf }, /* ANCHOR_LEFT_END_L anchor_left_end[7:0] = 0xcf */ 224 { CCI_REG8(0x4024), 0x09 }, /* ANCHOR_RIGHT_START_H anchor_right_start[11:8] = 0x09 */ 225 { CCI_REG8(0x4025), 0x60 }, /* ANCHOR_RIGHT_START_L anchor_right_start[7:0] = 0x60 */ 226 { CCI_REG8(0x4026), 0x09 }, /* ANCHOR_RIGHT_END_H anchor_right_end[11:8] = 0x09 */ 227 { CCI_REG8(0x4027), 0x6f }, /* ANCHOR_RIGHT_END_L anchor_right_end[7:0] = 0x6f */ 228 229 /* ADC sync control */ 230 { CCI_REG8(0x4500), 0x6c }, /* ADC_SYNC_CTRL */ 231 { CCI_REG8(0x4503), 0x01 }, /* ADC_SYNC_CTRL */ 232 233 /* VFIFO */ 234 { CCI_REG8(0x4601), 0xa7 }, /* VFIFO_CTRL_01 r_vfifo_read_start[7:0] = 0xa7 */ 235 236 /* Temperature monitor */ 237 { CCI_REG8(0x4d00), 0x04 }, /* TPM_CTRL_00 tmp_slope[15:8] = 0x04 */ 238 { CCI_REG8(0x4d01), 0x42 }, /* TPM_CTRL_01 tmp_slope[7:0] = 0x42 */ 239 { CCI_REG8(0x4d02), 0xd1 }, /* TPM_CTRL_02 tpm_offset[31:24] = 0xd1 */ 240 { CCI_REG8(0x4d03), 0x93 }, /* TPM_CTRL_03 tpm_offset[23:16] = 0x93 */ 241 { CCI_REG8(0x4d04), 0xf5 }, /* TPM_CTRL_04 tpm_offset[15:8] = 0xf5 */ 242 { CCI_REG8(0x4d05), 0xc1 }, /* TPM_CTRL_05 tpm_offset[7:0] = 0xc1 */ 243 244 /* pre-ISP control */ 245 { CCI_REG8(0x5050), 0x0c }, /* DEBUG_MODE */ 246 247 /* OTP-DPC control */ 248 { CCI_REG8(0x5501), 0x10 }, /* OTP_DPC_START_L otp_start_address[7:0] = 0x10 */ 249 { CCI_REG8(0x5503), 0x0f }, /* OTP_DPC_END_L otp_end_address[7:0] = 0x0f */ 250 }; 251 252 static const struct ov4689_mode supported_modes[] = { 253 { 254 .id = OV4689_MODE_2688_1520, 255 .width = 2688, 256 .height = 1520, 257 .sensor_width = 2720, 258 .sensor_height = 1536, 259 .crop_top = 8, 260 .crop_left = 16, 261 .exp_def = 1536, 262 .hts_def = 10296, 263 .hts_min = 3432, 264 .vts_def = 1554, 265 .pixel_rate = 480000000, 266 .reg_list = ov4689_2688x1520_regs, 267 .num_regs = ARRAY_SIZE(ov4689_2688x1520_regs), 268 }, 269 }; 270 271 static const u64 link_freq_menu_items[] = { 504000000 }; 272 273 static const char *const ov4689_test_pattern_menu[] = { 274 "Disabled", 275 "Vertical Color Bar Type 1", 276 "Vertical Color Bar Type 2", 277 "Vertical Color Bar Type 3", 278 "Vertical Color Bar Type 4" 279 }; 280 281 /* 282 * These coefficients are based on those used in Rockchip's camera 283 * engine, with minor tweaks for continuity. 284 */ 285 static const struct ov4689_gain_range ov4689_gain_ranges[] = { 286 { 287 .logical_min = 0, 288 .logical_max = 255, 289 .offset = 0, 290 .divider = 1, 291 .physical_min = 0, 292 .physical_max = 255, 293 }, 294 { 295 .logical_min = 256, 296 .logical_max = 511, 297 .offset = 252, 298 .divider = 2, 299 .physical_min = 376, 300 .physical_max = 504, 301 }, 302 { 303 .logical_min = 512, 304 .logical_max = 1023, 305 .offset = 758, 306 .divider = 4, 307 .physical_min = 884, 308 .physical_max = 1012, 309 }, 310 { 311 .logical_min = 1024, 312 .logical_max = 2047, 313 .offset = 1788, 314 .divider = 8, 315 .physical_min = 1912, 316 .physical_max = 2047, 317 }, 318 }; 319 320 static void ov4689_fill_fmt(const struct ov4689_mode *mode, 321 struct v4l2_mbus_framefmt *fmt) 322 { 323 fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; 324 fmt->width = mode->width; 325 fmt->height = mode->height; 326 fmt->field = V4L2_FIELD_NONE; 327 } 328 329 static int ov4689_set_fmt(struct v4l2_subdev *sd, 330 struct v4l2_subdev_state *sd_state, 331 struct v4l2_subdev_format *fmt) 332 { 333 struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format; 334 struct ov4689 *ov4689 = to_ov4689(sd); 335 336 /* only one mode supported for now */ 337 ov4689_fill_fmt(ov4689->cur_mode, mbus_fmt); 338 339 return 0; 340 } 341 342 static int ov4689_enum_mbus_code(struct v4l2_subdev *sd, 343 struct v4l2_subdev_state *sd_state, 344 struct v4l2_subdev_mbus_code_enum *code) 345 { 346 if (code->index != 0) 347 return -EINVAL; 348 code->code = MEDIA_BUS_FMT_SBGGR10_1X10; 349 350 return 0; 351 } 352 353 static int ov4689_enum_frame_sizes(struct v4l2_subdev *sd, 354 struct v4l2_subdev_state *sd_state, 355 struct v4l2_subdev_frame_size_enum *fse) 356 { 357 if (fse->index >= ARRAY_SIZE(supported_modes)) 358 return -EINVAL; 359 360 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10) 361 return -EINVAL; 362 363 fse->min_width = supported_modes[fse->index].width; 364 fse->max_width = supported_modes[fse->index].width; 365 fse->max_height = supported_modes[fse->index].height; 366 fse->min_height = supported_modes[fse->index].height; 367 368 return 0; 369 } 370 371 static int ov4689_enable_test_pattern(struct ov4689 *ov4689, u32 pattern) 372 { 373 u32 val; 374 375 if (pattern) 376 val = (pattern - 1) | OV4689_TEST_PATTERN_ENABLE; 377 else 378 val = OV4689_TEST_PATTERN_DISABLE; 379 380 return cci_write(ov4689->regmap, OV4689_REG_TEST_PATTERN, 381 val, NULL); 382 } 383 384 static int ov4689_get_selection(struct v4l2_subdev *sd, 385 struct v4l2_subdev_state *state, 386 struct v4l2_subdev_selection *sel) 387 { 388 const struct ov4689_mode *mode = to_ov4689(sd)->cur_mode; 389 390 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) 391 return -EINVAL; 392 393 switch (sel->target) { 394 case V4L2_SEL_TGT_CROP_BOUNDS: 395 sel->r.top = 0; 396 sel->r.left = 0; 397 sel->r.width = mode->sensor_width; 398 sel->r.height = mode->sensor_height; 399 return 0; 400 case V4L2_SEL_TGT_CROP: 401 case V4L2_SEL_TGT_CROP_DEFAULT: 402 sel->r.top = mode->crop_top; 403 sel->r.left = mode->crop_left; 404 sel->r.width = mode->width; 405 sel->r.height = mode->height; 406 return 0; 407 } 408 409 return -EINVAL; 410 } 411 412 static int ov4689_s_stream(struct v4l2_subdev *sd, int on) 413 { 414 struct ov4689 *ov4689 = to_ov4689(sd); 415 struct v4l2_subdev_state *sd_state; 416 struct device *dev = ov4689->dev; 417 int ret = 0; 418 419 sd_state = v4l2_subdev_lock_and_get_active_state(&ov4689->subdev); 420 421 if (on) { 422 ret = pm_runtime_resume_and_get(dev); 423 if (ret < 0) 424 goto unlock_and_return; 425 426 ret = cci_multi_reg_write(ov4689->regmap, 427 ov4689->cur_mode->reg_list, 428 ov4689->cur_mode->num_regs, 429 NULL); 430 if (ret) { 431 pm_runtime_put(dev); 432 goto unlock_and_return; 433 } 434 435 ret = __v4l2_ctrl_handler_setup(&ov4689->ctrl_handler); 436 if (ret) { 437 pm_runtime_put(dev); 438 goto unlock_and_return; 439 } 440 441 ret = cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE, 442 OV4689_MODE_STREAMING, NULL); 443 if (ret) { 444 pm_runtime_put(dev); 445 goto unlock_and_return; 446 } 447 } else { 448 cci_write(ov4689->regmap, OV4689_REG_CTRL_MODE, 449 OV4689_MODE_SW_STANDBY, NULL); 450 pm_runtime_mark_last_busy(dev); 451 pm_runtime_put_autosuspend(dev); 452 } 453 454 unlock_and_return: 455 v4l2_subdev_unlock_state(sd_state); 456 457 return ret; 458 } 459 460 /* Calculate the delay in us by clock rate and clock cycles */ 461 static inline u32 ov4689_cal_delay(struct ov4689 *ov4689, u32 cycles) 462 { 463 return DIV_ROUND_UP(cycles * 1000, 464 DIV_ROUND_UP(ov4689->clock_rate, 1000)); 465 } 466 467 static int __maybe_unused ov4689_power_on(struct device *dev) 468 { 469 struct v4l2_subdev *sd = dev_get_drvdata(dev); 470 struct ov4689 *ov4689 = to_ov4689(sd); 471 u32 delay_us; 472 int ret; 473 474 ret = clk_prepare_enable(ov4689->xvclk); 475 if (ret < 0) { 476 dev_err(dev, "Failed to enable xvclk\n"); 477 return ret; 478 } 479 480 gpiod_set_value_cansleep(ov4689->reset_gpio, 1); 481 482 ret = regulator_bulk_enable(ARRAY_SIZE(ov4689_supply_names), 483 ov4689->supplies); 484 if (ret < 0) { 485 dev_err(dev, "Failed to enable regulators\n"); 486 goto disable_clk; 487 } 488 489 gpiod_set_value_cansleep(ov4689->reset_gpio, 0); 490 usleep_range(500, 1000); 491 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0); 492 493 /* 8192 cycles prior to first SCCB transaction */ 494 delay_us = ov4689_cal_delay(ov4689, 8192); 495 usleep_range(delay_us, delay_us * 2); 496 497 return 0; 498 499 disable_clk: 500 clk_disable_unprepare(ov4689->xvclk); 501 502 return ret; 503 } 504 505 static int __maybe_unused ov4689_power_off(struct device *dev) 506 { 507 struct v4l2_subdev *sd = dev_get_drvdata(dev); 508 struct ov4689 *ov4689 = to_ov4689(sd); 509 510 gpiod_set_value_cansleep(ov4689->pwdn_gpio, 1); 511 clk_disable_unprepare(ov4689->xvclk); 512 gpiod_set_value_cansleep(ov4689->reset_gpio, 1); 513 regulator_bulk_disable(ARRAY_SIZE(ov4689_supply_names), 514 ov4689->supplies); 515 return 0; 516 } 517 518 static int ov4689_init_state(struct v4l2_subdev *sd, 519 struct v4l2_subdev_state *sd_state) 520 { 521 struct v4l2_mbus_framefmt *fmt = 522 v4l2_subdev_state_get_format(sd_state, 0); 523 524 ov4689_fill_fmt(&supported_modes[OV4689_MODE_2688_1520], fmt); 525 526 return 0; 527 } 528 529 static const struct dev_pm_ops ov4689_pm_ops = { 530 SET_RUNTIME_PM_OPS(ov4689_power_off, ov4689_power_on, NULL) 531 }; 532 533 static const struct v4l2_subdev_video_ops ov4689_video_ops = { 534 .s_stream = ov4689_s_stream, 535 }; 536 537 static const struct v4l2_subdev_pad_ops ov4689_pad_ops = { 538 .enum_mbus_code = ov4689_enum_mbus_code, 539 .enum_frame_size = ov4689_enum_frame_sizes, 540 .get_fmt = v4l2_subdev_get_fmt, 541 .set_fmt = ov4689_set_fmt, 542 .get_selection = ov4689_get_selection, 543 }; 544 545 static const struct v4l2_subdev_internal_ops ov4689_internal_ops = { 546 .init_state = ov4689_init_state, 547 }; 548 549 static const struct v4l2_subdev_ops ov4689_subdev_ops = { 550 .video = &ov4689_video_ops, 551 .pad = &ov4689_pad_ops, 552 }; 553 554 /* 555 * Map userspace (logical) gain to sensor (physical) gain using 556 * ov4689_gain_ranges table. 557 */ 558 static int ov4689_map_gain(struct ov4689 *ov4689, int logical_gain, int *result) 559 { 560 const struct ov4689_gain_range *range; 561 unsigned int n; 562 563 for (n = 0; n < ARRAY_SIZE(ov4689_gain_ranges); n++) { 564 if (logical_gain >= ov4689_gain_ranges[n].logical_min && 565 logical_gain <= ov4689_gain_ranges[n].logical_max) 566 break; 567 } 568 569 if (n == ARRAY_SIZE(ov4689_gain_ranges)) { 570 dev_warn_ratelimited(ov4689->dev, 571 "no mapping found for gain %d\n", 572 logical_gain); 573 return -EINVAL; 574 } 575 576 range = &ov4689_gain_ranges[n]; 577 578 *result = clamp(range->offset + (logical_gain) / range->divider, 579 range->physical_min, range->physical_max); 580 return 0; 581 } 582 583 static int ov4689_set_ctrl(struct v4l2_ctrl *ctrl) 584 { 585 struct ov4689 *ov4689 = 586 container_of(ctrl->handler, struct ov4689, ctrl_handler); 587 struct regmap *regmap = ov4689->regmap; 588 struct device *dev = ov4689->dev; 589 int sensor_gain = 0; 590 s64 max_expo; 591 int ret = 0; 592 593 /* Propagate change of current control to all related controls */ 594 switch (ctrl->id) { 595 case V4L2_CID_VBLANK: 596 /* Update max exposure while meeting expected vblanking */ 597 max_expo = ov4689->cur_mode->height + ctrl->val - 4; 598 __v4l2_ctrl_modify_range(ov4689->exposure, 599 ov4689->exposure->minimum, max_expo, 600 ov4689->exposure->step, 601 ov4689->exposure->default_value); 602 break; 603 } 604 605 if (!pm_runtime_get_if_in_use(dev)) 606 return 0; 607 608 switch (ctrl->id) { 609 case V4L2_CID_EXPOSURE: 610 /* 4 least significant bits of exposure are fractional part */ 611 cci_write(regmap, OV4689_REG_EXPOSURE, ctrl->val << 4, &ret); 612 break; 613 case V4L2_CID_ANALOGUE_GAIN: 614 ret = ov4689_map_gain(ov4689, ctrl->val, &sensor_gain); 615 cci_write(regmap, OV4689_REG_GAIN, sensor_gain, &ret); 616 break; 617 case V4L2_CID_VBLANK: 618 cci_write(regmap, OV4689_REG_VTS, 619 ctrl->val + ov4689->cur_mode->height, &ret); 620 break; 621 case V4L2_CID_TEST_PATTERN: 622 ret = ov4689_enable_test_pattern(ov4689, ctrl->val); 623 break; 624 case V4L2_CID_HBLANK: 625 cci_write(regmap, OV4689_REG_HTS, 626 (ctrl->val + ov4689->cur_mode->width) / 627 OV4689_HTS_DIVIDER, &ret); 628 break; 629 case V4L2_CID_VFLIP: 630 cci_update_bits(regmap, OV4689_REG_TIMING_FORMAT1, 631 OV4689_TIMING_FLIP_MASK, 632 ctrl->val ? OV4689_TIMING_FLIP_BOTH : 0, &ret); 633 break; 634 case V4L2_CID_HFLIP: 635 cci_update_bits(regmap, OV4689_REG_TIMING_FORMAT2, 636 OV4689_TIMING_FLIP_MASK, 637 ctrl->val ? 0 : OV4689_TIMING_FLIP_BOTH, &ret); 638 break; 639 case V4L2_CID_DIGITAL_GAIN: 640 cci_write(regmap, OV4689_REG_DIG_GAIN, ctrl->val, &ret); 641 break; 642 case V4L2_CID_RED_BALANCE: 643 cci_write(regmap, OV4689_REG_WB_GAIN_RED, ctrl->val, &ret); 644 break; 645 case V4L2_CID_BLUE_BALANCE: 646 cci_write(regmap, OV4689_REG_WB_GAIN_BLUE, ctrl->val, &ret); 647 break; 648 default: 649 dev_warn(dev, "%s Unhandled id:0x%x, val:0x%x\n", 650 __func__, ctrl->id, ctrl->val); 651 ret = -EINVAL; 652 break; 653 } 654 655 pm_runtime_mark_last_busy(dev); 656 pm_runtime_put_autosuspend(dev); 657 658 return ret; 659 } 660 661 static const struct v4l2_ctrl_ops ov4689_ctrl_ops = { 662 .s_ctrl = ov4689_set_ctrl, 663 }; 664 665 static int ov4689_initialize_controls(struct ov4689 *ov4689) 666 { 667 struct i2c_client *client = v4l2_get_subdevdata(&ov4689->subdev); 668 struct v4l2_fwnode_device_properties props; 669 struct v4l2_ctrl_handler *handler; 670 const struct ov4689_mode *mode; 671 s64 exposure_max, vblank_def; 672 s64 hblank_def, hblank_min; 673 struct v4l2_ctrl *ctrl; 674 int ret; 675 676 handler = &ov4689->ctrl_handler; 677 mode = ov4689->cur_mode; 678 ret = v4l2_ctrl_handler_init(handler, 15); 679 if (ret) 680 return ret; 681 682 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0, 683 link_freq_menu_items); 684 if (ctrl) 685 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY; 686 687 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, 688 mode->pixel_rate, 1, mode->pixel_rate); 689 690 hblank_def = mode->hts_def - mode->width; 691 hblank_min = mode->hts_min - mode->width; 692 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_HBLANK, 693 hblank_min, OV4689_HTS_MAX - mode->width, 694 OV4689_HTS_DIVIDER, hblank_def); 695 696 vblank_def = mode->vts_def - mode->height; 697 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VBLANK, 698 vblank_def, OV4689_VTS_MAX - mode->height, 1, 699 vblank_def); 700 701 exposure_max = mode->vts_def - 4; 702 ov4689->exposure = 703 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_EXPOSURE, 704 OV4689_EXPOSURE_MIN, exposure_max, 705 OV4689_EXPOSURE_STEP, mode->exp_def); 706 707 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, 708 ov4689_gain_ranges[0].logical_min, 709 ov4689_gain_ranges[ARRAY_SIZE(ov4689_gain_ranges) - 1] 710 .logical_max, 711 OV4689_GAIN_STEP, OV4689_GAIN_DEFAULT); 712 713 v4l2_ctrl_new_std_menu_items(handler, &ov4689_ctrl_ops, 714 V4L2_CID_TEST_PATTERN, 715 ARRAY_SIZE(ov4689_test_pattern_menu) - 1, 716 0, 0, ov4689_test_pattern_menu); 717 718 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0); 719 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0); 720 721 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_DIGITAL_GAIN, 722 OV4689_DIG_GAIN_MIN, OV4689_DIG_GAIN_MAX, 723 OV4689_DIG_GAIN_STEP, OV4689_DIG_GAIN_DEFAULT); 724 725 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_RED_BALANCE, 726 OV4689_WB_GAIN_MIN, OV4689_WB_GAIN_MAX, 727 OV4689_WB_GAIN_STEP, OV4689_WB_GAIN_DEFAULT); 728 729 v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops, V4L2_CID_BLUE_BALANCE, 730 OV4689_WB_GAIN_MIN, OV4689_WB_GAIN_MAX, 731 OV4689_WB_GAIN_STEP, OV4689_WB_GAIN_DEFAULT); 732 733 if (handler->error) { 734 ret = handler->error; 735 dev_err(ov4689->dev, "Failed to init controls(%d)\n", ret); 736 goto err_free_handler; 737 } 738 739 ret = v4l2_fwnode_device_parse(&client->dev, &props); 740 if (ret) 741 goto err_free_handler; 742 743 ret = v4l2_ctrl_new_fwnode_properties(handler, &ov4689_ctrl_ops, 744 &props); 745 if (ret) 746 goto err_free_handler; 747 748 ov4689->subdev.ctrl_handler = handler; 749 750 return 0; 751 752 err_free_handler: 753 v4l2_ctrl_handler_free(handler); 754 755 return ret; 756 } 757 758 static int ov4689_check_sensor_id(struct ov4689 *ov4689, 759 struct i2c_client *client) 760 { 761 struct device *dev = ov4689->dev; 762 u64 id = 0; 763 int ret; 764 765 ret = cci_read(ov4689->regmap, OV4689_REG_CHIP_ID, &id, NULL); 766 if (ret) { 767 dev_err(dev, "Cannot read sensor ID\n"); 768 return ret; 769 } 770 771 if (id != CHIP_ID) { 772 dev_err(dev, "Unexpected sensor ID %06llx, expected %06x\n", 773 id, CHIP_ID); 774 return -ENODEV; 775 } 776 777 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID); 778 779 return 0; 780 } 781 782 static int ov4689_configure_regulators(struct ov4689 *ov4689) 783 { 784 unsigned int i; 785 786 for (i = 0; i < ARRAY_SIZE(ov4689_supply_names); i++) 787 ov4689->supplies[i].supply = ov4689_supply_names[i]; 788 789 return devm_regulator_bulk_get(ov4689->dev, 790 ARRAY_SIZE(ov4689_supply_names), 791 ov4689->supplies); 792 } 793 794 static u64 ov4689_check_link_frequency(struct v4l2_fwnode_endpoint *ep) 795 { 796 const u64 *freqs = link_freq_menu_items; 797 unsigned int i, j; 798 799 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) { 800 for (j = 0; j < ep->nr_of_link_frequencies; j++) 801 if (freqs[i] == ep->link_frequencies[j]) 802 return freqs[i]; 803 } 804 805 return 0; 806 } 807 808 static int ov4689_check_hwcfg(struct device *dev) 809 { 810 struct fwnode_handle *fwnode = dev_fwnode(dev); 811 struct v4l2_fwnode_endpoint bus_cfg = { 812 .bus_type = V4L2_MBUS_CSI2_DPHY, 813 }; 814 struct fwnode_handle *endpoint; 815 int ret; 816 817 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL); 818 if (!endpoint) 819 return -EINVAL; 820 821 ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg); 822 fwnode_handle_put(endpoint); 823 if (ret) 824 return ret; 825 826 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV4689_LANES) { 827 dev_err(dev, "Only a 4-lane CSI2 config is supported"); 828 ret = -EINVAL; 829 goto out_free_bus_cfg; 830 } 831 832 if (!ov4689_check_link_frequency(&bus_cfg)) { 833 dev_err(dev, "No supported link frequency found\n"); 834 ret = -EINVAL; 835 } 836 837 out_free_bus_cfg: 838 v4l2_fwnode_endpoint_free(&bus_cfg); 839 840 return ret; 841 } 842 843 static int ov4689_probe(struct i2c_client *client) 844 { 845 struct device *dev = &client->dev; 846 struct v4l2_subdev *sd; 847 struct ov4689 *ov4689; 848 int ret; 849 850 ret = ov4689_check_hwcfg(dev); 851 if (ret) 852 return ret; 853 854 ov4689 = devm_kzalloc(dev, sizeof(*ov4689), GFP_KERNEL); 855 if (!ov4689) 856 return -ENOMEM; 857 858 ov4689->dev = dev; 859 860 ov4689->cur_mode = &supported_modes[OV4689_MODE_2688_1520]; 861 862 ov4689->xvclk = devm_clk_get_optional(dev, NULL); 863 if (IS_ERR(ov4689->xvclk)) 864 return dev_err_probe(dev, PTR_ERR(ov4689->xvclk), 865 "Failed to get external clock\n"); 866 867 if (!ov4689->xvclk) { 868 dev_dbg(dev, 869 "No clock provided, using clock-frequency property\n"); 870 device_property_read_u32(dev, "clock-frequency", 871 &ov4689->clock_rate); 872 } else { 873 ov4689->clock_rate = clk_get_rate(ov4689->xvclk); 874 } 875 876 if (ov4689->clock_rate != OV4689_XVCLK_FREQ) { 877 dev_err(dev, 878 "External clock rate mismatch: got %d Hz, expected %d Hz\n", 879 ov4689->clock_rate, OV4689_XVCLK_FREQ); 880 return -EINVAL; 881 } 882 883 ov4689->regmap = devm_cci_regmap_init_i2c(client, 16); 884 if (IS_ERR(ov4689->regmap)) { 885 ret = PTR_ERR(ov4689->regmap); 886 dev_err(dev, "failed to initialize CCI: %d\n", ret); 887 return ret; 888 } 889 890 ov4689->reset_gpio = devm_gpiod_get_optional(dev, "reset", 891 GPIOD_OUT_LOW); 892 if (IS_ERR(ov4689->reset_gpio)) { 893 dev_err(dev, "Failed to get reset-gpios\n"); 894 return PTR_ERR(ov4689->reset_gpio); 895 } 896 897 ov4689->pwdn_gpio = devm_gpiod_get_optional(dev, "pwdn", GPIOD_OUT_LOW); 898 if (IS_ERR(ov4689->pwdn_gpio)) { 899 dev_err(dev, "Failed to get pwdn-gpios\n"); 900 return PTR_ERR(ov4689->pwdn_gpio); 901 } 902 903 ret = ov4689_configure_regulators(ov4689); 904 if (ret) 905 return dev_err_probe(dev, ret, 906 "Failed to get power regulators\n"); 907 908 sd = &ov4689->subdev; 909 v4l2_i2c_subdev_init(sd, client, &ov4689_subdev_ops); 910 sd->internal_ops = &ov4689_internal_ops; 911 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 912 ret = ov4689_initialize_controls(ov4689); 913 if (ret) { 914 dev_err(dev, "Failed to initialize controls\n"); 915 return ret; 916 } 917 918 ret = ov4689_power_on(dev); 919 if (ret) 920 goto err_free_handler; 921 922 ret = ov4689_check_sensor_id(ov4689, client); 923 if (ret) 924 goto err_power_off; 925 926 927 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; 928 ov4689->pad.flags = MEDIA_PAD_FL_SOURCE; 929 ret = media_entity_pads_init(&sd->entity, 1, &ov4689->pad); 930 if (ret < 0) 931 goto err_power_off; 932 933 sd->state_lock = ov4689->ctrl_handler.lock; 934 ret = v4l2_subdev_init_finalize(sd); 935 if (ret) { 936 dev_err(dev, "Could not register v4l2 device\n"); 937 goto err_clean_entity; 938 } 939 940 pm_runtime_set_active(dev); 941 pm_runtime_get_noresume(dev); 942 pm_runtime_enable(dev); 943 pm_runtime_set_autosuspend_delay(dev, 1000); 944 pm_runtime_use_autosuspend(dev); 945 946 ret = v4l2_async_register_subdev_sensor(sd); 947 if (ret) { 948 dev_err(dev, "v4l2 async register subdev failed\n"); 949 goto err_clean_subdev_pm; 950 } 951 952 pm_runtime_mark_last_busy(dev); 953 pm_runtime_put_autosuspend(dev); 954 955 return 0; 956 957 err_clean_subdev_pm: 958 pm_runtime_disable(dev); 959 pm_runtime_put_noidle(dev); 960 v4l2_subdev_cleanup(sd); 961 err_clean_entity: 962 media_entity_cleanup(&sd->entity); 963 err_power_off: 964 ov4689_power_off(dev); 965 err_free_handler: 966 v4l2_ctrl_handler_free(&ov4689->ctrl_handler); 967 968 return ret; 969 } 970 971 static void ov4689_remove(struct i2c_client *client) 972 { 973 struct v4l2_subdev *sd = i2c_get_clientdata(client); 974 struct ov4689 *ov4689 = to_ov4689(sd); 975 976 v4l2_async_unregister_subdev(sd); 977 media_entity_cleanup(&sd->entity); 978 v4l2_subdev_cleanup(sd); 979 v4l2_ctrl_handler_free(&ov4689->ctrl_handler); 980 981 pm_runtime_disable(&client->dev); 982 if (!pm_runtime_status_suspended(&client->dev)) 983 ov4689_power_off(&client->dev); 984 pm_runtime_set_suspended(&client->dev); 985 } 986 987 static const struct of_device_id ov4689_of_match[] = { 988 { .compatible = "ovti,ov4689" }, 989 {}, 990 }; 991 MODULE_DEVICE_TABLE(of, ov4689_of_match); 992 993 static struct i2c_driver ov4689_i2c_driver = { 994 .driver = { 995 .name = "ov4689", 996 .pm = &ov4689_pm_ops, 997 .of_match_table = ov4689_of_match, 998 }, 999 .probe = ov4689_probe, 1000 .remove = ov4689_remove, 1001 }; 1002 1003 module_i2c_driver(ov4689_i2c_driver); 1004 1005 MODULE_DESCRIPTION("OmniVision ov4689 sensor driver"); 1006 MODULE_LICENSE("GPL"); 1007